Merge branch 'for-ingo' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-sfi-2.6 into x86/apic

Merge reason: the SFI (Simple Firmware Interface) feature in the ACPI
              tree needs this cleanup, pull it into the APIC branch as
	      well so that there's no interactions.

Signed-off-by: Ingo Molnar <mingo@elte.hu>

107 files changed, 1949 insertions, 617 deletions

diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 9e6e512f0117..17153b54613b 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -29,7 +29,6 @@ unsigned int __machine_arch_type;
 
 static void putstr(const char *ptr);
 
-#include <linux/compiler.h>
 #include <mach/uncompress.h>
 
 #ifdef CONFIG_DEBUG_ICEDCC
diff --git a/arch/arm/common/clkdev.c b/arch/arm/common/clkdev.c
index f37afd9422f3..aae5bc01acc8 100644
--- a/arch/arm/common/clkdev.c
+++ b/arch/arm/common/clkdev.c
@@ -17,6 +17,7 @@
 #include <linux/err.h>
 #include <linux/string.h>
 #include <linux/mutex.h>
+#include <linux/clk.h>
 
 #include <asm/clkdev.h>
 #include <mach/clkdev.h>
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 0a1abb978d7e..af74cc2de8b6 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -629,7 +629,7 @@ CONFIG_SCSI_LOWLEVEL=y
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
 CONFIG_SATA_PMP=y
-# CONFIG_SATA_AHCI is not set
+CONFIG_SATA_AHCI=y
 # CONFIG_SATA_SIL24 is not set
 CONFIG_ATA_SFF=y
 # CONFIG_SATA_SVW is not set
diff --git a/arch/arm/configs/mx27_defconfig b/arch/arm/configs/mx27_defconfig
index 083516cd0d7f..75263a83741c 100644
--- a/arch/arm/configs/mx27_defconfig
+++ b/arch/arm/configs/mx27_defconfig
@@ -1,15 +1,15 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc1
-# Wed Apr  8 10:18:06 2009
+# Linux kernel version: 2.6.31-rc4
+# Fri Jul 24 16:08:06 2009
 #
 CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -18,14 +18,13 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_ARCH_MTD_XIP=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -85,7 +84,12 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+
+#
+# Performance Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
@@ -99,6 +103,12 @@ CONFIG_KPROBES=y
 CONFIG_KRETPROBES=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
 # CONFIG_SLOW_WORK is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
@@ -111,7 +121,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -138,13 +148,14 @@ CONFIG_FREEZER=y
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
 # CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -153,25 +164,25 @@ CONFIG_FREEZER=y
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_LOKI is not set
 # CONFIG_ARCH_MV78XX0 is not set
-CONFIG_ARCH_MXC=y
 # CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_MSM is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_W90X900 is not set
 
 #
 # Freescale MXC Implementations
@@ -188,6 +199,8 @@ CONFIG_MACH_MX27=y
 CONFIG_MACH_MX27ADS=y
 CONFIG_MACH_PCM038=y
 CONFIG_MACH_PCM970_BASEBOARD=y
+CONFIG_MACH_MX27_3DS=y
+CONFIG_MACH_MX27LITE=y
 CONFIG_MXC_IRQ_PRIOR=y
 CONFIG_MXC_PWM=y
 
@@ -213,7 +226,6 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 # CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-# CONFIG_OUTER_CACHE is not set
 CONFIG_COMMON_CLKDEV=y
 
 #
@@ -238,7 +250,6 @@ CONFIG_PREEMPT=y
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 # CONFIG_HIGHMEM is not set
@@ -253,10 +264,11 @@ CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
 CONFIG_HAVE_MLOCK=y
 CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
 
 #
 # Boot options
@@ -361,6 +373,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 
@@ -474,7 +487,16 @@ CONFIG_MTD_PHYSMAP=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_MXC=y
 # CONFIG_MTD_ONENAND is not set
 
 #
@@ -485,7 +507,15 @@ CONFIG_MTD_PHYSMAP=y
 #
 # UBI - Unsorted block images
 #
-# CONFIG_MTD_UBI is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
@@ -494,7 +524,21 @@ CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MISC_DEVICES is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
@@ -508,7 +552,6 @@ CONFIG_HAVE_IDE=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -534,6 +577,8 @@ CONFIG_NET_ETHERNET=y
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
 CONFIG_FEC=y
 # CONFIG_FEC2 is not set
 # CONFIG_NETDEV_1000 is not set
@@ -580,6 +625,11 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
@@ -592,6 +642,7 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
 # CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -644,6 +695,7 @@ CONFIG_I2C_HELPER_AUTO=y
 #
 # I2C system bus drivers (mostly embedded / system-on-chip)
 #
+# CONFIG_I2C_DESIGNWARE is not set
 # CONFIG_I2C_GPIO is not set
 CONFIG_I2C_IMX=y
 # CONFIG_I2C_OCORES is not set
@@ -668,7 +720,6 @@ CONFIG_I2C_IMX=y
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -719,6 +770,7 @@ CONFIG_W1=y
 #
 # CONFIG_W1_MASTER_DS2482 is not set
 CONFIG_W1_MASTER_MXC=y
+# CONFIG_W1_MASTER_DS1WM is not set
 # CONFIG_W1_MASTER_GPIO is not set
 
 #
@@ -753,54 +805,16 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_TPS65010 is not set
 # CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
 # CONFIG_PMIC_DA903X is not set
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_PCF50633 is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=y
-CONFIG_VIDEO_ALLOW_V4L1=y
-CONFIG_VIDEO_V4L1_COMPAT=y
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=y
-
-#
-# Multimedia drivers
-#
-# CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_MEDIA_TUNER_SIMPLE=y
-CONFIG_MEDIA_TUNER_TDA8290=y
-CONFIG_MEDIA_TUNER_TDA9887=y
-CONFIG_MEDIA_TUNER_TEA5761=y
-CONFIG_MEDIA_TUNER_TEA5767=y
-CONFIG_MEDIA_TUNER_MT20XX=y
-CONFIG_MEDIA_TUNER_XC2028=y
-CONFIG_MEDIA_TUNER_XC5000=y
-CONFIG_MEDIA_TUNER_MC44S803=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_V4L1=y
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_CPIA is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-# CONFIG_SOC_CAMERA is not set
-# CONFIG_RADIO_ADAPTERS is not set
-# CONFIG_DAB is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -917,6 +931,7 @@ CONFIG_RTC_DRV_PCF8563=y
 # CONFIG_RTC_DRV_S35390A is not set
 # CONFIG_RTC_DRV_FM3130 is not set
 # CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 
 #
 # SPI RTC drivers
@@ -962,12 +977,15 @@ CONFIG_RTC_DRV_PCF8563=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
@@ -1021,6 +1039,12 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -1119,25 +1143,11 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_NOP_TRACER=y
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
 CONFIG_TRACING=y
 CONFIG_TRACING_SUPPORT=y
-
-#
-# Tracers
-#
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_EVENT_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_KMEMTRACE is not set
-# CONFIG_WORKQUEUE_TRACER is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_FTRACE is not set
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
@@ -1151,16 +1161,104 @@ CONFIG_ARM_UNWIND=y
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
 CONFIG_BINARY_PRINTF=y
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_RATIONAL=y
 CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
+CONFIG_CRC16=y
 # CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
@@ -1168,6 +1266,8 @@ CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig
index 20ada526f6de..a4f9a2a8149c 100644
--- a/arch/arm/configs/mx3_defconfig
+++ b/arch/arm/configs/mx3_defconfig
@@ -1,15 +1,15 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc1
-# Wed Apr  8 11:06:37 2009
+# Linux kernel version: 2.6.31-rc4
+# Tue Jul 28 14:11:34 2009
 #
 CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -18,14 +18,13 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_ARCH_MTD_XIP=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -86,7 +85,12 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+
+#
+# Performance Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
@@ -97,6 +101,11 @@ CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
 # CONFIG_SLOW_WORK is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
@@ -109,7 +118,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -136,13 +145,14 @@ CONFIG_FREEZER=y
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
 # CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
+CONFIG_ARCH_MXC=y
+# CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -151,25 +161,25 @@ CONFIG_FREEZER=y
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_LOKI is not set
 # CONFIG_ARCH_MV78XX0 is not set
-CONFIG_ARCH_MXC=y
 # CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_MSM is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_W90X900 is not set
 
 #
 # Freescale MXC Implementations
@@ -178,6 +188,7 @@ CONFIG_ARCH_MXC=y
 # CONFIG_ARCH_MX2 is not set
 CONFIG_ARCH_MX3=y
 CONFIG_ARCH_MX31=y
+CONFIG_ARCH_MX35=y
 
 #
 # MX3 platforms:
@@ -185,12 +196,19 @@ CONFIG_ARCH_MX31=y
 CONFIG_MACH_MX31ADS=y
 CONFIG_MACH_MX31ADS_WM1133_EV1=y
 CONFIG_MACH_PCM037=y
+CONFIG_MACH_PCM037_EET=y
 CONFIG_MACH_MX31LITE=y
 CONFIG_MACH_MX31_3DS=y
 CONFIG_MACH_MX31MOBOARD=y
+CONFIG_MACH_MX31LILLY=y
 CONFIG_MACH_QONG=y
+CONFIG_MACH_PCM043=y
+CONFIG_MACH_ARMADILLO5X0=y
+CONFIG_MACH_MX35_3DS=y
 CONFIG_MXC_IRQ_PRIOR=y
 CONFIG_MXC_PWM=y
+CONFIG_ARCH_HAS_RNGA=y
+CONFIG_ARCH_MXC_IOMUX_V3=y
 
 #
 # Processor Type
@@ -218,6 +236,7 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_OUTER_CACHE=y
 CONFIG_CACHE_L2X0=y
+# CONFIG_ARM_ERRATA_411920 is not set
 CONFIG_COMMON_CLKDEV=y
 
 #
@@ -242,7 +261,6 @@ CONFIG_PREEMPT=y
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 # CONFIG_HIGHMEM is not set
@@ -257,10 +275,11 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
 CONFIG_HAVE_MLOCK=y
 CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
 
 #
 # Boot options
@@ -362,6 +381,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 
@@ -465,7 +485,16 @@ CONFIG_MTD_PHYSMAP=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_MXC=y
 # CONFIG_MTD_ONENAND is not set
 
 #
@@ -476,10 +505,30 @@ CONFIG_MTD_PHYSMAP=y
 #
 # UBI - Unsorted block images
 #
-# CONFIG_MTD_UBI is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
 # CONFIG_PARPORT is not set
 # CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
@@ -493,7 +542,6 @@ CONFIG_HAVE_IDE=y
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
-CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -528,7 +576,7 @@ CONFIG_MII=y
 # CONFIG_ETHOC is not set
 # CONFIG_SMC911X is not set
 CONFIG_SMSC911X=y
-# CONFIG_DNET is not set
+CONFIG_DNET=y
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
 # CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -537,8 +585,10 @@ CONFIG_SMSC911X=y
 # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
-CONFIG_CS89x0=y
-CONFIG_CS89x0_NONISA_IRQ=y
+# CONFIG_CS89x0 is not set
+# CONFIG_KS8842 is not set
+CONFIG_FEC=y
+# CONFIG_FEC2 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 
@@ -609,6 +659,7 @@ CONFIG_I2C_HELPER_AUTO=y
 #
 # I2C system bus drivers (mostly embedded / system-on-chip)
 #
+# CONFIG_I2C_DESIGNWARE is not set
 # CONFIG_I2C_GPIO is not set
 CONFIG_I2C_IMX=y
 # CONFIG_I2C_OCORES is not set
@@ -633,7 +684,6 @@ CONFIG_I2C_IMX=y
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -669,6 +719,7 @@ CONFIG_W1=y
 #
 # CONFIG_W1_MASTER_DS2482 is not set
 CONFIG_W1_MASTER_MXC=y
+# CONFIG_W1_MASTER_DS1WM is not set
 # CONFIG_W1_MASTER_GPIO is not set
 
 #
@@ -703,6 +754,8 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_TPS65010 is not set
 # CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
 # CONFIG_PMIC_DA903X is not set
 # CONFIG_MFD_WM8400 is not set
@@ -711,10 +764,8 @@ CONFIG_MFD_WM8350_CONFIG_MODE_0=y
 CONFIG_MFD_WM8352_CONFIG_MODE_0=y
 CONFIG_MFD_WM8350_I2C=y
 # CONFIG_MFD_PCF50633 is not set
-
-#
-# Multimedia devices
-#
+# CONFIG_AB3100_CORE is not set
+CONFIG_MEDIA_SUPPORT=y
 
 #
 # Multimedia core support
@@ -758,8 +809,10 @@ CONFIG_SOC_CAMERA_MT9T031=y
 CONFIG_SOC_CAMERA_MT9V022=y
 CONFIG_SOC_CAMERA_TW9910=y
 # CONFIG_SOC_CAMERA_PLATFORM is not set
-# CONFIG_SOC_CAMERA_OV772X is not set
+CONFIG_SOC_CAMERA_OV772X=y
+CONFIG_MX3_VIDEO=y
 CONFIG_VIDEO_MX3=y
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
 # CONFIG_RADIO_ADAPTERS is not set
 # CONFIG_DAB is not set
 
@@ -847,8 +900,11 @@ CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_DEBUG is not set
 # CONFIG_REGULATOR_FIXED_VOLTAGE is not set
 # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
 # CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
 CONFIG_REGULATOR_WM8350=y
+# CONFIG_REGULATOR_LP3971 is not set
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
 
@@ -861,10 +917,12 @@ CONFIG_REGULATOR_WM8350=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -921,6 +979,12 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -937,6 +1001,7 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
 CONFIG_ROOT_NFS=y
 # CONFIG_NFSD is not set
 CONFIG_LOCKD=y
@@ -979,22 +1044,7 @@ CONFIG_FRAME_WARN=1024
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_TRACING_SUPPORT=y
-
-#
-# Tracers
-#
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_EVENT_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_KMEMTRACE is not set
-# CONFIG_WORKQUEUE_TRACER is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_FTRACE is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 CONFIG_ARM_UNWIND=y
@@ -1094,9 +1144,9 @@ CONFIG_CRYPTO_DES=y
 #
 # Compression
 #
-# CONFIG_CRYPTO_DEFLATE is not set
+CONFIG_CRYPTO_DEFLATE=y
 # CONFIG_CRYPTO_ZLIB is not set
-# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_LZO=y
 
 #
 # Random Number Generation
@@ -1109,9 +1159,10 @@ CONFIG_CRYPTO_HW=y
 # Library routines
 #
 CONFIG_BITREVERSE=y
+CONFIG_RATIONAL=y
 CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
+CONFIG_CRC16=y
 # CONFIG_CRC_T10DIF is not set
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
@@ -1119,6 +1170,8 @@ CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap3_evm_defconfig b/arch/arm/configs/omap3_evm_defconfig
index 28be17fbc157..d5ff4776cd0a 100644
--- a/arch/arm/configs/omap3_evm_defconfig
+++ b/arch/arm/configs/omap3_evm_defconfig
@@ -1107,7 +1107,7 @@ CONFIG_USB_ZERO=m
 CONFIG_USB_OTG_UTILS=y
 # CONFIG_USB_GPIO_VBUS is not set
 # CONFIG_ISP1301_OMAP is not set
-CONFIG_TWL4030_USB=y
+# CONFIG_TWL4030_USB is not set
 # CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig
index eb2cb31825c0..f238df66efd4 100644
--- a/arch/arm/configs/rx51_defconfig
+++ b/arch/arm/configs/rx51_defconfig
@@ -282,7 +282,7 @@ CONFIG_ALIGNMENT_TRAP=y
 #
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0"
+CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0 console=ttyS2,115200n8"
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
 
@@ -1354,7 +1354,7 @@ CONFIG_USB_OTG_UTILS=y
 # CONFIG_USB_GPIO_VBUS is not set
 # CONFIG_ISP1301_OMAP is not set
 CONFIG_TWL4030_USB=y
-CONFIG_MMC=m
+CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
@@ -1449,7 +1449,8 @@ CONFIG_RTC_DRV_TWL4030=m
 # on-CPU RTC drivers
 #
 # CONFIG_DMADEVICES is not set
-# CONFIG_REGULATOR is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_TWL4030=y
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
 
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 4762d9001298..7d61ae6e75da 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc1
-# Thu Jul  2 00:16:59 2009
+# Linux kernel version: 2.6.31-rc3
+# Thu Jul 16 23:36:10 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -9,7 +9,6 @@ CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
-CONFIG_HAVE_TCM=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -113,7 +112,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-CONFIG_LBDAF=y
+# CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -542,13 +541,14 @@ CONFIG_INPUT_EVDEV=y
 #
 CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
 # CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_LM8323 is not set
-# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
@@ -911,7 +911,6 @@ CONFIG_REGULATOR=y
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
 CONFIG_FILE_LOCKING=y
@@ -1122,7 +1121,6 @@ CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC32 is not set
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
-CONFIG_GENERIC_ALLOCATOR=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 9e07fe507029..9ed2377fe8e5 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -159,8 +159,6 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
 
 #else /* ARM_ARCH_6 */
 
-#include <asm/system.h>
-
 #ifdef CONFIG_SMP
 #error SMP not supported on pre-ARMv6 CPUs
 #endif
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index ee1304f22f94..5ccce0a9b03c 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -201,7 +201,8 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn }
 struct membank {
         unsigned long start;
         unsigned long size;
-        int           node;
+        unsigned short node;
+        unsigned short highmem;
 };
 
 struct meminfo {
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index 321c83e43a1e..f41a6f57cd12 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -102,8 +102,8 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
 }
 
 #define tlb_remove_page(tlb,page)       free_page_and_swap_cache(page)
-#define pte_free_tlb(tlb, ptep)         pte_free((tlb)->mm, ptep)
-#define pmd_free_tlb(tlb, pmdp)         pmd_free((tlb)->mm, pmdp)
+#define pte_free_tlb(tlb, ptep, addr)   pte_free((tlb)->mm, ptep)
+#define pmd_free_tlb(tlb, pmdp, addr)   pmd_free((tlb)->mm, pmdp)
 
 #define tlb_migrate_finish(mm)          do { } while (0)
 
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 366e5097a41a..8c3de1a350b5 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -148,7 +148,7 @@ trace:
         sub r0, r0, #MCOUNT_INSN_SIZE
         mov lr, pc
         mov pc, r2
-        mov lr, r1                              @ restore lr
+        ldr lr, [fp, #-4]                       @ restore lr
         ldmia sp!, {r0-r3, pc}
 
 #endif /* CONFIG_DYNAMIC_FTRACE */
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 93bb4247b7ed..f6bc5d442782 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -133,7 +133,7 @@ sys_sigaction(int sig, const struct old_sigaction __user *act,
 }
 
 #ifdef CONFIG_CRUNCH
-static int preserve_crunch_context(struct crunch_sigframe *frame)
+static int preserve_crunch_context(struct crunch_sigframe __user *frame)
 {
         char kbuf[sizeof(*frame) + 8];
         struct crunch_sigframe *kframe;
@@ -146,7 +146,7 @@ static int preserve_crunch_context(struct crunch_sigframe *frame)
         return __copy_to_user(frame, kframe, sizeof(*frame));
 }
 
-static int restore_crunch_context(struct crunch_sigframe *frame)
+static int restore_crunch_context(struct crunch_sigframe __user *frame)
 {
         char kbuf[sizeof(*frame) + 8];
         struct crunch_sigframe *kframe;
diff --git a/arch/arm/mach-at91/include/mach/at_hdmac.h b/arch/arm/mach-at91/include/mach/at_hdmac.h
new file mode 100644
index 000000000000..187cb58345c0
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at_hdmac.h
@@ -0,0 +1,102 @@
+/*
+ * Header file for the Atmel AHB DMA Controller driver
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT_HDMAC_H
+#define AT_HDMAC_H
+
+#include <linux/dmaengine.h>
+
+/**
+ * struct at_dma_platform_data - Controller configuration parameters
+ * @nr_channels: Number of channels supported by hardware (max 8)
+ * @cap_mask: dma_capability flags supported by the platform
+ */
+struct at_dma_platform_data {
+        unsigned int    nr_channels;
+        dma_cap_mask_t  cap_mask;
+};
+
+/**
+ * enum at_dma_slave_width - DMA slave register access width.
+ * @AT_DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
+ * @AT_DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
+ * @AT_DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
+ */
+enum at_dma_slave_width {
+        AT_DMA_SLAVE_WIDTH_8BIT = 0,
+        AT_DMA_SLAVE_WIDTH_16BIT,
+        AT_DMA_SLAVE_WIDTH_32BIT,
+};
+
+/**
+ * struct at_dma_slave - Controller-specific information about a slave
+ * @dma_dev: required DMA master device
+ * @tx_reg: physical address of data register used for
+ *      memory-to-peripheral transfers
+ * @rx_reg: physical address of data register used for
+ *      peripheral-to-memory transfers
+ * @reg_width: peripheral register width
+ * @cfg: Platform-specific initializer for the CFG register
+ * @ctrla: Platform-specific initializer for the CTRLA register
+ */
+struct at_dma_slave {
+        struct device           *dma_dev;
+        dma_addr_t              tx_reg;
+        dma_addr_t              rx_reg;
+        enum at_dma_slave_width reg_width;
+        u32                     cfg;
+        u32                     ctrla;
+};
+
+
+/* Platform-configurable bits in CFG */
+#define ATC_SRC_PER(h)          (0xFU & (h))    /* Channel src rq associated with periph handshaking ifc h */
+#define ATC_DST_PER(h)          ((0xFU & (h)) <<  4)    /* Channel dst rq associated with periph handshaking ifc h */
+#define ATC_SRC_REP             (0x1 <<  8)     /* Source Replay Mod */
+#define ATC_SRC_H2SEL           (0x1 <<  9)     /* Source Handshaking Mod */
+#define         ATC_SRC_H2SEL_SW        (0x0 <<  9)
+#define         ATC_SRC_H2SEL_HW        (0x1 <<  9)
+#define ATC_DST_REP             (0x1 << 12)     /* Destination Replay Mod */
+#define ATC_DST_H2SEL           (0x1 << 13)     /* Destination Handshaking Mod */
+#define         ATC_DST_H2SEL_SW        (0x0 << 13)
+#define         ATC_DST_H2SEL_HW        (0x1 << 13)
+#define ATC_SOD                 (0x1 << 16)     /* Stop On Done */
+#define ATC_LOCK_IF             (0x1 << 20)     /* Interface Lock */
+#define ATC_LOCK_B              (0x1 << 21)     /* AHB Bus Lock */
+#define ATC_LOCK_IF_L           (0x1 << 22)     /* Master Interface Arbiter Lock */
+#define         ATC_LOCK_IF_L_CHUNK     (0x0 << 22)
+#define         ATC_LOCK_IF_L_BUFFER    (0x1 << 22)
+#define ATC_AHB_PROT_MASK       (0x7 << 24)     /* AHB Protection */
+#define ATC_FIFOCFG_MASK        (0x3 << 28)     /* FIFO Request Configuration */
+#define         ATC_FIFOCFG_LARGESTBURST        (0x0 << 28)
+#define         ATC_FIFOCFG_HALFFIFO            (0x1 << 28)
+#define         ATC_FIFOCFG_ENOUGHSPACE         (0x2 << 28)
+
+/* Platform-configurable bits in CTRLA */
+#define ATC_SCSIZE_MASK         (0x7 << 16)     /* Source Chunk Transfer Size */
+#define         ATC_SCSIZE_1            (0x0 << 16)
+#define         ATC_SCSIZE_4            (0x1 << 16)
+#define         ATC_SCSIZE_8            (0x2 << 16)
+#define         ATC_SCSIZE_16           (0x3 << 16)
+#define         ATC_SCSIZE_32           (0x4 << 16)
+#define         ATC_SCSIZE_64           (0x5 << 16)
+#define         ATC_SCSIZE_128          (0x6 << 16)
+#define         ATC_SCSIZE_256          (0x7 << 16)
+#define ATC_DCSIZE_MASK         (0x7 << 20)     /* Destination Chunk Transfer Size */
+#define         ATC_DCSIZE_1            (0x0 << 20)
+#define         ATC_DCSIZE_4            (0x1 << 20)
+#define         ATC_DCSIZE_8            (0x2 << 20)
+#define         ATC_DCSIZE_16           (0x3 << 20)
+#define         ATC_DCSIZE_32           (0x4 << 20)
+#define         ATC_DCSIZE_64           (0x5 << 20)
+#define         ATC_DCSIZE_128          (0x6 << 20)
+#define         ATC_DCSIZE_256          (0x7 << 20)
+
+#endif /* AT_HDMAC_H */
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 5ac2f565d860..d6ab64ccd496 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -37,7 +37,6 @@
 #include <mach/serial.h>
 #include <mach/nand.h>
 #include <mach/mmc.h>
-#include <mach/common.h>
 
 #define DAVINCI_ASYNC_EMIF_CONTROL_BASE         0x01e10000
 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE        0x02000000
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 28c9008df4f4..84ad5d161a87 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -36,7 +36,6 @@
 #include <mach/serial.h>
 #include <mach/nand.h>
 #include <mach/mmc.h>
-#include <mach/common.h>
 
 #define DAVINCI_ASYNC_EMIF_CONTROL_BASE         0x01e10000
 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE        0x02000000
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index d9d40450bdc5..56c8cd01de9a 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -45,7 +45,6 @@
 #include <mach/nand.h>
 #include <mach/mmc.h>
 #include <mach/emac.h>
-#include <mach/common.h>
 
 #define DM644X_EVM_PHY_MASK             (0x2)
 #define DM644X_EVM_MDIO_FREQUENCY       (2200000) /* PHY bus frequency */
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index e17de6352624..8657e72debc1 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -47,7 +47,6 @@
 #include <mach/i2c.h>
 #include <mach/mmc.h>
 #include <mach/emac.h>
-#include <mach/common.h>
 
 #define DM646X_EVM_PHY_MASK             (0x2)
 #define DM646X_EVM_MDIO_FREQUENCY       (2200000) /* PHY bus frequency */
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 748a8e48541e..7acdfd8ac071 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -52,7 +52,6 @@
 #include <mach/serial.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
-#include <mach/common.h>
 
 #define SFFSDR_PHY_MASK         (0x2)
 #define SFFSDR_MDIO_FREQUENCY   (2200000) /* PHY bus frequency */
diff --git a/arch/arm/mach-ep93xx/dma-m2p.c b/arch/arm/mach-ep93xx/dma-m2p.c
index a2df5bb7dff0..dbcac9c40a28 100644
--- a/arch/arm/mach-ep93xx/dma-m2p.c
+++ b/arch/arm/mach-ep93xx/dma-m2p.c
@@ -33,6 +33,7 @@
 #include <linux/err.h>
 #include <linux/interrupt.h>
 #include <linux/module.h>
+#include <linux/io.h>
 
 #include <mach/dma.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
index 34ddec081c40..411734422c1d 100644
--- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h
+++ b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
@@ -41,9 +41,6 @@
 #define TS72XX_OPTIONS2_TS9420_BOOT     0x02
 
 
-#define TS72XX_NOR_PHYS_BASE            0x60000000
-#define TS72XX_NOR2_PHYS_BASE           0x62000000
-
 #define TS72XX_NAND1_DATA_PHYS_BASE     0x60000000
 #define TS72XX_NAND2_DATA_PHYS_BASE     0x70000000
 #define TS72XX_NAND_DATA_VIRT_BASE      0xfebfc000
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 7ee024d34829..aaf1371412af 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -112,13 +112,16 @@ static void __init ts72xx_map_io(void)
         }
 }
 
+/*************************************************************************
+ * NOR flash (TS-7200 only)
+ *************************************************************************/
 static struct physmap_flash_data ts72xx_flash_data = {
-        .width          = 1,
+        .width          = 2,
 };
 
 static struct resource ts72xx_flash_resource = {
-        .start          = TS72XX_NOR_PHYS_BASE,
-        .end            = TS72XX_NOR_PHYS_BASE + SZ_16M - 1,
+        .start          = EP93XX_CS6_PHYS_BASE,
+        .end            = EP93XX_CS6_PHYS_BASE + SZ_16M - 1,
         .flags          = IORESOURCE_MEM,
 };
 
@@ -132,6 +135,12 @@ static struct platform_device ts72xx_flash = {
         .resource       = &ts72xx_flash_resource,
 };
 
+static void __init ts72xx_register_flash(void)
+{
+        if (board_is_ts7200())
+                platform_device_register(&ts72xx_flash);
+}
+
 static unsigned char ts72xx_rtc_readbyte(unsigned long addr)
 {
         __raw_writeb(addr, TS72XX_RTC_INDEX_VIRT_BASE);
@@ -165,8 +174,7 @@ static struct ep93xx_eth_data ts72xx_eth_data = {
 static void __init ts72xx_init_machine(void)
 {
         ep93xx_init_devices();
-        if (board_is_ts7200())
-                platform_device_register(&ts72xx_flash);
+        ts72xx_register_flash();
         platform_device_register(&ts72xx_rtc_device);
 
         ep93xx_register_eth(&ts72xx_eth_data, 1);
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index ce63048d45eb..8a947d42a6f1 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -17,7 +17,7 @@
 
 #include <mach/hardware.h>
 
-#define IO_SPACE_LIMIT 0xffff0000
+#define IO_SPACE_LIMIT 0x0000ffff
 
 extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
 extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index e021a80c2caf..bc74278ed311 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -289,7 +289,7 @@
 
 #define MPP48_GPIO              MPP( 48, 0x0, 1, 1, 0,   0,   0,   1    )
 #define MPP48_TSMP12            MPP( 48, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TDM_DTX           MPP( 48. 0x2, 0, 1, 0,   0,   0,   1    )
+#define MPP48_TDM_DTX           MPP( 48, 0x2, 0, 1, 0,   0,   0,   1    )
 
 #define MPP49_GPIO              MPP( 49, 0x0, 1, 1, 0,   0,   0,   1    )
 #define MPP49_TSMP9             MPP( 49, 0x1, 1, 1, 0,   0,   0,   1    )
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 01aa213c0a6f..ec1a64f263d2 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -206,6 +206,15 @@ static void __init qnap_ts219_init(void)
 
 }
 
+static int __init ts219_pci_init(void)
+{
+   if (machine_is_ts219())
+           kirkwood_pcie_init();
+
+   return 0;
+}
+subsys_initcall(ts219_pci_init);
+
 MACHINE_START(TS219, "QNAP TS-119/TS-219")
         /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
         .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
diff --git a/arch/arm/mach-ks8695/include/mach/hardware.h b/arch/arm/mach-ks8695/include/mach/hardware.h
index 1d640d075b7e..e0f911d9e021 100644
--- a/arch/arm/mach-ks8695/include/mach/hardware.h
+++ b/arch/arm/mach-ks8695/include/mach/hardware.h
@@ -17,6 +17,11 @@
 #include <asm/sizes.h>
 
 /*
+ * Clocks are derived from MCLK, which is 25Mhz
+ */
+#define KS8695_CLOCK_RATE       25000000
+
+/*
  * Physical RAM address.
  */
 #define KS8695_SDRAM_PA         0x00000000
diff --git a/arch/arm/mach-ks8695/include/mach/timex.h b/arch/arm/mach-ks8695/include/mach/timex.h
index 4682e350369b..10f716371bd3 100644
--- a/arch/arm/mach-ks8695/include/mach/timex.h
+++ b/arch/arm/mach-ks8695/include/mach/timex.h
@@ -14,7 +14,8 @@
 #ifndef __ASM_ARCH_TIMEX_H
 #define __ASM_ARCH_TIMEX_H
 
-/* timers are derived from MCLK, which is 25MHz */
-#define CLOCK_TICK_RATE 25000000
+#include <mach/hardware.h>
+
+#define CLOCK_TICK_RATE         KS8695_CLOCK_RATE
 
 #endif
diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index f5ebcc0fcab9..78499667eb7b 100644
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -245,6 +245,9 @@ static int ks8695_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs
 
 static void __init ks8695_pci_preinit(void)
 {
+        /* make software reset to avoid freeze if PCI bus was messed up */
+        __raw_writel(0x80000000, KS8695_PCI_VA + KS8695_PBCS);
+
         /* stage 1 initialization, subid, subdevice = 0x0001 */
         __raw_writel(0x00010001, KS8695_PCI_VA + KS8695_CRCSID);
 
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 17a21a291e2f..851f2458bf65 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -36,6 +36,14 @@ config MACH_PCM037
           Include support for Phytec pcm037 platform. This includes
           specific configurations for the board and its peripherals.
 
+config MACH_PCM037_EET
+        bool "Support pcm037 EET board extensions"
+        depends on MACH_PCM037
+        help
+          Add support for PCM037 EET baseboard extensions. If you are using the
+          OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
+          command-line parameter.
+
 config MACH_MX31LITE
         bool "Support MX31 LITEKIT (LogicPD)"
         select ARCH_MX31
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 0322696bd11a..6b9775471be6 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_MACH_MX31ADS)	+= mx31ads.o
 obj-$(CONFIG_MACH_MX31LILLY)    += mx31lilly.o mx31lilly-db.o
 obj-$(CONFIG_MACH_MX31LITE)     += mx31lite.o
 obj-$(CONFIG_MACH_PCM037)       += pcm037.o
+obj-$(CONFIG_MACH_PCM037_EET)   += pcm037_eet.o
 obj-$(CONFIG_MACH_MX31_3DS)     += mx31pdk.o
 obj-$(CONFIG_MACH_MX31MOBOARD)  += mx31moboard.o mx31moboard-devboard.o \
                                    mx31moboard-marxbot.o
diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/armadillo5x0.c
index 541181090b37..ee331fd6b1bd 100644
--- a/arch/arm/mach-mx3/armadillo5x0.c
+++ b/arch/arm/mach-mx3/armadillo5x0.c
@@ -31,6 +31,8 @@
 #include <linux/smsc911x.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -46,8 +48,10 @@
 #include <mach/mmc.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
+#include <mach/mxc_nand.h>
 
 #include "devices.h"
+#include "crm_regs.h"
 
 static int armadillo5x0_pins[] = {
         /* UART1 */
@@ -93,7 +97,56 @@ static int armadillo5x0_pins[] = {
         MX31_PIN_FPSHIFT__FPSHIFT,
         MX31_PIN_DRDY0__DRDY0,
         IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/
+};
 
+/*
+ * NAND Flash
+ */
+static struct mxc_nand_platform_data armadillo5x0_nand_flash_pdata = {
+        .width          = 1,
+        .hw_ecc         = 1,
+};
+
+/*
+ * MTD NOR Flash
+ */
+static struct mtd_partition armadillo5x0_nor_flash_partitions[] = {
+        {
+                .name           = "nor.bootloader",
+                .offset         = 0x00000000,
+                .size           = 4*32*1024,
+        }, {
+                .name           = "nor.kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 16*128*1024,
+        }, {
+                .name           = "nor.userland",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 110*128*1024,
+        }, {
+                .name           = "nor.config",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 1*128*1024,
+        },
+};
+
+static struct physmap_flash_data armadillo5x0_nor_flash_pdata = {
+        .width          = 2,
+        .parts          = armadillo5x0_nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(armadillo5x0_nor_flash_partitions),
+};
+
+static struct resource armadillo5x0_nor_flash_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = CS0_BASE_ADDR,
+        .end            = CS0_BASE_ADDR + SZ_64M - 1,
+};
+
+static struct platform_device armadillo5x0_nor_flash = {
+        .name                   = "physmap-flash",
+        .id                     = -1,
+        .num_resources          = 1,
+        .resource               = &armadillo5x0_nor_flash_resource,
 };
 
 /*
@@ -272,6 +325,16 @@ static void __init armadillo5x0_init(void)
         /* Register FB */
         mxc_register_device(&mx3_ipu, &mx3_ipu_data);
         mxc_register_device(&mx3_fb, &mx3fb_pdata);
+
+        /* Register NOR Flash */
+        mxc_register_device(&armadillo5x0_nor_flash,
+                            &armadillo5x0_nor_flash_pdata);
+
+        /* Register NAND Flash */
+        mxc_register_device(&mxc_nand_device, &armadillo5x0_nand_flash_pdata);
+
+        /* set NAND page size to 2k if not configured via boot mode pins */
+        __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
 }
 
 static void __init armadillo5x0_timer_init(void)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index d927eddcad46..9e87e08fb121 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -22,7 +22,6 @@
 #include <linux/platform_device.h>
 #include <linux/serial.h>
 #include <linux/gpio.h>
-#include <linux/dma-mapping.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/common.h>
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 4704405165a1..b48581e7dedd 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -63,7 +63,7 @@ static struct imxuart_platform_data uart_pdata = {
 
 static int devboard_sdhc2_get_ro(struct device *dev)
 {
-        return gpio_get_value(SDHC2_WP);
+        return !gpio_get_value(SDHC2_WP);
 }
 
 static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 641c3d6153ae..901fb0166c0e 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -67,7 +67,7 @@ static unsigned int marxbot_pins[] = {
 
 static int marxbot_sdhc2_get_ro(struct device *dev)
 {
-        return gpio_get_value(SDHC2_WP);
+        return !gpio_get_value(SDHC2_WP);
 }
 
 static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c
index a17f2e411609..2a2da4739ecf 100644
--- a/arch/arm/mach-mx3/mx31moboard.c
+++ b/arch/arm/mach-mx3/mx31moboard.c
@@ -94,7 +94,7 @@ static struct imxi2c_platform_data moboard_i2c1_pdata = {
 
 static int moboard_sdhc1_get_ro(struct device *dev)
 {
-        return gpio_get_value(SDHC1_WP);
+        return !gpio_get_value(SDHC1_WP);
 }
 
 static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
index c6f61a1f06c8..840cfda341d0 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -18,7 +18,7 @@
 
 #include <linux/types.h>
 #include <linux/init.h>
-
+#include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/plat-ram.h>
@@ -33,29 +33,67 @@
 #include <linux/irq.h>
 #include <linux/fsl_devices.h>
 
-#include <mach/hardware.h>
+#include <media/soc_camera.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
+#include <mach/board-pcm037.h>
 #include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/i2c.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ipu.h>
-#include <mach/board-pcm037.h>
+#include <mach/mmc.h>
+#include <mach/mx3_camera.h>
 #include <mach/mx3fb.h>
 #include <mach/mxc_nand.h>
-#include <mach/mmc.h>
-#ifdef CONFIG_I2C_IMX
-#include <mach/i2c.h>
-#endif
 
 #include "devices.h"
+#include "pcm037.h"
+
+static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
+
+static int __init pcm037_variant_setup(char *str)
+{
+        if (!strcmp("eet", str))
+                pcm037_instance = PCM037_EET;
+        else if (strcmp("pcm970", str))
+                pr_warning("Unknown pcm037 baseboard variant %s\n", str);
+
+        return 1;
+}
+
+/* Supported values: "pcm970" (default) and "eet" */
+__setup("pcm037_variant=", pcm037_variant_setup);
+
+enum pcm037_board_variant pcm037_variant(void)
+{
+        return pcm037_instance;
+}
+
+/* UART1 with RTS/CTS handshake signals */
+static unsigned int pcm037_uart1_handshake_pins[] = {
+        MX31_PIN_CTS1__CTS1,
+        MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1,
+        MX31_PIN_RXD1__RXD1,
+};
+
+/* UART1 without RTS/CTS handshake signals */
+static unsigned int pcm037_uart1_pins[] = {
+        MX31_PIN_TXD1__TXD1,
+        MX31_PIN_RXD1__RXD1,
+};
 
 static unsigned int pcm037_pins[] = {
         /* I2C */
         MX31_PIN_CSPI2_MOSI__SCL,
         MX31_PIN_CSPI2_MISO__SDA,
+        MX31_PIN_CSPI2_SS2__I2C3_SDA,
+        MX31_PIN_CSPI2_SCLK__I2C3_SCL,
         /* SDHC1 */
         MX31_PIN_SD1_DATA3__SD1_DATA3,
         MX31_PIN_SD1_DATA2__SD1_DATA2,
@@ -73,11 +111,6 @@ static unsigned int pcm037_pins[] = {
         MX31_PIN_CSPI1_SS0__SS0,
         MX31_PIN_CSPI1_SS1__SS1,
         MX31_PIN_CSPI1_SS2__SS2,
-        /* UART1 */
-        MX31_PIN_CTS1__CTS1,
-        MX31_PIN_RTS1__RTS1,
-        MX31_PIN_TXD1__TXD1,
-        MX31_PIN_RXD1__RXD1,
         /* UART2 */
         MX31_PIN_TXD2__TXD2,
         MX31_PIN_RXD2__RXD2,
@@ -120,6 +153,22 @@ static unsigned int pcm037_pins[] = {
         MX31_PIN_D3_SPL__D3_SPL,
         MX31_PIN_D3_CLS__D3_CLS,
         MX31_PIN_LCS0__GPI03_23,
+        /* CSI */
+        IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
+        MX31_PIN_CSI_D6__CSI_D6,
+        MX31_PIN_CSI_D7__CSI_D7,
+        MX31_PIN_CSI_D8__CSI_D8,
+        MX31_PIN_CSI_D9__CSI_D9,
+        MX31_PIN_CSI_D10__CSI_D10,
+        MX31_PIN_CSI_D11__CSI_D11,
+        MX31_PIN_CSI_D12__CSI_D12,
+        MX31_PIN_CSI_D13__CSI_D13,
+        MX31_PIN_CSI_D14__CSI_D14,
+        MX31_PIN_CSI_D15__CSI_D15,
+        MX31_PIN_CSI_HSYNC__CSI_HSYNC,
+        MX31_PIN_CSI_MCLK__CSI_MCLK,
+        MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
+        MX31_PIN_CSI_VSYNC__CSI_VSYNC,
 };
 
 static struct physmap_flash_data pcm037_flash_data = {
@@ -250,19 +299,43 @@ static struct mxc_nand_platform_data pcm037_nand_board_info = {
         .hw_ecc = 1,
 };
 
-#ifdef CONFIG_I2C_IMX
 static struct imxi2c_platform_data pcm037_i2c_1_data = {
         .bitrate = 100000,
 };
 
+static struct imxi2c_platform_data pcm037_i2c_2_data = {
+        .bitrate = 20000,
+};
+
 static struct at24_platform_data board_eeprom = {
         .byte_len = 4096,
         .page_size = 32,
         .flags = AT24_FLAG_ADDR16,
 };
 
+static int pcm037_camera_power(struct device *dev, int on)
+{
+        /* disable or enable the camera in X7 or X8 PCM970 connector */
+        gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
+        return 0;
+}
+
+static struct i2c_board_info pcm037_i2c_2_devices[] = {
+        {
+                I2C_BOARD_INFO("mt9t031", 0x5d),
+        },
+};
+
+static struct soc_camera_link iclink = {
+        .bus_id         = 0,            /* Must match with the camera ID */
+        .power          = pcm037_camera_power,
+        .board_info     = &pcm037_i2c_2_devices[0],
+        .i2c_adapter_id = 2,
+        .module_name    = "mt9t031",
+};
+
 static struct i2c_board_info pcm037_i2c_devices[] = {
-       {
+        {
                 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
                 .platform_data = &board_eeprom,
         }, {
@@ -270,7 +343,14 @@ static struct i2c_board_info pcm037_i2c_devices[] = {
                 .type = "pcf8563",
         }
 };
-#endif
+
+static struct platform_device pcm037_camera = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &iclink,
+        },
+};
 
 /* Not connected by default */
 #ifdef PCM970_SDHC_RW_SWITCH
@@ -334,9 +414,41 @@ static struct imxmmc_platform_data sdhc_pdata = {
         .exit = pcm970_sdhc1_exit,
 };
 
+struct mx3_camera_pdata camera_pdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .flags          = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
+        .mclk_10khz     = 2000,
+};
+
+static int __init pcm037_camera_alloc_dma(const size_t buf_size)
+{
+        dma_addr_t dma_handle;
+        void *buf;
+        int dma;
+
+        if (buf_size < 2 * 1024 * 1024)
+                return -EINVAL;
+
+        buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
+        if (!buf) {
+                pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
+                return -ENOMEM;
+        }
+
+        memset(buf, 0, buf_size);
+
+        dma = dma_declare_coherent_memory(&mx3_camera.dev,
+                                        dma_handle, dma_handle, buf_size,
+                                        DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+
+        /* The way we call dma_declare_coherent_memory only a malloc can fail */
+        return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
+}
+
 static struct platform_device *devices[] __initdata = {
         &pcm037_flash,
         &pcm037_sram_device,
+        &pcm037_camera,
 };
 
 static struct ipu_platform_data mx3_ipu_data = {
@@ -377,6 +489,22 @@ static const struct fb_videomode fb_modedb[] = {
                 .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
                 .vmode          = FB_VMODE_NONINTERLACED,
                 .flag           = 0,
+        }, {
+                /* 240x320 @ 60 Hz */
+                .name           = "CMEL-OLED",
+                .refresh        = 60,
+                .xres           = 240,
+                .yres           = 320,
+                .pixclock       = 185925,
+                .left_margin    = 9,
+                .right_margin   = 16,
+                .upper_margin   = 7,
+                .lower_margin   = 9,
+                .hsync_len      = 1,
+                .vsync_len      = 1,
+                .sync           = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
         },
 };
 
@@ -397,6 +525,14 @@ static void __init mxc_board_init(void)
         mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
                         "pcm037");
 
+        if (pcm037_variant() == PCM037_EET)
+                mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
+                        ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
+        else
+                mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
+                        ARRAY_SIZE(pcm037_uart1_handshake_pins),
+                        "pcm037_uart1");
+
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         mxc_register_device(&mxc_uart_device0, &uart_pdata);
@@ -415,18 +551,30 @@ static void __init mxc_board_init(void)
         }
 
 
-#ifdef CONFIG_I2C_IMX
+        /* I2C adapters and devices */
         i2c_register_board_info(1, pcm037_i2c_devices,
                         ARRAY_SIZE(pcm037_i2c_devices));
 
         mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data);
-#endif
+        mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data);
+
         mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
         mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
         mxc_register_device(&mx3_ipu, &mx3_ipu_data);
         mxc_register_device(&mx3_fb, &mx3fb_pdata);
         if (!gpio_usbotg_hs_activate())
                 mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+
+        /* CSI */
+        /* Camera power: default - off */
+        ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
+        if (!ret)
+                gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
+        else
+                iclink.power = NULL;
+
+        if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
+                mxc_register_device(&mx3_camera, &camera_pdata);
 }
 
 static void __init pcm037_timer_init(void)
@@ -448,4 +596,3 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
         .init_machine   = mxc_board_init,
         .timer          = &pcm037_timer,
 MACHINE_END
-
diff --git a/arch/arm/mach-mx3/pcm037.h b/arch/arm/mach-mx3/pcm037.h
new file mode 100644
index 000000000000..d6929721a5fd
--- /dev/null
+++ b/arch/arm/mach-mx3/pcm037.h
@@ -0,0 +1,11 @@
+#ifndef __PCM037_H__
+#define __PCM037_H__
+
+enum pcm037_board_variant {
+        PCM037_PCM970,
+        PCM037_EET,
+};
+
+extern enum pcm037_board_variant pcm037_variant(void);
+
+#endif
diff --git a/arch/arm/mach-mx3/pcm037_eet.c b/arch/arm/mach-mx3/pcm037_eet.c
new file mode 100644
index 000000000000..8d386000fc40
--- /dev/null
+++ b/arch/arm/mach-mx3/pcm037_eet.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+
+#include <mach/common.h>
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+#include <mach/spi.h>
+#endif
+#include <mach/iomux-mx3.h>
+
+#include <asm/mach-types.h>
+
+#include "pcm037.h"
+#include "devices.h"
+
+static unsigned int pcm037_eet_pins[] = {
+        /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
+        IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_GPIO),
+        /* GPIO keys */
+        IOMUX_MODE(MX31_PIN_GPIO1_0,    IOMUX_CONFIG_GPIO), /* 0 */
+        IOMUX_MODE(MX31_PIN_GPIO1_1,    IOMUX_CONFIG_GPIO), /* 1 */
+        IOMUX_MODE(MX31_PIN_GPIO1_2,    IOMUX_CONFIG_GPIO), /* 2 */
+        IOMUX_MODE(MX31_PIN_GPIO1_3,    IOMUX_CONFIG_GPIO), /* 3 */
+        IOMUX_MODE(MX31_PIN_SVEN0,      IOMUX_CONFIG_GPIO), /* 32 */
+        IOMUX_MODE(MX31_PIN_STX0,       IOMUX_CONFIG_GPIO), /* 33 */
+        IOMUX_MODE(MX31_PIN_SRX0,       IOMUX_CONFIG_GPIO), /* 34 */
+        IOMUX_MODE(MX31_PIN_SIMPD0,     IOMUX_CONFIG_GPIO), /* 35 */
+        IOMUX_MODE(MX31_PIN_RTS1,       IOMUX_CONFIG_GPIO), /* 38 */
+        IOMUX_MODE(MX31_PIN_CTS1,       IOMUX_CONFIG_GPIO), /* 39 */
+        IOMUX_MODE(MX31_PIN_KEY_ROW4,   IOMUX_CONFIG_GPIO), /* 50 */
+        IOMUX_MODE(MX31_PIN_KEY_ROW5,   IOMUX_CONFIG_GPIO), /* 51 */
+        IOMUX_MODE(MX31_PIN_KEY_ROW6,   IOMUX_CONFIG_GPIO), /* 52 */
+        IOMUX_MODE(MX31_PIN_KEY_ROW7,   IOMUX_CONFIG_GPIO), /* 53 */
+
+        /* LEDs */
+        IOMUX_MODE(MX31_PIN_DTR_DTE1,   IOMUX_CONFIG_GPIO), /* 44 */
+        IOMUX_MODE(MX31_PIN_DSR_DTE1,   IOMUX_CONFIG_GPIO), /* 45 */
+        IOMUX_MODE(MX31_PIN_KEY_COL5,   IOMUX_CONFIG_GPIO), /* 55 */
+        IOMUX_MODE(MX31_PIN_KEY_COL6,   IOMUX_CONFIG_GPIO), /* 56 */
+};
+
+/* SPI */
+static struct spi_board_info pcm037_spi_dev[] = {
+        {
+                .modalias       = "dac124s085",
+                .max_speed_hz   = 400000,
+                .bus_num        = 0,
+                .chip_select    = 0,            /* Index in pcm037_spi1_cs[] */
+                .mode           = SPI_CPHA,
+        },
+};
+
+/* Platform Data for MXC CSPI */
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)};
+
+struct spi_imx_master pcm037_spi1_master = {
+        .chipselect = pcm037_spi1_cs,
+        .num_chipselect = ARRAY_SIZE(pcm037_spi1_cs),
+};
+#endif
+
+/* GPIO-keys input device */
+static struct gpio_keys_button pcm037_gpio_keys[] = {
+        {
+                .type   = EV_KEY,
+                .code   = KEY_L,
+                .gpio   = 0,
+                .desc   = "Wheel Manual",
+                .wakeup = 0,
+        }, {
+                .type   = EV_KEY,
+                .code   = KEY_A,
+                .gpio   = 1,
+                .desc   = "Wheel AF",
+                .wakeup = 0,
+        }, {
+                .type   = EV_KEY,
+                .code   = KEY_V,
+                .gpio   = 2,
+                .desc   = "Wheel View",
+                .wakeup = 0,
+        }, {
+                .type   = EV_KEY,
+                .code   = KEY_M,
+                .gpio   = 3,
+                .desc   = "Wheel Menu",
+                .wakeup = 0,
+        }, {
+                .type   = EV_KEY,
+                .code   = KEY_UP,
+                .gpio   = 32,
+                .desc   = "Nav Pad Up",
+                .wakeup = 0,
+        }, {
+                .type   = EV_KEY,
+                .code   = KEY_RIGHT,
+                .gpio   = 33,
+                .desc   = "Nav Pad Right",
+                .wakeup = 0,
+        }, {
+                .type   = EV_KEY,
+                .code   = KEY_DOWN,
+                .gpio   = 34,
+                .desc   = "Nav Pad Down",
+                .wakeup = 0,
+        }, {
+                .type   = EV_KEY,
+                .code   = KEY_LEFT,
+                .gpio   = 35,
+                .desc   = "Nav Pad Left",
+                .wakeup = 0,
+        }, {
+                .type   = EV_KEY,
+                .code   = KEY_ENTER,
+                .gpio   = 38,
+                .desc   = "Nav Pad Ok",
+                .wakeup = 0,
+        }, {
+                .type   = EV_KEY,
+                .code   = KEY_O,
+                .gpio   = 39,
+                .desc   = "Wheel Off",
+                .wakeup = 0,
+        }, {
+                .type   = EV_KEY,
+                .code   = BTN_FORWARD,
+                .gpio   = 50,
+                .desc   = "Focus Forward",
+                .wakeup = 0,
+        }, {
+                .type   = EV_KEY,
+                .code   = BTN_BACK,
+                .gpio   = 51,
+                .desc   = "Focus Backward",
+                .wakeup = 0,
+        }, {
+                .type   = EV_KEY,
+                .code   = BTN_MIDDLE,
+                .gpio   = 52,
+                .desc   = "Release Half",
+                .wakeup = 0,
+        }, {
+                .type   = EV_KEY,
+                .code   = BTN_EXTRA,
+                .gpio   = 53,
+                .desc   = "Release Full",
+                .wakeup = 0,
+        },
+};
+
+static struct gpio_keys_platform_data pcm037_gpio_keys_platform_data = {
+        .buttons        = pcm037_gpio_keys,
+        .nbuttons       = ARRAY_SIZE(pcm037_gpio_keys),
+        .rep            = 0, /* No auto-repeat */
+};
+
+static struct platform_device pcm037_gpio_keys_device = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &pcm037_gpio_keys_platform_data,
+        },
+};
+
+static int eet_init_devices(void)
+{
+        if (!machine_is_pcm037() || pcm037_variant() != PCM037_EET)
+                return 0;
+
+        mxc_iomux_setup_multiple_pins(pcm037_eet_pins,
+                                ARRAY_SIZE(pcm037_eet_pins), "pcm037_eet");
+
+        /* SPI */
+        spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+        mxc_register_device(&mxc_spi_device0, &pcm037_spi1_master);
+#endif
+
+        platform_device_register(&pcm037_gpio_keys_device);
+
+        return 0;
+}
+
+late_initcall(eet_init_devices);
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index a2d7814896be..505d98cfe508 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -19,7 +19,6 @@
 
 #include <mach/irqs.h>
 #include <mach/dma.h>
-#include <mach/irqs.h>
 #include <mach/mux.h>
 #include <mach/cpu.h>
 #include <mach/mcbsp.h>
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 9c3fdcdf76c3..8ec2a132904d 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -141,7 +141,7 @@ static inline void board_smc91x_init(void)
 
 static void __init omap_2430sdp_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
 }
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 496a90e4ea7a..ac262cd74503 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -169,7 +169,7 @@ static struct platform_device *sdp3430_devices[] __initdata = {
 
 static void __init omap_3430sdp_init_irq(void)
 {
-        omap2_init_common_hw(hyb18m512160af6_sdrc_params);
+        omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
         omap_init_irq();
         omap_gpio_init();
 }
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 57e477bd89c6..b0c7402248f7 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -59,7 +59,7 @@ static void __init gic_init_irq(void)
 
 static void __init omap_4430sdp_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(1);
 #endif
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 06dfba888b0c..dcfc20d03894 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -250,7 +250,7 @@ out:
 
 static void __init omap_apollon_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
         apollon_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 3492162a65c3..fd00aa03690c 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -33,7 +33,7 @@
 
 static void __init omap_generic_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
 }
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index e7d017cdc438..7b1d61d5bb2c 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -270,7 +270,7 @@ static void __init h4_init_flash(void)
 
 static void __init omap_h4_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
         h4_init_flash();
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d8bc0a7dcb8d..ea383f88cb1b 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -270,7 +270,7 @@ static inline void __init ldp_init_smsc911x(void)
 
 static void __init omap_ldp_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
         ldp_init_smsc911x();
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 991ac9c38032..e00ba128cece 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -282,7 +282,8 @@ static int __init omap3_beagle_i2c_init(void)
 
 static void __init omap3_beagle_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
@@ -408,6 +409,10 @@ static void __init omap3_beagle_init(void)
 
         usb_musb_init();
         omap3beagle_flash_init();
+
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_cfg_reg(H16_34XX_SDRC_CKE0);
+        omap_cfg_reg(H17_34XX_SDRC_CKE1);
 }
 
 static void __init omap3_beagle_map_io(void)
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index d3cc145814d0..c4b144647dc5 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -25,6 +25,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/i2c/twl4030.h>
+#include <linux/usb/otg.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -279,7 +280,7 @@ struct spi_board_info omap3evm_spi_board_info[] = {
 
 static void __init omap3_evm_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
         omap_init_irq();
         omap_gpio_init();
         omap3evm_init_smc911x();
@@ -307,6 +308,10 @@ static void __init omap3_evm_init(void)
                                 ARRAY_SIZE(omap3evm_spi_board_info));
 
         omap_serial_init();
+#ifdef CONFIG_NOP_USB_XCEIV
+        /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
+        usb_nop_xceiv_register();
+#endif
         usb_musb_init();
         ads7846_dev_init();
 }
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index e32aa23ce962..864ee3d021f7 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -40,6 +40,7 @@
 #include <mach/mcspi.h>
 #include <mach/usb.h>
 #include <mach/keypad.h>
+#include <mach/mux.h>
 
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mmc-twl4030.h"
@@ -310,7 +311,8 @@ static int __init omap3pandora_i2c_init(void)
 
 static void __init omap3pandora_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
         omap_init_irq();
         omap_gpio_init();
 }
@@ -397,6 +399,10 @@ static void __init omap3pandora_init(void)
         omap3pandora_ads7846_init();
         pandora_keys_gpio_init();
         usb_musb_init();
+
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_cfg_reg(H16_34XX_SDRC_CKE0);
+        omap_cfg_reg(H17_34XX_SDRC_CKE1);
 }
 
 static void __init omap3pandora_map_io(void)
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index dff5528fbfb5..6bce23004aa4 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -44,6 +44,7 @@
 #include <mach/gpmc.h>
 #include <mach/hardware.h>
 #include <mach/nand.h>
+#include <mach/mux.h>
 #include <mach/usb.h>
 
 #include "sdram-micron-mt46h32m32lf-6.h"
@@ -51,6 +52,7 @@
 
 #define OVERO_GPIO_BT_XGATE     15
 #define OVERO_GPIO_W2W_NRESET   16
+#define OVERO_GPIO_PENDOWN      114
 #define OVERO_GPIO_BT_NRESET    164
 #define OVERO_GPIO_USBH_CPEN    168
 #define OVERO_GPIO_USBH_NRESET  183
@@ -146,7 +148,7 @@ static struct platform_device overo_smsc911x_device = {
         .name           = "smsc911x",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(overo_smsc911x_resources),
-        .resource       = &overo_smsc911x_resources,
+        .resource       = overo_smsc911x_resources,
         .dev            = {
                 .platform_data = &overo_smsc911x_config,
         },
@@ -360,7 +362,8 @@ static int __init overo_i2c_init(void)
 
 static void __init overo_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
         omap_init_irq();
         omap_gpio_init();
 }
@@ -395,6 +398,10 @@ static void __init overo_init(void)
         overo_ads7846_init();
         overo_init_smsc911x();
 
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_cfg_reg(H16_34XX_SDRC_CKE0);
+        omap_cfg_reg(H17_34XX_SDRC_CKE1);
+
         if ((gpio_request(OVERO_GPIO_W2W_NRESET,
                           "OVERO_GPIO_W2W_NRESET") == 0) &&
             (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 9a0bf6744a05..56d931a425f7 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -278,6 +278,10 @@ static struct twl4030_gpio_platform_data rx51_gpio_data = {
         .setup                  = rx51_twlgpio_setup,
 };
 
+static struct twl4030_usb_data rx51_usb_data = {
+        .usb_mode               = T2_USB_MODE_ULPI,
+};
+
 static struct twl4030_platform_data rx51_twldata = {
         .irq_base               = TWL4030_IRQ_BASE,
         .irq_end                = TWL4030_IRQ_END,
@@ -286,6 +290,7 @@ static struct twl4030_platform_data rx51_twldata = {
         .gpio                   = &rx51_gpio_data,
         .keypad                 = &rx51_kp_data,
         .madc                   = &rx51_madc_data,
+        .usb                    = &rx51_usb_data,
 
         .vaux1                  = &rx51_vaux1,
         .vaux2                  = &rx51_vaux2,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 374ff63c3eb2..1c9e07fe8266 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -61,7 +61,7 @@ static struct omap_board_config_kernel rx51_config[] = {
 
 static void __init rx51_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
 }
@@ -75,6 +75,10 @@ static void __init rx51_init(void)
         omap_serial_init();
         usb_musb_init();
         rx51_peripherals_init();
+
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_cfg_reg(H16_34XX_SDRC_CKE0);
+        omap_cfg_reg(H17_34XX_SDRC_CKE1);
 }
 
 static void __init rx51_map_io(void)
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index bcc0f7632dea..427b7b8b1237 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -25,7 +25,7 @@
 
 static void __init omap_zoom2_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
 }
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index b0665f161c03..456e2ad5f621 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -27,6 +27,7 @@
 #include <mach/clock.h>
 #include <mach/clockdomain.h>
 #include <mach/cpu.h>
+#include <mach/prcm.h>
 #include <asm/div64.h>
 
 #include <mach/sdrc.h>
@@ -38,8 +39,6 @@
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
-#define MAX_CLOCK_ENABLE_WAIT           100000
-
 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
 #define DPLL_MIN_MULTIPLIER             1
 #define DPLL_MIN_DIVIDER                1
@@ -274,83 +273,97 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
 }
 
 /**
- * omap2_wait_clock_ready - wait for clock to enable
- * @reg: physical address of clock IDLEST register
- * @mask: value to mask against to determine if the clock is active
- * @name: name of the clock (for printk)
+ * omap2_clk_dflt_find_companion - find companion clock to @clk
+ * @clk: struct clk * to find the companion clock of
+ * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
+ * @other_bit: u8 ** to return the companion clock bit shift in
+ *
+ * Note: We don't need special code here for INVERT_ENABLE for the
+ * time being since INVERT_ENABLE only applies to clocks enabled by
+ * CM_CLKEN_PLL
  *
- * Returns 1 if the clock enabled in time, or 0 if it failed to enable
- * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
+ * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes it's
+ * just a matter of XORing the bits.
+ *
+ * Some clocks don't have companion clocks.  For example, modules with
+ * only an interface clock (such as MAILBOXES) don't have a companion
+ * clock.  Right now, this code relies on the hardware exporting a bit
+ * in the correct companion register that indicates that the
+ * nonexistent 'companion clock' is active.  Future patches will
+ * associate this type of code with per-module data structures to
+ * avoid this issue, and remove the casts.  No return value.
  */
-int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
+void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
+                                   u8 *other_bit)
 {
-        int i = 0;
-        int ena = 0;
+        u32 r;
 
         /*
-         * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
-         * 34xx reverses this, just to keep us on our toes
+         * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes
+         * it's just a matter of XORing the bits.
          */
-        if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
-                ena = mask;
-        else if (cpu_mask & RATE_IN_343X)
-                ena = 0;
-
-        /* Wait for lock */
-        while (((__raw_readl(reg) & mask) != ena) &&
-               (i++ < MAX_CLOCK_ENABLE_WAIT)) {
-                udelay(1);
-        }
-
-        if (i <= MAX_CLOCK_ENABLE_WAIT)
-                pr_debug("Clock %s stable after %d loops\n", name, i);
-        else
-                printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
-                       name, MAX_CLOCK_ENABLE_WAIT);
-
-
-        return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
-};
+        r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
 
+        *other_reg = (__force void __iomem *)r;
+        *other_bit = clk->enable_bit;
+}
 
-/*
- * Note: We don't need special code here for INVERT_ENABLE
- * for the time being since INVERT_ENABLE only applies to clocks enabled by
- * CM_CLKEN_PLL
+/**
+ * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
+ * @clk: struct clk * to find IDLEST info for
+ * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
+ * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in
+ *
+ * Return the CM_IDLEST register address and bit shift corresponding
+ * to the module that "owns" this clock.  This default code assumes
+ * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
+ * the IDLEST register address ID corresponds to the CM_*CLKEN
+ * register address ID (e.g., that CM_FCLKEN2 corresponds to
+ * CM_IDLEST2).  This is not true for all modules.  No return value.
  */
-static void omap2_clk_wait_ready(struct clk *clk)
+void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
+                                u8 *idlest_bit)
 {
-        void __iomem *reg, *other_reg, *st_reg;
-        u32 bit;
+        u32 r;
 
-        /*
-         * REVISIT: This code is pretty ugly.  It would be nice to generalize
-         * it and pull it into struct clk itself somehow.
-         */
-        reg = clk->enable_reg;
+        r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
+        *idlest_reg = (__force void __iomem *)r;
+        *idlest_bit = clk->enable_bit;
+}
 
-        /*
-         * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes
-         * it's just a matter of XORing the bits.
-         */
-        other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN));
+/**
+ * omap2_module_wait_ready - wait for an OMAP module to leave IDLE
+ * @clk: struct clk * belonging to the module
+ *
+ * If the necessary clocks for the OMAP hardware IP block that
+ * corresponds to clock @clk are enabled, then wait for the module to
+ * indicate readiness (i.e., to leave IDLE).  This code does not
+ * belong in the clock code and will be moved in the medium term to
+ * module-dependent code.  No return value.
+ */
+static void omap2_module_wait_ready(struct clk *clk)
+{
+        void __iomem *companion_reg, *idlest_reg;
+        u8 other_bit, idlest_bit;
+
+        /* Not all modules have multiple clocks that their IDLEST depends on */
+        if (clk->ops->find_companion) {
+                clk->ops->find_companion(clk, &companion_reg, &other_bit);
+                if (!(__raw_readl(companion_reg) & (1 << other_bit)))
+                        return;
+        }
 
-        /* Check if both functional and interface clocks
-         * are running. */
-        bit = 1 << clk->enable_bit;
-        if (!(__raw_readl(other_reg) & bit))
-                return;
-        st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
+        clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit);
 
-        omap2_wait_clock_ready(st_reg, bit, clk->name);
+        omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name);
 }
 
-static int omap2_dflt_clk_enable(struct clk *clk)
+int omap2_dflt_clk_enable(struct clk *clk)
 {
         u32 v;
 
         if (unlikely(clk->enable_reg == NULL)) {
-                printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
+                pr_err("clock.c: Enable for %s without enable code\n",
                        clk->name);
                 return 0; /* REVISIT: -EINVAL */
         }
@@ -363,26 +376,13 @@ static int omap2_dflt_clk_enable(struct clk *clk)
         __raw_writel(v, clk->enable_reg);
         v = __raw_readl(clk->enable_reg); /* OCP barrier */
 
-        return 0;
-}
+        if (clk->ops->find_idlest)
+                omap2_module_wait_ready(clk);
 
-static int omap2_dflt_clk_enable_wait(struct clk *clk)
-{
-        int ret;
-
-        if (!clk->enable_reg) {
-                printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
-                       clk->name);
-                return 0; /* REVISIT: -EINVAL */
-        }
-
-        ret = omap2_dflt_clk_enable(clk);
-        if (ret == 0)
-                omap2_clk_wait_ready(clk);
-        return ret;
+        return 0;
 }
 
-static void omap2_dflt_clk_disable(struct clk *clk)
+void omap2_dflt_clk_disable(struct clk *clk)
 {
         u32 v;
 
@@ -406,8 +406,10 @@ static void omap2_dflt_clk_disable(struct clk *clk)
 }
 
 const struct clkops clkops_omap2_dflt_wait = {
-        .enable         = omap2_dflt_clk_enable_wait,
+        .enable         = omap2_dflt_clk_enable,
         .disable        = omap2_dflt_clk_disable,
+        .find_companion = omap2_clk_dflt_find_companion,
+        .find_idlest    = omap2_clk_dflt_find_idlest,
 };
 
 const struct clkops clkops_omap2_dflt = {
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2679ddfa6424..9ae7540f8af2 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -65,6 +65,12 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 u32 omap2_get_dpll_rate(struct clk *clk);
 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
 void omap2_clk_prepare_for_reboot(void);
+int omap2_dflt_clk_enable(struct clk *clk);
+void omap2_dflt_clk_disable(struct clk *clk);
+void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
+                                   u8 *other_bit);
+void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
+                                u8 *idlest_bit);
 
 extern const struct clkops clkops_omap2_dflt_wait;
 extern const struct clkops clkops_omap2_dflt;
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 44de0271fc2f..bc5d3ac66611 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -30,6 +30,7 @@
 
 #include <mach/clock.h>
 #include <mach/sram.h>
+#include <mach/prcm.h>
 #include <asm/div64.h>
 #include <asm/clkdev.h>
 
@@ -43,6 +44,18 @@
 static const struct clkops clkops_oscck;
 static const struct clkops clkops_fixed;
 
+static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
+                                           void __iomem **idlest_reg,
+                                           u8 *idlest_bit);
+
+/* 2430 I2CHS has non-standard IDLEST register */
+static const struct clkops clkops_omap2430_i2chs_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap2430_clk_i2chs_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
 #include "clock24xx.h"
 
 struct omap_clk {
@@ -240,6 +253,26 @@ static void __iomem *prcm_clksrc_ctrl;
  *-------------------------------------------------------------------------*/
 
 /**
+ * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
+ * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE.  This custom function
+ * passes back the correct CM_IDLEST register address for I2CHS
+ * modules.  No return value.
+ */
+static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
+                                           void __iomem **idlest_reg,
+                                           u8 *idlest_bit)
+{
+        *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
+        *idlest_bit = clk->enable_bit;
+}
+
+
+/**
  * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
  * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
  *
@@ -325,8 +358,8 @@ static int omap2_clk_fixed_enable(struct clk *clk)
         else if (clk == &apll54_ck)
                 cval = OMAP24XX_ST_54M_APLL;
 
-        omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
-                            clk->name);
+        omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
+                             clk->name);
 
         /*
          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 458f00cdcbea..d19cf7a7d8db 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -2337,7 +2337,7 @@ static struct clk i2c2_fck = {
 
 static struct clk i2chs2_fck = {
         .name           = "i2c_fck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2430_i2chs_wait,
         .id             = 2,
         .parent         = &func_96m_ck,
         .clkdm_name     = "core_l4_clkdm",
@@ -2370,7 +2370,7 @@ static struct clk i2c1_fck = {
 
 static struct clk i2chs1_fck = {
         .name           = "i2c_fck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2430_i2chs_wait,
         .id             = 1,
         .parent         = &func_96m_ck,
         .clkdm_name     = "core_l4_clkdm",
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 045da923e75b..cd7819cc0c9e 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -2,7 +2,7 @@
  * OMAP3-specific clock framework functions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  * Testing and integration fixes by Jouni Högander
@@ -41,6 +41,37 @@
 
 static const struct clkops clkops_noncore_dpll_ops;
 
+static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
+                                            void __iomem **idlest_reg,
+                                            u8 *idlest_bit);
+static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
+                                            void __iomem **idlest_reg,
+                                            u8 *idlest_bit);
+static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
+                                                    void __iomem **idlest_reg,
+                                                    u8 *idlest_bit);
+
+static const struct clkops clkops_omap3430es2_ssi_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_ssi_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
+static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
+static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
 #include "clock34xx.h"
 
 struct omap_clk {
@@ -157,10 +188,13 @@ static struct omap_clk omap34xx_clks[] = {
         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_343X),
         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_343X),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck,   CK_343X),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck,   CK_343X),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
-        CLK("musb_hdrc",        "ick",  &hsotgusb_ick,  CK_343X),
+        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
+        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
@@ -193,18 +227,21 @@ static struct omap_clk omap34xx_clks[] = {
         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_343X),
         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
-        CLK(NULL,       "ssi_ick",      &ssi_ick,       CK_343X),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
         CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
         CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
         CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
         CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
-        CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck, CK_343X),
+        CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
+        CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2),
         CLK("omapfb",   "tv_fck",       &dss_tv_fck,    CK_343X),
         CLK("omapfb",   "video_fck",    &dss_96m_fck,   CK_343X),
         CLK("omapfb",   "dss2_fck",     &dss2_alwon_fck, CK_343X),
-        CLK("omapfb",   "ick",          &dss_ick,       CK_343X),
+        CLK("omapfb",   "ick",          &dss_ick_3430es1,       CK_3430ES1),
+        CLK("omapfb",   "ick",          &dss_ick_3430es2,       CK_3430ES2),
         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
         CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
@@ -301,6 +338,73 @@ static struct omap_clk omap34xx_clks[] = {
 #define SDRC_MPURATE_LOOPS              96
 
 /**
+ * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
+ * from the CM_{I,F}CLKEN bit.  Pass back the correct info via
+ * @idlest_reg and @idlest_bit.  No return value.
+ */
+static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
+                                            void __iomem **idlest_reg,
+                                            u8 *idlest_bit)
+{
+        u32 r;
+
+        r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
+        *idlest_reg = (__force void __iomem *)r;
+        *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
+}
+
+/**
+ * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
+ * target IDLEST bits.  For our purposes, we are concerned with the
+ * target IDLEST bits, which exist at a different bit position than
+ * the *CLKEN bit position for these modules (DSS and USBHOST) (The
+ * default find_idlest code assumes that they are at the same
+ * position.)  No return value.
+ */
+static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
+                                                    void __iomem **idlest_reg,
+                                                    u8 *idlest_bit)
+{
+        u32 r;
+
+        r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
+        *idlest_reg = (__force void __iomem *)r;
+        /* USBHOST_IDLE has same shift */
+        *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
+}
+
+/**
+ * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
+ * shift from the CM_{I,F}CLKEN bit.  Pass back the correct info via
+ * @idlest_reg and @idlest_bit.  No return value.
+ */
+static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
+                                                 void __iomem **idlest_reg,
+                                                 u8 *idlest_bit)
+{
+        u32 r;
+
+        r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
+        *idlest_reg = (__force void __iomem *)r;
+        *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
+}
+
+/**
  * omap3_dpll_recalc - recalculate DPLL rate
  * @clk: DPLL struct clk
  *
@@ -725,7 +829,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         u32 unlock_dll = 0;
         u32 c;
         unsigned long validrate, sdrcrate, mpurate;
-        struct omap_sdrc_params *sp;
+        struct omap_sdrc_params *sdrc_cs0;
+        struct omap_sdrc_params *sdrc_cs1;
+        int ret;
 
         if (!clk || !rate)
                 return -EINVAL;
@@ -743,8 +849,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         else
                 sdrcrate >>= ((clk->rate / rate) >> 1);
 
-        sp = omap2_sdrc_get_params(sdrcrate);
-        if (!sp)
+        ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
+        if (ret)
                 return -EINVAL;
 
         if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
@@ -765,12 +871,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 
         pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
                  validrate);
-        pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
-                 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
-
-        omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
-                                  sp->actim_ctrlb, new_div, unlock_dll, c,
-                                  sp->mr, rate > clk->rate);
+        pr_debug("clock: SDRC CS0 timing params used:"
+                 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+                 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+                 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
+        if (sdrc_cs1)
+                pr_debug("clock: SDRC CS1 timing params used: "
+                 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+                 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+                 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+
+        if (sdrc_cs1)
+                omap3_configure_core_dpll(
+                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+                                  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+                                  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+        else
+                omap3_configure_core_dpll(
+                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+                                  0, 0, 0, 0);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index e433aec4efdd..57cc2725b923 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1568,7 +1568,7 @@ static const struct clksel ssi_ssr_clksel[] = {
         { .parent = NULL }
 };
 
-static struct clk ssi_ssr_fck = {
+static struct clk ssi_ssr_fck_3430es1 = {
         .name           = "ssi_ssr_fck",
         .ops            = &clkops_omap2_dflt,
         .init           = &omap2_init_clksel_parent,
@@ -1581,10 +1581,31 @@ static struct clk ssi_ssr_fck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
-static struct clk ssi_sst_fck = {
+static struct clk ssi_ssr_fck_3430es2 = {
+        .name           = "ssi_ssr_fck",
+        .ops            = &clkops_omap3430es2_ssi_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk ssi_sst_fck_3430es1 = {
         .name           = "ssi_sst_fck",
         .ops            = &clkops_null,
-        .parent         = &ssi_ssr_fck,
+        .parent         = &ssi_ssr_fck_3430es1,
+        .fixed_div      = 2,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+static struct clk ssi_sst_fck_3430es2 = {
+        .name           = "ssi_sst_fck",
+        .ops            = &clkops_null,
+        .parent         = &ssi_ssr_fck_3430es2,
         .fixed_div      = 2,
         .recalc         = &omap2_fixed_divisor_recalc,
 };
@@ -1606,9 +1627,19 @@ static struct clk core_l3_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk hsotgusb_ick = {
+static struct clk hsotgusb_ick_3430es1 = {
         .name           = "hsotgusb_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hsotgusb_ick_3430es2 = {
+        .name           = "hsotgusb_ick",
+        .ops            = &clkops_omap3430es2_hsotgusb_wait,
         .parent         = &core_l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1947,7 +1978,7 @@ static struct clk ssi_l4_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk ssi_ick = {
+static struct clk ssi_ick_3430es1 = {
         .name           = "ssi_ick",
         .ops            = &clkops_omap2_dflt,
         .parent         = &ssi_l4_ick,
@@ -1957,6 +1988,16 @@ static struct clk ssi_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk ssi_ick_3430es2 = {
+        .name           = "ssi_ick",
+        .ops            = &clkops_omap3430es2_ssi_wait,
+        .parent         = &ssi_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
  * but l4_ick makes more sense to me */
 
@@ -2024,7 +2065,7 @@ static struct clk des1_ick = {
 };
 
 /* DSS */
-static struct clk dss1_alwon_fck = {
+static struct clk dss1_alwon_fck_3430es1 = {
         .name           = "dss1_alwon_fck",
         .ops            = &clkops_omap2_dflt,
         .parent         = &dpll4_m4x2_ck,
@@ -2034,6 +2075,16 @@ static struct clk dss1_alwon_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk dss1_alwon_fck_3430es2 = {
+        .name           = "dss1_alwon_fck",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &dpll4_m4x2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk dss_tv_fck = {
         .name           = "dss_tv_fck",
         .ops            = &clkops_omap2_dflt,
@@ -2067,7 +2118,7 @@ static struct clk dss2_alwon_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk dss_ick = {
+static struct clk dss_ick_3430es1 = {
         /* Handles both L3 and L4 clocks */
         .name           = "dss_ick",
         .ops            = &clkops_omap2_dflt,
@@ -2079,6 +2130,18 @@ static struct clk dss_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk dss_ick_3430es2 = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "dss_ick",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clk_clkdm,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 /* CAM */
 
 static struct clk cam_mclk = {
@@ -2118,7 +2181,7 @@ static struct clk csi2_96m_fck = {
 
 static struct clk usbhost_120m_fck = {
         .name           = "usbhost_120m_fck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_dflt,
         .parent         = &dpll5_m2_ck,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
@@ -2129,7 +2192,7 @@ static struct clk usbhost_120m_fck = {
 
 static struct clk usbhost_48m_fck = {
         .name           = "usbhost_48m_fck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
         .parent         = &omap_48m_fck,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
@@ -2141,7 +2204,7 @@ static struct clk usbhost_48m_fck = {
 static struct clk usbhost_ick = {
         /* Handles both L3 and L4 clocks */
         .name           = "usbhost_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
         .parent         = &l4_ick,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 1d3c93bf86d3..f3c91a1ca391 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -29,9 +29,9 @@
  * These registers appear once per CM module.
  */
 
-#define OMAP3430_CM_REVISION            OMAP_CM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP3430_CM_SYSCONFIG           OMAP_CM_REGADDR(OCP_MOD, 0x0010)
-#define OMAP3430_CM_POLCTRL             OMAP_CM_REGADDR(OCP_MOD, 0x009c)
+#define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
 
 #define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
 #define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3a86b0f66031..e9b9bcb19b4e 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -276,14 +276,15 @@ static int __init _omap2_init_reprogram_sdrc(void)
         return v;
 }
 
-void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
+void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
+                                 struct omap_sdrc_params *sdrc_cs1)
 {
         omap2_mux_init();
 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
         pwrdm_init(powerdomains_omap);
         clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
         omap2_clk_init();
-        omap2_sdrc_init(sp);
+        omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
         _omap2_init_reprogram_sdrc();
 #endif
         gpmc_init();
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index a5c0f0435cd6..99b6e1546311 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -19,7 +19,6 @@
 
 #include <mach/irqs.h>
 #include <mach/dma.h>
-#include <mach/irqs.h>
 #include <mach/mux.h>
 #include <mach/cpu.h>
 #include <mach/mcbsp.h>
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c
index 1541fd4c8d0f..3c04c2f1b23f 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.c
+++ b/arch/arm/mach-omap2/mmc-twl4030.c
@@ -119,6 +119,7 @@ static int twl_mmc_late_init(struct device *dev)
                                 if (i != 0)
                                         break;
                                 ret = PTR_ERR(reg);
+                                hsmmc[i].vcc = NULL;
                                 goto err;
                         }
                         hsmmc[i].vcc = reg;
@@ -165,8 +166,13 @@ done:
 static void twl_mmc_cleanup(struct device *dev)
 {
         struct omap_mmc_platform_data *mmc = dev->platform_data;
+        int i;
 
         gpio_free(mmc->slots[0].switch_pin);
+        for(i = 0; i < ARRAY_SIZE(hsmmc); i++) {
+                regulator_put(hsmmc[i].vcc);
+                regulator_put(hsmmc[i].vcc_aux);
+        }
 }
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 026c4fc883a7..43d6b92b65f2 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
                 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
 MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
                 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
+
+/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
+MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
 };
 
 #define OMAP34XX_PINS_SZ        ARRAY_SIZE(omap34xx_pins)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index f7b3baf76678..21201cd4117b 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -11,9 +11,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PM_H
 #define __ARCH_ARM_MACH_OMAP2_PM_H
 
-extern int omap2_pm_init(void);
-extern int omap3_pm_init(void);
-
 #ifdef CONFIG_PM_DEBUG
 extern void omap2_pm_dump(int mode, int resume, unsigned int us);
 extern int omap2_pm_debug;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index db1025562fb0..528dbdc26e23 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -470,7 +470,7 @@ static void __init prcm_setup_regs(void)
                           WKUP_MOD, PM_WKEN);
 }
 
-int __init omap2_pm_init(void)
+static int __init omap2_pm_init(void)
 {
         u32 l;
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 841d4c5ed8be..488d595d8e4b 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -39,7 +39,9 @@
 struct power_state {
         struct powerdomain *pwrdm;
         u32 next_state;
+#ifdef CONFIG_SUSPEND
         u32 saved_state;
+#endif
         struct list_head node;
 };
 
@@ -293,6 +295,9 @@ out:
         local_irq_enable();
 }
 
+#ifdef CONFIG_SUSPEND
+static suspend_state_t suspend_state;
+
 static int omap3_pm_prepare(void)
 {
         disable_hlt();
@@ -321,7 +326,6 @@ static int omap3_pm_suspend(void)
 restore:
         /* Restore next_pwrsts */
         list_for_each_entry(pwrst, &pwrst_list, node) {
-                set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
                 if (state > pwrst->next_state) {
                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
@@ -329,6 +333,7 @@ restore:
                                pwrst->pwrdm->name, pwrst->next_state);
                         ret = -1;
                 }
+                set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
         }
         if (ret)
                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
@@ -339,11 +344,11 @@ restore:
         return ret;
 }
 
-static int omap3_pm_enter(suspend_state_t state)
+static int omap3_pm_enter(suspend_state_t unused)
 {
         int ret = 0;
 
-        switch (state) {
+        switch (suspend_state) {
         case PM_SUSPEND_STANDBY:
         case PM_SUSPEND_MEM:
                 ret = omap3_pm_suspend();
@@ -360,12 +365,30 @@ static void omap3_pm_finish(void)
         enable_hlt();
 }
 
+/* Hooks to enable / disable UART interrupts during suspend */
+static int omap3_pm_begin(suspend_state_t state)
+{
+        suspend_state = state;
+        omap_uart_enable_irqs(0);
+        return 0;
+}
+
+static void omap3_pm_end(void)
+{
+        suspend_state = PM_SUSPEND_ON;
+        omap_uart_enable_irqs(1);
+        return;
+}
+
 static struct platform_suspend_ops omap_pm_ops = {
+        .begin          = omap3_pm_begin,
+        .end            = omap3_pm_end,
         .prepare        = omap3_pm_prepare,
         .enter          = omap3_pm_enter,
         .finish         = omap3_pm_finish,
         .valid          = suspend_valid_only_mem,
 };
+#endif /* CONFIG_SUSPEND */
 
 
 /**
@@ -613,6 +636,24 @@ static void __init prcm_setup_regs(void)
         /* Clear any pending PRCM interrupts */
         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
+        /* Don't attach IVA interrupts */
+        prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
+        prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
+        prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
+        prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
+
+        /* Clear any pending 'reset' flags */
+        prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
+
+        /* Clear any pending PRCM interrupts */
+        prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+
         omap3_iva_idle();
         omap3_d2d_idle();
 }
@@ -652,7 +693,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm)
         return 0;
 }
 
-int __init omap3_pm_init(void)
+static int __init omap3_pm_init(void)
 {
         struct power_state *pwrst, *tmp;
         int ret;
@@ -692,7 +733,9 @@ int __init omap3_pm_init(void)
         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
                                          omap34xx_cpu_suspend_sz);
 
+#ifdef CONFIG_SUSPEND
         suspend_set_ops(&omap_pm_ops);
+#endif /* CONFIG_SUSPEND */
 
         pm_idle = omap3_pm_idle;
 
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index f945156d5585..ced555a4cd1a 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/delay.h>
 
 #include <mach/common.h>
 #include <mach/prcm.h>
@@ -28,6 +29,8 @@
 static void __iomem *prm_base;
 static void __iomem *cm_base;
 
+#define MAX_MODULE_ENABLE_WAIT          100000
+
 u32 omap_prcm_get_reset_sources(void)
 {
         /* XXX This presumably needs modification for 34XX */
@@ -120,6 +123,46 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
 }
 EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
 
+/**
+ * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
+ * @reg: physical address of module IDLEST register
+ * @mask: value to mask against to determine if the module is active
+ * @name: name of the clock (for printk)
+ *
+ * Returns 1 if the module indicated readiness in time, or 0 if it
+ * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
+ */
+int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
+{
+        int i = 0;
+        int ena = 0;
+
+        /*
+         * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
+         * 34xx reverses this, just to keep us on our toes
+         */
+        if (cpu_is_omap24xx())
+                ena = mask;
+        else if (cpu_is_omap34xx())
+                ena = 0;
+        else
+                BUG();
+
+        /* Wait for lock */
+        while (((__raw_readl(reg) & mask) != ena) &&
+               (i++ < MAX_MODULE_ENABLE_WAIT))
+                udelay(1);
+
+        if (i < MAX_MODULE_ENABLE_WAIT)
+                pr_debug("cm: Module associated with clock %s ready after %d "
+                         "loops\n", name, i);
+        else
+                pr_err("cm: Module associated with clock %s didn't enable in "
+                       "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
+
+        return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
+};
+
 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
 {
         prm_base = omap2_globals->prm;
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 2045441e8385..9e3bd4fa7810 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -32,7 +32,7 @@
 #include <mach/sdrc.h>
 #include "sdrc.h"
 
-static struct omap_sdrc_params *sdrc_init_params;
+static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
 
 void __iomem *omap2_sdrc_base;
 void __iomem *omap2_sms_base;
@@ -45,33 +45,49 @@ void __iomem *omap2_sms_base;
 /**
  * omap2_sdrc_get_params - return SDRC register values for a given clock rate
  * @r: SDRC clock rate (in Hz)
+ * @sdrc_cs0: chip select 0 ram timings **
+ * @sdrc_cs1: chip select 1 ram timings **
  *
  * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
- * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
- * SDRC clock rate 'r'.  These parameters control various timing
- * delays in the SDRAM controller that are expressed in terms of the
- * number of SDRC clock cycles to wait; hence the clock rate
- * dependency. Note that sdrc_init_params must be sorted rate
- * descending.  Also assumes that both chip-selects use the same
- * timing parameters.  Returns a struct omap_sdrc_params * upon
- * success, or NULL upon failure.
+ *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
+ *  structs,for a given SDRC clock rate 'r'.
+ * These parameters control various timing delays in the SDRAM controller
+ *  that are expressed in terms of the number of SDRC clock cycles to
+ *  wait; hence the clock rate dependency.
+ *
+ * Supports 2 different timing parameters for both chip selects.
+ *
+ * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
+ * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
+ *  as sdrc_init_params_cs_0.
+ *
+ * Fills in the struct omap_sdrc_params * for each chip select.
+ * Returns 0 upon success or -1 upon failure.
  */
-struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
+int omap2_sdrc_get_params(unsigned long r,
+                          struct omap_sdrc_params **sdrc_cs0,
+                          struct omap_sdrc_params **sdrc_cs1)
 {
-        struct omap_sdrc_params *sp;
+        struct omap_sdrc_params *sp0, *sp1;
 
-        if (!sdrc_init_params)
-                return NULL;
+        if (!sdrc_init_params_cs0)
+                return -1;
 
-        sp = sdrc_init_params;
+        sp0 = sdrc_init_params_cs0;
+        sp1 = sdrc_init_params_cs1;
 
-        while (sp->rate && sp->rate != r)
-                sp++;
+        while (sp0->rate && sp0->rate != r) {
+                sp0++;
+                if (sdrc_init_params_cs1)
+                        sp1++;
+        }
 
-        if (!sp->rate)
-                return NULL;
+        if (!sp0->rate)
+                return -1;
 
-        return sp;
+        *sdrc_cs0 = sp0;
+        *sdrc_cs1 = sp1;
+        return 0;
 }
 
 
@@ -83,13 +99,15 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
 
 /**
  * omap2_sdrc_init - initialize SMS, SDRC devices on boot
- * @sp: pointer to a null-terminated list of struct omap_sdrc_params
+ * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
+ *  Support for 2 chip selects timings
  *
  * Turn on smart idle modes for SDRAM scheduler and controller.
  * Program a known-good configuration for the SDRC to deal with buggy
  * bootloaders.
  */
-void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
+void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                            struct omap_sdrc_params *sdrc_cs1)
 {
         u32 l;
 
@@ -103,11 +121,15 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
         l |= (0x2 << 3);
         sdrc_write_reg(l, SDRC_SYSCONFIG);
 
-        sdrc_init_params = sp;
+        sdrc_init_params_cs0 = sdrc_cs0;
+        sdrc_init_params_cs1 = sdrc_cs1;
 
         /* XXX Enable SRFRONIDLEREQ here also? */
+        /*
+         * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
+         * can cause random memory corruption
+         */
         l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
-                (1 << SDRC_POWER_PWDENA_SHIFT) |
                 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
         sdrc_write_reg(l, SDRC_POWER);
 }
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index b094c15bfe47..a7421a50410b 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -54,6 +54,7 @@ struct omap_uart_state {
 
         struct plat_serial8250_port *p;
         struct list_head node;
+        struct platform_device pdev;
 
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
         int context_valid;
@@ -68,10 +69,9 @@ struct omap_uart_state {
 #endif
 };
 
-static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
 static LIST_HEAD(uart_list);
 
-static struct plat_serial8250_port serial_platform_data[] = {
+static struct plat_serial8250_port serial_platform_data0[] = {
         {
                 .membase        = IO_ADDRESS(OMAP_UART1_BASE),
                 .mapbase        = OMAP_UART1_BASE,
@@ -81,6 +81,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .regshift       = 2,
                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
         }, {
+                .flags          = 0
+        }
+};
+
+static struct plat_serial8250_port serial_platform_data1[] = {
+        {
                 .membase        = IO_ADDRESS(OMAP_UART2_BASE),
                 .mapbase        = OMAP_UART2_BASE,
                 .irq            = 73,
@@ -89,6 +95,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .regshift       = 2,
                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
         }, {
+                .flags          = 0
+        }
+};
+
+static struct plat_serial8250_port serial_platform_data2[] = {
+        {
                 .membase        = IO_ADDRESS(OMAP_UART3_BASE),
                 .mapbase        = OMAP_UART3_BASE,
                 .irq            = 74,
@@ -217,6 +229,40 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
         clk_disable(uart->fck);
 }
 
+static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
+{
+        /* Set wake-enable bit */
+        if (uart->wk_en && uart->wk_mask) {
+                u32 v = __raw_readl(uart->wk_en);
+                v |= uart->wk_mask;
+                __raw_writel(v, uart->wk_en);
+        }
+
+        /* Ensure IOPAD wake-enables are set */
+        if (cpu_is_omap34xx() && uart->padconf) {
+                u16 v = omap_ctrl_readw(uart->padconf);
+                v |= OMAP3_PADCONF_WAKEUPENABLE0;
+                omap_ctrl_writew(v, uart->padconf);
+        }
+}
+
+static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
+{
+        /* Clear wake-enable bit */
+        if (uart->wk_en && uart->wk_mask) {
+                u32 v = __raw_readl(uart->wk_en);
+                v &= ~uart->wk_mask;
+                __raw_writel(v, uart->wk_en);
+        }
+
+        /* Ensure IOPAD wake-enables are cleared */
+        if (cpu_is_omap34xx() && uart->padconf) {
+                u16 v = omap_ctrl_readw(uart->padconf);
+                v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
+                omap_ctrl_writew(v, uart->padconf);
+        }
+}
+
 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
                                           int enable)
 {
@@ -246,6 +292,11 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart)
 
 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 {
+        if (device_may_wakeup(&uart->pdev.dev))
+                omap_uart_enable_wakeup(uart);
+        else
+                omap_uart_disable_wakeup(uart);
+
         if (!uart->clocked)
                 return;
 
@@ -292,7 +343,6 @@ void omap_uart_resume_idle(int num)
                         /* Check for normal UART wakeup */
                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
                                 omap_uart_block_sleep(uart);
-
                         return;
                 }
         }
@@ -346,16 +396,13 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
         return IRQ_NONE;
 }
 
-static u32 sleep_timeout = DEFAULT_TIMEOUT;
-
 static void omap_uart_idle_init(struct omap_uart_state *uart)
 {
-        u32 v;
         struct plat_serial8250_port *p = uart->p;
         int ret;
 
         uart->can_sleep = 0;
-        uart->timeout = sleep_timeout;
+        uart->timeout = DEFAULT_TIMEOUT;
         setup_timer(&uart->timer, omap_uart_idle_timer,
                     (unsigned long) uart);
         mod_timer(&uart->timer, jiffies + uart->timeout);
@@ -413,76 +460,101 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                 uart->padconf = 0;
         }
 
-        /* Set wake-enable bit */
-        if (uart->wk_en && uart->wk_mask) {
-                v = __raw_readl(uart->wk_en);
-                v |= uart->wk_mask;
-                __raw_writel(v, uart->wk_en);
-        }
-
-        /* Ensure IOPAD wake-enables are set */
-        if (cpu_is_omap34xx() && uart->padconf) {
-                u16 v;
-
-                v = omap_ctrl_readw(uart->padconf);
-                v |= OMAP3_PADCONF_WAKEUPENABLE0;
-                omap_ctrl_writew(v, uart->padconf);
-        }
-
         p->flags |= UPF_SHARE_IRQ;
         ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
                           "serial idle", (void *)uart);
         WARN_ON(ret);
 }
 
-static ssize_t sleep_timeout_show(struct kobject *kobj,
-                                  struct kobj_attribute *attr,
+void omap_uart_enable_irqs(int enable)
+{
+        int ret;
+        struct omap_uart_state *uart;
+
+        list_for_each_entry(uart, &uart_list, node) {
+                if (enable)
+                        ret = request_irq(uart->p->irq, omap_uart_interrupt,
+                                IRQF_SHARED, "serial idle", (void *)uart);
+                else
+                        free_irq(uart->p->irq, (void *)uart);
+        }
+}
+
+static ssize_t sleep_timeout_show(struct device *dev,
+                                  struct device_attribute *attr,
                                   char *buf)
 {
-        return sprintf(buf, "%u\n", sleep_timeout / HZ);
+        struct platform_device *pdev = container_of(dev,
+                                        struct platform_device, dev);
+        struct omap_uart_state *uart = container_of(pdev,
+                                        struct omap_uart_state, pdev);
+
+        return sprintf(buf, "%u\n", uart->timeout / HZ);
 }
 
-static ssize_t sleep_timeout_store(struct kobject *kobj,
-                                   struct kobj_attribute *attr,
+static ssize_t sleep_timeout_store(struct device *dev,
+                                   struct device_attribute *attr,
                                    const char *buf, size_t n)
 {
-        struct omap_uart_state *uart;
+        struct platform_device *pdev = container_of(dev,
+                                        struct platform_device, dev);
+        struct omap_uart_state *uart = container_of(pdev,
+                                        struct omap_uart_state, pdev);
         unsigned int value;
 
         if (sscanf(buf, "%u", &value) != 1) {
                 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
                 return -EINVAL;
         }
-        sleep_timeout = value * HZ;
-        list_for_each_entry(uart, &uart_list, node) {
-                uart->timeout = sleep_timeout;
-                if (uart->timeout)
-                        mod_timer(&uart->timer, jiffies + uart->timeout);
-                else
-                        /* A zero value means disable timeout feature */
-                        omap_uart_block_sleep(uart);
-        }
+
+        uart->timeout = value * HZ;
+        if (uart->timeout)
+                mod_timer(&uart->timer, jiffies + uart->timeout);
+        else
+                /* A zero value means disable timeout feature */
+                omap_uart_block_sleep(uart);
+
         return n;
 }
 
-static struct kobj_attribute sleep_timeout_attr =
-        __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
-
+DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
+#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 #else
 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
+#define DEV_CREATE_FILE(dev, attr)
 #endif /* CONFIG_PM */
 
-static struct platform_device serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = serial_platform_data,
+static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
+        {
+                .pdev = {
+                        .name                   = "serial8250",
+                        .id                     = PLAT8250_DEV_PLATFORM,
+                        .dev                    = {
+                                .platform_data  = serial_platform_data0,
+                        },
+                },
+        }, {
+                .pdev = {
+                        .name                   = "serial8250",
+                        .id                     = PLAT8250_DEV_PLATFORM1,
+                        .dev                    = {
+                                .platform_data  = serial_platform_data1,
+                        },
+                },
+        }, {
+                .pdev = {
+                        .name                   = "serial8250",
+                        .id                     = PLAT8250_DEV_PLATFORM2,
+                        .dev                    = {
+                                .platform_data  = serial_platform_data2,
+                        },
+                },
         },
 };
 
 void __init omap_serial_init(void)
 {
-        int i, err;
+        int i;
         const struct omap_uart_config *info;
         char name[16];
 
@@ -496,14 +568,12 @@ void __init omap_serial_init(void)
 
         if (info == NULL)
                 return;
-        if (cpu_is_omap44xx()) {
-                for (i = 0; i < OMAP_MAX_NR_PORTS; i++)
-                        serial_platform_data[i].irq += 32;
-        }
 
         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
-                struct plat_serial8250_port *p = serial_platform_data + i;
                 struct omap_uart_state *uart = &omap_uart[i];
+                struct platform_device *pdev = &uart->pdev;
+                struct device *dev = &pdev->dev;
+                struct plat_serial8250_port *p = dev->platform_data;
 
                 if (!(info->enabled_uarts & (1 << i))) {
                         p->membase = NULL;
@@ -531,20 +601,21 @@ void __init omap_serial_init(void)
                 uart->num = i;
                 p->private_data = uart;
                 uart->p = p;
-                list_add(&uart->node, &uart_list);
+                list_add_tail(&uart->node, &uart_list);
+
+                if (cpu_is_omap44xx())
+                        p->irq += 32;
 
                 omap_uart_enable_clocks(uart);
                 omap_uart_reset(uart);
                 omap_uart_idle_init(uart);
-        }
-
-        err = platform_device_register(&serial_device);
-
-#ifdef CONFIG_PM
-        if (!err)
-                err = sysfs_create_file(&serial_device.dev.kobj,
-                                        &sleep_timeout_attr.attr);
-#endif
 
+                if (WARN_ON(platform_device_register(pdev)))
+                        continue;
+                if ((cpu_is_omap34xx() && uart->padconf) ||
+                    (uart->wk_en && uart->wk_mask)) {
+                        device_init_wakeup(dev, true);
+                        DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
+                }
+        }
 }
-
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index f41f8d96ddba..82aa4a3d160c 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -36,7 +36,7 @@
 
         .text
 
-/* r4 parameters */
+/* r1 parameters */
 #define SDRC_NO_UNLOCK_DLL              0x0
 #define SDRC_UNLOCK_DLL                 0x1
 
@@ -58,7 +58,6 @@
 
 /* SDRC_POWER bit settings */
 #define SRFRONIDLEREQ_MASK              0x40
-#define PWDENA_MASK                     0x4
 
 /* CM_IDLEST1_CORE bit settings */
 #define ST_SDRC_MASK                    0x2
@@ -71,41 +70,72 @@
 
 /*
  * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
- * r0 = new SDRC_RFR_CTRL register contents
- * r1 = new SDRC_ACTIM_CTRLA register contents
- * r2 = new SDRC_ACTIM_CTRLB register contents
- * r3 = new M2 divider setting (only 1 and 2 supported right now)
- * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
+ *
+ * Params passed in registers:
+ *  r0 = new M2 divider setting (only 1 and 2 supported right now)
+ *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
  *      SDRC rates < 83MHz
- * r5 = number of MPU cycles to wait for SDRC to stabilize after
+ *  r2 = number of MPU cycles to wait for SDRC to stabilize after
  *      reprogramming the SDRC when switching to a slower MPU speed
- * r6 = new SDRC_MR_0 register value
- * r7 = increasing SDRC rate? (1 = yes, 0 = no)
+ *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
+ *
+ * Params passed via the stack. The needed params will be copied in SRAM
+ *  before use by the code in SRAM (SDRAM is not accessible during SDRC
+ *  reconfiguration):
+ *  new SDRC_RFR_CTRL_0 register contents
+ *  new SDRC_ACTIM_CTRL_A_0 register contents
+ *  new SDRC_ACTIM_CTRL_B_0 register contents
+ *  new SDRC_MR_0 register value
+ *  new SDRC_RFR_CTRL_1 register contents
+ *  new SDRC_ACTIM_CTRL_A_1 register contents
+ *  new SDRC_ACTIM_CTRL_B_1 register contents
+ *  new SDRC_MR_1 register value
  *
+ * If the param SDRC_RFR_CTRL_1 is 0, the parameters
+ *  are not programmed into the SDRC CS1 registers
  */
 ENTRY(omap3_sram_configure_core_dpll)
         stmfd   sp!, {r1-r12, lr}       @ store regs to stack
-        ldr     r4, [sp, #52]           @ pull extra args off the stack
-        ldr     r5, [sp, #56]           @ load extra args from the stack
-        ldr     r6, [sp, #60]           @ load extra args from the stack
-        ldr     r7, [sp, #64]           @ load extra args from the stack
+
+                                        @ pull the extra args off the stack
+                                        @  and store them in SRAM
+        ldr     r4, [sp, #52]
+        str     r4, omap_sdrc_rfr_ctrl_0_val
+        ldr     r4, [sp, #56]
+        str     r4, omap_sdrc_actim_ctrl_a_0_val
+        ldr     r4, [sp, #60]
+        str     r4, omap_sdrc_actim_ctrl_b_0_val
+        ldr     r4, [sp, #64]
+        str     r4, omap_sdrc_mr_0_val
+        ldr     r4, [sp, #68]
+        str     r4, omap_sdrc_rfr_ctrl_1_val
+        cmp     r4, #0                  @ if SDRC_RFR_CTRL_1 is 0,
+        beq     skip_cs1_params         @  do not use cs1 params
+        ldr     r4, [sp, #72]
+        str     r4, omap_sdrc_actim_ctrl_a_1_val
+        ldr     r4, [sp, #76]
+        str     r4, omap_sdrc_actim_ctrl_b_1_val
+        ldr     r4, [sp, #80]
+        str     r4, omap_sdrc_mr_1_val
+skip_cs1_params:
         dsb                             @ flush buffered writes to interconnect
-        cmp     r7, #1                  @ if increasing SDRC clk rate,
+
+        cmp     r3, #1                  @ if increasing SDRC clk rate,
         bleq    configure_sdrc          @ program the SDRC regs early (for RFR)
-        cmp     r4, #SDRC_UNLOCK_DLL    @ set the intended DLL state
+        cmp     r1, #SDRC_UNLOCK_DLL    @ set the intended DLL state
         bleq    unlock_dll
         blne    lock_dll
         bl      sdram_in_selfrefresh    @ put SDRAM in self refresh, idle SDRC
         bl      configure_core_dpll     @ change the DPLL3 M2 divider
+        mov     r12, r2
+        bl      wait_clk_stable         @ wait for SDRC to stabilize
         bl      enable_sdrc             @ take SDRC out of idle
-        cmp     r4, #SDRC_UNLOCK_DLL    @ wait for DLL status to change
+        cmp     r1, #SDRC_UNLOCK_DLL    @ wait for DLL status to change
         bleq    wait_dll_unlock
         blne    wait_dll_lock
-        cmp     r7, #1                  @ if increasing SDRC clk rate,
+        cmp     r3, #1                  @ if increasing SDRC clk rate,
         beq     return_to_sdram         @ return to SDRAM code, otherwise,
         bl      configure_sdrc          @ reprogram SDRC regs now
-        mov     r12, r5
-        bl      wait_clk_stable         @ wait for SDRC to stabilize
 return_to_sdram:
         isb                             @ prevent speculative exec past here
         mov     r0, #0                  @ return value
@@ -113,7 +143,7 @@ return_to_sdram:
 unlock_dll:
         ldr     r11, omap3_sdrc_dlla_ctrl
         ldr     r12, [r11]
-        and     r12, r12, #FIXEDDELAY_MASK
+        bic     r12, r12, #FIXEDDELAY_MASK
         orr     r12, r12, #FIXEDDELAY_DEFAULT
         orr     r12, r12, #DLLIDLE_MASK
         str     r12, [r11]              @ (no OCP barrier needed)
@@ -129,7 +159,6 @@ sdram_in_selfrefresh:
         ldr     r12, [r11]              @ read the contents of SDRC_POWER
         mov     r9, r12                 @ keep a copy of SDRC_POWER bits
         orr     r12, r12, #SRFRONIDLEREQ_MASK   @ enable self refresh on idle
-        bic     r12, r12, #PWDENA_MASK  @ clear PWDENA
         str     r12, [r11]              @ write back to SDRC_POWER register
         ldr     r12, [r11]              @ posted-write barrier for SDRC
 idle_sdrc:
@@ -149,7 +178,7 @@ configure_core_dpll:
         ldr     r12, [r11]
         ldr     r10, core_m2_mask_val   @ modify m2 for core dpll
         and     r12, r12, r10
-        orr     r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
+        orr     r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
         str     r12, [r11]
         ldr     r12, [r11]              @ posted-write barrier for CM
         bx      lr
@@ -187,15 +216,34 @@ wait_dll_unlock:
         bne     wait_dll_unlock
         bx      lr
 configure_sdrc:
-        ldr     r11, omap3_sdrc_rfr_ctrl
-        str     r0, [r11]
-        ldr     r11, omap3_sdrc_actim_ctrla
-        str     r1, [r11]
-        ldr     r11, omap3_sdrc_actim_ctrlb
-        str     r2, [r11]
+        ldr     r12, omap_sdrc_rfr_ctrl_0_val   @ fetch value from SRAM
+        ldr     r11, omap3_sdrc_rfr_ctrl_0      @ fetch addr from SRAM
+        str     r12, [r11]                      @ store
+        ldr     r12, omap_sdrc_actim_ctrl_a_0_val
+        ldr     r11, omap3_sdrc_actim_ctrl_a_0
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_actim_ctrl_b_0_val
+        ldr     r11, omap3_sdrc_actim_ctrl_b_0
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_mr_0_val
         ldr     r11, omap3_sdrc_mr_0
-        str     r6, [r11]
-        ldr     r6, [r11]               @ posted-write barrier for SDRC
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_rfr_ctrl_1_val
+        cmp     r12, #0                 @ if SDRC_RFR_CTRL_1 is 0,
+        beq     skip_cs1_prog           @  do not program cs1 params
+        ldr     r11, omap3_sdrc_rfr_ctrl_1
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_actim_ctrl_a_1_val
+        ldr     r11, omap3_sdrc_actim_ctrl_a_1
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_actim_ctrl_b_1_val
+        ldr     r11, omap3_sdrc_actim_ctrl_b_1
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_mr_1_val
+        ldr     r11, omap3_sdrc_mr_1
+        str     r12, [r11]
+skip_cs1_prog:
+        ldr     r12, [r11]              @ posted-write barrier for SDRC
         bx      lr
 
 omap3_sdrc_power:
@@ -206,14 +254,40 @@ omap3_cm_idlest1_core:
         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
 omap3_cm_iclken1_core:
         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
-omap3_sdrc_rfr_ctrl:
+
+omap3_sdrc_rfr_ctrl_0:
         .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap3_sdrc_actim_ctrla:
+omap3_sdrc_rfr_ctrl_1:
+        .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
+omap3_sdrc_actim_ctrl_a_0:
         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
-omap3_sdrc_actim_ctrlb:
+omap3_sdrc_actim_ctrl_a_1:
+        .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
+omap3_sdrc_actim_ctrl_b_0:
         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
+omap3_sdrc_actim_ctrl_b_1:
+        .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
 omap3_sdrc_mr_0:
         .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
+omap3_sdrc_mr_1:
+        .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
+omap_sdrc_rfr_ctrl_0_val:
+        .word 0xDEADBEEF
+omap_sdrc_rfr_ctrl_1_val:
+        .word 0xDEADBEEF
+omap_sdrc_actim_ctrl_a_0_val:
+        .word 0xDEADBEEF
+omap_sdrc_actim_ctrl_a_1_val:
+        .word 0xDEADBEEF
+omap_sdrc_actim_ctrl_b_0_val:
+        .word 0xDEADBEEF
+omap_sdrc_actim_ctrl_b_1_val:
+        .word 0xDEADBEEF
+omap_sdrc_mr_0_val:
+        .word 0xDEADBEEF
+omap_sdrc_mr_1_val:
+        .word 0xDEADBEEF
+
 omap3_sdrc_dlla_status:
         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 omap3_sdrc_dlla_ctrl:
@@ -223,3 +297,4 @@ core_m2_mask_val:
 
 ENTRY(omap3_sram_configure_core_dpll_sz)
         .word   . - omap3_sram_configure_core_dpll
+
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index d85296dc896c..739e59e8025c 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -155,20 +155,6 @@ static struct platform_device musb_device = {
         .resource       = musb_resources,
 };
 
-#ifdef CONFIG_NOP_USB_XCEIV
-static u64 nop_xceiv_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device nop_xceiv_device = {
-        .name           = "nop_usb_xceiv",
-        .id             = -1,
-        .dev = {
-                .dma_mask               = &nop_xceiv_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data          = NULL,
-        },
-};
-#endif
-
 void __init usb_musb_init(void)
 {
         if (cpu_is_omap243x())
@@ -183,13 +169,6 @@ void __init usb_musb_init(void)
          */
         musb_plat.clock = "ick";
 
-#ifdef CONFIG_NOP_USB_XCEIV
-        if (platform_device_register(&nop_xceiv_device) < 0) {
-                printk(KERN_ERR "Unable to register NOP-XCEIV device\n");
-                return;
-        }
-#endif
-
         if (platform_device_register(&musb_device) < 0) {
                 printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n");
                 return;
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 63b10d9bb1d3..9cd09465a0e8 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -1141,12 +1141,16 @@ struct power_supply_info em_x270_psy_info = {
 
 static void em_x270_battery_low(void)
 {
+#if defined(CONFIG_APM_EMULATION)
         apm_queue_event(APM_LOW_BATTERY);
+#endif
 }
 
 static void em_x270_battery_critical(void)
 {
+#if defined(CONFIG_APM_EMULATION)
         apm_queue_event(APM_CRITICAL_SUSPEND);
+#endif
 }
 
 struct da9030_battery_info em_x270_batterty_info = {
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
index ae8441192ef0..7139e0dc26d1 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
@@ -567,9 +567,9 @@
 #define GPIO37_ULPI_DATA_OUT_7  MFP_CFG(GPIO37, AF3)
 #define GPIO33_ULPI_OTG_INTR    MFP_CFG(GPIO33, AF1)
 
-#define ULPI_DIR        MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X)
-#define ULPI_NXT        MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X)
-#define ULPI_STP        MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X)
+#define ULPI_DIR        MFP_CFG_DRV(ULPI_DIR, AF0, DS01X)
+#define ULPI_NXT        MFP_CFG_DRV(ULPI_NXT, AF0, DS01X)
+#define ULPI_STP        MFP_CFG_DRV(ULPI_STP, AF0, DS01X)
 #endif /* CONFIG_CPU_PXA310 */
 
 #endif /* __ASM_ARCH_MFP_PXA300_H */
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index ed70f281dd09..169fcc18154e 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -128,6 +128,10 @@ static unsigned long palmld_pin_config[] __initdata = {
         GPIO38_GPIO,    /* wifi ready */
         GPIO81_GPIO,    /* wifi reset */
 
+        /* FFUART */
+        GPIO34_FFUART_RXD,
+        GPIO39_FFUART_TXD,
+
         /* HDD */
         GPIO98_GPIO,    /* HDD reset */
         GPIO115_GPIO,   /* HDD power */
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index aae64a12a734..33f726ff55e5 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -111,6 +111,10 @@ static unsigned long palmt5_pin_config[] __initdata = {
         /* PWM */
         GPIO16_PWM0_OUT,
 
+        /* FFUART */
+        GPIO34_FFUART_RXD,
+        GPIO39_FFUART_TXD,
+
         /* MISC */
         GPIO10_GPIO,    /* hotsync button */
         GPIO90_GPIO,    /* power detect */
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 6c15d84bde53..83d020879581 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -127,6 +127,10 @@ static unsigned long palmtx_pin_config[] __initdata = {
         GPIO76_LCD_PCLK,
         GPIO77_LCD_BIAS,
 
+        /* FFUART */
+        GPIO34_FFUART_RXD,
+        GPIO39_FFUART_TXD,
+
         /* MISC. */
         GPIO10_GPIO,    /* hotsync button */
         GPIO12_GPIO,    /* power detect */
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 6f678d93bf4e..09b7b1a10cad 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -250,7 +250,7 @@ static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
 static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
         /* Power I2C clock is always on */
-        INIT_CLKREG(&clk_dummy, "pxa2xx-i2c.1", NULL),
+        INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
         INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
         INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
         INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
diff --git a/arch/arm/mach-pxa/treo680.c b/arch/arm/mach-pxa/treo680.c
index a06f19edebb3..753ec4df17b9 100644
--- a/arch/arm/mach-pxa/treo680.c
+++ b/arch/arm/mach-pxa/treo680.c
@@ -409,7 +409,7 @@ err1:
 
 static void treo680_irda_shutdown(struct device *dev)
 {
-        gpio_free(GPIO_NR_TREO680_AMP_EN);
+        gpio_free(GPIO_NR_TREO680_IR_EN);
 }
 
 static struct pxaficp_platform_data treo680_ficp_info = {
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index cefd1c0a854a..84095440a878 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -197,10 +197,12 @@ static void __init zylonite_detect_lcd_panel(void)
         for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
                 id = id << 1;
                 gpio = mfp_to_gpio(lcd_detect_pins[i]);
+                gpio_request(gpio, "LCD_ID_PINS");
                 gpio_direction_input(gpio);
 
                 if (gpio_get_value(gpio))
                         id = id | 0x1;
+                gpio_free(gpio);
         }
 
         /* lcd id, flush out bit 1 */
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
index cc5a22833605..60d08f23f5e4 100644
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -176,10 +176,12 @@ static void __init zylonite_detect_lcd_panel(void)
         for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
                 id = id << 1;
                 gpio = mfp_to_gpio(lcd_detect_pins[i]);
+                gpio_request(gpio, "LCD_ID_PINS");
                 gpio_direction_input(gpio);
 
                 if (gpio_get_value(gpio))
                         id = id | 0x1;
+                gpio_free(gpio);
         }
 
         /* lcd id, flush out bit 1 */
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 9ea9c05093cd..facbd49eec67 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -208,8 +208,7 @@ struct platform_device realview_i2c_device = {
 
 static struct i2c_board_info realview_i2c_board_info[] = {
         {
-                I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1),
-                .type = "ds1338",
+                I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
         },
 };
 
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
index 8fe192081d3a..f8b879a7973c 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-core.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
@@ -28,7 +28,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
                 return NULL;
 
         chip = &s3c24xx_gpios[pin/32];
-        return (S3C2410_GPIO_OFFSET(pin) > chip->chip.ngpio) ? chip : NULL;
+        return (S3C2410_GPIO_OFFSET(pin) < chip->chip.ngpio) ? chip : NULL;
 }
 
 #endif /* __ASM_ARCH_GPIO_CORE_H */
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 89b3ccf35e1b..2e9b8ccd8ec2 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -455,8 +455,8 @@ void __init u300_init_irq(void)
         for (i = 0; i < NR_IRQS; i++)
                 set_bit(i, (unsigned long *) &mask[0]);
         u300_enable_intcon_clock();
-        vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], 0);
-        vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], 0);
+        vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
+        vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
 }
 
 
@@ -510,7 +510,7 @@ static struct db_chip db_chips[] __initdata = {
         }
 };
 
-static void u300_init_check_chip(void)
+static void __init u300_init_check_chip(void)
 {
 
         u16 val;
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 69214fc8bd19..31093af7d052 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -342,8 +342,7 @@ static struct platform_device versatile_i2c_device = {
 
 static struct i2c_board_info versatile_i2c_board_info[] = {
         {
-                I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1),
-                .type = "ds1338",
+                I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
         },
 };
 
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 8277802ec859..3a7279c1ce5e 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -120,6 +120,32 @@ void show_mem(void)
         printk("%d pages swap cached\n", cached);
 }
 
+static void __init find_node_limits(int node, struct meminfo *mi,
+        unsigned long *min, unsigned long *max_low, unsigned long *max_high)
+{
+        int i;
+
+        *min = -1UL;
+        *max_low = *max_high = 0;
+
+        for_each_nodebank(i, mi, node) {
+                struct membank *bank = &mi->bank[i];
+                unsigned long start, end;
+
+                start = bank_pfn_start(bank);
+                end = bank_pfn_end(bank);
+
+                if (*min > start)
+                        *min = start;
+                if (*max_high < end)
+                        *max_high = end;
+                if (bank->highmem)
+                        continue;
+                if (*max_low < end)
+                        *max_low = end;
+        }
+}
+
 /*
  * FIXME: We really want to avoid allocating the bootmap bitmap
  * over the top of the initrd.  Hopefully, this is located towards
@@ -210,41 +236,25 @@ static inline void map_memory_bank(struct membank *bank)
 #endif
 }
 
-static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
+static void __init bootmem_init_node(int node, struct meminfo *mi,
+        unsigned long start_pfn, unsigned long end_pfn)
 {
-        unsigned long start_pfn, end_pfn, boot_pfn;
+        unsigned long boot_pfn;
         unsigned int boot_pages;
         pg_data_t *pgdat;
         int i;
 
-        start_pfn = -1UL;
-        end_pfn = 0;
-
         /*
-         * Calculate the pfn range, and map the memory banks for this node.
+         * Map the memory banks for this node.
          */
         for_each_nodebank(i, mi, node) {
                 struct membank *bank = &mi->bank[i];
-                unsigned long start, end;
 
-                start = bank_pfn_start(bank);
-                end = bank_pfn_end(bank);
-
-                if (start_pfn > start)
-                        start_pfn = start;
-                if (end_pfn < end)
-                        end_pfn = end;
-
-                map_memory_bank(bank);
+                if (!bank->highmem)
+                        map_memory_bank(bank);
         }
 
         /*
-         * If there is no memory in this node, ignore it.
-         */
-        if (end_pfn == 0)
-                return end_pfn;
-
-        /*
          * Allocate the bootmem bitmap page.
          */
         boot_pages = bootmem_bootmap_pages(end_pfn - start_pfn);
@@ -260,7 +270,8 @@ static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
 
         for_each_nodebank(i, mi, node) {
                 struct membank *bank = &mi->bank[i];
-                free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
+                if (!bank->highmem)
+                        free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
                 memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank));
         }
 
@@ -269,8 +280,6 @@ static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
          */
         reserve_bootmem_node(pgdat, boot_pfn << PAGE_SHIFT,
                              boot_pages << PAGE_SHIFT, BOOTMEM_DEFAULT);
-
-        return end_pfn;
 }
 
 static void __init bootmem_reserve_initrd(int node)
@@ -297,33 +306,39 @@ static void __init bootmem_reserve_initrd(int node)
 static void __init bootmem_free_node(int node, struct meminfo *mi)
 {
         unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
-        unsigned long start_pfn, end_pfn;
-        pg_data_t *pgdat = NODE_DATA(node);
+        unsigned long min, max_low, max_high;
         int i;
 
-        start_pfn = pgdat->bdata->node_min_pfn;
-        end_pfn = pgdat->bdata->node_low_pfn;
+        find_node_limits(node, mi, &min, &max_low, &max_high);
 
         /*
          * initialise the zones within this node.
          */
         memset(zone_size, 0, sizeof(zone_size));
-        memset(zhole_size, 0, sizeof(zhole_size));
 
         /*
          * The size of this node has already been determined.  If we need
          * to do anything fancy with the allocation of this memory to the
          * zones, now is the time to do it.
          */
-        zone_size[0] = end_pfn - start_pfn;
+        zone_size[0] = max_low - min;
+#ifdef CONFIG_HIGHMEM
+        zone_size[ZONE_HIGHMEM] = max_high - max_low;
+#endif
 
         /*
          * For each bank in this node, calculate the size of the holes.
          *  holes = node_size - sum(bank_sizes_in_node)
          */
-        zhole_size[0] = zone_size[0];
-        for_each_nodebank(i, mi, node)
-                zhole_size[0] -= bank_pfn_size(&mi->bank[i]);
+        memcpy(zhole_size, zone_size, sizeof(zhole_size));
+        for_each_nodebank(i, mi, node) {
+                int idx = 0;
+#ifdef CONFIG_HIGHMEM
+                if (mi->bank[i].highmem)
+                        idx = ZONE_HIGHMEM;
+#endif
+                zhole_size[idx] -= bank_pfn_size(&mi->bank[i]);
+        }
 
         /*
          * Adjust the sizes according to any special requirements for
@@ -331,13 +346,13 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
          */
         arch_adjust_zones(node, zone_size, zhole_size);
 
-        free_area_init_node(node, zone_size, start_pfn, zhole_size);
+        free_area_init_node(node, zone_size, min, zhole_size);
 }
 
 void __init bootmem_init(void)
 {
         struct meminfo *mi = &meminfo;
-        unsigned long memend_pfn = 0;
+        unsigned long min, max_low, max_high;
         int node, initrd_node;
 
         /*
@@ -345,11 +360,29 @@ void __init bootmem_init(void)
          */
         initrd_node = check_initrd(mi);
 
+        max_low = max_high = 0;
+
         /*
          * Run through each node initialising the bootmem allocator.
          */
         for_each_node(node) {
-                unsigned long end_pfn = bootmem_init_node(node, mi);
+                unsigned long node_low, node_high;
+
+                find_node_limits(node, mi, &min, &node_low, &node_high);
+
+                if (node_low > max_low)
+                        max_low = node_low;
+                if (node_high > max_high)
+                        max_high = node_high;
+
+                /*
+                 * If there is no memory in this node, ignore it.
+                 * (We can't have nodes which have no lowmem)
+                 */
+                if (node_low == 0)
+                        continue;
+
+                bootmem_init_node(node, mi, min, node_low);
 
                 /*
                  * Reserve any special node zero regions.
@@ -362,12 +395,6 @@ void __init bootmem_init(void)
                  */
                 if (node == initrd_node)
                         bootmem_reserve_initrd(node);
-
-                /*
-                 * Remember the highest memory PFN.
-                 */
-                if (end_pfn > memend_pfn)
-                        memend_pfn = end_pfn;
         }
 
         /*
@@ -383,7 +410,7 @@ void __init bootmem_init(void)
         for_each_node(node)
                 bootmem_free_node(node, mi);
 
-        high_memory = __va((memend_pfn << PAGE_SHIFT) - 1) + 1;
+        high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1;
 
         /*
          * This doesn't seem to be used by the Linux memory manager any
@@ -393,7 +420,8 @@ void __init bootmem_init(void)
          * Note: max_low_pfn and max_pfn reflect the number of _pages_ in
          * the system, not the maximum PFN.
          */
-        max_pfn = max_low_pfn = memend_pfn - PHYS_PFN_OFFSET;
+        max_low_pfn = max_low - PHYS_PFN_OFFSET;
+        max_pfn = max_high - PHYS_PFN_OFFSET;
 }
 
 static inline int free_area(unsigned long pfn, unsigned long end, char *s)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4722582b17b8..4426ee67ceca 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -687,13 +687,19 @@ __early_param("vmalloc=", early_vmalloc);
 
 static void __init sanity_check_meminfo(void)
 {
-        int i, j;
+        int i, j, highmem = 0;
 
         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
                 struct membank *bank = &meminfo.bank[j];
                 *bank = meminfo.bank[i];
 
 #ifdef CONFIG_HIGHMEM
+                if (__va(bank->start) > VMALLOC_MIN ||
+                    __va(bank->start) < (void *)PAGE_OFFSET)
+                        highmem = 1;
+
+                bank->highmem = highmem;
+
                 /*
                  * Split those memory banks which are partially overlapping
                  * the vmalloc area greatly simplifying things later.
@@ -714,6 +720,7 @@ static void __init sanity_check_meminfo(void)
                                 i++;
                                 bank[1].size -= VMALLOC_MIN - __va(bank->start);
                                 bank[1].start = __pa(VMALLOC_MIN - 1) + 1;
+                                bank[1].highmem = highmem = 1;
                                 j++;
                         }
                         bank->size = VMALLOC_MIN - __va(bank->start);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 27f8d1b2bc6b..2eb182f73876 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -602,6 +602,8 @@ enum iomux_pins {
 #define MX31_PIN_I2C_DAT__SDA           IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_DCD_DTE1__I2C2_SDA     IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_RI_DTE1__I2C2_SCL      IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
+#define MX31_PIN_CSPI2_SS2__I2C3_SDA    IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI2_SCLK__I2C3_SCL   IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT1)
 #define MX31_PIN_CSI_D4__CSI_D4         IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_CSI_D5__CSI_D5         IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_CSI_D6__CSI_D6         IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC)
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 843e8af64066..1868c0d8f9b5 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -78,10 +78,10 @@ static int omap_target(struct cpufreq_policy *policy,
 
         /* Ensure desired rate is within allowed range.  Some govenors
          * (ondemand) will just pass target_freq=0 to get the minimum. */
-        if (target_freq < policy->cpuinfo.min_freq)
-                target_freq = policy->cpuinfo.min_freq;
-        if (target_freq > policy->cpuinfo.max_freq)
-                target_freq = policy->cpuinfo.max_freq;
+        if (target_freq < policy->min)
+                target_freq = policy->min;
+        if (target_freq > policy->max)
+                target_freq = policy->max;
 
         freqs.old = omap_getspeed(0);
         freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7677a4a1cef2..e3ac94f09006 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -946,7 +946,9 @@ void omap_start_dma(int lch)
 
                         cur_lch = next_lch;
                 } while (next_lch != -1);
-        } else if (cpu_class_is_omap2()) {
+        } else if (cpu_is_omap242x() ||
+                (cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {
+
                 /* Errata: Need to write lch even if not using chaining */
                 dma_write(lch, CLNK_CTRL(lch));
         }
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 26b387c12423..9298bc0ab171 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -476,14 +476,12 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
         __raw_writel(l, reg);
 }
 
-static int __omap_get_gpio_datain(int gpio)
+static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
 {
-        struct gpio_bank *bank;
         void __iomem *reg;
 
         if (check_gpio(gpio) < 0)
                 return -EINVAL;
-        bank = get_gpio_bank(gpio);
         reg = bank->base;
         switch (bank->method) {
 #ifdef CONFIG_ARCH_OMAP1
@@ -524,6 +522,53 @@ static int __omap_get_gpio_datain(int gpio)
                         & (1 << get_gpio_index(gpio))) != 0;
 }
 
+static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
+{
+        void __iomem *reg;
+
+        if (check_gpio(gpio) < 0)
+                return -EINVAL;
+        reg = bank->base;
+
+        switch (bank->method) {
+#ifdef CONFIG_ARCH_OMAP1
+        case METHOD_MPUIO:
+                reg += OMAP_MPUIO_OUTPUT;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP15XX
+        case METHOD_GPIO_1510:
+                reg += OMAP1510_GPIO_DATA_OUTPUT;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+        case METHOD_GPIO_1610:
+                reg += OMAP1610_GPIO_DATAOUT;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP730
+        case METHOD_GPIO_730:
+                reg += OMAP730_GPIO_DATA_OUTPUT;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP850
+        case METHOD_GPIO_850:
+                reg += OMAP850_GPIO_DATA_OUTPUT;
+                break;
+#endif
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                defined(CONFIG_ARCH_OMAP4)
+        case METHOD_GPIO_24XX:
+                reg += OMAP24XX_GPIO_DATAOUT;
+                break;
+#endif
+        default:
+                return -EINVAL;
+        }
+
+        return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
+}
+
 #define MOD_REG_BIT(reg, bit_mask, set) \
 do {    \
         int l = __raw_readl(base + reg); \
@@ -1189,6 +1234,7 @@ static void gpio_mask_irq(unsigned int irq)
         struct gpio_bank *bank = get_irq_chip_data(irq);
 
         _set_gpio_irqenable(bank, gpio, 0);
+        _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
 }
 
 static void gpio_unmask_irq(unsigned int irq)
@@ -1196,6 +1242,11 @@ static void gpio_unmask_irq(unsigned int irq)
         unsigned int gpio = irq - IH_GPIO_BASE;
         struct gpio_bank *bank = get_irq_chip_data(irq);
         unsigned int irq_mask = 1 << get_gpio_index(gpio);
+        struct irq_desc *desc = irq_to_desc(irq);
+        u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
+
+        if (trigger)
+                _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
 
         /* For level-triggered GPIOs, the clearing must be done after
          * the HW source is cleared, thus after the handler has run */
@@ -1350,9 +1401,49 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset)
         return 0;
 }
 
+static int gpio_is_input(struct gpio_bank *bank, int mask)
+{
+        void __iomem *reg = bank->base;
+
+        switch (bank->method) {
+        case METHOD_MPUIO:
+                reg += OMAP_MPUIO_IO_CNTL;
+                break;
+        case METHOD_GPIO_1510:
+                reg += OMAP1510_GPIO_DIR_CONTROL;
+                break;
+        case METHOD_GPIO_1610:
+                reg += OMAP1610_GPIO_DIRECTION;
+                break;
+        case METHOD_GPIO_730:
+                reg += OMAP730_GPIO_DIR_CONTROL;
+                break;
+        case METHOD_GPIO_850:
+                reg += OMAP850_GPIO_DIR_CONTROL;
+                break;
+        case METHOD_GPIO_24XX:
+                reg += OMAP24XX_GPIO_OE;
+                break;
+        }
+        return __raw_readl(reg) & mask;
+}
+
 static int gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        return __omap_get_gpio_datain(chip->base + offset);
+        struct gpio_bank *bank;
+        void __iomem *reg;
+        int gpio;
+        u32 mask;
+
+        gpio = chip->base + offset;
+        bank = get_gpio_bank(gpio);
+        reg = bank->base;
+        mask = 1 << get_gpio_index(gpio);
+
+        if (gpio_is_input(bank, mask))
+                return _get_gpio_datain(bank, gpio);
+        else
+                return _get_gpio_dataout(bank, gpio);
 }
 
 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
@@ -1886,34 +1977,6 @@ arch_initcall(omap_gpio_sysinit);
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 
-static int gpio_is_input(struct gpio_bank *bank, int mask)
-{
-        void __iomem *reg = bank->base;
-
-        switch (bank->method) {
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_IO_CNTL;
-                break;
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_DIRECTION;
-                break;
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_OE;
-                break;
-        }
-        return __raw_readl(reg) & mask;
-}
-
-
 static int dbg_gpio_show(struct seq_file *s, void *unused)
 {
         unsigned        i, j, gpio;
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index f9f65e1ba3f1..4b8b0d65cbf2 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -20,6 +20,8 @@ struct clockdomain;
 struct clkops {
         int                     (*enable)(struct clk *);
         void                    (*disable)(struct clk *);
+        void                    (*find_idlest)(struct clk *, void __iomem **, u8 *);
+        void                    (*find_companion)(struct clk *, void __iomem **, u8 *);
 };
 
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index 285eaa3a8275..11e73d9e8928 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -378,9 +378,6 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx() || \
                                 cpu_is_omap44xx())
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                        defined(CONFIG_ARCH_OMAP4)
-
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
 #define OMAP2420_REV_ES1_0      0x24200024
@@ -436,5 +433,3 @@ IS_OMAP_TYPE(3430, 0x3430)
 
 int omap_chip_is(struct omap_chip_id oci);
 void omap2_check_revision(void);
-
-#endif    /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index 73f483d56ca6..21fb0efdda86 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -228,7 +228,8 @@ extern void omap1_map_common_io(void);
 extern void omap1_init_common_hw(void);
 
 extern void omap2_map_common_io(void);
-extern void omap2_init_common_hw(struct omap_sdrc_params *sp);
+extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
+                                 struct omap_sdrc_params *sdrc_cs1);
 
 #define __arch_ioremap(p,s,t)   omap_ioremap(p,s,t)
 #define __arch_iounmap(v)       omap_iounmap(v)
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 85a621705766..80281c458baf 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -853,6 +853,10 @@ enum omap34xx_index {
         AE5_34XX_GPIO143,
         H19_34XX_GPIO164_OUT,
         J25_34XX_GPIO170,
+
+        /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
+        H16_34XX_SDRC_CKE0,
+        H17_34XX_SDRC_CKE1,
 };
 
 struct omap_mux_cfg {
diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/mach/prcm.h
index 24ac3c715912..cda2a70397b4 100644
--- a/arch/arm/plat-omap/include/mach/prcm.h
+++ b/arch/arm/plat-omap/include/mach/prcm.h
@@ -25,6 +25,7 @@
 
 u32 omap_prcm_get_reset_sources(void);
 void omap_prcm_arch_reset(char mode);
+int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
 
 #endif
 
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index adc73522491f..0be18e4ff182 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -30,6 +30,10 @@
 #define SDRC_ACTIM_CTRL_A_0     0x09c
 #define SDRC_ACTIM_CTRL_B_0     0x0a0
 #define SDRC_RFR_CTRL_0         0x0a4
+#define SDRC_MR_1               0x0B4
+#define SDRC_ACTIM_CTRL_A_1     0x0C4
+#define SDRC_ACTIM_CTRL_B_1     0x0C8
+#define SDRC_RFR_CTRL_1         0x0D4
 
 /*
  * These values represent the number of memory clock cycles between
@@ -102,8 +106,11 @@ struct omap_sdrc_params {
         u32 mr;
 };
 
-void __init omap2_sdrc_init(struct omap_sdrc_params *sp);
-struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
+void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                            struct omap_sdrc_params *sdrc_cs1);
+int omap2_sdrc_get_params(unsigned long r,
+                          struct omap_sdrc_params **sdrc_cs0,
+                          struct omap_sdrc_params **sdrc_cs1);
 
 #ifdef CONFIG_ARCH_OMAP2
 
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
index 13abd02d1527..def0529c75eb 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -59,6 +59,7 @@ extern void omap_uart_check_wakeup(void);
 extern void omap_uart_prepare_suspend(void);
 extern void omap_uart_prepare_idle(int num);
 extern void omap_uart_resume_idle(int num);
+extern void omap_uart_enable_irqs(int enable);
 #endif
 
 #endif
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index 4d53cc59d7a3..8974e3fc2691 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -21,11 +21,12 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
                                       u32 mem_type);
 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 
-extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
-                                     u32 sdrc_actim_ctrla,
-                                     u32 sdrc_actim_ctrlb, u32 m2,
-                                     u32 unlock_dll, u32 f, u32 sdrc_mr,
-                                     u32 inc);
+extern u32 omap3_configure_core_dpll(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 
 /* Do not use these */
 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -59,12 +60,12 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
                                                 u32 mem_type);
 extern unsigned long omap243x_sram_reprogram_sdrc_sz;
 
-
-extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
-                                          u32 sdrc_actim_ctrla,
-                                          u32 sdrc_actim_ctrlb, u32 m2,
-                                          u32 unlock_dll, u32 f, u32 sdrc_mr,
-                                          u32 inc);
+extern u32 omap3_sram_configure_core_dpll(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
 
 #endif
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 4ea73804d21e..5eae7876979c 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -44,9 +44,9 @@
 #define OMAP2_SRAM_VA           0xe3000000
 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
 #define OMAP3_SRAM_PA           0x40200000
-#define OMAP3_SRAM_VA           0xd7000000
+#define OMAP3_SRAM_VA           0xe3000000
 #define OMAP3_SRAM_PUB_PA       0x40208000
-#define OMAP3_SRAM_PUB_VA       0xd7008000
+#define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
 #define OMAP4_SRAM_PA           0x40200000              /*0x402f0000*/
 #define OMAP4_SRAM_VA           0xd7000000              /*0xd70f0000*/
 
@@ -373,20 +373,26 @@ static inline int omap243x_sram_init(void)
 
 #ifdef CONFIG_ARCH_OMAP3
 
-static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
-                                              u32 sdrc_actim_ctrla,
-                                              u32 sdrc_actim_ctrlb,
-                                              u32 m2, u32 unlock_dll,
-                                              u32 f, u32 sdrc_mr, u32 inc);
-u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
-                              u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
-                              u32 f, u32 sdrc_mr, u32 inc)
+static u32 (*_omap3_sram_configure_core_dpll)(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+
+u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 {
         BUG_ON(!_omap3_sram_configure_core_dpll);
-        return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
-                                               sdrc_actim_ctrla,
-                                               sdrc_actim_ctrlb, m2,
-                                               unlock_dll, f, sdrc_mr, inc);
+        return _omap3_sram_configure_core_dpll(
+                        m2, unlock_dll, f, inc,
+                        sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
+                        sdrc_actim_ctrl_b_0, sdrc_mr_0,
+                        sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
+                        sdrc_actim_ctrl_b_1, sdrc_mr_1);
 }
 
 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 9646a94ed3d0..07c430fdc9ef 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -11,6 +11,8 @@
 #ifndef __PLAT_GPIO_H
 #define __PLAT_GPIO_H
 
+#include <linux/init.h>
+
 /*
  * GENERIC_GPIO primitives.
  */
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
index abc79d44acaa..98548c6903a0 100644
--- a/arch/arm/plat-pxa/gpio.c
+++ b/arch/arm/plat-pxa/gpio.c
@@ -16,7 +16,7 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/sysdev.h>
-#include <linux/bootmem.h>
+#include <linux/slab.h>
 
 #include <mach/gpio.h>
 
@@ -112,17 +112,12 @@ static int __init pxa_init_gpio_chip(int gpio_end)
         int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
         struct pxa_gpio_chip *chips;
 
-        /* this is early, we have to use bootmem allocator, and we really
-         * want this to be allocated dynamically for different 'gpio_end'
-         */
-        chips = alloc_bootmem_low(nbanks * sizeof(struct pxa_gpio_chip));
+        chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
         if (chips == NULL) {
                 pr_err("%s: failed to allocate GPIO chips\n", __func__);
                 return -ENOMEM;
         }
 
-        memset(chips, 0, nbanks * sizeof(struct pxa_gpio_chip));
-
         for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
                 struct gpio_chip *c = &chips[i].chip;
 
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index 5b75a797b5ab..0afb217a775e 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -129,7 +129,7 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
 
         /* calculate the MISCCR setting for the clock */
 
-        if (parent == &clk_xtal)
+        if (parent == &clk_mpll)
                 source = S3C2410_MISCCR_CLK0_MPLL;
         else if (parent == &clk_upll)
                 source = S3C2410_MISCCR_CLK0_UPLL;
diff --git a/arch/arm/plat-s3c24xx/pwm.c b/arch/arm/plat-s3c24xx/pwm.c
index 0120b760315b..82a6d4de02a3 100644
--- a/arch/arm/plat-s3c24xx/pwm.c
+++ b/arch/arm/plat-s3c24xx/pwm.c
@@ -246,6 +246,10 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 
         tcmp = duty_ns / tin_ns;
         tcmp = tcnt - tcmp;
+        /* the pwm hw only checks the compare register after a decrement,
+           so the pin never toggles if tcmp = tcnt */
+        if (tcmp == tcnt)
+                tcmp--;
 
         pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
 
diff --git a/arch/arm/plat-s3c64xx/pm.c b/arch/arm/plat-s3c64xx/pm.c
index 07a6516a4f3c..47632fc7eb66 100644
--- a/arch/arm/plat-s3c64xx/pm.c
+++ b/arch/arm/plat-s3c64xx/pm.c
@@ -117,8 +117,6 @@ void s3c_pm_save_core(void)
  * this.
  */
 
-#include <plat/regs-gpio.h>
-
 static void s3c64xx_cpu_suspend(void)
 {
         unsigned long tmp;
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 1debc1f9f987..febac1950d8e 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -153,7 +153,7 @@ static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
         u32 div;
 
         if (parent < rate)
-                return rate;
+                return parent;
 
         div = (parent / rate) - 1;
         if (div > armclk_mask)
@@ -175,7 +175,7 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
         div = clk_get_rate(clk->parent) / rate;
 
         val = __raw_readl(S3C_CLK_DIV0);
-        val &= armclk_mask;
+        val &= ~armclk_mask;
         val |= (div - 1);
         __raw_writel(val, S3C_CLK_DIV0);
 
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c
index d41200382208..6d6b1a468eda 100644
--- a/arch/arm/plat-stmp3xxx/pinmux.c
+++ b/arch/arm/plat-stmp3xxx/pinmux.c
@@ -22,7 +22,6 @@
 #include <linux/sysdev.h>
 #include <linux/string.h>
 #include <linux/bitops.h>
-#include <linux/sysdev.h>
 #include <linux/irq.h>
 
 #include <mach/hardware.h>