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authorDavid S. Miller <davem@davemloft.net>2014-09-08 00:41:53 -0400
committerDavid S. Miller <davem@davemloft.net>2014-09-08 00:41:53 -0400
commiteb84d6b60491a3ca3d90d62ee5346b007770d40d (patch)
tree22aadf9ada15e1ae5ba4c400aafab6f2541996e6 /arch/arm
parent97a13e5289baa96eaddd06e61d277457d837af3a (diff)
parentd030671f3f261e528dc6e396a13f10859a74ae7c (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/dts/am4372.dtsi4
-rw-r--r--arch/arm/boot/dts/am437x-gp-evm.dts6
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts9
-rw-r--r--arch/arm/boot/dts/at91rm9200.dtsi2
-rw-r--r--arch/arm/boot/dts/at91sam9g20.dtsi1
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts47
-rw-r--r--arch/arm/boot/dts/dra7.dtsi16
-rw-r--r--arch/arm/boot/dts/exynos4412-odroid-common.dtsi13
-rw-r--r--arch/arm/boot/dts/imx53-qsrb.dts8
-rw-r--r--arch/arm/boot/dts/imx53.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6dl-hummingboard.dts4
-rw-r--r--arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts3
-rw-r--r--arch/arm/boot/dts/imx6qdl-cubox-i.dtsi19
-rw-r--r--arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6sx-pinfunc.h26
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts1
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts2
-rw-r--r--arch/arm/boot/dts/omap3430-sdp.dts2
-rw-r--r--arch/arm/boot/dts/omap3xxx-clocks.dtsi1
-rw-r--r--arch/arm/boot/dts/omap54xx-clocks.dtsi16
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts7
-rw-r--r--arch/arm/boot/dts/rk3066a-bqcurie2.dts2
-rw-r--r--arch/arm/boot/dts/rk3188-radxarock.dts2
-rw-r--r--arch/arm/boot/dts/ste-snowball.dts1
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi8
-rw-r--r--arch/arm/boot/dts/tegra30-apalis.dtsi11
-rw-r--r--arch/arm/boot/dts/tegra30-colibri.dtsi11
-rw-r--r--arch/arm/boot/dts/twl6030.dtsi4
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts2
-rw-r--r--arch/arm/common/edma.c9
-rw-r--r--arch/arm/include/asm/cacheflush.h1
-rw-r--r--arch/arm/include/asm/cputype.h3
-rw-r--r--arch/arm/include/asm/elf.h1
-rw-r--r--arch/arm/include/asm/smp_plat.h15
-rw-r--r--arch/arm/kernel/entry-header.S29
-rw-r--r--arch/arm/kernel/module.c1
-rw-r--r--arch/arm/kvm/handle_exit.c2
-rw-r--r--arch/arm/kvm/init.S4
-rw-r--r--arch/arm/mach-at91/board-dt-rm9200.c11
-rw-r--r--arch/arm/mach-bcm/Makefile1
-rw-r--r--arch/arm/mach-bcm/brcmstb.h19
-rw-r--r--arch/arm/mach-bcm/headsmp-brcmstb.S33
-rw-r--r--arch/arm/mach-bcm/platsmp-brcmstb.c363
-rw-r--r--arch/arm/mach-exynos/mcpm-exynos.c1
-rw-r--r--arch/arm/mach-imx/Kconfig2
-rw-r--r--arch/arm/mach-imx/Makefile2
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c10
-rw-r--r--arch/arm/mach-imx/suspend-imx6.S2
-rw-r--r--arch/arm/mach-omap2/board-flash.c2
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c3
-rw-r--r--arch/arm/mach-omap2/gpmc.c14
-rw-r--r--arch/arm/mach-omap2/id.c2
-rw-r--r--arch/arm/mach-omap2/omap_device.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c7
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c22
-rw-r--r--arch/arm/mach-omap2/soc.h6
-rw-r--r--arch/arm/mach-shmobile/Kconfig2
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c4
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7791.c2
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c2
-rw-r--r--arch/arm/mach-vexpress/spc.c14
-rw-r--r--arch/arm/mm/abort-ev6.S6
-rw-r--r--arch/arm/mm/abort-ev7.S6
64 files changed, 286 insertions, 551 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c49a775937db..32cbbd565902 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1983,8 +1983,6 @@ config XIP_PHYS_ADDR
1983config KEXEC 1983config KEXEC
1984 bool "Kexec system call (EXPERIMENTAL)" 1984 bool "Kexec system call (EXPERIMENTAL)"
1985 depends on (!SMP || PM_SLEEP_SMP) 1985 depends on (!SMP || PM_SLEEP_SMP)
1986 select CRYPTO
1987 select CRYPTO_SHA256
1988 help 1986 help
1989 kexec is a system call that implements the ability to shutdown your 1987 kexec is a system call that implements the ability to shutdown your
1990 current kernel, and to start another kernel. It is like a reboot 1988 current kernel, and to start another kernel. It is like a reboot
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 9b3d2ba82f13..8689949bdba3 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -804,7 +804,7 @@
804 804
805 usb1: usb@48390000 { 805 usb1: usb@48390000 {
806 compatible = "synopsys,dwc3"; 806 compatible = "synopsys,dwc3";
807 reg = <0x48390000 0x17000>; 807 reg = <0x48390000 0x10000>;
808 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 808 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
809 phys = <&usb2_phy1>; 809 phys = <&usb2_phy1>;
810 phy-names = "usb2-phy"; 810 phy-names = "usb2-phy";
@@ -826,7 +826,7 @@
826 826
827 usb2: usb@483d0000 { 827 usb2: usb@483d0000 {
828 compatible = "synopsys,dwc3"; 828 compatible = "synopsys,dwc3";
829 reg = <0x483d0000 0x17000>; 829 reg = <0x483d0000 0x10000>;
830 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 830 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
831 phys = <&usb2_phy2>; 831 phys = <&usb2_phy2>;
832 phy-names = "usb2-phy"; 832 phy-names = "usb2-phy";
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 646a6eade788..e7ac47fa6615 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -260,7 +260,7 @@
260 status = "okay"; 260 status = "okay";
261 pinctrl-names = "default"; 261 pinctrl-names = "default";
262 pinctrl-0 = <&i2c0_pins>; 262 pinctrl-0 = <&i2c0_pins>;
263 clock-frequency = <400000>; 263 clock-frequency = <100000>;
264 264
265 tps65218: tps65218@24 { 265 tps65218: tps65218@24 {
266 reg = <0x24>; 266 reg = <0x24>;
@@ -424,7 +424,7 @@
424 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ 424 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
425 nand@0,0 { 425 nand@0,0 {
426 reg = <0 0 4>; /* device IO registers */ 426 reg = <0 0 4>; /* device IO registers */
427 ti,nand-ecc-opt = "bch8"; 427 ti,nand-ecc-opt = "bch16";
428 ti,elm-id = <&elm>; 428 ti,elm-id = <&elm>;
429 nand-bus-width = <8>; 429 nand-bus-width = <8>;
430 gpmc,device-width = <1>; 430 gpmc,device-width = <1>;
@@ -443,8 +443,6 @@
443 gpmc,rd-cycle-ns = <40>; 443 gpmc,rd-cycle-ns = <40>;
444 gpmc,wr-cycle-ns = <40>; 444 gpmc,wr-cycle-ns = <40>;
445 gpmc,wait-pin = <0>; 445 gpmc,wait-pin = <0>;
446 gpmc,wait-on-read;
447 gpmc,wait-on-write;
448 gpmc,bus-turnaround-ns = <0>; 446 gpmc,bus-turnaround-ns = <0>;
449 gpmc,cycle2cycle-delay-ns = <0>; 447 gpmc,cycle2cycle-delay-ns = <0>;
450 gpmc,clk-activation-ns = <0>; 448 gpmc,clk-activation-ns = <0>;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index ed7dd2395915..ac3e4859935f 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -435,13 +435,13 @@
435}; 435};
436 436
437&gpmc { 437&gpmc {
438 status = "okay"; 438 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
439 pinctrl-names = "default"; 439 pinctrl-names = "default";
440 pinctrl-0 = <&nand_flash_x8>; 440 pinctrl-0 = <&nand_flash_x8>;
441 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 441 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
442 nand@0,0 { 442 nand@0,0 {
443 reg = <0 0 0>; /* CS0, offset 0 */ 443 reg = <0 0 0>; /* CS0, offset 0 */
444 ti,nand-ecc-opt = "bch8"; 444 ti,nand-ecc-opt = "bch16";
445 ti,elm-id = <&elm>; 445 ti,elm-id = <&elm>;
446 nand-bus-width = <8>; 446 nand-bus-width = <8>;
447 gpmc,device-width = <1>; 447 gpmc,device-width = <1>;
@@ -459,8 +459,7 @@
459 gpmc,access-ns = <30>; /* tCEA + 4*/ 459 gpmc,access-ns = <30>; /* tCEA + 4*/
460 gpmc,rd-cycle-ns = <40>; 460 gpmc,rd-cycle-ns = <40>;
461 gpmc,wr-cycle-ns = <40>; 461 gpmc,wr-cycle-ns = <40>;
462 gpmc,wait-on-read = "true"; 462 gpmc,wait-pin = <0>;
463 gpmc,wait-on-write = "true";
464 gpmc,bus-turnaround-ns = <0>; 463 gpmc,bus-turnaround-ns = <0>;
465 gpmc,cycle2cycle-delay-ns = <0>; 464 gpmc,cycle2cycle-delay-ns = <0>;
466 gpmc,clk-activation-ns = <0>; 465 gpmc,clk-activation-ns = <0>;
@@ -557,7 +556,7 @@
557}; 556};
558 557
559&qspi { 558&qspi {
560 status = "okay"; 559 status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */
561 pinctrl-names = "default"; 560 pinctrl-names = "default";
562 pinctrl-0 = <&qspi1_default>; 561 pinctrl-0 = <&qspi1_default>;
563 562
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 65ccf564b9a5..6c97d4af61ee 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -149,7 +149,7 @@
149 usb: usbck { 149 usb: usbck {
150 compatible = "atmel,at91rm9200-clk-usb"; 150 compatible = "atmel,at91rm9200-clk-usb";
151 #clock-cells = <0>; 151 #clock-cells = <0>;
152 atmel,clk-divisors = <1 2>; 152 atmel,clk-divisors = <1 2 0 0>;
153 clocks = <&pllb>; 153 clocks = <&pllb>;
154 }; 154 };
155 155
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 31f7652612fc..4e0abbd9d655 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -40,6 +40,7 @@
40 }; 40 };
41 41
42 pllb: pllbck { 42 pllb: pllbck {
43 compatible = "atmel,at91sam9g20-clk-pllb";
43 atmel,clk-input-range = <2000000 32000000>; 44 atmel,clk-input-range = <2000000 32000000>;
44 atmel,pll-clk-output-ranges = <30000000 100000000 0 0>; 45 atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
45 }; 46 };
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 50f8022905a1..e03fbf3c6889 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -8,6 +8,7 @@
8/dts-v1/; 8/dts-v1/;
9 9
10#include "dra74x.dtsi" 10#include "dra74x.dtsi"
11#include <dt-bindings/gpio/gpio.h>
11 12
12/ { 13/ {
13 model = "TI DRA742"; 14 model = "TI DRA742";
@@ -24,9 +25,29 @@
24 regulator-min-microvolt = <3300000>; 25 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>; 26 regulator-max-microvolt = <3300000>;
26 }; 27 };
28
29 vtt_fixed: fixedregulator-vtt {
30 compatible = "regulator-fixed";
31 regulator-name = "vtt_fixed";
32 regulator-min-microvolt = <1350000>;
33 regulator-max-microvolt = <1350000>;
34 regulator-always-on;
35 regulator-boot-on;
36 enable-active-high;
37 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
38 };
27}; 39};
28 40
29&dra7_pmx_core { 41&dra7_pmx_core {
42 pinctrl-names = "default";
43 pinctrl-0 = <&vtt_pin>;
44
45 vtt_pin: pinmux_vtt_pin {
46 pinctrl-single,pins = <
47 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
48 >;
49 };
50
30 i2c1_pins: pinmux_i2c1_pins { 51 i2c1_pins: pinmux_i2c1_pins {
31 pinctrl-single,pins = < 52 pinctrl-single,pins = <
32 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */ 53 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
@@ -43,20 +64,19 @@
43 64
44 i2c3_pins: pinmux_i2c3_pins { 65 i2c3_pins: pinmux_i2c3_pins {
45 pinctrl-single,pins = < 66 pinctrl-single,pins = <
46 0x410 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */ 67 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
47 0x414 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */ 68 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
48 >; 69 >;
49 }; 70 };
50 71
51 mcspi1_pins: pinmux_mcspi1_pins { 72 mcspi1_pins: pinmux_mcspi1_pins {
52 pinctrl-single,pins = < 73 pinctrl-single,pins = <
53 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */ 74 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
54 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */ 75 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
55 0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */ 76 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
56 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ 77 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
57 0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs1 */ 78 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
58 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */ 79 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
59 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */
60 >; 80 >;
61 }; 81 };
62 82
@@ -284,7 +304,7 @@
284 status = "okay"; 304 status = "okay";
285 pinctrl-names = "default"; 305 pinctrl-names = "default";
286 pinctrl-0 = <&i2c3_pins>; 306 pinctrl-0 = <&i2c3_pins>;
287 clock-frequency = <3400000>; 307 clock-frequency = <400000>;
288}; 308};
289 309
290&mcspi1 { 310&mcspi1 {
@@ -483,7 +503,7 @@
483 reg = <0x001c0000 0x00020000>; 503 reg = <0x001c0000 0x00020000>;
484 }; 504 };
485 partition@7 { 505 partition@7 {
486 label = "NAND.u-boot-env"; 506 label = "NAND.u-boot-env.backup1";
487 reg = <0x001e0000 0x00020000>; 507 reg = <0x001e0000 0x00020000>;
488 }; 508 };
489 partition@8 { 509 partition@8 {
@@ -504,3 +524,8 @@
504&usb2_phy2 { 524&usb2_phy2 {
505 phy-supply = <&ldousb_reg>; 525 phy-supply = <&ldousb_reg>;
506}; 526};
527
528&gpio7 {
529 ti,no-reset-on-init;
530 ti,no-idle-on-init;
531};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 97f603c4483d..d678152db4cb 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -245,7 +245,7 @@
245 gpio-controller; 245 gpio-controller;
246 #gpio-cells = <2>; 246 #gpio-cells = <2>;
247 interrupt-controller; 247 interrupt-controller;
248 #interrupt-cells = <1>; 248 #interrupt-cells = <2>;
249 }; 249 };
250 250
251 gpio2: gpio@48055000 { 251 gpio2: gpio@48055000 {
@@ -256,7 +256,7 @@
256 gpio-controller; 256 gpio-controller;
257 #gpio-cells = <2>; 257 #gpio-cells = <2>;
258 interrupt-controller; 258 interrupt-controller;
259 #interrupt-cells = <1>; 259 #interrupt-cells = <2>;
260 }; 260 };
261 261
262 gpio3: gpio@48057000 { 262 gpio3: gpio@48057000 {
@@ -267,7 +267,7 @@
267 gpio-controller; 267 gpio-controller;
268 #gpio-cells = <2>; 268 #gpio-cells = <2>;
269 interrupt-controller; 269 interrupt-controller;
270 #interrupt-cells = <1>; 270 #interrupt-cells = <2>;
271 }; 271 };
272 272
273 gpio4: gpio@48059000 { 273 gpio4: gpio@48059000 {
@@ -278,7 +278,7 @@
278 gpio-controller; 278 gpio-controller;
279 #gpio-cells = <2>; 279 #gpio-cells = <2>;
280 interrupt-controller; 280 interrupt-controller;
281 #interrupt-cells = <1>; 281 #interrupt-cells = <2>;
282 }; 282 };
283 283
284 gpio5: gpio@4805b000 { 284 gpio5: gpio@4805b000 {
@@ -289,7 +289,7 @@
289 gpio-controller; 289 gpio-controller;
290 #gpio-cells = <2>; 290 #gpio-cells = <2>;
291 interrupt-controller; 291 interrupt-controller;
292 #interrupt-cells = <1>; 292 #interrupt-cells = <2>;
293 }; 293 };
294 294
295 gpio6: gpio@4805d000 { 295 gpio6: gpio@4805d000 {
@@ -300,7 +300,7 @@
300 gpio-controller; 300 gpio-controller;
301 #gpio-cells = <2>; 301 #gpio-cells = <2>;
302 interrupt-controller; 302 interrupt-controller;
303 #interrupt-cells = <1>; 303 #interrupt-cells = <2>;
304 }; 304 };
305 305
306 gpio7: gpio@48051000 { 306 gpio7: gpio@48051000 {
@@ -311,7 +311,7 @@
311 gpio-controller; 311 gpio-controller;
312 #gpio-cells = <2>; 312 #gpio-cells = <2>;
313 interrupt-controller; 313 interrupt-controller;
314 #interrupt-cells = <1>; 314 #interrupt-cells = <2>;
315 }; 315 };
316 316
317 gpio8: gpio@48053000 { 317 gpio8: gpio@48053000 {
@@ -322,7 +322,7 @@
322 gpio-controller; 322 gpio-controller;
323 #gpio-cells = <2>; 323 #gpio-cells = <2>;
324 interrupt-controller; 324 interrupt-controller;
325 #interrupt-cells = <1>; 325 #interrupt-cells = <2>;
326 }; 326 };
327 327
328 uart1: serial@4806a000 { 328 uart1: serial@4806a000 {
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 6d6d23c83d30..adadaf97ac01 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -134,6 +134,8 @@
134 i2c@13860000 { 134 i2c@13860000 {
135 pinctrl-0 = <&i2c0_bus>; 135 pinctrl-0 = <&i2c0_bus>;
136 pinctrl-names = "default"; 136 pinctrl-names = "default";
137 samsung,i2c-sda-delay = <100>;
138 samsung,i2c-max-bus-freq = <400000>;
137 status = "okay"; 139 status = "okay";
138 140
139 usb3503: usb3503@08 { 141 usb3503: usb3503@08 {
@@ -148,6 +150,10 @@
148 150
149 max77686: pmic@09 { 151 max77686: pmic@09 {
150 compatible = "maxim,max77686"; 152 compatible = "maxim,max77686";
153 interrupt-parent = <&gpx3>;
154 interrupts = <2 0>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&max77686_irq>;
151 reg = <0x09>; 157 reg = <0x09>;
152 #clock-cells = <1>; 158 #clock-cells = <1>;
153 159
@@ -368,4 +374,11 @@
368 samsung,pins = "gpx1-3"; 374 samsung,pins = "gpx1-3";
369 samsung,pin-pud = <0>; 375 samsung,pin-pud = <0>;
370 }; 376 };
377
378 max77686_irq: max77686-irq {
379 samsung,pins = "gpx3-2";
380 samsung,pin-function = <0>;
381 samsung,pin-pud = <0>;
382 samsung,pin-drv = <0>;
383 };
371}; 384};
diff --git a/arch/arm/boot/dts/imx53-qsrb.dts b/arch/arm/boot/dts/imx53-qsrb.dts
index f1bbf9a32991..82d623d05915 100644
--- a/arch/arm/boot/dts/imx53-qsrb.dts
+++ b/arch/arm/boot/dts/imx53-qsrb.dts
@@ -28,6 +28,12 @@
28 MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec 28 MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
29 >; 29 >;
30 }; 30 };
31
32 pinctrl_pmic: pmicgrp {
33 fsl,pins = <
34 MX53_PAD_CSI0_DAT5__GPIO5_23 0x1e4 /* IRQ */
35 >;
36 };
31 }; 37 };
32}; 38};
33 39
@@ -38,6 +44,8 @@
38 44
39 pmic: mc34708@8 { 45 pmic: mc34708@8 {
40 compatible = "fsl,mc34708"; 46 compatible = "fsl,mc34708";
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_pmic>;
41 reg = <0x08>; 49 reg = <0x08>;
42 interrupt-parent = <&gpio5>; 50 interrupt-parent = <&gpio5>;
43 interrupts = <23 0x8>; 51 interrupts = <23 0x8>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 64fa27b36be0..c6c58c1c00e3 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -731,7 +731,7 @@
731 compatible = "fsl,imx53-vpu"; 731 compatible = "fsl,imx53-vpu";
732 reg = <0x63ff4000 0x1000>; 732 reg = <0x63ff4000 0x1000>;
733 interrupts = <9>; 733 interrupts = <9>;
734 clocks = <&clks IMX5_CLK_VPU_GATE>, 734 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
735 <&clks IMX5_CLK_VPU_GATE>; 735 <&clks IMX5_CLK_VPU_GATE>;
736 clock-names = "per", "ahb"; 736 clock-names = "per", "ahb";
737 resets = <&src 1>; 737 resets = <&src 1>;
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index c8e51dd41b8f..71598546087f 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -58,7 +58,7 @@
58 58
59 sound-spdif { 59 sound-spdif {
60 compatible = "fsl,imx-audio-spdif"; 60 compatible = "fsl,imx-audio-spdif";
61 model = "imx-spdif"; 61 model = "On-board SPDIF";
62 /* IMX6 doesn't implement this yet */ 62 /* IMX6 doesn't implement this yet */
63 spdif-controller = <&spdif>; 63 spdif-controller = <&spdif>;
64 spdif-out; 64 spdif-out;
@@ -181,11 +181,13 @@
181}; 181};
182 182
183&usbh1 { 183&usbh1 {
184 disable-over-current;
184 vbus-supply = <&reg_usbh1_vbus>; 185 vbus-supply = <&reg_usbh1_vbus>;
185 status = "okay"; 186 status = "okay";
186}; 187};
187 188
188&usbotg { 189&usbotg {
190 disable-over-current;
189 pinctrl-names = "default"; 191 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>; 192 pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
191 vbus-supply = <&reg_usbotg_vbus>; 193 vbus-supply = <&reg_usbotg_vbus>;
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index 8c1cb53464a0..4fa254347798 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -119,7 +119,7 @@
119 pinctrl-names = "default"; 119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_enet>; 120 pinctrl-0 = <&pinctrl_enet>;
121 phy-mode = "rgmii"; 121 phy-mode = "rgmii";
122 phy-reset-gpios = <&gpio3 23 0>; 122 phy-reset-gpios = <&gpio1 25 0>;
123 phy-supply = <&vgen2_1v2_eth>; 123 phy-supply = <&vgen2_1v2_eth>;
124 status = "okay"; 124 status = "okay";
125}; 125};
@@ -339,6 +339,7 @@
339 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 339 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
340 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 340 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
341 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 341 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
342 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
342 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 343 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
343 >; 344 >;
344 }; 345 };
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index e8e781656b3f..6a524ca011e7 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -61,7 +61,7 @@
61 61
62 sound-spdif { 62 sound-spdif {
63 compatible = "fsl,imx-audio-spdif"; 63 compatible = "fsl,imx-audio-spdif";
64 model = "imx-spdif"; 64 model = "Integrated SPDIF";
65 /* IMX6 doesn't implement this yet */ 65 /* IMX6 doesn't implement this yet */
66 spdif-controller = <&spdif>; 66 spdif-controller = <&spdif>;
67 spdif-out; 67 spdif-out;
@@ -130,16 +130,23 @@
130 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; 130 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
131 }; 131 };
132 132
133 pinctrl_cubox_i_usbh1: cubox-i-usbh1 {
134 fsl,pins = <MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0>;
135 };
136
133 pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus { 137 pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus {
134 fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>; 138 fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>;
135 }; 139 };
136 140
137 pinctrl_cubox_i_usbotg_id: cubox-i-usbotg-id { 141 pinctrl_cubox_i_usbotg: cubox-i-usbotg {
138 /* 142 /*
139 * The Cubox-i pulls this low, but as it's pointless 143 * The Cubox-i pulls ID low, but as it's pointless
140 * leaving it as a pull-up, even if it is just 10uA. 144 * leaving it as a pull-up, even if it is just 10uA.
141 */ 145 */
142 fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>; 146 fsl,pins = <
147 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
148 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
149 >;
143 }; 150 };
144 151
145 pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus { 152 pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus {
@@ -173,13 +180,15 @@
173}; 180};
174 181
175&usbh1 { 182&usbh1 {
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_cubox_i_usbh1>;
176 vbus-supply = <&reg_usbh1_vbus>; 185 vbus-supply = <&reg_usbh1_vbus>;
177 status = "okay"; 186 status = "okay";
178}; 187};
179 188
180&usbotg { 189&usbotg {
181 pinctrl-names = "default"; 190 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_cubox_i_usbotg_id>; 191 pinctrl-0 = <&pinctrl_cubox_i_usbotg>;
183 vbus-supply = <&reg_usbotg_vbus>; 192 vbus-supply = <&reg_usbotg_vbus>;
184 status = "okay"; 193 status = "okay";
185}; 194};
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
index d16066608e21..db9f45b2c573 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -17,7 +17,7 @@
17 enet { 17 enet {
18 pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { 18 pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
19 fsl,pins = < 19 fsl,pins = <
20 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 20 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
21 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 21 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
22 /* AR8035 reset */ 22 /* AR8035 reset */
23 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 23 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h
index 3e0b816dac08..bb9c6b78cb97 100644
--- a/arch/arm/boot/dts/imx6sx-pinfunc.h
+++ b/arch/arm/boot/dts/imx6sx-pinfunc.h
@@ -78,7 +78,7 @@
78#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1 78#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1
79#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0 79#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0
80#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 80#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0
81#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x082C 0x4 0x1 81#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0
82#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 82#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0
83#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 83#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0
84#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 84#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0
@@ -96,7 +96,7 @@
96#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0 96#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0
97#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0 97#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0
98#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 98#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0
99#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0834 0x4 0x1 99#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0
100#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 100#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0
101#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 101#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0
102#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 102#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0
@@ -213,7 +213,7 @@
213#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1 213#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1
214#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2 214#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2
215#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 215#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0
216#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0854 0x4 0x1 216#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0
217#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 217#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0
218#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 218#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0
219#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 219#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0
@@ -254,7 +254,7 @@
254#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0 254#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0
255#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1 255#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1
256#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 256#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1
257#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0844 0x3 0x3 257#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0
258#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 258#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0
259#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 259#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0
260#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 260#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0
@@ -352,7 +352,7 @@
352#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0 352#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0
353#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1 353#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1
354#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 354#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1
355#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x082C 0x3 0x3 355#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0
356#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 356#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1
357#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 357#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0
358#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 358#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0
@@ -404,7 +404,7 @@
404#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0 404#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0
405#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0 405#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0
406#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 406#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0
407#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0854 0x2 0x3 407#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0
408#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 408#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0
409#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 409#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0
410#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 410#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0
@@ -423,7 +423,7 @@
423#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0 423#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0
424#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0 424#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0
425#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 425#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1
426#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x084C 0x2 0x3 426#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0
427#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 427#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1
428#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 428#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1
429#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 429#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0
@@ -815,7 +815,7 @@
815#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0 815#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0
816#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0 816#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0
817#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 817#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0
818#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x083C 0x3 0x1 818#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0
819#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 819#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0
820#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 820#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0
821#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 821#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0
@@ -957,7 +957,7 @@
957#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0 957#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0
958#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0 958#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0
959#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 959#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0
960#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x083C 0x1 0x4 960#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0
961#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 961#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1
962#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 962#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2
963#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 963#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1
@@ -1236,7 +1236,7 @@
1236#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1 1236#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1
1237#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0 1237#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0
1238#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 1238#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0
1239#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0834 0x4 0x2 1239#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0
1240#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 1240#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0
1241#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 1241#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0
1242#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 1242#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0
@@ -1315,7 +1315,7 @@
1315#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0 1315#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0
1316#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0 1316#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0
1317#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 1317#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0
1318#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0844 0x1 0x0 1318#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0
1319#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 1319#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0
1320#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 1320#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0
1321#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 1321#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0
@@ -1409,7 +1409,7 @@
1409#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0 1409#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0
1410#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0 1410#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0
1411#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 1411#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0
1412#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x083C 0x3 0x3 1412#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0
1413#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 1413#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0
1414#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 1414#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0
1415#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 1415#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0
@@ -1510,7 +1510,7 @@
1510#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0 1510#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0
1511#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0 1511#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0
1512#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 1512#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0
1513#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x084C 0x2 0x1 1513#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0
1514#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 1514#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0
1515#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 1515#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0
1516#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0 1516#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 3c3e6da1deac..a9aae88b74f5 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -292,6 +292,7 @@
292&uart3 { 292&uart3 {
293 pinctrl-names = "default"; 293 pinctrl-names = "default";
294 pinctrl-0 = <&uart3_pins>; 294 pinctrl-0 = <&uart3_pins>;
295 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
295}; 296};
296 297
297&gpio1 { 298&gpio1 {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index b15f1a77d684..1fe45d1f75ec 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -353,7 +353,7 @@
353 }; 353 };
354 354
355 twl_power: power { 355 twl_power: power {
356 compatible = "ti,twl4030-power-n900"; 356 compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
357 ti,use_poweroff; 357 ti,use_poweroff;
358 }; 358 };
359}; 359};
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 02f69f4a8fd3..9bad94efe1c8 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -107,7 +107,7 @@
107 #address-cells = <1>; 107 #address-cells = <1>;
108 #size-cells = <1>; 108 #size-cells = <1>;
109 reg = <1 0 0x08000000>; 109 reg = <1 0 0x08000000>;
110 ti,nand-ecc-opt = "ham1"; 110 ti,nand-ecc-opt = "sw";
111 nand-bus-width = <8>; 111 nand-bus-width = <8>;
112 gpmc,cs-on-ns = <0>; 112 gpmc,cs-on-ns = <0>;
113 gpmc,cs-rd-off-ns = <36>; 113 gpmc,cs-rd-off-ns = <36>;
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index e47ff69dcf70..5c375003bad1 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -467,6 +467,7 @@
467 ti,bit-shift = <0x1e>; 467 ti,bit-shift = <0x1e>;
468 reg = <0x0d00>; 468 reg = <0x0d00>;
469 ti,set-bit-to-disable; 469 ti,set-bit-to-disable;
470 ti,set-rate-parent;
470 }; 471 };
471 472
472 dpll4_m6_ck: dpll4_m6_ck { 473 dpll4_m6_ck: dpll4_m6_ck {
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index e67a23b5d788..58c27466f012 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -367,10 +367,12 @@
367 367
368 l3_iclk_div: l3_iclk_div { 368 l3_iclk_div: l3_iclk_div {
369 #clock-cells = <0>; 369 #clock-cells = <0>;
370 compatible = "fixed-factor-clock"; 370 compatible = "ti,divider-clock";
371 ti,max-div = <2>;
372 ti,bit-shift = <4>;
373 reg = <0x100>;
371 clocks = <&dpll_core_h12x2_ck>; 374 clocks = <&dpll_core_h12x2_ck>;
372 clock-mult = <1>; 375 ti,index-power-of-two;
373 clock-div = <1>;
374 }; 376 };
375 377
376 gpu_l3_iclk: gpu_l3_iclk { 378 gpu_l3_iclk: gpu_l3_iclk {
@@ -383,10 +385,12 @@
383 385
384 l4_root_clk_div: l4_root_clk_div { 386 l4_root_clk_div: l4_root_clk_div {
385 #clock-cells = <0>; 387 #clock-cells = <0>;
386 compatible = "fixed-factor-clock"; 388 compatible = "ti,divider-clock";
389 ti,max-div = <2>;
390 ti,bit-shift = <8>;
391 reg = <0x100>;
387 clocks = <&l3_iclk_div>; 392 clocks = <&l3_iclk_div>;
388 clock-mult = <1>; 393 ti,index-power-of-two;
389 clock-div = <1>;
390 }; 394 };
391 395
392 slimbus1_slimbus_clk: slimbus1_slimbus_clk { 396 slimbus1_slimbus_clk: slimbus1_slimbus_clk {
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 23486c081a69..be59014474b2 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -275,11 +275,6 @@
275 renesas,function = "msiof0"; 275 renesas,function = "msiof0";
276 }; 276 };
277 277
278 i2c6_pins: i2c6 {
279 renesas,groups = "i2c6";
280 renesas,function = "i2c6";
281 };
282
283 usb0_pins: usb0 { 278 usb0_pins: usb0 {
284 renesas,groups = "usb0"; 279 renesas,groups = "usb0";
285 renesas,function = "usb0"; 280 renesas,function = "usb0";
@@ -420,8 +415,6 @@
420}; 415};
421 416
422&i2c6 { 417&i2c6 {
423 pinctrl-names = "default";
424 pinctrl-0 = <&i2c6_pins>;
425 status = "okay"; 418 status = "okay";
426 clock-frequency = <100000>; 419 clock-frequency = <100000>;
427 420
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index 042f821d9e4d..c9d912da6141 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -149,6 +149,8 @@
149&mmc0 { /* sdmmc */ 149&mmc0 { /* sdmmc */
150 num-slots = <1>; 150 num-slots = <1>;
151 status = "okay"; 151 status = "okay";
152 pinctrl-names = "default";
153 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
152 vmmc-supply = <&vcc_sd0>; 154 vmmc-supply = <&vcc_sd0>;
153 155
154 slot@0 { 156 slot@0 {
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 171b610db709..5e4e3c238b2d 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -179,6 +179,8 @@
179&mmc0 { 179&mmc0 {
180 num-slots = <1>; 180 num-slots = <1>;
181 status = "okay"; 181 status = "okay";
182 pinctrl-names = "default";
183 pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
182 vmmc-supply = <&vcc_sd0>; 184 vmmc-supply = <&vcc_sd0>;
183 185
184 slot@0 { 186 slot@0 {
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 4a2000c620ad..3e97a669f15e 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -116,7 +116,6 @@
116 msp2: msp@80117000 { 116 msp2: msp@80117000 {
117 pinctrl-names = "default"; 117 pinctrl-names = "default";
118 pinctrl-0 = <&msp2_default_mode>; 118 pinctrl-0 = <&msp2_default_mode>;
119 status = "okay";
120 }; 119 };
121 120
122 msp3: msp@80125000 { 121 msp3: msp@80125000 {
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 44b07e512c24..e06fbfc55bb7 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -660,6 +660,8 @@
660 clock-frequency = <100000>; 660 clock-frequency = <100000>;
661 resets = <&apb2_rst 0>; 661 resets = <&apb2_rst 0>;
662 status = "disabled"; 662 status = "disabled";
663 #address-cells = <1>;
664 #size-cells = <0>;
663 }; 665 };
664 666
665 i2c1: i2c@01c2b000 { 667 i2c1: i2c@01c2b000 {
@@ -670,6 +672,8 @@
670 clock-frequency = <100000>; 672 clock-frequency = <100000>;
671 resets = <&apb2_rst 1>; 673 resets = <&apb2_rst 1>;
672 status = "disabled"; 674 status = "disabled";
675 #address-cells = <1>;
676 #size-cells = <0>;
673 }; 677 };
674 678
675 i2c2: i2c@01c2b400 { 679 i2c2: i2c@01c2b400 {
@@ -680,6 +684,8 @@
680 clock-frequency = <100000>; 684 clock-frequency = <100000>;
681 resets = <&apb2_rst 2>; 685 resets = <&apb2_rst 2>;
682 status = "disabled"; 686 status = "disabled";
687 #address-cells = <1>;
688 #size-cells = <0>;
683 }; 689 };
684 690
685 i2c3: i2c@01c2b800 { 691 i2c3: i2c@01c2b800 {
@@ -690,6 +696,8 @@
690 clock-frequency = <100000>; 696 clock-frequency = <100000>;
691 resets = <&apb2_rst 3>; 697 resets = <&apb2_rst 3>;
692 status = "disabled"; 698 status = "disabled";
699 #address-cells = <1>;
700 #size-cells = <0>;
693 }; 701 };
694 702
695 gmac: ethernet@01c30000 { 703 gmac: ethernet@01c30000 {
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 8adaa7871dd3..a5446cba9804 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -423,7 +423,7 @@
423 vcc4-supply = <&sys_3v3_reg>; 423 vcc4-supply = <&sys_3v3_reg>;
424 vcc5-supply = <&sys_3v3_reg>; 424 vcc5-supply = <&sys_3v3_reg>;
425 vcc6-supply = <&vio_reg>; 425 vcc6-supply = <&vio_reg>;
426 vcc7-supply = <&sys_5v0_reg>; 426 vcc7-supply = <&charge_pump_5v0_reg>;
427 vccio-supply = <&sys_3v3_reg>; 427 vccio-supply = <&sys_3v3_reg>;
428 428
429 regulators { 429 regulators {
@@ -674,5 +674,14 @@
674 regulator-max-microvolt = <3300000>; 674 regulator-max-microvolt = <3300000>;
675 regulator-always-on; 675 regulator-always-on;
676 }; 676 };
677
678 charge_pump_5v0_reg: regulator@101 {
679 compatible = "regulator-fixed";
680 reg = <101>;
681 regulator-name = "5v0";
682 regulator-min-microvolt = <5000000>;
683 regulator-max-microvolt = <5000000>;
684 regulator-always-on;
685 };
677 }; 686 };
678}; 687};
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index bf16f8e65627..c4ed1bec4d92 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -201,7 +201,7 @@
201 vcc4-supply = <&sys_3v3_reg>; 201 vcc4-supply = <&sys_3v3_reg>;
202 vcc5-supply = <&sys_3v3_reg>; 202 vcc5-supply = <&sys_3v3_reg>;
203 vcc6-supply = <&vio_reg>; 203 vcc6-supply = <&vio_reg>;
204 vcc7-supply = <&sys_5v0_reg>; 204 vcc7-supply = <&charge_pump_5v0_reg>;
205 vccio-supply = <&sys_3v3_reg>; 205 vccio-supply = <&sys_3v3_reg>;
206 206
207 regulators { 207 regulators {
@@ -373,5 +373,14 @@
373 regulator-max-microvolt = <3300000>; 373 regulator-max-microvolt = <3300000>;
374 regulator-always-on; 374 regulator-always-on;
375 }; 375 };
376
377 charge_pump_5v0_reg: regulator@101 {
378 compatible = "regulator-fixed";
379 reg = <101>;
380 regulator-name = "5v0";
381 regulator-min-microvolt = <5000000>;
382 regulator-max-microvolt = <5000000>;
383 regulator-always-on;
384 };
376 }; 385 };
377}; 386};
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index 2e3bd3172b23..55eb35f068fb 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -83,10 +83,6 @@
83 regulator-always-on; 83 regulator-always-on;
84 }; 84 };
85 85
86 clk32kg: regulator-clk32kg {
87 compatible = "ti,twl6030-clk32kg";
88 };
89
90 twl_usb_comparator: usb-comparator { 86 twl_usb_comparator: usb-comparator {
91 compatible = "ti,twl6030-usb"; 87 compatible = "ti,twl6030-usb";
92 interrupts = <4>, <10>; 88 interrupts = <4>, <10>;
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 11d733406c7e..b8a5e8c68f06 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -168,7 +168,7 @@
168 }; 168 };
169 169
170 pinctrl_esdhc1: esdhc1grp { 170 pinctrl_esdhc1: esdhc1grp {
171 fsl,fsl,pins = < 171 fsl,pins = <
172 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef 172 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
173 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef 173 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
174 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef 174 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 88099175fc56..d86771abbf57 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1443,14 +1443,14 @@ void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no)
1443EXPORT_SYMBOL(edma_assign_channel_eventq); 1443EXPORT_SYMBOL(edma_assign_channel_eventq);
1444 1444
1445static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, 1445static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1446 struct edma *edma_cc) 1446 struct edma *edma_cc, int cc_id)
1447{ 1447{
1448 int i; 1448 int i;
1449 u32 value, cccfg; 1449 u32 value, cccfg;
1450 s8 (*queue_priority_map)[2]; 1450 s8 (*queue_priority_map)[2];
1451 1451
1452 /* Decode the eDMA3 configuration from CCCFG register */ 1452 /* Decode the eDMA3 configuration from CCCFG register */
1453 cccfg = edma_read(0, EDMA_CCCFG); 1453 cccfg = edma_read(cc_id, EDMA_CCCFG);
1454 1454
1455 value = GET_NUM_REGN(cccfg); 1455 value = GET_NUM_REGN(cccfg);
1456 edma_cc->num_region = BIT(value); 1456 edma_cc->num_region = BIT(value);
@@ -1464,7 +1464,8 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1464 value = GET_NUM_EVQUE(cccfg); 1464 value = GET_NUM_EVQUE(cccfg);
1465 edma_cc->num_tc = value + 1; 1465 edma_cc->num_tc = value + 1;
1466 1466
1467 dev_dbg(dev, "eDMA3 HW configuration (cccfg: 0x%08x):\n", cccfg); 1467 dev_dbg(dev, "eDMA3 CC%d HW configuration (cccfg: 0x%08x):\n", cc_id,
1468 cccfg);
1468 dev_dbg(dev, "num_region: %u\n", edma_cc->num_region); 1469 dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
1469 dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels); 1470 dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
1470 dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots); 1471 dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
@@ -1684,7 +1685,7 @@ static int edma_probe(struct platform_device *pdev)
1684 return -ENOMEM; 1685 return -ENOMEM;
1685 1686
1686 /* Get eDMA3 configuration from IP */ 1687 /* Get eDMA3 configuration from IP */
1687 ret = edma_setup_from_hw(dev, info[j], edma_cc[j]); 1688 ret = edma_setup_from_hw(dev, info[j], edma_cc[j], j);
1688 if (ret) 1689 if (ret)
1689 return ret; 1690 return ret;
1690 1691
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index fd43f7f55b70..79ecb4f34ffb 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -472,7 +472,6 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size)
472 "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \ 472 "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \
473 "isb \n\t" \ 473 "isb \n\t" \
474 "bl v7_flush_dcache_"__stringify(level)" \n\t" \ 474 "bl v7_flush_dcache_"__stringify(level)" \n\t" \
475 "clrex \n\t" \
476 "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \ 475 "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \
477 "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \ 476 "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \
478 "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \ 477 "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 963a2515906d..819777d0e91f 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -74,6 +74,7 @@
74#define ARM_CPU_PART_CORTEX_A12 0x4100c0d0 74#define ARM_CPU_PART_CORTEX_A12 0x4100c0d0
75#define ARM_CPU_PART_CORTEX_A17 0x4100c0e0 75#define ARM_CPU_PART_CORTEX_A17 0x4100c0e0
76#define ARM_CPU_PART_CORTEX_A15 0x4100c0f0 76#define ARM_CPU_PART_CORTEX_A15 0x4100c0f0
77#define ARM_CPU_PART_MASK 0xff00fff0
77 78
78#define ARM_CPU_XSCALE_ARCH_MASK 0xe000 79#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
79#define ARM_CPU_XSCALE_ARCH_V1 0x2000 80#define ARM_CPU_XSCALE_ARCH_V1 0x2000
@@ -179,7 +180,7 @@ static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
179 */ 180 */
180static inline unsigned int __attribute_const__ read_cpuid_part(void) 181static inline unsigned int __attribute_const__ read_cpuid_part(void)
181{ 182{
182 return read_cpuid_id() & 0xff00fff0; 183 return read_cpuid_id() & ARM_CPU_PART_MASK;
183} 184}
184 185
185static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void) 186static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index f4b46d39b9cf..afb9cafd3786 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -50,6 +50,7 @@ typedef struct user_fp elf_fpregset_t;
50#define R_ARM_ABS32 2 50#define R_ARM_ABS32 2
51#define R_ARM_CALL 28 51#define R_ARM_CALL 28
52#define R_ARM_JUMP24 29 52#define R_ARM_JUMP24 29
53#define R_ARM_TARGET1 38
53#define R_ARM_V4BX 40 54#define R_ARM_V4BX 40
54#define R_ARM_PREL31 42 55#define R_ARM_PREL31 42
55#define R_ARM_MOVW_ABS_NC 43 56#define R_ARM_MOVW_ABS_NC 43
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index a252c0bfacf5..0ad7d490ee6f 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -8,6 +8,7 @@
8#include <linux/cpumask.h> 8#include <linux/cpumask.h>
9#include <linux/err.h> 9#include <linux/err.h>
10 10
11#include <asm/cpu.h>
11#include <asm/cputype.h> 12#include <asm/cputype.h>
12 13
13/* 14/*
@@ -25,6 +26,20 @@ static inline bool is_smp(void)
25#endif 26#endif
26} 27}
27 28
29/**
30 * smp_cpuid_part() - return part id for a given cpu
31 * @cpu: logical cpu id.
32 *
33 * Return: part id of logical cpu passed as argument.
34 */
35static inline unsigned int smp_cpuid_part(int cpu)
36{
37 struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpu);
38
39 return is_smp() ? cpu_info->cpuid & ARM_CPU_PART_MASK :
40 read_cpuid_part();
41}
42
28/* all SMP configurations have the extended CPUID registers */ 43/* all SMP configurations have the extended CPUID registers */
29#ifndef CONFIG_MMU 44#ifndef CONFIG_MMU
30#define tlb_ops_need_broadcast() 0 45#define tlb_ops_need_broadcast() 0
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 8db307d0954b..2fdf8679b46e 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -208,26 +208,21 @@
208#endif 208#endif
209 .endif 209 .endif
210 msr spsr_cxsf, \rpsr 210 msr spsr_cxsf, \rpsr
211#if defined(CONFIG_CPU_V6) 211#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
212 ldr r0, [sp] 212 @ We must avoid clrex due to Cortex-A15 erratum #830321
213 strex r1, r2, [sp] @ clear the exclusive monitor 213 sub r0, sp, #4 @ uninhabited address
214 ldmib sp, {r1 - pc}^ @ load r1 - pc, cpsr 214 strex r1, r2, [r0] @ clear the exclusive monitor
215#elif defined(CONFIG_CPU_32v6K)
216 clrex @ clear the exclusive monitor
217 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
218#else
219 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
220#endif 215#endif
216 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
221 .endm 217 .endm
222 218
223 .macro restore_user_regs, fast = 0, offset = 0 219 .macro restore_user_regs, fast = 0, offset = 0
224 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr 220 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
225 ldr lr, [sp, #\offset + S_PC]! @ get pc 221 ldr lr, [sp, #\offset + S_PC]! @ get pc
226 msr spsr_cxsf, r1 @ save in spsr_svc 222 msr spsr_cxsf, r1 @ save in spsr_svc
227#if defined(CONFIG_CPU_V6) 223#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
224 @ We must avoid clrex due to Cortex-A15 erratum #830321
228 strex r1, r2, [sp] @ clear the exclusive monitor 225 strex r1, r2, [sp] @ clear the exclusive monitor
229#elif defined(CONFIG_CPU_32v6K)
230 clrex @ clear the exclusive monitor
231#endif 226#endif
232 .if \fast 227 .if \fast
233 ldmdb sp, {r1 - lr}^ @ get calling r1 - lr 228 ldmdb sp, {r1 - lr}^ @ get calling r1 - lr
@@ -261,7 +256,10 @@
261 .endif 256 .endif
262 ldr lr, [sp, #S_SP] @ top of the stack 257 ldr lr, [sp, #S_SP] @ top of the stack
263 ldrd r0, r1, [sp, #S_LR] @ calling lr and pc 258 ldrd r0, r1, [sp, #S_LR] @ calling lr and pc
264 clrex @ clear the exclusive monitor 259
260 @ We must avoid clrex due to Cortex-A15 erratum #830321
261 strex r2, r1, [sp, #S_LR] @ clear the exclusive monitor
262
265 stmdb lr!, {r0, r1, \rpsr} @ calling lr and rfe context 263 stmdb lr!, {r0, r1, \rpsr} @ calling lr and rfe context
266 ldmia sp, {r0 - r12} 264 ldmia sp, {r0 - r12}
267 mov sp, lr 265 mov sp, lr
@@ -282,13 +280,16 @@
282 .endm 280 .endm
283#else /* ifdef CONFIG_CPU_V7M */ 281#else /* ifdef CONFIG_CPU_V7M */
284 .macro restore_user_regs, fast = 0, offset = 0 282 .macro restore_user_regs, fast = 0, offset = 0
285 clrex @ clear the exclusive monitor
286 mov r2, sp 283 mov r2, sp
287 load_user_sp_lr r2, r3, \offset + S_SP @ calling sp, lr 284 load_user_sp_lr r2, r3, \offset + S_SP @ calling sp, lr
288 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr 285 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
289 ldr lr, [sp, #\offset + S_PC] @ get pc 286 ldr lr, [sp, #\offset + S_PC] @ get pc
290 add sp, sp, #\offset + S_SP 287 add sp, sp, #\offset + S_SP
291 msr spsr_cxsf, r1 @ save in spsr_svc 288 msr spsr_cxsf, r1 @ save in spsr_svc
289
290 @ We must avoid clrex due to Cortex-A15 erratum #830321
291 strex r1, r2, [sp] @ clear the exclusive monitor
292
292 .if \fast 293 .if \fast
293 ldmdb sp, {r1 - r12} @ get calling r1 - r12 294 ldmdb sp, {r1 - r12} @ get calling r1 - r12
294 .else 295 .else
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 45e478157278..6a4dffefd357 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -91,6 +91,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
91 break; 91 break;
92 92
93 case R_ARM_ABS32: 93 case R_ARM_ABS32:
94 case R_ARM_TARGET1:
94 *(u32 *)loc += sym->st_value; 95 *(u32 *)loc += sym->st_value;
95 break; 96 break;
96 97
diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c
index 4c979d466cc1..a96a8043277c 100644
--- a/arch/arm/kvm/handle_exit.c
+++ b/arch/arm/kvm/handle_exit.c
@@ -93,6 +93,8 @@ static int kvm_handle_wfx(struct kvm_vcpu *vcpu, struct kvm_run *run)
93 else 93 else
94 kvm_vcpu_block(vcpu); 94 kvm_vcpu_block(vcpu);
95 95
96 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
97
96 return 1; 98 return 1;
97} 99}
98 100
diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S
index 991415d978b6..3988e72d16ff 100644
--- a/arch/arm/kvm/init.S
+++ b/arch/arm/kvm/init.S
@@ -99,6 +99,10 @@ __do_hyp_init:
99 mrc p15, 0, r0, c10, c2, 1 99 mrc p15, 0, r0, c10, c2, 1
100 mcr p15, 4, r0, c10, c2, 1 100 mcr p15, 4, r0, c10, c2, 1
101 101
102 @ Invalidate the stale TLBs from Bootloader
103 mcr p15, 4, r0, c8, c7, 0 @ TLBIALLH
104 dsb ish
105
102 @ Set the HSCTLR to: 106 @ Set the HSCTLR to:
103 @ - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel) 107 @ - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
104 @ - Endianness: Kernel config 108 @ - Endianness: Kernel config
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 3a185faee795..f4b6e91843e4 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -14,6 +14,7 @@
14#include <linux/gpio.h> 14#include <linux/gpio.h>
15#include <linux/of.h> 15#include <linux/of.h>
16#include <linux/of_irq.h> 16#include <linux/of_irq.h>
17#include <linux/clk-provider.h>
17 18
18#include <asm/setup.h> 19#include <asm/setup.h>
19#include <asm/irq.h> 20#include <asm/irq.h>
@@ -35,13 +36,21 @@ static void __init at91rm9200_dt_init_irq(void)
35 of_irq_init(irq_of_match); 36 of_irq_init(irq_of_match);
36} 37}
37 38
39static void __init at91rm9200_dt_timer_init(void)
40{
41#if defined(CONFIG_COMMON_CLK)
42 of_clk_init(NULL);
43#endif
44 at91rm9200_timer_init();
45}
46
38static const char *at91rm9200_dt_board_compat[] __initdata = { 47static const char *at91rm9200_dt_board_compat[] __initdata = {
39 "atmel,at91rm9200", 48 "atmel,at91rm9200",
40 NULL 49 NULL
41}; 50};
42 51
43DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)") 52DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
44 .init_time = at91rm9200_timer_init, 53 .init_time = at91rm9200_dt_timer_init,
45 .map_io = at91_map_io, 54 .map_io = at91_map_io,
46 .handle_irq = at91_aic_handle_irq, 55 .handle_irq = at91_aic_handle_irq,
47 .init_early = at91rm9200_dt_initialize, 56 .init_early = at91rm9200_dt_initialize,
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 67c492aabf4d..b19a39652545 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -36,5 +36,4 @@ obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
36 36
37ifeq ($(CONFIG_ARCH_BRCMSTB),y) 37ifeq ($(CONFIG_ARCH_BRCMSTB),y)
38obj-y += brcmstb.o 38obj-y += brcmstb.o
39obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o
40endif 39endif
diff --git a/arch/arm/mach-bcm/brcmstb.h b/arch/arm/mach-bcm/brcmstb.h
deleted file mode 100644
index ec0c3d112b36..000000000000
--- a/arch/arm/mach-bcm/brcmstb.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Copyright (C) 2013-2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __BRCMSTB_H__
15#define __BRCMSTB_H__
16
17void brcmstb_secondary_startup(void);
18
19#endif /* __BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.S b/arch/arm/mach-bcm/headsmp-brcmstb.S
deleted file mode 100644
index 199c1ea58248..000000000000
--- a/arch/arm/mach-bcm/headsmp-brcmstb.S
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * SMP boot code for secondary CPUs
3 * Based on arch/arm/mach-tegra/headsmp.S
4 *
5 * Copyright (C) 2010 NVIDIA, Inc.
6 * Copyright (C) 2013-2014 Broadcom Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <asm/assembler.h>
19#include <linux/linkage.h>
20#include <linux/init.h>
21
22 .section ".text.head", "ax"
23
24ENTRY(brcmstb_secondary_startup)
25 /*
26 * Ensure CPU is in a sane state by disabling all IRQs and switching
27 * into SVC mode.
28 */
29 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
30
31 bl v7_invalidate_l1
32 b secondary_startup
33ENDPROC(brcmstb_secondary_startup)
diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
deleted file mode 100644
index af780e9c23a6..000000000000
--- a/arch/arm/mach-bcm/platsmp-brcmstb.c
+++ /dev/null
@@ -1,363 +0,0 @@
1/*
2 * Broadcom STB CPU SMP and hotplug support for ARM
3 *
4 * Copyright (C) 2013-2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/delay.h>
17#include <linux/errno.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/of_address.h>
21#include <linux/of_platform.h>
22#include <linux/printk.h>
23#include <linux/regmap.h>
24#include <linux/smp.h>
25#include <linux/mfd/syscon.h>
26#include <linux/spinlock.h>
27
28#include <asm/cacheflush.h>
29#include <asm/cp15.h>
30#include <asm/mach-types.h>
31#include <asm/smp_plat.h>
32
33#include "brcmstb.h"
34
35enum {
36 ZONE_MAN_CLKEN_MASK = BIT(0),
37 ZONE_MAN_RESET_CNTL_MASK = BIT(1),
38 ZONE_MAN_MEM_PWR_MASK = BIT(4),
39 ZONE_RESERVED_1_MASK = BIT(5),
40 ZONE_MAN_ISO_CNTL_MASK = BIT(6),
41 ZONE_MANUAL_CONTROL_MASK = BIT(7),
42 ZONE_PWR_DN_REQ_MASK = BIT(9),
43 ZONE_PWR_UP_REQ_MASK = BIT(10),
44 ZONE_BLK_RST_ASSERT_MASK = BIT(12),
45 ZONE_PWR_OFF_STATE_MASK = BIT(25),
46 ZONE_PWR_ON_STATE_MASK = BIT(26),
47 ZONE_DPG_PWR_STATE_MASK = BIT(28),
48 ZONE_MEM_PWR_STATE_MASK = BIT(29),
49 ZONE_RESET_STATE_MASK = BIT(31),
50 CPU0_PWR_ZONE_CTRL_REG = 1,
51 CPU_RESET_CONFIG_REG = 2,
52};
53
54static void __iomem *cpubiuctrl_block;
55static void __iomem *hif_cont_block;
56static u32 cpu0_pwr_zone_ctrl_reg;
57static u32 cpu_rst_cfg_reg;
58static u32 hif_cont_reg;
59
60#ifdef CONFIG_HOTPLUG_CPU
61static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
62
63static int per_cpu_sw_state_rd(u32 cpu)
64{
65 sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
66 return per_cpu(per_cpu_sw_state, cpu);
67}
68
69static void per_cpu_sw_state_wr(u32 cpu, int val)
70{
71 per_cpu(per_cpu_sw_state, cpu) = val;
72 dmb();
73 sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
74 dsb_sev();
75}
76#else
77static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
78#endif
79
80static void __iomem *pwr_ctrl_get_base(u32 cpu)
81{
82 void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
83 base += (cpu_logical_map(cpu) * 4);
84 return base;
85}
86
87static u32 pwr_ctrl_rd(u32 cpu)
88{
89 void __iomem *base = pwr_ctrl_get_base(cpu);
90 return readl_relaxed(base);
91}
92
93static void pwr_ctrl_wr(u32 cpu, u32 val)
94{
95 void __iomem *base = pwr_ctrl_get_base(cpu);
96 writel(val, base);
97}
98
99static void cpu_rst_cfg_set(u32 cpu, int set)
100{
101 u32 val;
102 val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
103 if (set)
104 val |= BIT(cpu_logical_map(cpu));
105 else
106 val &= ~BIT(cpu_logical_map(cpu));
107 writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
108}
109
110static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
111{
112 const int reg_ofs = cpu_logical_map(cpu) * 8;
113 writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
114 writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
115}
116
117static void brcmstb_cpu_boot(u32 cpu)
118{
119 pr_info("SMP: Booting CPU%d...\n", cpu);
120
121 /*
122 * set the reset vector to point to the secondary_startup
123 * routine
124 */
125 cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
126
127 /* unhalt the cpu */
128 cpu_rst_cfg_set(cpu, 0);
129}
130
131static void brcmstb_cpu_power_on(u32 cpu)
132{
133 /*
134 * The secondary cores power was cut, so we must go through
135 * power-on initialization.
136 */
137 u32 tmp;
138
139 pr_info("SMP: Powering up CPU%d...\n", cpu);
140
141 /* Request zone power up */
142 pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
143
144 /* Wait for the power up FSM to complete */
145 do {
146 tmp = pwr_ctrl_rd(cpu);
147 } while (!(tmp & ZONE_PWR_ON_STATE_MASK));
148
149 per_cpu_sw_state_wr(cpu, 1);
150}
151
152static int brcmstb_cpu_get_power_state(u32 cpu)
153{
154 int tmp = pwr_ctrl_rd(cpu);
155 return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
156}
157
158#ifdef CONFIG_HOTPLUG_CPU
159
160static void brcmstb_cpu_die(u32 cpu)
161{
162 v7_exit_coherency_flush(all);
163
164 /* Prevent all interrupts from reaching this CPU. */
165 arch_local_irq_disable();
166
167 /*
168 * Final full barrier to ensure everything before this instruction has
169 * quiesced.
170 */
171 isb();
172 dsb();
173
174 per_cpu_sw_state_wr(cpu, 0);
175
176 /* Sit and wait to die */
177 wfi();
178
179 /* We should never get here... */
180 panic("Spurious interrupt on CPU %d received!\n", cpu);
181}
182
183static int brcmstb_cpu_kill(u32 cpu)
184{
185 u32 tmp;
186
187 pr_info("SMP: Powering down CPU%d...\n", cpu);
188
189 while (per_cpu_sw_state_rd(cpu))
190 ;
191
192 /* Program zone reset */
193 pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
194 ZONE_PWR_DN_REQ_MASK);
195
196 /* Verify zone reset */
197 tmp = pwr_ctrl_rd(cpu);
198 if (!(tmp & ZONE_RESET_STATE_MASK))
199 pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
200 __func__, cpu);
201
202 /* Wait for power down */
203 do {
204 tmp = pwr_ctrl_rd(cpu);
205 } while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
206
207 /* Settle-time from Broadcom-internal DVT reference code */
208 udelay(7);
209
210 /* Assert reset on the CPU */
211 cpu_rst_cfg_set(cpu, 1);
212
213 return 1;
214}
215
216#endif /* CONFIG_HOTPLUG_CPU */
217
218static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
219{
220 int rc = 0;
221 char *name;
222 struct device_node *syscon_np = NULL;
223
224 name = "syscon-cpu";
225
226 syscon_np = of_parse_phandle(np, name, 0);
227 if (!syscon_np) {
228 pr_err("can't find phandle %s\n", name);
229 rc = -EINVAL;
230 goto cleanup;
231 }
232
233 cpubiuctrl_block = of_iomap(syscon_np, 0);
234 if (!cpubiuctrl_block) {
235 pr_err("iomap failed for cpubiuctrl_block\n");
236 rc = -EINVAL;
237 goto cleanup;
238 }
239
240 rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
241 &cpu0_pwr_zone_ctrl_reg);
242 if (rc) {
243 pr_err("failed to read 1st entry from %s property (%d)\n", name,
244 rc);
245 rc = -EINVAL;
246 goto cleanup;
247 }
248
249 rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
250 &cpu_rst_cfg_reg);
251 if (rc) {
252 pr_err("failed to read 2nd entry from %s property (%d)\n", name,
253 rc);
254 rc = -EINVAL;
255 goto cleanup;
256 }
257
258cleanup:
259 if (syscon_np)
260 of_node_put(syscon_np);
261
262 return rc;
263}
264
265static int __init setup_hifcont_regs(struct device_node *np)
266{
267 int rc = 0;
268 char *name;
269 struct device_node *syscon_np = NULL;
270
271 name = "syscon-cont";
272
273 syscon_np = of_parse_phandle(np, name, 0);
274 if (!syscon_np) {
275 pr_err("can't find phandle %s\n", name);
276 rc = -EINVAL;
277 goto cleanup;
278 }
279
280 hif_cont_block = of_iomap(syscon_np, 0);
281 if (!hif_cont_block) {
282 pr_err("iomap failed for hif_cont_block\n");
283 rc = -EINVAL;
284 goto cleanup;
285 }
286
287 /* offset is at top of hif_cont_block */
288 hif_cont_reg = 0;
289
290cleanup:
291 if (syscon_np)
292 of_node_put(syscon_np);
293
294 return rc;
295}
296
297static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
298{
299 int rc;
300 struct device_node *np;
301 char *name;
302
303 name = "brcm,brcmstb-smpboot";
304 np = of_find_compatible_node(NULL, NULL, name);
305 if (!np) {
306 pr_err("can't find compatible node %s\n", name);
307 return;
308 }
309
310 rc = setup_hifcpubiuctrl_regs(np);
311 if (rc)
312 return;
313
314 rc = setup_hifcont_regs(np);
315 if (rc)
316 return;
317}
318
319static DEFINE_SPINLOCK(boot_lock);
320
321static void brcmstb_secondary_init(unsigned int cpu)
322{
323 /*
324 * Synchronise with the boot thread.
325 */
326 spin_lock(&boot_lock);
327 spin_unlock(&boot_lock);
328}
329
330static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
331{
332 /*
333 * set synchronisation state between this boot processor
334 * and the secondary one
335 */
336 spin_lock(&boot_lock);
337
338 /* Bring up power to the core if necessary */
339 if (brcmstb_cpu_get_power_state(cpu) == 0)
340 brcmstb_cpu_power_on(cpu);
341
342 brcmstb_cpu_boot(cpu);
343
344 /*
345 * now the secondary core is starting up let it run its
346 * calibrations, then wait for it to finish
347 */
348 spin_unlock(&boot_lock);
349
350 return 0;
351}
352
353static struct smp_operations brcmstb_smp_ops __initdata = {
354 .smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
355 .smp_secondary_init = brcmstb_secondary_init,
356 .smp_boot_secondary = brcmstb_boot_secondary,
357#ifdef CONFIG_HOTPLUG_CPU
358 .cpu_kill = brcmstb_cpu_kill,
359 .cpu_die = brcmstb_cpu_die,
360#endif
361};
362
363CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index b2f8b60cf0e9..dc9a764a7c37 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -43,7 +43,6 @@
43 "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \ 43 "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \
44 "isb\n\t"\ 44 "isb\n\t"\
45 "bl v7_flush_dcache_"__stringify(level)"\n\t" \ 45 "bl v7_flush_dcache_"__stringify(level)"\n\t" \
46 "clrex\n\t"\
47 "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" \ 46 "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" \
48 "bic r0, r0, #(1 << 6) @ disable local coherency\n\t" \ 47 "bic r0, r0, #(1 << 6) @ disable local coherency\n\t" \
49 /* Dummy Load of a device register to avoid Erratum 799270 */ \ 48 /* Dummy Load of a device register to avoid Erratum 799270 */ \
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 9de84a215abd..be9a51afe05a 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -85,7 +85,6 @@ config SOC_IMX25
85 85
86config SOC_IMX27 86config SOC_IMX27
87 bool 87 bool
88 select ARCH_HAS_OPP
89 select CPU_ARM926T 88 select CPU_ARM926T
90 select IMX_HAVE_IOMUX_V1 89 select IMX_HAVE_IOMUX_V1
91 select MXC_AVIC 90 select MXC_AVIC
@@ -659,7 +658,6 @@ comment "Device tree only"
659 658
660config SOC_IMX5 659config SOC_IMX5
661 bool 660 bool
662 select ARCH_HAS_OPP
663 select HAVE_IMX_SRC 661 select HAVE_IMX_SRC
664 select MXC_TZIC 662 select MXC_TZIC
665 663
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index ac88599ca080..23c02932bf84 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -93,9 +93,11 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
93obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o 93obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
94obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o 94obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
95obj-$(CONFIG_HAVE_IMX_SRC) += src.o 95obj-$(CONFIG_HAVE_IMX_SRC) += src.o
96ifdef CONFIG_SOC_IMX6
96AFLAGS_headsmp.o :=-Wa,-march=armv7-a 97AFLAGS_headsmp.o :=-Wa,-march=armv7-a
97obj-$(CONFIG_SMP) += headsmp.o platsmp.o 98obj-$(CONFIG_SMP) += headsmp.o platsmp.o
98obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 99obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
100endif
99obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o 101obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
100obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o 102obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
101obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o 103obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 6cceb7765c14..29d412975aff 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -194,6 +194,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
194 clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); 194 clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
195 clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); 195 clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
196 clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); 196 clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
197 if (cpu_is_imx6dl()) {
198 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
199 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
200 }
197 201
198 clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); 202 clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
199 clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); 203 clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
@@ -217,8 +221,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
217 clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); 221 clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
218 clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); 222 clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
219 clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); 223 clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
220 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 224 if (cpu_is_imx6q()) {
221 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 225 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
226 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
227 }
222 clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); 228 clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
223 clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); 229 clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
224 clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); 230 clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index 74b50f1982db..ca4ea2daf25b 100644
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -173,6 +173,8 @@ ENTRY(imx6_suspend)
173 ldr r6, [r11, #0x0] 173 ldr r6, [r11, #0x0]
174 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] 174 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
175 ldr r6, [r11, #0x0] 175 ldr r6, [r11, #0x0]
176 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
177 ldr r6, [r11, #0x0]
176 178
177 /* use r11 to store the IO address */ 179 /* use r11 to store the IO address */
178 ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] 180 ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index e87f2a83d6bf..2d245c2e641c 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
142 board_nand_data.nr_parts = nr_parts; 142 board_nand_data.nr_parts = nr_parts;
143 board_nand_data.devsize = nand_type; 143 board_nand_data.devsize = nand_type;
144 144
145 board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW; 145 board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
146 gpmc_nand_init(&board_nand_data, gpmc_t); 146 gpmc_nand_init(&board_nand_data, gpmc_t);
147} 147}
148#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ 148#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 8897ad7035fd..cb7764314f17 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -49,7 +49,8 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
49 return 0; 49 return 0;
50 50
51 /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */ 51 /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
52 if (ecc_opt == OMAP_ECC_HAM1_CODE_HW) 52 if (ecc_opt == OMAP_ECC_HAM1_CODE_HW ||
53 ecc_opt == OMAP_ECC_HAM1_CODE_SW)
53 return 1; 54 return 1;
54 else 55 else
55 return 0; 56 return 0;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 8bc13380f0a0..2f97228f188a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1207,8 +1207,7 @@ int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1207 } 1207 }
1208 } 1208 }
1209 1209
1210 if ((p->wait_on_read || p->wait_on_write) && 1210 if (p->wait_pin > gpmc_nr_waitpins) {
1211 (p->wait_pin > gpmc_nr_waitpins)) {
1212 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); 1211 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1213 return -EINVAL; 1212 return -EINVAL;
1214 } 1213 }
@@ -1288,8 +1287,8 @@ void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1288 p->wait_on_write = of_property_read_bool(np, 1287 p->wait_on_write = of_property_read_bool(np,
1289 "gpmc,wait-on-write"); 1288 "gpmc,wait-on-write");
1290 if (!p->wait_on_read && !p->wait_on_write) 1289 if (!p->wait_on_read && !p->wait_on_write)
1291 pr_warn("%s: read/write wait monitoring not enabled!\n", 1290 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1292 __func__); 1291 __func__);
1293 } 1292 }
1294} 1293}
1295 1294
@@ -1403,8 +1402,11 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,
1403 pr_err("%s: ti,nand-ecc-opt not found\n", __func__); 1402 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1404 return -ENODEV; 1403 return -ENODEV;
1405 } 1404 }
1406 if (!strcmp(s, "ham1") || !strcmp(s, "sw") || 1405
1407 !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) 1406 if (!strcmp(s, "sw"))
1407 gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1408 else if (!strcmp(s, "ham1") ||
1409 !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
1408 gpmc_nand_data->ecc_opt = 1410 gpmc_nand_data->ecc_opt =
1409 OMAP_ECC_HAM1_CODE_HW; 1411 OMAP_ECC_HAM1_CODE_HW;
1410 else if (!strcmp(s, "bch4")) 1412 else if (!strcmp(s, "bch4"))
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index d42022f2a71e..53841dea80ea 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -663,7 +663,7 @@ void __init dra7xxx_check_revision(void)
663 663
664 default: 664 default:
665 /* Unknown default to latest silicon rev as default*/ 665 /* Unknown default to latest silicon rev as default*/
666 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n", 666 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
667 __func__, idcode, hawkeye, rev); 667 __func__, idcode, hawkeye, rev);
668 omap_revision = DRA752_REV_ES1_1; 668 omap_revision = DRA752_REV_ES1_1;
669 } 669 }
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 01ef59def44b..d22c30d3ccfa 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -56,7 +56,7 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
56 56
57 r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias); 57 r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
58 if (!IS_ERR(r)) { 58 if (!IS_ERR(r)) {
59 dev_warn(&od->pdev->dev, 59 dev_dbg(&od->pdev->dev,
60 "alias %s already exists\n", clk_alias); 60 "alias %s already exists\n", clk_alias);
61 clk_put(r); 61 clk_put(r);
62 return; 62 return;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6c074f37cdd2..8fd87a3055bf 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2185,6 +2185,8 @@ static int _enable(struct omap_hwmod *oh)
2185 oh->mux->pads_dynamic))) { 2185 oh->mux->pads_dynamic))) {
2186 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); 2186 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
2187 _reconfigure_io_chain(); 2187 _reconfigure_io_chain();
2188 } else if (oh->flags & HWMOD_FORCE_MSTANDBY) {
2189 _reconfigure_io_chain();
2188 } 2190 }
2189 2191
2190 _add_initiator_dep(oh, mpu_oh); 2192 _add_initiator_dep(oh, mpu_oh);
@@ -2291,6 +2293,8 @@ static int _idle(struct omap_hwmod *oh)
2291 if (oh->mux && oh->mux->pads_dynamic) { 2293 if (oh->mux && oh->mux->pads_dynamic) {
2292 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); 2294 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
2293 _reconfigure_io_chain(); 2295 _reconfigure_io_chain();
2296 } else if (oh->flags & HWMOD_FORCE_MSTANDBY) {
2297 _reconfigure_io_chain();
2294 } 2298 }
2295 2299
2296 oh->_state = _HWMOD_STATE_IDLE; 2300 oh->_state = _HWMOD_STATE_IDLE;
@@ -3345,6 +3349,9 @@ int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
3345 if (!ois) 3349 if (!ois)
3346 return 0; 3350 return 0;
3347 3351
3352 if (ois[0] == NULL) /* Empty list */
3353 return 0;
3354
3348 if (!linkspace) { 3355 if (!linkspace) {
3349 if (_alloc_linkspace(ois)) { 3356 if (_alloc_linkspace(ois)) {
3350 pr_err("omap_hwmod: could not allocate link space\n"); 3357 pr_err("omap_hwmod: could not allocate link space\n");
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 2757abf87fbc..5684f112654b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -35,6 +35,7 @@
35#include "i2c.h" 35#include "i2c.h"
36#include "mmc.h" 36#include "mmc.h"
37#include "wd_timer.h" 37#include "wd_timer.h"
38#include "soc.h"
38 39
39/* Base offset for all DRA7XX interrupts external to MPUSS */ 40/* Base offset for all DRA7XX interrupts external to MPUSS */
40#define DRA7XX_IRQ_GIC_START 32 41#define DRA7XX_IRQ_GIC_START 32
@@ -3261,7 +3262,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3261 &dra7xx_l4_per3__usb_otg_ss1, 3262 &dra7xx_l4_per3__usb_otg_ss1,
3262 &dra7xx_l4_per3__usb_otg_ss2, 3263 &dra7xx_l4_per3__usb_otg_ss2,
3263 &dra7xx_l4_per3__usb_otg_ss3, 3264 &dra7xx_l4_per3__usb_otg_ss3,
3264 &dra7xx_l4_per3__usb_otg_ss4,
3265 &dra7xx_l3_main_1__vcp1, 3265 &dra7xx_l3_main_1__vcp1,
3266 &dra7xx_l4_per2__vcp1, 3266 &dra7xx_l4_per2__vcp1,
3267 &dra7xx_l3_main_1__vcp2, 3267 &dra7xx_l3_main_1__vcp2,
@@ -3270,8 +3270,26 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3270 NULL, 3270 NULL,
3271}; 3271};
3272 3272
3273static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3274 &dra7xx_l4_per3__usb_otg_ss4,
3275 NULL,
3276};
3277
3278static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3279 NULL,
3280};
3281
3273int __init dra7xx_hwmod_init(void) 3282int __init dra7xx_hwmod_init(void)
3274{ 3283{
3284 int ret;
3285
3275 omap_hwmod_init(); 3286 omap_hwmod_init();
3276 return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); 3287 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3288
3289 if (!ret && soc_is_dra74x())
3290 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3291 else if (!ret && soc_is_dra72x())
3292 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3293
3294 return ret;
3277} 3295}
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 01ca8086fb6c..4376f59626d1 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -245,6 +245,8 @@ IS_AM_SUBCLASS(437x, 0x437)
245#define soc_is_omap54xx() 0 245#define soc_is_omap54xx() 0
246#define soc_is_omap543x() 0 246#define soc_is_omap543x() 0
247#define soc_is_dra7xx() 0 247#define soc_is_dra7xx() 0
248#define soc_is_dra74x() 0
249#define soc_is_dra72x() 0
248 250
249#if defined(MULTI_OMAP2) 251#if defined(MULTI_OMAP2)
250# if defined(CONFIG_ARCH_OMAP2) 252# if defined(CONFIG_ARCH_OMAP2)
@@ -393,7 +395,11 @@ IS_OMAP_TYPE(3430, 0x3430)
393 395
394#if defined(CONFIG_SOC_DRA7XX) 396#if defined(CONFIG_SOC_DRA7XX)
395#undef soc_is_dra7xx 397#undef soc_is_dra7xx
398#undef soc_is_dra74x
399#undef soc_is_dra72x
396#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7")) 400#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7"))
401#define soc_is_dra74x() (of_machine_is_compatible("ti,dra74"))
402#define soc_is_dra72x() (of_machine_is_compatible("ti,dra72"))
397#endif 403#endif
398 404
399/* Various silicon revisions for omap2 */ 405/* Various silicon revisions for omap2 */
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index e15dff790dbb..1e6c51c7c2d5 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -75,6 +75,7 @@ config ARCH_SH7372
75 select ARM_CPU_SUSPEND if PM || CPU_IDLE 75 select ARM_CPU_SUSPEND if PM || CPU_IDLE
76 select CPU_V7 76 select CPU_V7
77 select SH_CLK_CPG 77 select SH_CLK_CPG
78 select SH_INTC
78 select SYS_SUPPORTS_SH_CMT 79 select SYS_SUPPORTS_SH_CMT
79 select SYS_SUPPORTS_SH_TMU 80 select SYS_SUPPORTS_SH_TMU
80 81
@@ -85,6 +86,7 @@ config ARCH_SH73A0
85 select CPU_V7 86 select CPU_V7
86 select I2C 87 select I2C
87 select SH_CLK_CPG 88 select SH_CLK_CPG
89 select SH_INTC
88 select RENESAS_INTC_IRQPIN 90 select RENESAS_INTC_IRQPIN
89 select SYS_SUPPORTS_SH_CMT 91 select SYS_SUPPORTS_SH_CMT
90 select SYS_SUPPORTS_SH_TMU 92 select SYS_SUPPORTS_SH_TMU
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 17435c1aa2fe..126ddafad526 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -183,8 +183,8 @@ enum {
183 183
184static struct clk div4_clks[DIV4_NR] = { 184static struct clk div4_clks[DIV4_NR] = {
185 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT), 185 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
186 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT), 186 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
187 [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT), 187 [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
188}; 188};
189 189
190/* DIV6 clocks */ 190/* DIV6 clocks */
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index 10e193d707f5..453b23129cfa 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -152,7 +152,7 @@ enum {
152 152
153static struct clk div4_clks[DIV4_NR] = { 153static struct clk div4_clks[DIV4_NR] = {
154 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT), 154 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
155 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT), 155 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
156}; 156};
157 157
158/* DIV6 clocks */ 158/* DIV6 clocks */
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index d8c4048b9e33..02a6f45a0b9e 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
644 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ 644 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
645 CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */ 645 CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */
646 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */ 646 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
647 CLKDEV_DEV_ID("0xe6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */ 647 CLKDEV_DEV_ID("e6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
648 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ 648 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
649 CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */ 649 CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */
650 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ 650 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
index 2c2754e79cb3..f61158c6ce71 100644
--- a/arch/arm/mach-vexpress/spc.c
+++ b/arch/arm/mach-vexpress/spc.c
@@ -426,9 +426,15 @@ static int ve_spc_populate_opps(uint32_t cluster)
426 426
427static int ve_init_opp_table(struct device *cpu_dev) 427static int ve_init_opp_table(struct device *cpu_dev)
428{ 428{
429 int cluster = topology_physical_package_id(cpu_dev->id); 429 int cluster;
430 int idx, ret = 0, max_opp = info->num_opps[cluster]; 430 int idx, ret = 0, max_opp;
431 struct ve_spc_opp *opps = info->opps[cluster]; 431 struct ve_spc_opp *opps;
432
433 cluster = topology_physical_package_id(cpu_dev->id);
434 cluster = cluster < 0 ? 0 : cluster;
435
436 max_opp = info->num_opps[cluster];
437 opps = info->opps[cluster];
432 438
433 for (idx = 0; idx < max_opp; idx++, opps++) { 439 for (idx = 0; idx < max_opp; idx++, opps++) {
434 ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt); 440 ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt);
@@ -537,6 +543,8 @@ static struct clk *ve_spc_clk_register(struct device *cpu_dev)
537 spc->hw.init = &init; 543 spc->hw.init = &init;
538 spc->cluster = topology_physical_package_id(cpu_dev->id); 544 spc->cluster = topology_physical_package_id(cpu_dev->id);
539 545
546 spc->cluster = spc->cluster < 0 ? 0 : spc->cluster;
547
540 init.name = dev_name(cpu_dev); 548 init.name = dev_name(cpu_dev);
541 init.ops = &clk_spc_ops; 549 init.ops = &clk_spc_ops;
542 init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE; 550 init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 3815a8262af0..8c48c5c22a33 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -17,12 +17,6 @@
17 */ 17 */
18 .align 5 18 .align 5
19ENTRY(v6_early_abort) 19ENTRY(v6_early_abort)
20#ifdef CONFIG_CPU_V6
21 sub r1, sp, #4 @ Get unused stack location
22 strex r0, r1, [r1] @ Clear the exclusive monitor
23#elif defined(CONFIG_CPU_32v6K)
24 clrex
25#endif
26 mrc p15, 0, r1, c5, c0, 0 @ get FSR 20 mrc p15, 0, r1, c5, c0, 0 @ get FSR
27 mrc p15, 0, r0, c6, c0, 0 @ get FAR 21 mrc p15, 0, r0, c6, c0, 0 @ get FAR
28/* 22/*
diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S
index 703375277ba6..4812ad054214 100644
--- a/arch/arm/mm/abort-ev7.S
+++ b/arch/arm/mm/abort-ev7.S
@@ -13,12 +13,6 @@
13 */ 13 */
14 .align 5 14 .align 5
15ENTRY(v7_early_abort) 15ENTRY(v7_early_abort)
16 /*
17 * The effect of data aborts on on the exclusive access monitor are
18 * UNPREDICTABLE. Do a CLREX to clear the state
19 */
20 clrex
21
22 mrc p15, 0, r1, c5, c0, 0 @ get FSR 16 mrc p15, 0, r1, c5, c0, 0 @ get FSR
23 mrc p15, 0, r0, c6, c0, 0 @ get FAR 17 mrc p15, 0, r0, c6, c0, 0 @ get FAR
24 18
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-24 10:19:56 -0400