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authorCyril Chemparathy <cyril@ti.com>2010-04-14 14:44:49 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2010-05-06 18:02:07 -0400
commitd6961e6889a26de427aa6e0df823c789cf4a848f (patch)
tree121e053a0f993cfbde7f4de26704f138c47bbad1 /arch/arm
parentce100669d2ee202acac94d39f1a585c6b066cecc (diff)
Davinci: configurable pll divider mask
This patch allows socs to override the divider ratio mask by setting an optional field (div_ratio_mask) in the pll_data structure. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Tested-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-davinci/clock.c9
-rw-r--r--arch/arm/mach-davinci/clock.h1
2 files changed, 7 insertions, 3 deletions
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 5de60ae57903..868cb7693499 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -279,7 +279,7 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
279 279
280 v = __raw_readl(pll->base + clk->div_reg); 280 v = __raw_readl(pll->base + clk->div_reg);
281 if (v & PLLDIV_EN) { 281 if (v & PLLDIV_EN) {
282 plldiv = (v & PLLDIV_RATIO_MASK) + 1; 282 plldiv = (v & pll->div_ratio_mask) + 1;
283 if (plldiv) 283 if (plldiv)
284 rate /= plldiv; 284 rate /= plldiv;
285 } 285 }
@@ -319,7 +319,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
319 if (pll->flags & PLL_HAS_PREDIV) { 319 if (pll->flags & PLL_HAS_PREDIV) {
320 prediv = __raw_readl(pll->base + PREDIV); 320 prediv = __raw_readl(pll->base + PREDIV);
321 if (prediv & PLLDIV_EN) 321 if (prediv & PLLDIV_EN)
322 prediv = (prediv & PLLDIV_RATIO_MASK) + 1; 322 prediv = (prediv & pll->div_ratio_mask) + 1;
323 else 323 else
324 prediv = 1; 324 prediv = 1;
325 } 325 }
@@ -331,7 +331,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
331 if (pll->flags & PLL_HAS_POSTDIV) { 331 if (pll->flags & PLL_HAS_POSTDIV) {
332 postdiv = __raw_readl(pll->base + POSTDIV); 332 postdiv = __raw_readl(pll->base + POSTDIV);
333 if (postdiv & PLLDIV_EN) 333 if (postdiv & PLLDIV_EN)
334 postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1; 334 postdiv = (postdiv & pll->div_ratio_mask) + 1;
335 else 335 else
336 postdiv = 1; 336 postdiv = 1;
337 } 337 }
@@ -458,6 +458,9 @@ int __init davinci_clk_init(struct clk_lookup *clocks)
458 clk->recalc = clk_leafclk_recalc; 458 clk->recalc = clk_leafclk_recalc;
459 } 459 }
460 460
461 if (clk->pll_data && !clk->pll_data->div_ratio_mask)
462 clk->pll_data->div_ratio_mask = PLLDIV_RATIO_MASK;
463
461 if (clk->recalc) 464 if (clk->recalc)
462 clk->rate = clk->recalc(clk); 465 clk->rate = clk->recalc(clk);
463 466
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 53a0f7b90119..ce260153a717 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -76,6 +76,7 @@ struct pll_data {
76 u32 num; 76 u32 num;
77 u32 flags; 77 u32 flags;
78 u32 input_rate; 78 u32 input_rate;
79 u32 div_ratio_mask;
79}; 80};
80#define PLL_HAS_PREDIV 0x01 81#define PLL_HAS_PREDIV 0x01
81#define PLL_HAS_POSTDIV 0x02 82#define PLL_HAS_POSTDIV 0x02