diff options
author | Gregory Bean <gbean@codeaurora.org> | 2010-05-01 00:33:38 -0400 |
---|---|---|
committer | Daniel Walker <dwalker@codeaurora.org> | 2010-05-13 19:07:54 -0400 |
commit | d2e753bf935bb67fcddfd64017d2b302d6e2330d (patch) | |
tree | 5169f043592cd6a20fac1fe21ba6f4f74aa5a75e /arch/arm | |
parent | 8f90c7b60d487866841bfa2fd51792873e54a3a5 (diff) |
msm: generialize iomap to support multiple SOCs.
msm_iomap.h is specific to the MSM7x00 series devices. Generalize
this in preparation to support more devices.
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap-7x00.h | 139 | ||||
-rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap.h | 97 |
2 files changed, 142 insertions, 94 deletions
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h new file mode 100644 index 000000000000..cfff0e74f128 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h | |||
@@ -0,0 +1,139 @@ | |||
1 | /* arch/arm/mach-msm/include/mach/msm_iomap.h | ||
2 | * | ||
3 | * Copyright (C) 2007 Google, Inc. | ||
4 | * Author: Brian Swetland <swetland@google.com> | ||
5 | * | ||
6 | * This software is licensed under the terms of the GNU General Public | ||
7 | * License version 2, as published by the Free Software Foundation, and | ||
8 | * may be copied, distributed, and modified under those terms. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * | ||
16 | * The MSM peripherals are spread all over across 768MB of physical | ||
17 | * space, which makes just having a simple IO_ADDRESS macro to slide | ||
18 | * them into the right virtual location rough. Instead, we will | ||
19 | * provide a master phys->virt mapping for peripherals here. | ||
20 | * | ||
21 | */ | ||
22 | |||
23 | #ifndef __ASM_ARCH_MSM_IOMAP_7X00_H | ||
24 | #define __ASM_ARCH_MSM_IOMAP_7X00_H | ||
25 | |||
26 | #include <asm/sizes.h> | ||
27 | |||
28 | /* Physical base address and size of peripherals. | ||
29 | * Ordered by the virtual base addresses they will be mapped at. | ||
30 | * | ||
31 | * MSM_VIC_BASE must be an value that can be loaded via a "mov" | ||
32 | * instruction, otherwise entry-macro.S will not compile. | ||
33 | * | ||
34 | * If you add or remove entries here, you'll want to edit the | ||
35 | * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your | ||
36 | * changes. | ||
37 | * | ||
38 | */ | ||
39 | |||
40 | #ifdef __ASSEMBLY__ | ||
41 | #define IOMEM(x) x | ||
42 | #else | ||
43 | #define IOMEM(x) ((void __force __iomem *)(x)) | ||
44 | #endif | ||
45 | |||
46 | #define MSM_VIC_BASE IOMEM(0xE0000000) | ||
47 | #define MSM_VIC_PHYS 0xC0000000 | ||
48 | #define MSM_VIC_SIZE SZ_4K | ||
49 | |||
50 | #define MSM_CSR_BASE IOMEM(0xE0001000) | ||
51 | #define MSM_CSR_PHYS 0xC0100000 | ||
52 | #define MSM_CSR_SIZE SZ_4K | ||
53 | |||
54 | #define MSM_GPT_PHYS MSM_CSR_PHYS | ||
55 | #define MSM_GPT_BASE MSM_CSR_BASE | ||
56 | #define MSM_GPT_SIZE SZ_4K | ||
57 | |||
58 | #define MSM_DMOV_BASE IOMEM(0xE0002000) | ||
59 | #define MSM_DMOV_PHYS 0xA9700000 | ||
60 | #define MSM_DMOV_SIZE SZ_4K | ||
61 | |||
62 | #define MSM_GPIO1_BASE IOMEM(0xE0003000) | ||
63 | #define MSM_GPIO1_PHYS 0xA9200000 | ||
64 | #define MSM_GPIO1_SIZE SZ_4K | ||
65 | |||
66 | #define MSM_GPIO2_BASE IOMEM(0xE0004000) | ||
67 | #define MSM_GPIO2_PHYS 0xA9300000 | ||
68 | #define MSM_GPIO2_SIZE SZ_4K | ||
69 | |||
70 | #define MSM_CLK_CTL_BASE IOMEM(0xE0005000) | ||
71 | #define MSM_CLK_CTL_PHYS 0xA8600000 | ||
72 | #define MSM_CLK_CTL_SIZE SZ_4K | ||
73 | |||
74 | #define MSM_SHARED_RAM_BASE IOMEM(0xE0100000) | ||
75 | #define MSM_SHARED_RAM_PHYS 0x01F00000 | ||
76 | #define MSM_SHARED_RAM_SIZE SZ_1M | ||
77 | |||
78 | #define MSM_UART1_PHYS 0xA9A00000 | ||
79 | #define MSM_UART1_SIZE SZ_4K | ||
80 | |||
81 | #define MSM_UART2_PHYS 0xA9B00000 | ||
82 | #define MSM_UART2_SIZE SZ_4K | ||
83 | |||
84 | #define MSM_UART3_PHYS 0xA9C00000 | ||
85 | #define MSM_UART3_SIZE SZ_4K | ||
86 | |||
87 | #ifdef CONFIG_MSM_DEBUG_UART | ||
88 | #define MSM_DEBUG_UART_BASE 0xE1000000 | ||
89 | #if CONFIG_MSM_DEBUG_UART == 1 | ||
90 | #define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS | ||
91 | #elif CONFIG_MSM_DEBUG_UART == 2 | ||
92 | #define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS | ||
93 | #elif CONFIG_MSM_DEBUG_UART == 3 | ||
94 | #define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS | ||
95 | #endif | ||
96 | #define MSM_DEBUG_UART_SIZE SZ_4K | ||
97 | #endif | ||
98 | |||
99 | #define MSM_SDC1_PHYS 0xA0400000 | ||
100 | #define MSM_SDC1_SIZE SZ_4K | ||
101 | |||
102 | #define MSM_SDC2_PHYS 0xA0500000 | ||
103 | #define MSM_SDC2_SIZE SZ_4K | ||
104 | |||
105 | #define MSM_SDC3_PHYS 0xA0600000 | ||
106 | #define MSM_SDC3_SIZE SZ_4K | ||
107 | |||
108 | #define MSM_SDC4_PHYS 0xA0700000 | ||
109 | #define MSM_SDC4_SIZE SZ_4K | ||
110 | |||
111 | #define MSM_I2C_PHYS 0xA9900000 | ||
112 | #define MSM_I2C_SIZE SZ_4K | ||
113 | |||
114 | #define MSM_HSUSB_PHYS 0xA0800000 | ||
115 | #define MSM_HSUSB_SIZE SZ_4K | ||
116 | |||
117 | #define MSM_PMDH_PHYS 0xAA600000 | ||
118 | #define MSM_PMDH_SIZE SZ_4K | ||
119 | |||
120 | #define MSM_EMDH_PHYS 0xAA700000 | ||
121 | #define MSM_EMDH_SIZE SZ_4K | ||
122 | |||
123 | #define MSM_MDP_PHYS 0xAA200000 | ||
124 | #define MSM_MDP_SIZE 0x000F0000 | ||
125 | |||
126 | #define MSM_MDC_PHYS 0xAA500000 | ||
127 | #define MSM_MDC_SIZE SZ_1M | ||
128 | |||
129 | #define MSM_AD5_PHYS 0xAC000000 | ||
130 | #define MSM_AD5_SIZE (SZ_1M*13) | ||
131 | |||
132 | |||
133 | #if defined(CONFIG_ARCH_MSM7X30) | ||
134 | #define MSM_GCC_BASE IOMEM(0xF8009000) | ||
135 | #define MSM_GCC_PHYS 0xC0182000 | ||
136 | #define MSM_GCC_SIZE SZ_4K | ||
137 | #endif | ||
138 | |||
139 | #endif | ||
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index ce1effed5894..81da6b8e25a0 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /* arch/arm/mach-msm/include/mach/msm_iomap.h | 1 | /* |
2 | * | ||
3 | * Copyright (C) 2007 Google, Inc. | 2 | * Copyright (C) 2007 Google, Inc. |
3 | * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. | ||
4 | * Author: Brian Swetland <swetland@google.com> | 4 | * Author: Brian Swetland <swetland@google.com> |
5 | * | 5 | * |
6 | * This software is licensed under the terms of the GNU General Public | 6 | * This software is licensed under the terms of the GNU General Public |
@@ -43,97 +43,6 @@ | |||
43 | #define IOMEM(x) ((void __force __iomem *)(x)) | 43 | #define IOMEM(x) ((void __force __iomem *)(x)) |
44 | #endif | 44 | #endif |
45 | 45 | ||
46 | #define MSM_VIC_BASE IOMEM(0xE0000000) | 46 | #include "msm_iomap-7x00.h" |
47 | #define MSM_VIC_PHYS 0xC0000000 | ||
48 | #define MSM_VIC_SIZE SZ_4K | ||
49 | |||
50 | #define MSM_CSR_BASE IOMEM(0xE0001000) | ||
51 | #define MSM_CSR_PHYS 0xC0100000 | ||
52 | #define MSM_CSR_SIZE SZ_4K | ||
53 | |||
54 | #define MSM_GPT_PHYS MSM_CSR_PHYS | ||
55 | #define MSM_GPT_BASE MSM_CSR_BASE | ||
56 | #define MSM_GPT_SIZE SZ_4K | ||
57 | |||
58 | #define MSM_DMOV_BASE IOMEM(0xE0002000) | ||
59 | #define MSM_DMOV_PHYS 0xA9700000 | ||
60 | #define MSM_DMOV_SIZE SZ_4K | ||
61 | |||
62 | #define MSM_GPIO1_BASE IOMEM(0xE0003000) | ||
63 | #define MSM_GPIO1_PHYS 0xA9200000 | ||
64 | #define MSM_GPIO1_SIZE SZ_4K | ||
65 | |||
66 | #define MSM_GPIO2_BASE IOMEM(0xE0004000) | ||
67 | #define MSM_GPIO2_PHYS 0xA9300000 | ||
68 | #define MSM_GPIO2_SIZE SZ_4K | ||
69 | |||
70 | #define MSM_CLK_CTL_BASE IOMEM(0xE0005000) | ||
71 | #define MSM_CLK_CTL_PHYS 0xA8600000 | ||
72 | #define MSM_CLK_CTL_SIZE SZ_4K | ||
73 | |||
74 | #define MSM_SHARED_RAM_BASE IOMEM(0xE0100000) | ||
75 | #define MSM_SHARED_RAM_PHYS 0x01F00000 | ||
76 | #define MSM_SHARED_RAM_SIZE SZ_1M | ||
77 | |||
78 | #define MSM_UART1_PHYS 0xA9A00000 | ||
79 | #define MSM_UART1_SIZE SZ_4K | ||
80 | |||
81 | #define MSM_UART2_PHYS 0xA9B00000 | ||
82 | #define MSM_UART2_SIZE SZ_4K | ||
83 | |||
84 | #define MSM_UART3_PHYS 0xA9C00000 | ||
85 | #define MSM_UART3_SIZE SZ_4K | ||
86 | |||
87 | #ifdef CONFIG_MSM_DEBUG_UART | ||
88 | #define MSM_DEBUG_UART_BASE 0xE1000000 | ||
89 | #if CONFIG_MSM_DEBUG_UART == 1 | ||
90 | #define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS | ||
91 | #elif CONFIG_MSM_DEBUG_UART == 2 | ||
92 | #define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS | ||
93 | #elif CONFIG_MSM_DEBUG_UART == 3 | ||
94 | #define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS | ||
95 | #endif | ||
96 | #define MSM_DEBUG_UART_SIZE SZ_4K | ||
97 | #endif | ||
98 | |||
99 | #define MSM_SDC1_PHYS 0xA0400000 | ||
100 | #define MSM_SDC1_SIZE SZ_4K | ||
101 | |||
102 | #define MSM_SDC2_PHYS 0xA0500000 | ||
103 | #define MSM_SDC2_SIZE SZ_4K | ||
104 | |||
105 | #define MSM_SDC3_PHYS 0xA0600000 | ||
106 | #define MSM_SDC3_SIZE SZ_4K | ||
107 | |||
108 | #define MSM_SDC4_PHYS 0xA0700000 | ||
109 | #define MSM_SDC4_SIZE SZ_4K | ||
110 | |||
111 | #define MSM_I2C_PHYS 0xA9900000 | ||
112 | #define MSM_I2C_SIZE SZ_4K | ||
113 | |||
114 | #define MSM_HSUSB_PHYS 0xA0800000 | ||
115 | #define MSM_HSUSB_SIZE SZ_4K | ||
116 | |||
117 | #define MSM_PMDH_PHYS 0xAA600000 | ||
118 | #define MSM_PMDH_SIZE SZ_4K | ||
119 | |||
120 | #define MSM_EMDH_PHYS 0xAA700000 | ||
121 | #define MSM_EMDH_SIZE SZ_4K | ||
122 | |||
123 | #define MSM_MDP_PHYS 0xAA200000 | ||
124 | #define MSM_MDP_SIZE 0x000F0000 | ||
125 | |||
126 | #define MSM_MDC_PHYS 0xAA500000 | ||
127 | #define MSM_MDC_SIZE SZ_1M | ||
128 | |||
129 | #define MSM_AD5_PHYS 0xAC000000 | ||
130 | #define MSM_AD5_SIZE (SZ_1M*13) | ||
131 | |||
132 | |||
133 | #if defined(CONFIG_ARCH_MSM7X30) | ||
134 | #define MSM_GCC_BASE IOMEM(0xF8009000) | ||
135 | #define MSM_GCC_PHYS 0xC0182000 | ||
136 | #define MSM_GCC_SIZE SZ_4K | ||
137 | #endif | ||
138 | 47 | ||
139 | #endif | 48 | #endif |