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authorDaniel Walker <dwalker@codeaurora.org>2010-05-04 18:12:27 -0400
committerDaniel Walker <dwalker@codeaurora.org>2010-05-13 19:08:35 -0400
commitcf62ffae2550102557c0848ab63a771e032fcfd3 (patch)
tree676b8b833a168c8f8dee3cffbd63b784a471223c /arch/arm
parentacb241cb61945d9943e89da51e33bf4b71104164 (diff)
msm: io: add io support for 8x50
Signed-off-by: Daniel Walker <dwalker@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org> Signed-off-by: Gregory Bean <gbean@codeaurora.org> Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-msm/include/mach/io.h3
-rw-r--r--arch/arm/mach-msm/io.c39
2 files changed, 39 insertions, 3 deletions
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index aab964591db4..dbfb01304c82 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -26,4 +26,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m
26#define __io(a) __typesafe_io(a) 26#define __io(a) __typesafe_io(a)
27#define __mem_pci(a) (a) 27#define __mem_pci(a) (a)
28 28
29void msm_map_qsd8x50_io(void);
30extern unsigned int msm_shared_ram_phys;
31
29#endif 32#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index fde5e58b51c3..c94ba336c7fd 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -1,8 +1,9 @@
1/* arch/arm/mach-msm/io.c 1/* arch/arm/mach-msm/io.c
2 * 2 *
3 * MSM7K io support 3 * MSM7K, QSD io support
4 * 4 *
5 * Copyright (C) 2007 Google, Inc. 5 * Copyright (C) 2007 Google, Inc.
6 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
6 * Author: Brian Swetland <swetland@google.com> 7 * Author: Brian Swetland <swetland@google.com>
7 * 8 *
8 * This software is licensed under the terms of the GNU General Public 9 * This software is licensed under the terms of the GNU General Public
@@ -34,6 +35,8 @@
34 .type = MT_DEVICE_NONSHARED, \ 35 .type = MT_DEVICE_NONSHARED, \
35 } 36 }
36 37
38#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
39 || defined(CONFIG_ARCH_MSM7X25)
37static struct map_desc msm_io_desc[] __initdata = { 40static struct map_desc msm_io_desc[] __initdata = {
38 MSM_DEVICE(VIC), 41 MSM_DEVICE(VIC),
39 MSM_DEVICE(CSR), 42 MSM_DEVICE(CSR),
@@ -50,7 +53,7 @@ static struct map_desc msm_io_desc[] __initdata = {
50#endif 53#endif
51 { 54 {
52 .virtual = (unsigned long) MSM_SHARED_RAM_BASE, 55 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
53 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), 56 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
54 .length = MSM_SHARED_RAM_SIZE, 57 .length = MSM_SHARED_RAM_SIZE,
55 .type = MT_DEVICE, 58 .type = MT_DEVICE,
56 }, 59 },
@@ -63,9 +66,39 @@ void __init msm_map_common_io(void)
63 * pages are peripheral interface or not. 66 * pages are peripheral interface or not.
64 */ 67 */
65 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0)); 68 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
66
67 iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc)); 69 iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc));
68} 70}
71#endif
72
73#ifdef CONFIG_ARCH_QSD8X50
74static struct map_desc qsd8x50_io_desc[] __initdata = {
75 MSM_DEVICE(VIC),
76 MSM_DEVICE(CSR),
77 MSM_DEVICE(TMR),
78 MSM_DEVICE(DMOV),
79 MSM_DEVICE(GPIO1),
80 MSM_DEVICE(GPIO2),
81 MSM_DEVICE(CLK_CTL),
82 MSM_DEVICE(SIRC),
83 MSM_DEVICE(SCPLL),
84 MSM_DEVICE(AD5),
85 MSM_DEVICE(MDC),
86#ifdef CONFIG_MSM_DEBUG_UART
87 MSM_DEVICE(DEBUG_UART),
88#endif
89 {
90 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
91 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
92 .length = MSM_SHARED_RAM_SIZE,
93 .type = MT_DEVICE,
94 },
95};
96
97void __init msm_map_qsd8x50_io(void)
98{
99 iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc));
100}
101#endif /* CONFIG_ARCH_QSD8X50 */
69 102
70void __iomem * 103void __iomem *
71__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) 104__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)