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authorKukjin Kim <kgene.kim@samsung.com>2011-07-20 13:09:46 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-07-20 13:09:46 -0400
commitcf2e9c7b48f1e6c715e30952e5a3a5ef5cd0f8e4 (patch)
tree8e485f710138a330a56285b2a17d7debadf81c9b /arch/arm
parentb5930b83c2791bd3b2da120f98f844f96fb2ca50 (diff)
parente48055999575750158108b4cfc7fc22e4c972efc (diff)
Merge branch 'next-samsung-clkdev-fix' into next-samsung-cleanup
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig6
-rw-r--r--arch/arm/mach-exynos4/clock.c177
-rw-r--r--arch/arm/mach-exynos4/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-s3c2412/clock.c36
-rw-r--r--arch/arm/mach-s3c2416/clock.c10
-rw-r--r--arch/arm/mach-s3c2440/clock.c3
-rw-r--r--arch/arm/mach-s3c2443/clock.c16
-rw-r--r--arch/arm/mach-s3c64xx/clock.c86
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c74
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c68
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-s5pc100/clock.c163
-rw-r--r--arch/arm/mach-s5pc100/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-s5pv210/clock.c130
-rw-r--r--arch/arm/mach-s5pv210/include/mach/clkdev.h7
-rw-r--r--arch/arm/plat-s3c24xx/clock-dclk.c4
-rw-r--r--arch/arm/plat-s3c24xx/include/mach/clkdev.h7
-rw-r--r--arch/arm/plat-s3c24xx/s3c2410-clock.c21
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c39
-rw-r--r--arch/arm/plat-s5p/s5p-time.c9
-rw-r--r--arch/arm/plat-samsung/clock.c98
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h3
-rw-r--r--arch/arm/plat-samsung/pwm-clock.c10
-rw-r--r--arch/arm/plat-samsung/time.c2
25 files changed, 298 insertions, 699 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9adc278a22ab..2b5f82f34a7e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -682,6 +682,7 @@ config ARCH_S3C2410
682 select GENERIC_GPIO 682 select GENERIC_GPIO
683 select ARCH_HAS_CPUFREQ 683 select ARCH_HAS_CPUFREQ
684 select HAVE_CLK 684 select HAVE_CLK
685 select CLKDEV_LOOKUP
685 select ARCH_USES_GETTIMEOFFSET 686 select ARCH_USES_GETTIMEOFFSET
686 select HAVE_S3C2410_I2C if I2C 687 select HAVE_S3C2410_I2C if I2C
687 help 688 help
@@ -699,6 +700,7 @@ config ARCH_S3C64XX
699 select CPU_V6 700 select CPU_V6
700 select ARM_VIC 701 select ARM_VIC
701 select HAVE_CLK 702 select HAVE_CLK
703 select CLKDEV_LOOKUP
702 select NO_IOPORT 704 select NO_IOPORT
703 select ARCH_USES_GETTIMEOFFSET 705 select ARCH_USES_GETTIMEOFFSET
704 select ARCH_HAS_CPUFREQ 706 select ARCH_HAS_CPUFREQ
@@ -723,6 +725,7 @@ config ARCH_S5P64X0
723 select CPU_V6 725 select CPU_V6
724 select GENERIC_GPIO 726 select GENERIC_GPIO
725 select HAVE_CLK 727 select HAVE_CLK
728 select CLKDEV_LOOKUP
726 select HAVE_S3C2410_WATCHDOG if WATCHDOG 729 select HAVE_S3C2410_WATCHDOG if WATCHDOG
727 select GENERIC_CLOCKEVENTS 730 select GENERIC_CLOCKEVENTS
728 select HAVE_SCHED_CLOCK 731 select HAVE_SCHED_CLOCK
@@ -736,6 +739,7 @@ config ARCH_S5PC100
736 bool "Samsung S5PC100" 739 bool "Samsung S5PC100"
737 select GENERIC_GPIO 740 select GENERIC_GPIO
738 select HAVE_CLK 741 select HAVE_CLK
742 select CLKDEV_LOOKUP
739 select CPU_V7 743 select CPU_V7
740 select ARM_L1_CACHE_SHIFT_6 744 select ARM_L1_CACHE_SHIFT_6
741 select ARCH_USES_GETTIMEOFFSET 745 select ARCH_USES_GETTIMEOFFSET
@@ -751,6 +755,7 @@ config ARCH_S5PV210
751 select ARCH_SPARSEMEM_ENABLE 755 select ARCH_SPARSEMEM_ENABLE
752 select GENERIC_GPIO 756 select GENERIC_GPIO
753 select HAVE_CLK 757 select HAVE_CLK
758 select CLKDEV_LOOKUP
754 select ARM_L1_CACHE_SHIFT_6 759 select ARM_L1_CACHE_SHIFT_6
755 select ARCH_HAS_CPUFREQ 760 select ARCH_HAS_CPUFREQ
756 select GENERIC_CLOCKEVENTS 761 select GENERIC_CLOCKEVENTS
@@ -767,6 +772,7 @@ config ARCH_EXYNOS4
767 select ARCH_SPARSEMEM_ENABLE 772 select ARCH_SPARSEMEM_ENABLE
768 select GENERIC_GPIO 773 select GENERIC_GPIO
769 select HAVE_CLK 774 select HAVE_CLK
775 select CLKDEV_LOOKUP
770 select ARCH_HAS_CPUFREQ 776 select ARCH_HAS_CPUFREQ
771 select GENERIC_CLOCKEVENTS 777 select GENERIC_CLOCKEVENTS
772 select HAVE_S3C_RTC if RTC_CLASS 778 select HAVE_S3C_RTC if RTC_CLASS
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 871f9d508fde..98b5cc4a9b20 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -27,24 +27,20 @@
27 27
28static struct clk clk_sclk_hdmi27m = { 28static struct clk clk_sclk_hdmi27m = {
29 .name = "sclk_hdmi27m", 29 .name = "sclk_hdmi27m",
30 .id = -1,
31 .rate = 27000000, 30 .rate = 27000000,
32}; 31};
33 32
34static struct clk clk_sclk_hdmiphy = { 33static struct clk clk_sclk_hdmiphy = {
35 .name = "sclk_hdmiphy", 34 .name = "sclk_hdmiphy",
36 .id = -1,
37}; 35};
38 36
39static struct clk clk_sclk_usbphy0 = { 37static struct clk clk_sclk_usbphy0 = {
40 .name = "sclk_usbphy0", 38 .name = "sclk_usbphy0",
41 .id = -1,
42 .rate = 27000000, 39 .rate = 27000000,
43}; 40};
44 41
45static struct clk clk_sclk_usbphy1 = { 42static struct clk clk_sclk_usbphy1 = {
46 .name = "sclk_usbphy1", 43 .name = "sclk_usbphy1",
47 .id = -1,
48}; 44};
49 45
50static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) 46static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
@@ -132,7 +128,6 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
132static struct clksrc_clk clk_mout_apll = { 128static struct clksrc_clk clk_mout_apll = {
133 .clk = { 129 .clk = {
134 .name = "mout_apll", 130 .name = "mout_apll",
135 .id = -1,
136 }, 131 },
137 .sources = &clk_src_apll, 132 .sources = &clk_src_apll,
138 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, 133 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
@@ -141,7 +136,6 @@ static struct clksrc_clk clk_mout_apll = {
141static struct clksrc_clk clk_sclk_apll = { 136static struct clksrc_clk clk_sclk_apll = {
142 .clk = { 137 .clk = {
143 .name = "sclk_apll", 138 .name = "sclk_apll",
144 .id = -1,
145 .parent = &clk_mout_apll.clk, 139 .parent = &clk_mout_apll.clk,
146 }, 140 },
147 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, 141 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
@@ -150,7 +144,6 @@ static struct clksrc_clk clk_sclk_apll = {
150static struct clksrc_clk clk_mout_epll = { 144static struct clksrc_clk clk_mout_epll = {
151 .clk = { 145 .clk = {
152 .name = "mout_epll", 146 .name = "mout_epll",
153 .id = -1,
154 }, 147 },
155 .sources = &clk_src_epll, 148 .sources = &clk_src_epll,
156 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, 149 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
@@ -159,7 +152,6 @@ static struct clksrc_clk clk_mout_epll = {
159static struct clksrc_clk clk_mout_mpll = { 152static struct clksrc_clk clk_mout_mpll = {
160 .clk = { 153 .clk = {
161 .name = "mout_mpll", 154 .name = "mout_mpll",
162 .id = -1,
163 }, 155 },
164 .sources = &clk_src_mpll, 156 .sources = &clk_src_mpll,
165 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, 157 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
@@ -178,7 +170,6 @@ static struct clksrc_sources clkset_moutcore = {
178static struct clksrc_clk clk_moutcore = { 170static struct clksrc_clk clk_moutcore = {
179 .clk = { 171 .clk = {
180 .name = "moutcore", 172 .name = "moutcore",
181 .id = -1,
182 }, 173 },
183 .sources = &clkset_moutcore, 174 .sources = &clkset_moutcore,
184 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, 175 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
@@ -187,7 +178,6 @@ static struct clksrc_clk clk_moutcore = {
187static struct clksrc_clk clk_coreclk = { 178static struct clksrc_clk clk_coreclk = {
188 .clk = { 179 .clk = {
189 .name = "core_clk", 180 .name = "core_clk",
190 .id = -1,
191 .parent = &clk_moutcore.clk, 181 .parent = &clk_moutcore.clk,
192 }, 182 },
193 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, 183 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
@@ -196,7 +186,6 @@ static struct clksrc_clk clk_coreclk = {
196static struct clksrc_clk clk_armclk = { 186static struct clksrc_clk clk_armclk = {
197 .clk = { 187 .clk = {
198 .name = "armclk", 188 .name = "armclk",
199 .id = -1,
200 .parent = &clk_coreclk.clk, 189 .parent = &clk_coreclk.clk,
201 }, 190 },
202}; 191};
@@ -204,7 +193,6 @@ static struct clksrc_clk clk_armclk = {
204static struct clksrc_clk clk_aclk_corem0 = { 193static struct clksrc_clk clk_aclk_corem0 = {
205 .clk = { 194 .clk = {
206 .name = "aclk_corem0", 195 .name = "aclk_corem0",
207 .id = -1,
208 .parent = &clk_coreclk.clk, 196 .parent = &clk_coreclk.clk,
209 }, 197 },
210 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, 198 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@@ -213,7 +201,6 @@ static struct clksrc_clk clk_aclk_corem0 = {
213static struct clksrc_clk clk_aclk_cores = { 201static struct clksrc_clk clk_aclk_cores = {
214 .clk = { 202 .clk = {
215 .name = "aclk_cores", 203 .name = "aclk_cores",
216 .id = -1,
217 .parent = &clk_coreclk.clk, 204 .parent = &clk_coreclk.clk,
218 }, 205 },
219 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, 206 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@@ -222,7 +209,6 @@ static struct clksrc_clk clk_aclk_cores = {
222static struct clksrc_clk clk_aclk_corem1 = { 209static struct clksrc_clk clk_aclk_corem1 = {
223 .clk = { 210 .clk = {
224 .name = "aclk_corem1", 211 .name = "aclk_corem1",
225 .id = -1,
226 .parent = &clk_coreclk.clk, 212 .parent = &clk_coreclk.clk,
227 }, 213 },
228 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, 214 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
@@ -231,7 +217,6 @@ static struct clksrc_clk clk_aclk_corem1 = {
231static struct clksrc_clk clk_periphclk = { 217static struct clksrc_clk clk_periphclk = {
232 .clk = { 218 .clk = {
233 .name = "periphclk", 219 .name = "periphclk",
234 .id = -1,
235 .parent = &clk_coreclk.clk, 220 .parent = &clk_coreclk.clk,
236 }, 221 },
237 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, 222 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
@@ -252,7 +237,6 @@ static struct clksrc_sources clkset_mout_corebus = {
252static struct clksrc_clk clk_mout_corebus = { 237static struct clksrc_clk clk_mout_corebus = {
253 .clk = { 238 .clk = {
254 .name = "mout_corebus", 239 .name = "mout_corebus",
255 .id = -1,
256 }, 240 },
257 .sources = &clkset_mout_corebus, 241 .sources = &clkset_mout_corebus,
258 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, 242 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
@@ -261,7 +245,6 @@ static struct clksrc_clk clk_mout_corebus = {
261static struct clksrc_clk clk_sclk_dmc = { 245static struct clksrc_clk clk_sclk_dmc = {
262 .clk = { 246 .clk = {
263 .name = "sclk_dmc", 247 .name = "sclk_dmc",
264 .id = -1,
265 .parent = &clk_mout_corebus.clk, 248 .parent = &clk_mout_corebus.clk,
266 }, 249 },
267 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, 250 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
@@ -270,7 +253,6 @@ static struct clksrc_clk clk_sclk_dmc = {
270static struct clksrc_clk clk_aclk_cored = { 253static struct clksrc_clk clk_aclk_cored = {
271 .clk = { 254 .clk = {
272 .name = "aclk_cored", 255 .name = "aclk_cored",
273 .id = -1,
274 .parent = &clk_sclk_dmc.clk, 256 .parent = &clk_sclk_dmc.clk,
275 }, 257 },
276 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, 258 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
@@ -279,7 +261,6 @@ static struct clksrc_clk clk_aclk_cored = {
279static struct clksrc_clk clk_aclk_corep = { 261static struct clksrc_clk clk_aclk_corep = {
280 .clk = { 262 .clk = {
281 .name = "aclk_corep", 263 .name = "aclk_corep",
282 .id = -1,
283 .parent = &clk_aclk_cored.clk, 264 .parent = &clk_aclk_cored.clk,
284 }, 265 },
285 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, 266 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
@@ -288,7 +269,6 @@ static struct clksrc_clk clk_aclk_corep = {
288static struct clksrc_clk clk_aclk_acp = { 269static struct clksrc_clk clk_aclk_acp = {
289 .clk = { 270 .clk = {
290 .name = "aclk_acp", 271 .name = "aclk_acp",
291 .id = -1,
292 .parent = &clk_mout_corebus.clk, 272 .parent = &clk_mout_corebus.clk,
293 }, 273 },
294 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, 274 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
@@ -297,7 +277,6 @@ static struct clksrc_clk clk_aclk_acp = {
297static struct clksrc_clk clk_pclk_acp = { 277static struct clksrc_clk clk_pclk_acp = {
298 .clk = { 278 .clk = {
299 .name = "pclk_acp", 279 .name = "pclk_acp",
300 .id = -1,
301 .parent = &clk_aclk_acp.clk, 280 .parent = &clk_aclk_acp.clk,
302 }, 281 },
303 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, 282 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
@@ -318,7 +297,6 @@ static struct clksrc_sources clkset_aclk = {
318static struct clksrc_clk clk_aclk_200 = { 297static struct clksrc_clk clk_aclk_200 = {
319 .clk = { 298 .clk = {
320 .name = "aclk_200", 299 .name = "aclk_200",
321 .id = -1,
322 }, 300 },
323 .sources = &clkset_aclk, 301 .sources = &clkset_aclk,
324 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, 302 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
@@ -328,7 +306,6 @@ static struct clksrc_clk clk_aclk_200 = {
328static struct clksrc_clk clk_aclk_100 = { 306static struct clksrc_clk clk_aclk_100 = {
329 .clk = { 307 .clk = {
330 .name = "aclk_100", 308 .name = "aclk_100",
331 .id = -1,
332 }, 309 },
333 .sources = &clkset_aclk, 310 .sources = &clkset_aclk,
334 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, 311 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
@@ -338,7 +315,6 @@ static struct clksrc_clk clk_aclk_100 = {
338static struct clksrc_clk clk_aclk_160 = { 315static struct clksrc_clk clk_aclk_160 = {
339 .clk = { 316 .clk = {
340 .name = "aclk_160", 317 .name = "aclk_160",
341 .id = -1,
342 }, 318 },
343 .sources = &clkset_aclk, 319 .sources = &clkset_aclk,
344 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, 320 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
@@ -348,7 +324,6 @@ static struct clksrc_clk clk_aclk_160 = {
348static struct clksrc_clk clk_aclk_133 = { 324static struct clksrc_clk clk_aclk_133 = {
349 .clk = { 325 .clk = {
350 .name = "aclk_133", 326 .name = "aclk_133",
351 .id = -1,
352 }, 327 },
353 .sources = &clkset_aclk, 328 .sources = &clkset_aclk,
354 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, 329 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
@@ -368,7 +343,6 @@ static struct clksrc_sources clkset_vpllsrc = {
368static struct clksrc_clk clk_vpllsrc = { 343static struct clksrc_clk clk_vpllsrc = {
369 .clk = { 344 .clk = {
370 .name = "vpll_src", 345 .name = "vpll_src",
371 .id = -1,
372 .enable = exynos4_clksrc_mask_top_ctrl, 346 .enable = exynos4_clksrc_mask_top_ctrl,
373 .ctrlbit = (1 << 0), 347 .ctrlbit = (1 << 0),
374 }, 348 },
@@ -389,7 +363,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
389static struct clksrc_clk clk_sclk_vpll = { 363static struct clksrc_clk clk_sclk_vpll = {
390 .clk = { 364 .clk = {
391 .name = "sclk_vpll", 365 .name = "sclk_vpll",
392 .id = -1,
393 }, 366 },
394 .sources = &clkset_sclk_vpll, 367 .sources = &clkset_sclk_vpll,
395 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, 368 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
@@ -398,161 +371,151 @@ static struct clksrc_clk clk_sclk_vpll = {
398static struct clk init_clocks_off[] = { 371static struct clk init_clocks_off[] = {
399 { 372 {
400 .name = "timers", 373 .name = "timers",
401 .id = -1,
402 .parent = &clk_aclk_100.clk, 374 .parent = &clk_aclk_100.clk,
403 .enable = exynos4_clk_ip_peril_ctrl, 375 .enable = exynos4_clk_ip_peril_ctrl,
404 .ctrlbit = (1<<24), 376 .ctrlbit = (1<<24),
405 }, { 377 }, {
406 .name = "csis", 378 .name = "csis",
407 .id = 0, 379 .devname = "s5p-mipi-csis.0",
408 .enable = exynos4_clk_ip_cam_ctrl, 380 .enable = exynos4_clk_ip_cam_ctrl,
409 .ctrlbit = (1 << 4), 381 .ctrlbit = (1 << 4),
410 }, { 382 }, {
411 .name = "csis", 383 .name = "csis",
412 .id = 1, 384 .devname = "s5p-mipi-csis.1",
413 .enable = exynos4_clk_ip_cam_ctrl, 385 .enable = exynos4_clk_ip_cam_ctrl,
414 .ctrlbit = (1 << 5), 386 .ctrlbit = (1 << 5),
415 }, { 387 }, {
416 .name = "fimc", 388 .name = "fimc",
417 .id = 0, 389 .devname = "exynos4-fimc.0",
418 .enable = exynos4_clk_ip_cam_ctrl, 390 .enable = exynos4_clk_ip_cam_ctrl,
419 .ctrlbit = (1 << 0), 391 .ctrlbit = (1 << 0),
420 }, { 392 }, {
421 .name = "fimc", 393 .name = "fimc",
422 .id = 1, 394 .devname = "exynos4-fimc.1",
423 .enable = exynos4_clk_ip_cam_ctrl, 395 .enable = exynos4_clk_ip_cam_ctrl,
424 .ctrlbit = (1 << 1), 396 .ctrlbit = (1 << 1),
425 }, { 397 }, {
426 .name = "fimc", 398 .name = "fimc",
427 .id = 2, 399 .devname = "exynos4-fimc.2",
428 .enable = exynos4_clk_ip_cam_ctrl, 400 .enable = exynos4_clk_ip_cam_ctrl,
429 .ctrlbit = (1 << 2), 401 .ctrlbit = (1 << 2),
430 }, { 402 }, {
431 .name = "fimc", 403 .name = "fimc",
432 .id = 3, 404 .devname = "exynos4-fimc.3",
433 .enable = exynos4_clk_ip_cam_ctrl, 405 .enable = exynos4_clk_ip_cam_ctrl,
434 .ctrlbit = (1 << 3), 406 .ctrlbit = (1 << 3),
435 }, { 407 }, {
436 .name = "fimd", 408 .name = "fimd",
437 .id = 0, 409 .devname = "s5pv310-fb.0",
438 .enable = exynos4_clk_ip_lcd0_ctrl, 410 .enable = exynos4_clk_ip_lcd0_ctrl,
439 .ctrlbit = (1 << 0), 411 .ctrlbit = (1 << 0),
440 }, { 412 }, {
441 .name = "fimd", 413 .name = "fimd",
442 .id = 1, 414 .devname = "s5pv310-fb.1",
443 .enable = exynos4_clk_ip_lcd1_ctrl, 415 .enable = exynos4_clk_ip_lcd1_ctrl,
444 .ctrlbit = (1 << 0), 416 .ctrlbit = (1 << 0),
445 }, { 417 }, {
446 .name = "sataphy", 418 .name = "sataphy",
447 .id = -1,
448 .parent = &clk_aclk_133.clk, 419 .parent = &clk_aclk_133.clk,
449 .enable = exynos4_clk_ip_fsys_ctrl, 420 .enable = exynos4_clk_ip_fsys_ctrl,
450 .ctrlbit = (1 << 3), 421 .ctrlbit = (1 << 3),
451 }, { 422 }, {
452 .name = "hsmmc", 423 .name = "hsmmc",
453 .id = 0, 424 .devname = "s3c-sdhci.0",
454 .parent = &clk_aclk_133.clk, 425 .parent = &clk_aclk_133.clk,
455 .enable = exynos4_clk_ip_fsys_ctrl, 426 .enable = exynos4_clk_ip_fsys_ctrl,
456 .ctrlbit = (1 << 5), 427 .ctrlbit = (1 << 5),
457 }, { 428 }, {
458 .name = "hsmmc", 429 .name = "hsmmc",
459 .id = 1, 430 .devname = "s3c-sdhci.1",
460 .parent = &clk_aclk_133.clk, 431 .parent = &clk_aclk_133.clk,
461 .enable = exynos4_clk_ip_fsys_ctrl, 432 .enable = exynos4_clk_ip_fsys_ctrl,
462 .ctrlbit = (1 << 6), 433 .ctrlbit = (1 << 6),
463 }, { 434 }, {
464 .name = "hsmmc", 435 .name = "hsmmc",
465 .id = 2, 436 .devname = "s3c-sdhci.2",
466 .parent = &clk_aclk_133.clk, 437 .parent = &clk_aclk_133.clk,
467 .enable = exynos4_clk_ip_fsys_ctrl, 438 .enable = exynos4_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 7), 439 .ctrlbit = (1 << 7),
469 }, { 440 }, {
470 .name = "hsmmc", 441 .name = "hsmmc",
471 .id = 3, 442 .devname = "s3c-sdhci.3",
472 .parent = &clk_aclk_133.clk, 443 .parent = &clk_aclk_133.clk,
473 .enable = exynos4_clk_ip_fsys_ctrl, 444 .enable = exynos4_clk_ip_fsys_ctrl,
474 .ctrlbit = (1 << 8), 445 .ctrlbit = (1 << 8),
475 }, { 446 }, {
476 .name = "hsmmc", 447 .name = "dwmmc",
477 .id = 4,
478 .parent = &clk_aclk_133.clk, 448 .parent = &clk_aclk_133.clk,
479 .enable = exynos4_clk_ip_fsys_ctrl, 449 .enable = exynos4_clk_ip_fsys_ctrl,
480 .ctrlbit = (1 << 9), 450 .ctrlbit = (1 << 9),
481 }, { 451 }, {
482 .name = "sata", 452 .name = "sata",
483 .id = -1,
484 .parent = &clk_aclk_133.clk, 453 .parent = &clk_aclk_133.clk,
485 .enable = exynos4_clk_ip_fsys_ctrl, 454 .enable = exynos4_clk_ip_fsys_ctrl,
486 .ctrlbit = (1 << 10), 455 .ctrlbit = (1 << 10),
487 }, { 456 }, {
488 .name = "pdma", 457 .name = "pdma",
489 .id = 0, 458 .devname = "s3c-pl330.0",
490 .enable = exynos4_clk_ip_fsys_ctrl, 459 .enable = exynos4_clk_ip_fsys_ctrl,
491 .ctrlbit = (1 << 0), 460 .ctrlbit = (1 << 0),
492 }, { 461 }, {
493 .name = "pdma", 462 .name = "pdma",
494 .id = 1, 463 .devname = "s3c-pl330.1",
495 .enable = exynos4_clk_ip_fsys_ctrl, 464 .enable = exynos4_clk_ip_fsys_ctrl,
496 .ctrlbit = (1 << 1), 465 .ctrlbit = (1 << 1),
497 }, { 466 }, {
498 .name = "adc", 467 .name = "adc",
499 .id = -1,
500 .enable = exynos4_clk_ip_peril_ctrl, 468 .enable = exynos4_clk_ip_peril_ctrl,
501 .ctrlbit = (1 << 15), 469 .ctrlbit = (1 << 15),
502 }, { 470 }, {
503 .name = "keypad", 471 .name = "keypad",
504 .id = -1,
505 .enable = exynos4_clk_ip_perir_ctrl, 472 .enable = exynos4_clk_ip_perir_ctrl,
506 .ctrlbit = (1 << 16), 473 .ctrlbit = (1 << 16),
507 }, { 474 }, {
508 .name = "rtc", 475 .name = "rtc",
509 .id = -1,
510 .enable = exynos4_clk_ip_perir_ctrl, 476 .enable = exynos4_clk_ip_perir_ctrl,
511 .ctrlbit = (1 << 15), 477 .ctrlbit = (1 << 15),
512 }, { 478 }, {
513 .name = "watchdog", 479 .name = "watchdog",
514 .id = -1,
515 .parent = &clk_aclk_100.clk, 480 .parent = &clk_aclk_100.clk,
516 .enable = exynos4_clk_ip_perir_ctrl, 481 .enable = exynos4_clk_ip_perir_ctrl,
517 .ctrlbit = (1 << 14), 482 .ctrlbit = (1 << 14),
518 }, { 483 }, {
519 .name = "usbhost", 484 .name = "usbhost",
520 .id = -1,
521 .enable = exynos4_clk_ip_fsys_ctrl , 485 .enable = exynos4_clk_ip_fsys_ctrl ,
522 .ctrlbit = (1 << 12), 486 .ctrlbit = (1 << 12),
523 }, { 487 }, {
524 .name = "otg", 488 .name = "otg",
525 .id = -1,
526 .enable = exynos4_clk_ip_fsys_ctrl, 489 .enable = exynos4_clk_ip_fsys_ctrl,
527 .ctrlbit = (1 << 13), 490 .ctrlbit = (1 << 13),
528 }, { 491 }, {
529 .name = "spi", 492 .name = "spi",
530 .id = 0, 493 .devname = "s3c64xx-spi.0",
531 .enable = exynos4_clk_ip_peril_ctrl, 494 .enable = exynos4_clk_ip_peril_ctrl,
532 .ctrlbit = (1 << 16), 495 .ctrlbit = (1 << 16),
533 }, { 496 }, {
534 .name = "spi", 497 .name = "spi",
535 .id = 1, 498 .devname = "s3c64xx-spi.1",
536 .enable = exynos4_clk_ip_peril_ctrl, 499 .enable = exynos4_clk_ip_peril_ctrl,
537 .ctrlbit = (1 << 17), 500 .ctrlbit = (1 << 17),
538 }, { 501 }, {
539 .name = "spi", 502 .name = "spi",
540 .id = 2, 503 .devname = "s3c64xx-spi.2",
541 .enable = exynos4_clk_ip_peril_ctrl, 504 .enable = exynos4_clk_ip_peril_ctrl,
542 .ctrlbit = (1 << 18), 505 .ctrlbit = (1 << 18),
543 }, { 506 }, {
544 .name = "iis", 507 .name = "iis",
545 .id = 0, 508 .devname = "samsung-i2s.0",
546 .enable = exynos4_clk_ip_peril_ctrl, 509 .enable = exynos4_clk_ip_peril_ctrl,
547 .ctrlbit = (1 << 19), 510 .ctrlbit = (1 << 19),
548 }, { 511 }, {
549 .name = "iis", 512 .name = "iis",
550 .id = 1, 513 .devname = "samsung-i2s.1",
551 .enable = exynos4_clk_ip_peril_ctrl, 514 .enable = exynos4_clk_ip_peril_ctrl,
552 .ctrlbit = (1 << 20), 515 .ctrlbit = (1 << 20),
553 }, { 516 }, {
554 .name = "iis", 517 .name = "iis",
555 .id = 2, 518 .devname = "samsung-i2s.2",
556 .enable = exynos4_clk_ip_peril_ctrl, 519 .enable = exynos4_clk_ip_peril_ctrl,
557 .ctrlbit = (1 << 21), 520 .ctrlbit = (1 << 21),
558 }, { 521 }, {
@@ -562,125 +525,110 @@ static struct clk init_clocks_off[] = {
562 .ctrlbit = (1 << 27), 525 .ctrlbit = (1 << 27),
563 }, { 526 }, {
564 .name = "fimg2d", 527 .name = "fimg2d",
565 .id = -1,
566 .enable = exynos4_clk_ip_image_ctrl, 528 .enable = exynos4_clk_ip_image_ctrl,
567 .ctrlbit = (1 << 0), 529 .ctrlbit = (1 << 0),
568 }, { 530 }, {
569 .name = "i2c", 531 .name = "i2c",
570 .id = 0, 532 .devname = "s3c2440-i2c.0",
571 .parent = &clk_aclk_100.clk, 533 .parent = &clk_aclk_100.clk,
572 .enable = exynos4_clk_ip_peril_ctrl, 534 .enable = exynos4_clk_ip_peril_ctrl,
573 .ctrlbit = (1 << 6), 535 .ctrlbit = (1 << 6),
574 }, { 536 }, {
575 .name = "i2c", 537 .name = "i2c",
576 .id = 1, 538 .devname = "s3c2440-i2c.1",
577 .parent = &clk_aclk_100.clk, 539 .parent = &clk_aclk_100.clk,
578 .enable = exynos4_clk_ip_peril_ctrl, 540 .enable = exynos4_clk_ip_peril_ctrl,
579 .ctrlbit = (1 << 7), 541 .ctrlbit = (1 << 7),
580 }, { 542 }, {
581 .name = "i2c", 543 .name = "i2c",
582 .id = 2, 544 .devname = "s3c2440-i2c.2",
583 .parent = &clk_aclk_100.clk, 545 .parent = &clk_aclk_100.clk,
584 .enable = exynos4_clk_ip_peril_ctrl, 546 .enable = exynos4_clk_ip_peril_ctrl,
585 .ctrlbit = (1 << 8), 547 .ctrlbit = (1 << 8),
586 }, { 548 }, {
587 .name = "i2c", 549 .name = "i2c",
588 .id = 3, 550 .devname = "s3c2440-i2c.3",
589 .parent = &clk_aclk_100.clk, 551 .parent = &clk_aclk_100.clk,
590 .enable = exynos4_clk_ip_peril_ctrl, 552 .enable = exynos4_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 9), 553 .ctrlbit = (1 << 9),
592 }, { 554 }, {
593 .name = "i2c", 555 .name = "i2c",
594 .id = 4, 556 .devname = "s3c2440-i2c.4",
595 .parent = &clk_aclk_100.clk, 557 .parent = &clk_aclk_100.clk,
596 .enable = exynos4_clk_ip_peril_ctrl, 558 .enable = exynos4_clk_ip_peril_ctrl,
597 .ctrlbit = (1 << 10), 559 .ctrlbit = (1 << 10),
598 }, { 560 }, {
599 .name = "i2c", 561 .name = "i2c",
600 .id = 5, 562 .devname = "s3c2440-i2c.5",
601 .parent = &clk_aclk_100.clk, 563 .parent = &clk_aclk_100.clk,
602 .enable = exynos4_clk_ip_peril_ctrl, 564 .enable = exynos4_clk_ip_peril_ctrl,
603 .ctrlbit = (1 << 11), 565 .ctrlbit = (1 << 11),
604 }, { 566 }, {
605 .name = "i2c", 567 .name = "i2c",
606 .id = 6, 568 .devname = "s3c2440-i2c.6",
607 .parent = &clk_aclk_100.clk, 569 .parent = &clk_aclk_100.clk,
608 .enable = exynos4_clk_ip_peril_ctrl, 570 .enable = exynos4_clk_ip_peril_ctrl,
609 .ctrlbit = (1 << 12), 571 .ctrlbit = (1 << 12),
610 }, { 572 }, {
611 .name = "i2c", 573 .name = "i2c",
612 .id = 7, 574 .devname = "s3c2440-i2c.7",
613 .parent = &clk_aclk_100.clk, 575 .parent = &clk_aclk_100.clk,
614 .enable = exynos4_clk_ip_peril_ctrl, 576 .enable = exynos4_clk_ip_peril_ctrl,
615 .ctrlbit = (1 << 13), 577 .ctrlbit = (1 << 13),
616 }, { 578 }, {
617 .name = "SYSMMU_MDMA", 579 .name = "SYSMMU_MDMA",
618 .id = -1,
619 .enable = exynos4_clk_ip_image_ctrl, 580 .enable = exynos4_clk_ip_image_ctrl,
620 .ctrlbit = (1 << 5), 581 .ctrlbit = (1 << 5),
621 }, { 582 }, {
622 .name = "SYSMMU_FIMC0", 583 .name = "SYSMMU_FIMC0",
623 .id = -1,
624 .enable = exynos4_clk_ip_cam_ctrl, 584 .enable = exynos4_clk_ip_cam_ctrl,
625 .ctrlbit = (1 << 7), 585 .ctrlbit = (1 << 7),
626 }, { 586 }, {
627 .name = "SYSMMU_FIMC1", 587 .name = "SYSMMU_FIMC1",
628 .id = -1,
629 .enable = exynos4_clk_ip_cam_ctrl, 588 .enable = exynos4_clk_ip_cam_ctrl,
630 .ctrlbit = (1 << 8), 589 .ctrlbit = (1 << 8),
631 }, { 590 }, {
632 .name = "SYSMMU_FIMC2", 591 .name = "SYSMMU_FIMC2",
633 .id = -1,
634 .enable = exynos4_clk_ip_cam_ctrl, 592 .enable = exynos4_clk_ip_cam_ctrl,
635 .ctrlbit = (1 << 9), 593 .ctrlbit = (1 << 9),
636 }, { 594 }, {
637 .name = "SYSMMU_FIMC3", 595 .name = "SYSMMU_FIMC3",
638 .id = -1,
639 .enable = exynos4_clk_ip_cam_ctrl, 596 .enable = exynos4_clk_ip_cam_ctrl,
640 .ctrlbit = (1 << 10), 597 .ctrlbit = (1 << 10),
641 }, { 598 }, {
642 .name = "SYSMMU_JPEG", 599 .name = "SYSMMU_JPEG",
643 .id = -1,
644 .enable = exynos4_clk_ip_cam_ctrl, 600 .enable = exynos4_clk_ip_cam_ctrl,
645 .ctrlbit = (1 << 11), 601 .ctrlbit = (1 << 11),
646 }, { 602 }, {
647 .name = "SYSMMU_FIMD0", 603 .name = "SYSMMU_FIMD0",
648 .id = -1,
649 .enable = exynos4_clk_ip_lcd0_ctrl, 604 .enable = exynos4_clk_ip_lcd0_ctrl,
650 .ctrlbit = (1 << 4), 605 .ctrlbit = (1 << 4),
651 }, { 606 }, {
652 .name = "SYSMMU_FIMD1", 607 .name = "SYSMMU_FIMD1",
653 .id = -1,
654 .enable = exynos4_clk_ip_lcd1_ctrl, 608 .enable = exynos4_clk_ip_lcd1_ctrl,
655 .ctrlbit = (1 << 4), 609 .ctrlbit = (1 << 4),
656 }, { 610 }, {
657 .name = "SYSMMU_PCIe", 611 .name = "SYSMMU_PCIe",
658 .id = -1,
659 .enable = exynos4_clk_ip_fsys_ctrl, 612 .enable = exynos4_clk_ip_fsys_ctrl,
660 .ctrlbit = (1 << 18), 613 .ctrlbit = (1 << 18),
661 }, { 614 }, {
662 .name = "SYSMMU_G2D", 615 .name = "SYSMMU_G2D",
663 .id = -1,
664 .enable = exynos4_clk_ip_image_ctrl, 616 .enable = exynos4_clk_ip_image_ctrl,
665 .ctrlbit = (1 << 3), 617 .ctrlbit = (1 << 3),
666 }, { 618 }, {
667 .name = "SYSMMU_ROTATOR", 619 .name = "SYSMMU_ROTATOR",
668 .id = -1,
669 .enable = exynos4_clk_ip_image_ctrl, 620 .enable = exynos4_clk_ip_image_ctrl,
670 .ctrlbit = (1 << 4), 621 .ctrlbit = (1 << 4),
671 }, { 622 }, {
672 .name = "SYSMMU_TV", 623 .name = "SYSMMU_TV",
673 .id = -1,
674 .enable = exynos4_clk_ip_tv_ctrl, 624 .enable = exynos4_clk_ip_tv_ctrl,
675 .ctrlbit = (1 << 4), 625 .ctrlbit = (1 << 4),
676 }, { 626 }, {
677 .name = "SYSMMU_MFC_L", 627 .name = "SYSMMU_MFC_L",
678 .id = -1,
679 .enable = exynos4_clk_ip_mfc_ctrl, 628 .enable = exynos4_clk_ip_mfc_ctrl,
680 .ctrlbit = (1 << 1), 629 .ctrlbit = (1 << 1),
681 }, { 630 }, {
682 .name = "SYSMMU_MFC_R", 631 .name = "SYSMMU_MFC_R",
683 .id = -1,
684 .enable = exynos4_clk_ip_mfc_ctrl, 632 .enable = exynos4_clk_ip_mfc_ctrl,
685 .ctrlbit = (1 << 2), 633 .ctrlbit = (1 << 2),
686 } 634 }
@@ -689,32 +637,32 @@ static struct clk init_clocks_off[] = {
689static struct clk init_clocks[] = { 637static struct clk init_clocks[] = {
690 { 638 {
691 .name = "uart", 639 .name = "uart",
692 .id = 0, 640 .devname = "s5pv210-uart.0",
693 .enable = exynos4_clk_ip_peril_ctrl, 641 .enable = exynos4_clk_ip_peril_ctrl,
694 .ctrlbit = (1 << 0), 642 .ctrlbit = (1 << 0),
695 }, { 643 }, {
696 .name = "uart", 644 .name = "uart",
697 .id = 1, 645 .devname = "s5pv210-uart.1",
698 .enable = exynos4_clk_ip_peril_ctrl, 646 .enable = exynos4_clk_ip_peril_ctrl,
699 .ctrlbit = (1 << 1), 647 .ctrlbit = (1 << 1),
700 }, { 648 }, {
701 .name = "uart", 649 .name = "uart",
702 .id = 2, 650 .devname = "s5pv210-uart.2",
703 .enable = exynos4_clk_ip_peril_ctrl, 651 .enable = exynos4_clk_ip_peril_ctrl,
704 .ctrlbit = (1 << 2), 652 .ctrlbit = (1 << 2),
705 }, { 653 }, {
706 .name = "uart", 654 .name = "uart",
707 .id = 3, 655 .devname = "s5pv210-uart.3",
708 .enable = exynos4_clk_ip_peril_ctrl, 656 .enable = exynos4_clk_ip_peril_ctrl,
709 .ctrlbit = (1 << 3), 657 .ctrlbit = (1 << 3),
710 }, { 658 }, {
711 .name = "uart", 659 .name = "uart",
712 .id = 4, 660 .devname = "s5pv210-uart.4",
713 .enable = exynos4_clk_ip_peril_ctrl, 661 .enable = exynos4_clk_ip_peril_ctrl,
714 .ctrlbit = (1 << 4), 662 .ctrlbit = (1 << 4),
715 }, { 663 }, {
716 .name = "uart", 664 .name = "uart",
717 .id = 5, 665 .devname = "s5pv210-uart.5",
718 .enable = exynos4_clk_ip_peril_ctrl, 666 .enable = exynos4_clk_ip_peril_ctrl,
719 .ctrlbit = (1 << 5), 667 .ctrlbit = (1 << 5),
720 } 668 }
@@ -750,7 +698,6 @@ static struct clksrc_sources clkset_mout_g2d0 = {
750static struct clksrc_clk clk_mout_g2d0 = { 698static struct clksrc_clk clk_mout_g2d0 = {
751 .clk = { 699 .clk = {
752 .name = "mout_g2d0", 700 .name = "mout_g2d0",
753 .id = -1,
754 }, 701 },
755 .sources = &clkset_mout_g2d0, 702 .sources = &clkset_mout_g2d0,
756 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, 703 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
@@ -769,7 +716,6 @@ static struct clksrc_sources clkset_mout_g2d1 = {
769static struct clksrc_clk clk_mout_g2d1 = { 716static struct clksrc_clk clk_mout_g2d1 = {
770 .clk = { 717 .clk = {
771 .name = "mout_g2d1", 718 .name = "mout_g2d1",
772 .id = -1,
773 }, 719 },
774 .sources = &clkset_mout_g2d1, 720 .sources = &clkset_mout_g2d1,
775 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, 721 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
@@ -788,7 +734,6 @@ static struct clksrc_sources clkset_mout_g2d = {
788static struct clksrc_clk clk_dout_mmc0 = { 734static struct clksrc_clk clk_dout_mmc0 = {
789 .clk = { 735 .clk = {
790 .name = "dout_mmc0", 736 .name = "dout_mmc0",
791 .id = -1,
792 }, 737 },
793 .sources = &clkset_group, 738 .sources = &clkset_group,
794 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, 739 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
@@ -798,7 +743,6 @@ static struct clksrc_clk clk_dout_mmc0 = {
798static struct clksrc_clk clk_dout_mmc1 = { 743static struct clksrc_clk clk_dout_mmc1 = {
799 .clk = { 744 .clk = {
800 .name = "dout_mmc1", 745 .name = "dout_mmc1",
801 .id = -1,
802 }, 746 },
803 .sources = &clkset_group, 747 .sources = &clkset_group,
804 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, 748 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
@@ -808,7 +752,6 @@ static struct clksrc_clk clk_dout_mmc1 = {
808static struct clksrc_clk clk_dout_mmc2 = { 752static struct clksrc_clk clk_dout_mmc2 = {
809 .clk = { 753 .clk = {
810 .name = "dout_mmc2", 754 .name = "dout_mmc2",
811 .id = -1,
812 }, 755 },
813 .sources = &clkset_group, 756 .sources = &clkset_group,
814 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, 757 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
@@ -818,7 +761,6 @@ static struct clksrc_clk clk_dout_mmc2 = {
818static struct clksrc_clk clk_dout_mmc3 = { 761static struct clksrc_clk clk_dout_mmc3 = {
819 .clk = { 762 .clk = {
820 .name = "dout_mmc3", 763 .name = "dout_mmc3",
821 .id = -1,
822 }, 764 },
823 .sources = &clkset_group, 765 .sources = &clkset_group,
824 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, 766 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
@@ -828,7 +770,6 @@ static struct clksrc_clk clk_dout_mmc3 = {
828static struct clksrc_clk clk_dout_mmc4 = { 770static struct clksrc_clk clk_dout_mmc4 = {
829 .clk = { 771 .clk = {
830 .name = "dout_mmc4", 772 .name = "dout_mmc4",
831 .id = -1,
832 }, 773 },
833 .sources = &clkset_group, 774 .sources = &clkset_group,
834 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, 775 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
@@ -839,7 +780,7 @@ static struct clksrc_clk clksrcs[] = {
839 { 780 {
840 .clk = { 781 .clk = {
841 .name = "uclk1", 782 .name = "uclk1",
842 .id = 0, 783 .devname = "s5pv210-uart.0",
843 .enable = exynos4_clksrc_mask_peril0_ctrl, 784 .enable = exynos4_clksrc_mask_peril0_ctrl,
844 .ctrlbit = (1 << 0), 785 .ctrlbit = (1 << 0),
845 }, 786 },
@@ -849,7 +790,7 @@ static struct clksrc_clk clksrcs[] = {
849 }, { 790 }, {
850 .clk = { 791 .clk = {
851 .name = "uclk1", 792 .name = "uclk1",
852 .id = 1, 793 .devname = "s5pv210-uart.1",
853 .enable = exynos4_clksrc_mask_peril0_ctrl, 794 .enable = exynos4_clksrc_mask_peril0_ctrl,
854 .ctrlbit = (1 << 4), 795 .ctrlbit = (1 << 4),
855 }, 796 },
@@ -859,7 +800,7 @@ static struct clksrc_clk clksrcs[] = {
859 }, { 800 }, {
860 .clk = { 801 .clk = {
861 .name = "uclk1", 802 .name = "uclk1",
862 .id = 2, 803 .devname = "s5pv210-uart.2",
863 .enable = exynos4_clksrc_mask_peril0_ctrl, 804 .enable = exynos4_clksrc_mask_peril0_ctrl,
864 .ctrlbit = (1 << 8), 805 .ctrlbit = (1 << 8),
865 }, 806 },
@@ -869,7 +810,7 @@ static struct clksrc_clk clksrcs[] = {
869 }, { 810 }, {
870 .clk = { 811 .clk = {
871 .name = "uclk1", 812 .name = "uclk1",
872 .id = 3, 813 .devname = "s5pv210-uart.3",
873 .enable = exynos4_clksrc_mask_peril0_ctrl, 814 .enable = exynos4_clksrc_mask_peril0_ctrl,
874 .ctrlbit = (1 << 12), 815 .ctrlbit = (1 << 12),
875 }, 816 },
@@ -879,7 +820,6 @@ static struct clksrc_clk clksrcs[] = {
879 }, { 820 }, {
880 .clk = { 821 .clk = {
881 .name = "sclk_pwm", 822 .name = "sclk_pwm",
882 .id = -1,
883 .enable = exynos4_clksrc_mask_peril0_ctrl, 823 .enable = exynos4_clksrc_mask_peril0_ctrl,
884 .ctrlbit = (1 << 24), 824 .ctrlbit = (1 << 24),
885 }, 825 },
@@ -889,7 +829,7 @@ static struct clksrc_clk clksrcs[] = {
889 }, { 829 }, {
890 .clk = { 830 .clk = {
891 .name = "sclk_csis", 831 .name = "sclk_csis",
892 .id = 0, 832 .devname = "s5p-mipi-csis.0",
893 .enable = exynos4_clksrc_mask_cam_ctrl, 833 .enable = exynos4_clksrc_mask_cam_ctrl,
894 .ctrlbit = (1 << 24), 834 .ctrlbit = (1 << 24),
895 }, 835 },
@@ -899,7 +839,7 @@ static struct clksrc_clk clksrcs[] = {
899 }, { 839 }, {
900 .clk = { 840 .clk = {
901 .name = "sclk_csis", 841 .name = "sclk_csis",
902 .id = 1, 842 .devname = "s5p-mipi-csis.1",
903 .enable = exynos4_clksrc_mask_cam_ctrl, 843 .enable = exynos4_clksrc_mask_cam_ctrl,
904 .ctrlbit = (1 << 28), 844 .ctrlbit = (1 << 28),
905 }, 845 },
@@ -909,7 +849,7 @@ static struct clksrc_clk clksrcs[] = {
909 }, { 849 }, {
910 .clk = { 850 .clk = {
911 .name = "sclk_cam", 851 .name = "sclk_cam",
912 .id = 0, 852 .devname = "exynos4-fimc.0",
913 .enable = exynos4_clksrc_mask_cam_ctrl, 853 .enable = exynos4_clksrc_mask_cam_ctrl,
914 .ctrlbit = (1 << 16), 854 .ctrlbit = (1 << 16),
915 }, 855 },
@@ -919,7 +859,7 @@ static struct clksrc_clk clksrcs[] = {
919 }, { 859 }, {
920 .clk = { 860 .clk = {
921 .name = "sclk_cam", 861 .name = "sclk_cam",
922 .id = 1, 862 .devname = "exynos4-fimc.1",
923 .enable = exynos4_clksrc_mask_cam_ctrl, 863 .enable = exynos4_clksrc_mask_cam_ctrl,
924 .ctrlbit = (1 << 20), 864 .ctrlbit = (1 << 20),
925 }, 865 },
@@ -929,7 +869,7 @@ static struct clksrc_clk clksrcs[] = {
929 }, { 869 }, {
930 .clk = { 870 .clk = {
931 .name = "sclk_fimc", 871 .name = "sclk_fimc",
932 .id = 0, 872 .devname = "exynos4-fimc.0",
933 .enable = exynos4_clksrc_mask_cam_ctrl, 873 .enable = exynos4_clksrc_mask_cam_ctrl,
934 .ctrlbit = (1 << 0), 874 .ctrlbit = (1 << 0),
935 }, 875 },
@@ -939,7 +879,7 @@ static struct clksrc_clk clksrcs[] = {
939 }, { 879 }, {
940 .clk = { 880 .clk = {
941 .name = "sclk_fimc", 881 .name = "sclk_fimc",
942 .id = 1, 882 .devname = "exynos4-fimc.1",
943 .enable = exynos4_clksrc_mask_cam_ctrl, 883 .enable = exynos4_clksrc_mask_cam_ctrl,
944 .ctrlbit = (1 << 4), 884 .ctrlbit = (1 << 4),
945 }, 885 },
@@ -949,7 +889,7 @@ static struct clksrc_clk clksrcs[] = {
949 }, { 889 }, {
950 .clk = { 890 .clk = {
951 .name = "sclk_fimc", 891 .name = "sclk_fimc",
952 .id = 2, 892 .devname = "exynos4-fimc.2",
953 .enable = exynos4_clksrc_mask_cam_ctrl, 893 .enable = exynos4_clksrc_mask_cam_ctrl,
954 .ctrlbit = (1 << 8), 894 .ctrlbit = (1 << 8),
955 }, 895 },
@@ -959,7 +899,7 @@ static struct clksrc_clk clksrcs[] = {
959 }, { 899 }, {
960 .clk = { 900 .clk = {
961 .name = "sclk_fimc", 901 .name = "sclk_fimc",
962 .id = 3, 902 .devname = "exynos4-fimc.3",
963 .enable = exynos4_clksrc_mask_cam_ctrl, 903 .enable = exynos4_clksrc_mask_cam_ctrl,
964 .ctrlbit = (1 << 12), 904 .ctrlbit = (1 << 12),
965 }, 905 },
@@ -969,7 +909,7 @@ static struct clksrc_clk clksrcs[] = {
969 }, { 909 }, {
970 .clk = { 910 .clk = {
971 .name = "sclk_fimd", 911 .name = "sclk_fimd",
972 .id = 0, 912 .devname = "s5pv310-fb.0",
973 .enable = exynos4_clksrc_mask_lcd0_ctrl, 913 .enable = exynos4_clksrc_mask_lcd0_ctrl,
974 .ctrlbit = (1 << 0), 914 .ctrlbit = (1 << 0),
975 }, 915 },
@@ -979,7 +919,7 @@ static struct clksrc_clk clksrcs[] = {
979 }, { 919 }, {
980 .clk = { 920 .clk = {
981 .name = "sclk_fimd", 921 .name = "sclk_fimd",
982 .id = 1, 922 .devname = "s5pv310-fb.1",
983 .enable = exynos4_clksrc_mask_lcd1_ctrl, 923 .enable = exynos4_clksrc_mask_lcd1_ctrl,
984 .ctrlbit = (1 << 0), 924 .ctrlbit = (1 << 0),
985 }, 925 },
@@ -989,7 +929,6 @@ static struct clksrc_clk clksrcs[] = {
989 }, { 929 }, {
990 .clk = { 930 .clk = {
991 .name = "sclk_sata", 931 .name = "sclk_sata",
992 .id = -1,
993 .enable = exynos4_clksrc_mask_fsys_ctrl, 932 .enable = exynos4_clksrc_mask_fsys_ctrl,
994 .ctrlbit = (1 << 24), 933 .ctrlbit = (1 << 24),
995 }, 934 },
@@ -999,7 +938,7 @@ static struct clksrc_clk clksrcs[] = {
999 }, { 938 }, {
1000 .clk = { 939 .clk = {
1001 .name = "sclk_spi", 940 .name = "sclk_spi",
1002 .id = 0, 941 .devname = "s3c64xx-spi.0",
1003 .enable = exynos4_clksrc_mask_peril1_ctrl, 942 .enable = exynos4_clksrc_mask_peril1_ctrl,
1004 .ctrlbit = (1 << 16), 943 .ctrlbit = (1 << 16),
1005 }, 944 },
@@ -1009,7 +948,7 @@ static struct clksrc_clk clksrcs[] = {
1009 }, { 948 }, {
1010 .clk = { 949 .clk = {
1011 .name = "sclk_spi", 950 .name = "sclk_spi",
1012 .id = 1, 951 .devname = "s3c64xx-spi.1",
1013 .enable = exynos4_clksrc_mask_peril1_ctrl, 952 .enable = exynos4_clksrc_mask_peril1_ctrl,
1014 .ctrlbit = (1 << 20), 953 .ctrlbit = (1 << 20),
1015 }, 954 },
@@ -1019,7 +958,7 @@ static struct clksrc_clk clksrcs[] = {
1019 }, { 958 }, {
1020 .clk = { 959 .clk = {
1021 .name = "sclk_spi", 960 .name = "sclk_spi",
1022 .id = 2, 961 .devname = "s3c64xx-spi.2",
1023 .enable = exynos4_clksrc_mask_peril1_ctrl, 962 .enable = exynos4_clksrc_mask_peril1_ctrl,
1024 .ctrlbit = (1 << 24), 963 .ctrlbit = (1 << 24),
1025 }, 964 },
@@ -1029,7 +968,6 @@ static struct clksrc_clk clksrcs[] = {
1029 }, { 968 }, {
1030 .clk = { 969 .clk = {
1031 .name = "sclk_fimg2d", 970 .name = "sclk_fimg2d",
1032 .id = -1,
1033 }, 971 },
1034 .sources = &clkset_mout_g2d, 972 .sources = &clkset_mout_g2d,
1035 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, 973 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
@@ -1037,7 +975,7 @@ static struct clksrc_clk clksrcs[] = {
1037 }, { 975 }, {
1038 .clk = { 976 .clk = {
1039 .name = "sclk_mmc", 977 .name = "sclk_mmc",
1040 .id = 0, 978 .devname = "s3c-sdhci.0",
1041 .parent = &clk_dout_mmc0.clk, 979 .parent = &clk_dout_mmc0.clk,
1042 .enable = exynos4_clksrc_mask_fsys_ctrl, 980 .enable = exynos4_clksrc_mask_fsys_ctrl,
1043 .ctrlbit = (1 << 0), 981 .ctrlbit = (1 << 0),
@@ -1046,7 +984,7 @@ static struct clksrc_clk clksrcs[] = {
1046 }, { 984 }, {
1047 .clk = { 985 .clk = {
1048 .name = "sclk_mmc", 986 .name = "sclk_mmc",
1049 .id = 1, 987 .devname = "s3c-sdhci.1",
1050 .parent = &clk_dout_mmc1.clk, 988 .parent = &clk_dout_mmc1.clk,
1051 .enable = exynos4_clksrc_mask_fsys_ctrl, 989 .enable = exynos4_clksrc_mask_fsys_ctrl,
1052 .ctrlbit = (1 << 4), 990 .ctrlbit = (1 << 4),
@@ -1055,7 +993,7 @@ static struct clksrc_clk clksrcs[] = {
1055 }, { 993 }, {
1056 .clk = { 994 .clk = {
1057 .name = "sclk_mmc", 995 .name = "sclk_mmc",
1058 .id = 2, 996 .devname = "s3c-sdhci.2",
1059 .parent = &clk_dout_mmc2.clk, 997 .parent = &clk_dout_mmc2.clk,
1060 .enable = exynos4_clksrc_mask_fsys_ctrl, 998 .enable = exynos4_clksrc_mask_fsys_ctrl,
1061 .ctrlbit = (1 << 8), 999 .ctrlbit = (1 << 8),
@@ -1064,7 +1002,7 @@ static struct clksrc_clk clksrcs[] = {
1064 }, { 1002 }, {
1065 .clk = { 1003 .clk = {
1066 .name = "sclk_mmc", 1004 .name = "sclk_mmc",
1067 .id = 3, 1005 .devname = "s3c-sdhci.3",
1068 .parent = &clk_dout_mmc3.clk, 1006 .parent = &clk_dout_mmc3.clk,
1069 .enable = exynos4_clksrc_mask_fsys_ctrl, 1007 .enable = exynos4_clksrc_mask_fsys_ctrl,
1070 .ctrlbit = (1 << 12), 1008 .ctrlbit = (1 << 12),
@@ -1072,8 +1010,7 @@ static struct clksrc_clk clksrcs[] = {
1072 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, 1010 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1073 }, { 1011 }, {
1074 .clk = { 1012 .clk = {
1075 .name = "sclk_mmc", 1013 .name = "sclk_dwmmc",
1076 .id = 4,
1077 .parent = &clk_dout_mmc4.clk, 1014 .parent = &clk_dout_mmc4.clk,
1078 .enable = exynos4_clksrc_mask_fsys_ctrl, 1015 .enable = exynos4_clksrc_mask_fsys_ctrl,
1079 .ctrlbit = (1 << 16), 1016 .ctrlbit = (1 << 16),
diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 0c0505b025cb..140711db6c89 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable)
95 95
96static struct clk clk_erefclk = { 96static struct clk clk_erefclk = {
97 .name = "erefclk", 97 .name = "erefclk",
98 .id = -1,
99}; 98};
100 99
101static struct clk clk_urefclk = { 100static struct clk clk_urefclk = {
102 .name = "urefclk", 101 .name = "urefclk",
103 .id = -1,
104}; 102};
105 103
106static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) 104static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
@@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
122 120
123static struct clk clk_usysclk = { 121static struct clk clk_usysclk = {
124 .name = "usysclk", 122 .name = "usysclk",
125 .id = -1,
126 .parent = &clk_xtal, 123 .parent = &clk_xtal,
127 .ops = &(struct clk_ops) { 124 .ops = &(struct clk_ops) {
128 .set_parent = s3c2412_setparent_usysclk, 125 .set_parent = s3c2412_setparent_usysclk,
@@ -132,13 +129,11 @@ static struct clk clk_usysclk = {
132static struct clk clk_mrefclk = { 129static struct clk clk_mrefclk = {
133 .name = "mrefclk", 130 .name = "mrefclk",
134 .parent = &clk_xtal, 131 .parent = &clk_xtal,
135 .id = -1,
136}; 132};
137 133
138static struct clk clk_mdivclk = { 134static struct clk clk_mdivclk = {
139 .name = "mdivclk", 135 .name = "mdivclk",
140 .parent = &clk_xtal, 136 .parent = &clk_xtal,
141 .id = -1,
142}; 137};
143 138
144static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent) 139static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
@@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
200 195
201static struct clk clk_usbsrc = { 196static struct clk clk_usbsrc = {
202 .name = "usbsrc", 197 .name = "usbsrc",
203 .id = -1,
204 .ops = &(struct clk_ops) { 198 .ops = &(struct clk_ops) {
205 .get_rate = s3c2412_getrate_usbsrc, 199 .get_rate = s3c2412_getrate_usbsrc,
206 .set_rate = s3c2412_setrate_usbsrc, 200 .set_rate = s3c2412_setrate_usbsrc,
@@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
228 222
229static struct clk clk_msysclk = { 223static struct clk clk_msysclk = {
230 .name = "msysclk", 224 .name = "msysclk",
231 .id = -1,
232 .ops = &(struct clk_ops) { 225 .ops = &(struct clk_ops) {
233 .set_parent = s3c2412_setparent_msysclk, 226 .set_parent = s3c2412_setparent_msysclk,
234 }, 227 },
@@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
268 261
269static struct clk clk_armclk = { 262static struct clk clk_armclk = {
270 .name = "armclk", 263 .name = "armclk",
271 .id = -1,
272 .parent = &clk_msysclk, 264 .parent = &clk_msysclk,
273 .ops = &(struct clk_ops) { 265 .ops = &(struct clk_ops) {
274 .set_parent = s3c2412_setparent_armclk, 266 .set_parent = s3c2412_setparent_armclk,
@@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
344 336
345static struct clk clk_uart = { 337static struct clk clk_uart = {
346 .name = "uartclk", 338 .name = "uartclk",
347 .id = -1,
348 .ops = &(struct clk_ops) { 339 .ops = &(struct clk_ops) {
349 .get_rate = s3c2412_getrate_uart, 340 .get_rate = s3c2412_getrate_uart,
350 .set_rate = s3c2412_setrate_uart, 341 .set_rate = s3c2412_setrate_uart,
@@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
397 388
398static struct clk clk_i2s = { 389static struct clk clk_i2s = {
399 .name = "i2sclk", 390 .name = "i2sclk",
400 .id = -1,
401 .ops = &(struct clk_ops) { 391 .ops = &(struct clk_ops) {
402 .get_rate = s3c2412_getrate_i2s, 392 .get_rate = s3c2412_getrate_i2s,
403 .set_rate = s3c2412_setrate_i2s, 393 .set_rate = s3c2412_setrate_i2s,
@@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
449 439
450static struct clk clk_cam = { 440static struct clk clk_cam = {
451 .name = "camif-upll", /* same as 2440 name */ 441 .name = "camif-upll", /* same as 2440 name */
452 .id = -1,
453 .ops = &(struct clk_ops) { 442 .ops = &(struct clk_ops) {
454 .get_rate = s3c2412_getrate_cam, 443 .get_rate = s3c2412_getrate_cam,
455 .set_rate = s3c2412_setrate_cam, 444 .set_rate = s3c2412_setrate_cam,
@@ -463,37 +452,31 @@ static struct clk clk_cam = {
463static struct clk init_clocks_disable[] = { 452static struct clk init_clocks_disable[] = {
464 { 453 {
465 .name = "nand", 454 .name = "nand",
466 .id = -1,
467 .parent = &clk_h, 455 .parent = &clk_h,
468 .enable = s3c2412_clkcon_enable, 456 .enable = s3c2412_clkcon_enable,
469 .ctrlbit = S3C2412_CLKCON_NAND, 457 .ctrlbit = S3C2412_CLKCON_NAND,
470 }, { 458 }, {
471 .name = "sdi", 459 .name = "sdi",
472 .id = -1,
473 .parent = &clk_p, 460 .parent = &clk_p,
474 .enable = s3c2412_clkcon_enable, 461 .enable = s3c2412_clkcon_enable,
475 .ctrlbit = S3C2412_CLKCON_SDI, 462 .ctrlbit = S3C2412_CLKCON_SDI,
476 }, { 463 }, {
477 .name = "adc", 464 .name = "adc",
478 .id = -1,
479 .parent = &clk_p, 465 .parent = &clk_p,
480 .enable = s3c2412_clkcon_enable, 466 .enable = s3c2412_clkcon_enable,
481 .ctrlbit = S3C2412_CLKCON_ADC, 467 .ctrlbit = S3C2412_CLKCON_ADC,
482 }, { 468 }, {
483 .name = "i2c", 469 .name = "i2c",
484 .id = -1,
485 .parent = &clk_p, 470 .parent = &clk_p,
486 .enable = s3c2412_clkcon_enable, 471 .enable = s3c2412_clkcon_enable,
487 .ctrlbit = S3C2412_CLKCON_IIC, 472 .ctrlbit = S3C2412_CLKCON_IIC,
488 }, { 473 }, {
489 .name = "iis", 474 .name = "iis",
490 .id = -1,
491 .parent = &clk_p, 475 .parent = &clk_p,
492 .enable = s3c2412_clkcon_enable, 476 .enable = s3c2412_clkcon_enable,
493 .ctrlbit = S3C2412_CLKCON_IIS, 477 .ctrlbit = S3C2412_CLKCON_IIS,
494 }, { 478 }, {
495 .name = "spi", 479 .name = "spi",
496 .id = -1,
497 .parent = &clk_p, 480 .parent = &clk_p,
498 .enable = s3c2412_clkcon_enable, 481 .enable = s3c2412_clkcon_enable,
499 .ctrlbit = S3C2412_CLKCON_SPI, 482 .ctrlbit = S3C2412_CLKCON_SPI,
@@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = {
503static struct clk init_clocks[] = { 486static struct clk init_clocks[] = {
504 { 487 {
505 .name = "dma", 488 .name = "dma",
506 .id = 0,
507 .parent = &clk_h, 489 .parent = &clk_h,
508 .enable = s3c2412_clkcon_enable, 490 .enable = s3c2412_clkcon_enable,
509 .ctrlbit = S3C2412_CLKCON_DMA0, 491 .ctrlbit = S3C2412_CLKCON_DMA0,
510 }, { 492 }, {
511 .name = "dma", 493 .name = "dma",
512 .id = 1,
513 .parent = &clk_h, 494 .parent = &clk_h,
514 .enable = s3c2412_clkcon_enable, 495 .enable = s3c2412_clkcon_enable,
515 .ctrlbit = S3C2412_CLKCON_DMA1, 496 .ctrlbit = S3C2412_CLKCON_DMA1,
516 }, { 497 }, {
517 .name = "dma", 498 .name = "dma",
518 .id = 2,
519 .parent = &clk_h, 499 .parent = &clk_h,
520 .enable = s3c2412_clkcon_enable, 500 .enable = s3c2412_clkcon_enable,
521 .ctrlbit = S3C2412_CLKCON_DMA2, 501 .ctrlbit = S3C2412_CLKCON_DMA2,
522 }, { 502 }, {
523 .name = "dma", 503 .name = "dma",
524 .id = 3,
525 .parent = &clk_h, 504 .parent = &clk_h,
526 .enable = s3c2412_clkcon_enable, 505 .enable = s3c2412_clkcon_enable,
527 .ctrlbit = S3C2412_CLKCON_DMA3, 506 .ctrlbit = S3C2412_CLKCON_DMA3,
528 }, { 507 }, {
529 .name = "lcd", 508 .name = "lcd",
530 .id = -1,
531 .parent = &clk_h, 509 .parent = &clk_h,
532 .enable = s3c2412_clkcon_enable, 510 .enable = s3c2412_clkcon_enable,
533 .ctrlbit = S3C2412_CLKCON_LCDC, 511 .ctrlbit = S3C2412_CLKCON_LCDC,
534 }, { 512 }, {
535 .name = "gpio", 513 .name = "gpio",
536 .id = -1,
537 .parent = &clk_p, 514 .parent = &clk_p,
538 .enable = s3c2412_clkcon_enable, 515 .enable = s3c2412_clkcon_enable,
539 .ctrlbit = S3C2412_CLKCON_GPIO, 516 .ctrlbit = S3C2412_CLKCON_GPIO,
540 }, { 517 }, {
541 .name = "usb-host", 518 .name = "usb-host",
542 .id = -1,
543 .parent = &clk_h, 519 .parent = &clk_h,
544 .enable = s3c2412_clkcon_enable, 520 .enable = s3c2412_clkcon_enable,
545 .ctrlbit = S3C2412_CLKCON_USBH, 521 .ctrlbit = S3C2412_CLKCON_USBH,
546 }, { 522 }, {
547 .name = "usb-device", 523 .name = "usb-device",
548 .id = -1,
549 .parent = &clk_h, 524 .parent = &clk_h,
550 .enable = s3c2412_clkcon_enable, 525 .enable = s3c2412_clkcon_enable,
551 .ctrlbit = S3C2412_CLKCON_USBD, 526 .ctrlbit = S3C2412_CLKCON_USBD,
552 }, { 527 }, {
553 .name = "timers", 528 .name = "timers",
554 .id = -1,
555 .parent = &clk_p, 529 .parent = &clk_p,
556 .enable = s3c2412_clkcon_enable, 530 .enable = s3c2412_clkcon_enable,
557 .ctrlbit = S3C2412_CLKCON_PWMT, 531 .ctrlbit = S3C2412_CLKCON_PWMT,
558 }, { 532 }, {
559 .name = "uart", 533 .name = "uart",
560 .id = 0, 534 .devname = "s3c2412-uart.0",
561 .parent = &clk_p, 535 .parent = &clk_p,
562 .enable = s3c2412_clkcon_enable, 536 .enable = s3c2412_clkcon_enable,
563 .ctrlbit = S3C2412_CLKCON_UART0, 537 .ctrlbit = S3C2412_CLKCON_UART0,
564 }, { 538 }, {
565 .name = "uart", 539 .name = "uart",
566 .id = 1, 540 .devname = "s3c2412-uart.1",
567 .parent = &clk_p, 541 .parent = &clk_p,
568 .enable = s3c2412_clkcon_enable, 542 .enable = s3c2412_clkcon_enable,
569 .ctrlbit = S3C2412_CLKCON_UART1, 543 .ctrlbit = S3C2412_CLKCON_UART1,
570 }, { 544 }, {
571 .name = "uart", 545 .name = "uart",
572 .id = 2, 546 .devname = "s3c2412-uart.2",
573 .parent = &clk_p, 547 .parent = &clk_p,
574 .enable = s3c2412_clkcon_enable, 548 .enable = s3c2412_clkcon_enable,
575 .ctrlbit = S3C2412_CLKCON_UART2, 549 .ctrlbit = S3C2412_CLKCON_UART2,
576 }, { 550 }, {
577 .name = "rtc", 551 .name = "rtc",
578 .id = -1,
579 .parent = &clk_p, 552 .parent = &clk_p,
580 .enable = s3c2412_clkcon_enable, 553 .enable = s3c2412_clkcon_enable,
581 .ctrlbit = S3C2412_CLKCON_RTC, 554 .ctrlbit = S3C2412_CLKCON_RTC,
582 }, { 555 }, {
583 .name = "watchdog", 556 .name = "watchdog",
584 .id = -1,
585 .parent = &clk_p, 557 .parent = &clk_p,
586 .ctrlbit = 0, 558 .ctrlbit = 0,
587 }, { 559 }, {
588 .name = "usb-bus-gadget", 560 .name = "usb-bus-gadget",
589 .id = -1,
590 .parent = &clk_usb_bus, 561 .parent = &clk_usb_bus,
591 .enable = s3c2412_clkcon_enable, 562 .enable = s3c2412_clkcon_enable,
592 .ctrlbit = S3C2412_CLKCON_USB_DEV48, 563 .ctrlbit = S3C2412_CLKCON_USB_DEV48,
593 }, { 564 }, {
594 .name = "usb-bus-host", 565 .name = "usb-bus-host",
595 .id = -1,
596 .parent = &clk_usb_bus, 566 .parent = &clk_usb_bus,
597 .enable = s3c2412_clkcon_enable, 567 .enable = s3c2412_clkcon_enable,
598 .ctrlbit = S3C2412_CLKCON_USB_HOST48, 568 .ctrlbit = S3C2412_CLKCON_USB_HOST48,
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 3b02d8506e25..21a5e81f0ab5 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = {
42 [0] = { 42 [0] = {
43 .clk = { 43 .clk = {
44 .name = "hsmmc-div", 44 .name = "hsmmc-div",
45 .id = 0, 45 .devname = "s3c-sdhci.0",
46 .parent = &clk_esysclk.clk, 46 .parent = &clk_esysclk.clk,
47 }, 47 },
48 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 }, 48 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
@@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = {
50 [1] = { 50 [1] = {
51 .clk = { 51 .clk = {
52 .name = "hsmmc-div", 52 .name = "hsmmc-div",
53 .id = 1, 53 .devname = "s3c-sdhci.1",
54 .parent = &clk_esysclk.clk, 54 .parent = &clk_esysclk.clk,
55 }, 55 },
56 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, 56 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = {
60static struct clksrc_clk hsmmc_mux[] = { 60static struct clksrc_clk hsmmc_mux[] = {
61 [0] = { 61 [0] = {
62 .clk = { 62 .clk = {
63 .id = 0,
64 .name = "hsmmc-if", 63 .name = "hsmmc-if",
64 .devname = "s3c-sdhci.0",
65 .ctrlbit = (1 << 6), 65 .ctrlbit = (1 << 6),
66 .enable = s3c2443_clkcon_enable_s, 66 .enable = s3c2443_clkcon_enable_s,
67 }, 67 },
@@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = {
76 }, 76 },
77 [1] = { 77 [1] = {
78 .clk = { 78 .clk = {
79 .id = 1,
80 .name = "hsmmc-if", 79 .name = "hsmmc-if",
80 .devname = "s3c-sdhci.1",
81 .ctrlbit = (1 << 12), 81 .ctrlbit = (1 << 12),
82 .enable = s3c2443_clkcon_enable_s, 82 .enable = s3c2443_clkcon_enable_s,
83 }, 83 },
@@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = {
94 94
95static struct clk hsmmc0_clk = { 95static struct clk hsmmc0_clk = {
96 .name = "hsmmc", 96 .name = "hsmmc",
97 .id = 0, 97 .devname = "s3c-sdhci.0",
98 .parent = &clk_h, 98 .parent = &clk_h,
99 .enable = s3c2443_clkcon_enable_h, 99 .enable = s3c2443_clkcon_enable_h,
100 .ctrlbit = S3C2416_HCLKCON_HSMMC0, 100 .ctrlbit = S3C2416_HCLKCON_HSMMC0,
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index 3dc2426e2345..554e0d3ec70b 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -90,14 +90,12 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
90 90
91static struct clk s3c2440_clk_cam = { 91static struct clk s3c2440_clk_cam = {
92 .name = "camif", 92 .name = "camif",
93 .id = -1,
94 .enable = s3c2410_clkcon_enable, 93 .enable = s3c2410_clkcon_enable,
95 .ctrlbit = S3C2440_CLKCON_CAMERA, 94 .ctrlbit = S3C2440_CLKCON_CAMERA,
96}; 95};
97 96
98static struct clk s3c2440_clk_cam_upll = { 97static struct clk s3c2440_clk_cam_upll = {
99 .name = "camif-upll", 98 .name = "camif-upll",
100 .id = -1,
101 .ops = &(struct clk_ops) { 99 .ops = &(struct clk_ops) {
102 .set_rate = s3c2440_camif_upll_setrate, 100 .set_rate = s3c2440_camif_upll_setrate,
103 .round_rate = s3c2440_camif_upll_round, 101 .round_rate = s3c2440_camif_upll_round,
@@ -106,7 +104,6 @@ static struct clk s3c2440_clk_cam_upll = {
106 104
107static struct clk s3c2440_clk_ac97 = { 105static struct clk s3c2440_clk_ac97 = {
108 .name = "ac97", 106 .name = "ac97",
109 .id = -1,
110 .enable = s3c2410_clkcon_enable, 107 .enable = s3c2410_clkcon_enable,
111 .ctrlbit = S3C2440_CLKCON_CAMERA, 108 .ctrlbit = S3C2440_CLKCON_CAMERA,
112}; 109};
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index f4ec6d5715c8..a1a7176675b9 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -59,7 +59,6 @@
59 59
60static struct clk clk_i2s_ext = { 60static struct clk clk_i2s_ext = {
61 .name = "i2s-ext", 61 .name = "i2s-ext",
62 .id = -1,
63}; 62};
64 63
65/* armdiv 64/* armdiv
@@ -139,7 +138,6 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
139 138
140static struct clk clk_armdiv = { 139static struct clk clk_armdiv = {
141 .name = "armdiv", 140 .name = "armdiv",
142 .id = -1,
143 .parent = &clk_msysclk.clk, 141 .parent = &clk_msysclk.clk,
144 .ops = &(struct clk_ops) { 142 .ops = &(struct clk_ops) {
145 .round_rate = s3c2443_armclk_roundrate, 143 .round_rate = s3c2443_armclk_roundrate,
@@ -160,7 +158,6 @@ static struct clk *clk_arm_sources[] = {
160static struct clksrc_clk clk_arm = { 158static struct clksrc_clk clk_arm = {
161 .clk = { 159 .clk = {
162 .name = "armclk", 160 .name = "armclk",
163 .id = -1,
164 }, 161 },
165 .sources = &(struct clksrc_sources) { 162 .sources = &(struct clksrc_sources) {
166 .sources = clk_arm_sources, 163 .sources = clk_arm_sources,
@@ -177,7 +174,6 @@ static struct clksrc_clk clk_arm = {
177static struct clksrc_clk clk_hsspi = { 174static struct clksrc_clk clk_hsspi = {
178 .clk = { 175 .clk = {
179 .name = "hsspi", 176 .name = "hsspi",
180 .id = -1,
181 .parent = &clk_esysclk.clk, 177 .parent = &clk_esysclk.clk,
182 .ctrlbit = S3C2443_SCLKCON_HSSPICLK, 178 .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
183 .enable = s3c2443_clkcon_enable_s, 179 .enable = s3c2443_clkcon_enable_s,
@@ -196,7 +192,7 @@ static struct clksrc_clk clk_hsspi = {
196static struct clksrc_clk clk_hsmmc_div = { 192static struct clksrc_clk clk_hsmmc_div = {
197 .clk = { 193 .clk = {
198 .name = "hsmmc-div", 194 .name = "hsmmc-div",
199 .id = 1, 195 .devname = "s3c-sdhci.1",
200 .parent = &clk_esysclk.clk, 196 .parent = &clk_esysclk.clk,
201 }, 197 },
202 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, 198 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -231,7 +227,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
231 227
232static struct clk clk_hsmmc = { 228static struct clk clk_hsmmc = {
233 .name = "hsmmc-if", 229 .name = "hsmmc-if",
234 .id = 1, 230 .devname = "s3c-sdhci.1",
235 .parent = &clk_hsmmc_div.clk, 231 .parent = &clk_hsmmc_div.clk,
236 .enable = s3c2443_enable_hsmmc, 232 .enable = s3c2443_enable_hsmmc,
237 .ops = &(struct clk_ops) { 233 .ops = &(struct clk_ops) {
@@ -248,7 +244,6 @@ static struct clk clk_hsmmc = {
248static struct clksrc_clk clk_i2s_eplldiv = { 244static struct clksrc_clk clk_i2s_eplldiv = {
249 .clk = { 245 .clk = {
250 .name = "i2s-eplldiv", 246 .name = "i2s-eplldiv",
251 .id = -1,
252 .parent = &clk_esysclk.clk, 247 .parent = &clk_esysclk.clk,
253 }, 248 },
254 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, 249 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
@@ -271,7 +266,6 @@ struct clk *clk_i2s_srclist[] = {
271static struct clksrc_clk clk_i2s = { 266static struct clksrc_clk clk_i2s = {
272 .clk = { 267 .clk = {
273 .name = "i2s-if", 268 .name = "i2s-if",
274 .id = -1,
275 .ctrlbit = S3C2443_SCLKCON_I2SCLK, 269 .ctrlbit = S3C2443_SCLKCON_I2SCLK,
276 .enable = s3c2443_clkcon_enable_s, 270 .enable = s3c2443_clkcon_enable_s,
277 271
@@ -288,25 +282,23 @@ static struct clksrc_clk clk_i2s = {
288static struct clk init_clocks_off[] = { 282static struct clk init_clocks_off[] = {
289 { 283 {
290 .name = "sdi", 284 .name = "sdi",
291 .id = -1,
292 .parent = &clk_p, 285 .parent = &clk_p,
293 .enable = s3c2443_clkcon_enable_p, 286 .enable = s3c2443_clkcon_enable_p,
294 .ctrlbit = S3C2443_PCLKCON_SDI, 287 .ctrlbit = S3C2443_PCLKCON_SDI,
295 }, { 288 }, {
296 .name = "iis", 289 .name = "iis",
297 .id = -1,
298 .parent = &clk_p, 290 .parent = &clk_p,
299 .enable = s3c2443_clkcon_enable_p, 291 .enable = s3c2443_clkcon_enable_p,
300 .ctrlbit = S3C2443_PCLKCON_IIS, 292 .ctrlbit = S3C2443_PCLKCON_IIS,
301 }, { 293 }, {
302 .name = "spi", 294 .name = "spi",
303 .id = 0, 295 .devname = "s3c2410-spi.0",
304 .parent = &clk_p, 296 .parent = &clk_p,
305 .enable = s3c2443_clkcon_enable_p, 297 .enable = s3c2443_clkcon_enable_p,
306 .ctrlbit = S3C2443_PCLKCON_SPI0, 298 .ctrlbit = S3C2443_PCLKCON_SPI0,
307 }, { 299 }, {
308 .name = "spi", 300 .name = "spi",
309 .id = 1, 301 .devname = "s3c2410-spi.1",
310 .parent = &clk_p, 302 .parent = &clk_p,
311 .enable = s3c2443_clkcon_enable_p, 303 .enable = s3c2443_clkcon_enable_p,
312 .ctrlbit = S3C2443_PCLKCON_SPI1, 304 .ctrlbit = S3C2443_PCLKCON_SPI1,
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index fdfc4d5e37a1..8cf39e33579e 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -39,7 +39,6 @@
39 39
40static struct clk clk_ext_xtal_mux = { 40static struct clk clk_ext_xtal_mux = {
41 .name = "ext_xtal", 41 .name = "ext_xtal",
42 .id = -1,
43}; 42};
44 43
45#define clk_fin_apll clk_ext_xtal_mux 44#define clk_fin_apll clk_ext_xtal_mux
@@ -51,13 +50,11 @@ static struct clk clk_ext_xtal_mux = {
51 50
52struct clk clk_h2 = { 51struct clk clk_h2 = {
53 .name = "hclk2", 52 .name = "hclk2",
54 .id = -1,
55 .rate = 0, 53 .rate = 0,
56}; 54};
57 55
58struct clk clk_27m = { 56struct clk clk_27m = {
59 .name = "clk_27m", 57 .name = "clk_27m",
60 .id = -1,
61 .rate = 27000000, 58 .rate = 27000000,
62}; 59};
63 60
@@ -83,14 +80,12 @@ static int clk_48m_ctrl(struct clk *clk, int enable)
83 80
84struct clk clk_48m = { 81struct clk clk_48m = {
85 .name = "clk_48m", 82 .name = "clk_48m",
86 .id = -1,
87 .rate = 48000000, 83 .rate = 48000000,
88 .enable = clk_48m_ctrl, 84 .enable = clk_48m_ctrl,
89}; 85};
90 86
91struct clk clk_xusbxti = { 87struct clk clk_xusbxti = {
92 .name = "xusbxti", 88 .name = "xusbxti",
93 .id = -1,
94 .rate = 48000000, 89 .rate = 48000000,
95}; 90};
96 91
@@ -130,109 +125,101 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
130static struct clk init_clocks_off[] = { 125static struct clk init_clocks_off[] = {
131 { 126 {
132 .name = "nand", 127 .name = "nand",
133 .id = -1,
134 .parent = &clk_h, 128 .parent = &clk_h,
135 }, { 129 }, {
136 .name = "rtc", 130 .name = "rtc",
137 .id = -1,
138 .parent = &clk_p, 131 .parent = &clk_p,
139 .enable = s3c64xx_pclk_ctrl, 132 .enable = s3c64xx_pclk_ctrl,
140 .ctrlbit = S3C_CLKCON_PCLK_RTC, 133 .ctrlbit = S3C_CLKCON_PCLK_RTC,
141 }, { 134 }, {
142 .name = "adc", 135 .name = "adc",
143 .id = -1,
144 .parent = &clk_p, 136 .parent = &clk_p,
145 .enable = s3c64xx_pclk_ctrl, 137 .enable = s3c64xx_pclk_ctrl,
146 .ctrlbit = S3C_CLKCON_PCLK_TSADC, 138 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
147 }, { 139 }, {
148 .name = "i2c", 140 .name = "i2c",
149 .id = -1,
150 .parent = &clk_p, 141 .parent = &clk_p,
151 .enable = s3c64xx_pclk_ctrl, 142 .enable = s3c64xx_pclk_ctrl,
152 .ctrlbit = S3C_CLKCON_PCLK_IIC, 143 .ctrlbit = S3C_CLKCON_PCLK_IIC,
153 }, { 144 }, {
154 .name = "i2c", 145 .name = "i2c",
155 .id = 1, 146 .devname = "s3c2440-i2c.1",
156 .parent = &clk_p, 147 .parent = &clk_p,
157 .enable = s3c64xx_pclk_ctrl, 148 .enable = s3c64xx_pclk_ctrl,
158 .ctrlbit = S3C6410_CLKCON_PCLK_I2C1, 149 .ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
159 }, { 150 }, {
160 .name = "iis", 151 .name = "iis",
161 .id = 0, 152 .devname = "samsung-i2s.0",
162 .parent = &clk_p, 153 .parent = &clk_p,
163 .enable = s3c64xx_pclk_ctrl, 154 .enable = s3c64xx_pclk_ctrl,
164 .ctrlbit = S3C_CLKCON_PCLK_IIS0, 155 .ctrlbit = S3C_CLKCON_PCLK_IIS0,
165 }, { 156 }, {
166 .name = "iis", 157 .name = "iis",
167 .id = 1, 158 .devname = "samsung-i2s.1",
168 .parent = &clk_p, 159 .parent = &clk_p,
169 .enable = s3c64xx_pclk_ctrl, 160 .enable = s3c64xx_pclk_ctrl,
170 .ctrlbit = S3C_CLKCON_PCLK_IIS1, 161 .ctrlbit = S3C_CLKCON_PCLK_IIS1,
171 }, { 162 }, {
172#ifdef CONFIG_CPU_S3C6410 163#ifdef CONFIG_CPU_S3C6410
173 .name = "iis", 164 .name = "iis",
174 .id = -1, /* There's only one IISv4 port */
175 .parent = &clk_p, 165 .parent = &clk_p,
176 .enable = s3c64xx_pclk_ctrl, 166 .enable = s3c64xx_pclk_ctrl,
177 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2, 167 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
178 }, { 168 }, {
179#endif 169#endif
180 .name = "keypad", 170 .name = "keypad",
181 .id = -1,
182 .parent = &clk_p, 171 .parent = &clk_p,
183 .enable = s3c64xx_pclk_ctrl, 172 .enable = s3c64xx_pclk_ctrl,
184 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, 173 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
185 }, { 174 }, {
186 .name = "spi", 175 .name = "spi",
187 .id = 0, 176 .devname = "s3c64xx-spi.0",
188 .parent = &clk_p, 177 .parent = &clk_p,
189 .enable = s3c64xx_pclk_ctrl, 178 .enable = s3c64xx_pclk_ctrl,
190 .ctrlbit = S3C_CLKCON_PCLK_SPI0, 179 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
191 }, { 180 }, {
192 .name = "spi", 181 .name = "spi",
193 .id = 1, 182 .devname = "s3c64xx-spi.1",
194 .parent = &clk_p, 183 .parent = &clk_p,
195 .enable = s3c64xx_pclk_ctrl, 184 .enable = s3c64xx_pclk_ctrl,
196 .ctrlbit = S3C_CLKCON_PCLK_SPI1, 185 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
197 }, { 186 }, {
198 .name = "spi_48m", 187 .name = "spi_48m",
199 .id = 0, 188 .devname = "s3c64xx-spi.0",
200 .parent = &clk_48m, 189 .parent = &clk_48m,
201 .enable = s3c64xx_sclk_ctrl, 190 .enable = s3c64xx_sclk_ctrl,
202 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, 191 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
203 }, { 192 }, {
204 .name = "spi_48m", 193 .name = "spi_48m",
205 .id = 1, 194 .devname = "s3c64xx-spi.1",
206 .parent = &clk_48m, 195 .parent = &clk_48m,
207 .enable = s3c64xx_sclk_ctrl, 196 .enable = s3c64xx_sclk_ctrl,
208 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, 197 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
209 }, { 198 }, {
210 .name = "48m", 199 .name = "48m",
211 .id = 0, 200 .devname = "s3c-sdhci.0",
212 .parent = &clk_48m, 201 .parent = &clk_48m,
213 .enable = s3c64xx_sclk_ctrl, 202 .enable = s3c64xx_sclk_ctrl,
214 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48, 203 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
215 }, { 204 }, {
216 .name = "48m", 205 .name = "48m",
217 .id = 1, 206 .devname = "s3c-sdhci.1",
218 .parent = &clk_48m, 207 .parent = &clk_48m,
219 .enable = s3c64xx_sclk_ctrl, 208 .enable = s3c64xx_sclk_ctrl,
220 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48, 209 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
221 }, { 210 }, {
222 .name = "48m", 211 .name = "48m",
223 .id = 2, 212 .devname = "s3c-sdhci.2",
224 .parent = &clk_48m, 213 .parent = &clk_48m,
225 .enable = s3c64xx_sclk_ctrl, 214 .enable = s3c64xx_sclk_ctrl,
226 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, 215 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
227 }, { 216 }, {
228 .name = "dma0", 217 .name = "dma0",
229 .id = -1,
230 .parent = &clk_h, 218 .parent = &clk_h,
231 .enable = s3c64xx_hclk_ctrl, 219 .enable = s3c64xx_hclk_ctrl,
232 .ctrlbit = S3C_CLKCON_HCLK_DMA0, 220 .ctrlbit = S3C_CLKCON_HCLK_DMA0,
233 }, { 221 }, {
234 .name = "dma1", 222 .name = "dma1",
235 .id = -1,
236 .parent = &clk_h, 223 .parent = &clk_h,
237 .enable = s3c64xx_hclk_ctrl, 224 .enable = s3c64xx_hclk_ctrl,
238 .ctrlbit = S3C_CLKCON_HCLK_DMA1, 225 .ctrlbit = S3C_CLKCON_HCLK_DMA1,
@@ -242,89 +229,81 @@ static struct clk init_clocks_off[] = {
242static struct clk init_clocks[] = { 229static struct clk init_clocks[] = {
243 { 230 {
244 .name = "lcd", 231 .name = "lcd",
245 .id = -1,
246 .parent = &clk_h, 232 .parent = &clk_h,
247 .enable = s3c64xx_hclk_ctrl, 233 .enable = s3c64xx_hclk_ctrl,
248 .ctrlbit = S3C_CLKCON_HCLK_LCD, 234 .ctrlbit = S3C_CLKCON_HCLK_LCD,
249 }, { 235 }, {
250 .name = "gpio", 236 .name = "gpio",
251 .id = -1,
252 .parent = &clk_p, 237 .parent = &clk_p,
253 .enable = s3c64xx_pclk_ctrl, 238 .enable = s3c64xx_pclk_ctrl,
254 .ctrlbit = S3C_CLKCON_PCLK_GPIO, 239 .ctrlbit = S3C_CLKCON_PCLK_GPIO,
255 }, { 240 }, {
256 .name = "usb-host", 241 .name = "usb-host",
257 .id = -1,
258 .parent = &clk_h, 242 .parent = &clk_h,
259 .enable = s3c64xx_hclk_ctrl, 243 .enable = s3c64xx_hclk_ctrl,
260 .ctrlbit = S3C_CLKCON_HCLK_UHOST, 244 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
261 }, { 245 }, {
262 .name = "hsmmc", 246 .name = "hsmmc",
263 .id = 0, 247 .devname = "s3c-sdhci.0",
264 .parent = &clk_h, 248 .parent = &clk_h,
265 .enable = s3c64xx_hclk_ctrl, 249 .enable = s3c64xx_hclk_ctrl,
266 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, 250 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
267 }, { 251 }, {
268 .name = "hsmmc", 252 .name = "hsmmc",
269 .id = 1, 253 .devname = "s3c-sdhci.1",
270 .parent = &clk_h, 254 .parent = &clk_h,
271 .enable = s3c64xx_hclk_ctrl, 255 .enable = s3c64xx_hclk_ctrl,
272 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, 256 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
273 }, { 257 }, {
274 .name = "hsmmc", 258 .name = "hsmmc",
275 .id = 2, 259 .devname = "s3c-sdhci.2",
276 .parent = &clk_h, 260 .parent = &clk_h,
277 .enable = s3c64xx_hclk_ctrl, 261 .enable = s3c64xx_hclk_ctrl,
278 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, 262 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
279 }, { 263 }, {
280 .name = "otg", 264 .name = "otg",
281 .id = -1,
282 .parent = &clk_h, 265 .parent = &clk_h,
283 .enable = s3c64xx_hclk_ctrl, 266 .enable = s3c64xx_hclk_ctrl,
284 .ctrlbit = S3C_CLKCON_HCLK_USB, 267 .ctrlbit = S3C_CLKCON_HCLK_USB,
285 }, { 268 }, {
286 .name = "timers", 269 .name = "timers",
287 .id = -1,
288 .parent = &clk_p, 270 .parent = &clk_p,
289 .enable = s3c64xx_pclk_ctrl, 271 .enable = s3c64xx_pclk_ctrl,
290 .ctrlbit = S3C_CLKCON_PCLK_PWM, 272 .ctrlbit = S3C_CLKCON_PCLK_PWM,
291 }, { 273 }, {
292 .name = "uart", 274 .name = "uart",
293 .id = 0, 275 .devname = "s3c6400-uart.0",
294 .parent = &clk_p, 276 .parent = &clk_p,
295 .enable = s3c64xx_pclk_ctrl, 277 .enable = s3c64xx_pclk_ctrl,
296 .ctrlbit = S3C_CLKCON_PCLK_UART0, 278 .ctrlbit = S3C_CLKCON_PCLK_UART0,
297 }, { 279 }, {
298 .name = "uart", 280 .name = "uart",
299 .id = 1, 281 .devname = "s3c6400-uart.1",
300 .parent = &clk_p, 282 .parent = &clk_p,
301 .enable = s3c64xx_pclk_ctrl, 283 .enable = s3c64xx_pclk_ctrl,
302 .ctrlbit = S3C_CLKCON_PCLK_UART1, 284 .ctrlbit = S3C_CLKCON_PCLK_UART1,
303 }, { 285 }, {
304 .name = "uart", 286 .name = "uart",
305 .id = 2, 287 .devname = "s3c6400-uart.2",
306 .parent = &clk_p, 288 .parent = &clk_p,
307 .enable = s3c64xx_pclk_ctrl, 289 .enable = s3c64xx_pclk_ctrl,
308 .ctrlbit = S3C_CLKCON_PCLK_UART2, 290 .ctrlbit = S3C_CLKCON_PCLK_UART2,
309 }, { 291 }, {
310 .name = "uart", 292 .name = "uart",
311 .id = 3, 293 .devname = "s3c6400-uart.3",
312 .parent = &clk_p, 294 .parent = &clk_p,
313 .enable = s3c64xx_pclk_ctrl, 295 .enable = s3c64xx_pclk_ctrl,
314 .ctrlbit = S3C_CLKCON_PCLK_UART3, 296 .ctrlbit = S3C_CLKCON_PCLK_UART3,
315 }, { 297 }, {
316 .name = "watchdog", 298 .name = "watchdog",
317 .id = -1,
318 .parent = &clk_p, 299 .parent = &clk_p,
319 .ctrlbit = S3C_CLKCON_PCLK_WDT, 300 .ctrlbit = S3C_CLKCON_PCLK_WDT,
320 }, { 301 }, {
321 .name = "ac97", 302 .name = "ac97",
322 .id = -1,
323 .parent = &clk_p, 303 .parent = &clk_p,
324 .ctrlbit = S3C_CLKCON_PCLK_AC97, 304 .ctrlbit = S3C_CLKCON_PCLK_AC97,
325 }, { 305 }, {
326 .name = "cfcon", 306 .name = "cfcon",
327 .id = -1,
328 .parent = &clk_h, 307 .parent = &clk_h,
329 .enable = s3c64xx_hclk_ctrl, 308 .enable = s3c64xx_hclk_ctrl,
330 .ctrlbit = S3C_CLKCON_HCLK_IHOST, 309 .ctrlbit = S3C_CLKCON_HCLK_IHOST,
@@ -334,7 +313,6 @@ static struct clk init_clocks[] = {
334 313
335static struct clk clk_fout_apll = { 314static struct clk clk_fout_apll = {
336 .name = "fout_apll", 315 .name = "fout_apll",
337 .id = -1,
338}; 316};
339 317
340static struct clk *clk_src_apll_list[] = { 318static struct clk *clk_src_apll_list[] = {
@@ -350,7 +328,6 @@ static struct clksrc_sources clk_src_apll = {
350static struct clksrc_clk clk_mout_apll = { 328static struct clksrc_clk clk_mout_apll = {
351 .clk = { 329 .clk = {
352 .name = "mout_apll", 330 .name = "mout_apll",
353 .id = -1,
354 }, 331 },
355 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, 332 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
356 .sources = &clk_src_apll, 333 .sources = &clk_src_apll,
@@ -369,7 +346,6 @@ static struct clksrc_sources clk_src_epll = {
369static struct clksrc_clk clk_mout_epll = { 346static struct clksrc_clk clk_mout_epll = {
370 .clk = { 347 .clk = {
371 .name = "mout_epll", 348 .name = "mout_epll",
372 .id = -1,
373 }, 349 },
374 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, 350 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
375 .sources = &clk_src_epll, 351 .sources = &clk_src_epll,
@@ -388,7 +364,6 @@ static struct clksrc_sources clk_src_mpll = {
388static struct clksrc_clk clk_mout_mpll = { 364static struct clksrc_clk clk_mout_mpll = {
389 .clk = { 365 .clk = {
390 .name = "mout_mpll", 366 .name = "mout_mpll",
391 .id = -1,
392 }, 367 },
393 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, 368 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
394 .sources = &clk_src_mpll, 369 .sources = &clk_src_mpll,
@@ -446,7 +421,6 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
446 421
447static struct clk clk_arm = { 422static struct clk clk_arm = {
448 .name = "armclk", 423 .name = "armclk",
449 .id = -1,
450 .parent = &clk_mout_apll.clk, 424 .parent = &clk_mout_apll.clk,
451 .ops = &(struct clk_ops) { 425 .ops = &(struct clk_ops) {
452 .get_rate = s3c64xx_clk_arm_get_rate, 426 .get_rate = s3c64xx_clk_arm_get_rate,
@@ -473,7 +447,6 @@ static struct clk_ops clk_dout_ops = {
473 447
474static struct clk clk_dout_mpll = { 448static struct clk clk_dout_mpll = {
475 .name = "dout_mpll", 449 .name = "dout_mpll",
476 .id = -1,
477 .parent = &clk_mout_mpll.clk, 450 .parent = &clk_mout_mpll.clk,
478 .ops = &clk_dout_ops, 451 .ops = &clk_dout_ops,
479}; 452};
@@ -540,22 +513,18 @@ static struct clksrc_sources clkset_uhost = {
540 513
541static struct clk clk_iis_cd0 = { 514static struct clk clk_iis_cd0 = {
542 .name = "iis_cdclk0", 515 .name = "iis_cdclk0",
543 .id = -1,
544}; 516};
545 517
546static struct clk clk_iis_cd1 = { 518static struct clk clk_iis_cd1 = {
547 .name = "iis_cdclk1", 519 .name = "iis_cdclk1",
548 .id = -1,
549}; 520};
550 521
551static struct clk clk_iisv4_cd = { 522static struct clk clk_iisv4_cd = {
552 .name = "iis_cdclk_v4", 523 .name = "iis_cdclk_v4",
553 .id = -1,
554}; 524};
555 525
556static struct clk clk_pcm_cd = { 526static struct clk clk_pcm_cd = {
557 .name = "pcm_cdclk", 527 .name = "pcm_cdclk",
558 .id = -1,
559}; 528};
560 529
561static struct clk *clkset_audio0_list[] = { 530static struct clk *clkset_audio0_list[] = {
@@ -610,7 +579,7 @@ static struct clksrc_clk clksrcs[] = {
610 { 579 {
611 .clk = { 580 .clk = {
612 .name = "mmc_bus", 581 .name = "mmc_bus",
613 .id = 0, 582 .devname = "s3c-sdhci.0",
614 .ctrlbit = S3C_CLKCON_SCLK_MMC0, 583 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
615 .enable = s3c64xx_sclk_ctrl, 584 .enable = s3c64xx_sclk_ctrl,
616 }, 585 },
@@ -620,7 +589,7 @@ static struct clksrc_clk clksrcs[] = {
620 }, { 589 }, {
621 .clk = { 590 .clk = {
622 .name = "mmc_bus", 591 .name = "mmc_bus",
623 .id = 1, 592 .devname = "s3c-sdhci.1",
624 .ctrlbit = S3C_CLKCON_SCLK_MMC1, 593 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
625 .enable = s3c64xx_sclk_ctrl, 594 .enable = s3c64xx_sclk_ctrl,
626 }, 595 },
@@ -630,7 +599,7 @@ static struct clksrc_clk clksrcs[] = {
630 }, { 599 }, {
631 .clk = { 600 .clk = {
632 .name = "mmc_bus", 601 .name = "mmc_bus",
633 .id = 2, 602 .devname = "s3c-sdhci.2",
634 .ctrlbit = S3C_CLKCON_SCLK_MMC2, 603 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
635 .enable = s3c64xx_sclk_ctrl, 604 .enable = s3c64xx_sclk_ctrl,
636 }, 605 },
@@ -640,7 +609,6 @@ static struct clksrc_clk clksrcs[] = {
640 }, { 609 }, {
641 .clk = { 610 .clk = {
642 .name = "usb-bus-host", 611 .name = "usb-bus-host",
643 .id = -1,
644 .ctrlbit = S3C_CLKCON_SCLK_UHOST, 612 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
645 .enable = s3c64xx_sclk_ctrl, 613 .enable = s3c64xx_sclk_ctrl,
646 }, 614 },
@@ -650,7 +618,6 @@ static struct clksrc_clk clksrcs[] = {
650 }, { 618 }, {
651 .clk = { 619 .clk = {
652 .name = "uclk1", 620 .name = "uclk1",
653 .id = -1,
654 .ctrlbit = S3C_CLKCON_SCLK_UART, 621 .ctrlbit = S3C_CLKCON_SCLK_UART,
655 .enable = s3c64xx_sclk_ctrl, 622 .enable = s3c64xx_sclk_ctrl,
656 }, 623 },
@@ -661,7 +628,7 @@ static struct clksrc_clk clksrcs[] = {
661/* Where does UCLK0 come from? */ 628/* Where does UCLK0 come from? */
662 .clk = { 629 .clk = {
663 .name = "spi-bus", 630 .name = "spi-bus",
664 .id = 0, 631 .devname = "s3c64xx-spi.0",
665 .ctrlbit = S3C_CLKCON_SCLK_SPI0, 632 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
666 .enable = s3c64xx_sclk_ctrl, 633 .enable = s3c64xx_sclk_ctrl,
667 }, 634 },
@@ -671,8 +638,7 @@ static struct clksrc_clk clksrcs[] = {
671 }, { 638 }, {
672 .clk = { 639 .clk = {
673 .name = "spi-bus", 640 .name = "spi-bus",
674 .id = 1, 641 .devname = "s3c64xx-spi.1",
675 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
676 .enable = s3c64xx_sclk_ctrl, 642 .enable = s3c64xx_sclk_ctrl,
677 }, 643 },
678 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, 644 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
@@ -681,7 +647,7 @@ static struct clksrc_clk clksrcs[] = {
681 }, { 647 }, {
682 .clk = { 648 .clk = {
683 .name = "audio-bus", 649 .name = "audio-bus",
684 .id = 0, 650 .devname = "samsung-i2s.0",
685 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, 651 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
686 .enable = s3c64xx_sclk_ctrl, 652 .enable = s3c64xx_sclk_ctrl,
687 }, 653 },
@@ -691,7 +657,7 @@ static struct clksrc_clk clksrcs[] = {
691 }, { 657 }, {
692 .clk = { 658 .clk = {
693 .name = "audio-bus", 659 .name = "audio-bus",
694 .id = 1, 660 .devname = "samsung-i2s.1",
695 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, 661 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
696 .enable = s3c64xx_sclk_ctrl, 662 .enable = s3c64xx_sclk_ctrl,
697 }, 663 },
@@ -701,7 +667,7 @@ static struct clksrc_clk clksrcs[] = {
701 }, { 667 }, {
702 .clk = { 668 .clk = {
703 .name = "audio-bus", 669 .name = "audio-bus",
704 .id = 2, 670 .devname = "samsung-i2s.2",
705 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, 671 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
706 .enable = s3c64xx_sclk_ctrl, 672 .enable = s3c64xx_sclk_ctrl,
707 }, 673 },
@@ -711,7 +677,6 @@ static struct clksrc_clk clksrcs[] = {
711 }, { 677 }, {
712 .clk = { 678 .clk = {
713 .name = "irda-bus", 679 .name = "irda-bus",
714 .id = 0,
715 .ctrlbit = S3C_CLKCON_SCLK_IRDA, 680 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
716 .enable = s3c64xx_sclk_ctrl, 681 .enable = s3c64xx_sclk_ctrl,
717 }, 682 },
@@ -721,7 +686,6 @@ static struct clksrc_clk clksrcs[] = {
721 }, { 686 }, {
722 .clk = { 687 .clk = {
723 .name = "camera", 688 .name = "camera",
724 .id = -1,
725 .ctrlbit = S3C_CLKCON_SCLK_CAM, 689 .ctrlbit = S3C_CLKCON_SCLK_CAM,
726 .enable = s3c64xx_sclk_ctrl, 690 .enable = s3c64xx_sclk_ctrl,
727 }, 691 },
diff --git a/arch/arm/mach-s3c64xx/include/mach/clkdev.h b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 9f12c2ebf416..0e9cd3092dd2 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -95,7 +95,6 @@ static struct clk_ops s5p6440_epll_ops = {
95static struct clksrc_clk clk_hclk = { 95static struct clksrc_clk clk_hclk = {
96 .clk = { 96 .clk = {
97 .name = "clk_hclk", 97 .name = "clk_hclk",
98 .id = -1,
99 .parent = &clk_armclk.clk, 98 .parent = &clk_armclk.clk,
100 }, 99 },
101 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 }, 100 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
@@ -104,7 +103,6 @@ static struct clksrc_clk clk_hclk = {
104static struct clksrc_clk clk_pclk = { 103static struct clksrc_clk clk_pclk = {
105 .clk = { 104 .clk = {
106 .name = "clk_pclk", 105 .name = "clk_pclk",
107 .id = -1,
108 .parent = &clk_hclk.clk, 106 .parent = &clk_hclk.clk,
109 }, 107 },
110 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, 108 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
@@ -112,7 +110,6 @@ static struct clksrc_clk clk_pclk = {
112static struct clksrc_clk clk_hclk_low = { 110static struct clksrc_clk clk_hclk_low = {
113 .clk = { 111 .clk = {
114 .name = "clk_hclk_low", 112 .name = "clk_hclk_low",
115 .id = -1,
116 }, 113 },
117 .sources = &clkset_hclk_low, 114 .sources = &clkset_hclk_low,
118 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 }, 115 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
@@ -122,7 +119,6 @@ static struct clksrc_clk clk_hclk_low = {
122static struct clksrc_clk clk_pclk_low = { 119static struct clksrc_clk clk_pclk_low = {
123 .clk = { 120 .clk = {
124 .name = "clk_pclk_low", 121 .name = "clk_pclk_low",
125 .id = -1,
126 .parent = &clk_hclk_low.clk, 122 .parent = &clk_hclk_low.clk,
127 }, 123 },
128 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, 124 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
@@ -136,187 +132,167 @@ static struct clksrc_clk clk_pclk_low = {
136static struct clk init_clocks_off[] = { 132static struct clk init_clocks_off[] = {
137 { 133 {
138 .name = "nand", 134 .name = "nand",
139 .id = -1,
140 .parent = &clk_hclk.clk, 135 .parent = &clk_hclk.clk,
141 .enable = s5p64x0_mem_ctrl, 136 .enable = s5p64x0_mem_ctrl,
142 .ctrlbit = (1 << 2), 137 .ctrlbit = (1 << 2),
143 }, { 138 }, {
144 .name = "post", 139 .name = "post",
145 .id = -1,
146 .parent = &clk_hclk_low.clk, 140 .parent = &clk_hclk_low.clk,
147 .enable = s5p64x0_hclk0_ctrl, 141 .enable = s5p64x0_hclk0_ctrl,
148 .ctrlbit = (1 << 5) 142 .ctrlbit = (1 << 5)
149 }, { 143 }, {
150 .name = "2d", 144 .name = "2d",
151 .id = -1,
152 .parent = &clk_hclk.clk, 145 .parent = &clk_hclk.clk,
153 .enable = s5p64x0_hclk0_ctrl, 146 .enable = s5p64x0_hclk0_ctrl,
154 .ctrlbit = (1 << 8), 147 .ctrlbit = (1 << 8),
155 }, { 148 }, {
156 .name = "pdma", 149 .name = "pdma",
157 .id = -1,
158 .parent = &clk_hclk_low.clk, 150 .parent = &clk_hclk_low.clk,
159 .enable = s5p64x0_hclk0_ctrl, 151 .enable = s5p64x0_hclk0_ctrl,
160 .ctrlbit = (1 << 12), 152 .ctrlbit = (1 << 12),
161 }, { 153 }, {
162 .name = "hsmmc", 154 .name = "hsmmc",
163 .id = 0, 155 .devname = "s3c-sdhci.0",
164 .parent = &clk_hclk_low.clk, 156 .parent = &clk_hclk_low.clk,
165 .enable = s5p64x0_hclk0_ctrl, 157 .enable = s5p64x0_hclk0_ctrl,
166 .ctrlbit = (1 << 17), 158 .ctrlbit = (1 << 17),
167 }, { 159 }, {
168 .name = "hsmmc", 160 .name = "hsmmc",
169 .id = 1, 161 .devname = "s3c-sdhci.1",
170 .parent = &clk_hclk_low.clk, 162 .parent = &clk_hclk_low.clk,
171 .enable = s5p64x0_hclk0_ctrl, 163 .enable = s5p64x0_hclk0_ctrl,
172 .ctrlbit = (1 << 18), 164 .ctrlbit = (1 << 18),
173 }, { 165 }, {
174 .name = "hsmmc", 166 .name = "hsmmc",
175 .id = 2, 167 .devname = "s3c-sdhci.2",
176 .parent = &clk_hclk_low.clk, 168 .parent = &clk_hclk_low.clk,
177 .enable = s5p64x0_hclk0_ctrl, 169 .enable = s5p64x0_hclk0_ctrl,
178 .ctrlbit = (1 << 19), 170 .ctrlbit = (1 << 19),
179 }, { 171 }, {
180 .name = "otg", 172 .name = "otg",
181 .id = -1,
182 .parent = &clk_hclk_low.clk, 173 .parent = &clk_hclk_low.clk,
183 .enable = s5p64x0_hclk0_ctrl, 174 .enable = s5p64x0_hclk0_ctrl,
184 .ctrlbit = (1 << 20) 175 .ctrlbit = (1 << 20)
185 }, { 176 }, {
186 .name = "irom", 177 .name = "irom",
187 .id = -1,
188 .parent = &clk_hclk.clk, 178 .parent = &clk_hclk.clk,
189 .enable = s5p64x0_hclk0_ctrl, 179 .enable = s5p64x0_hclk0_ctrl,
190 .ctrlbit = (1 << 25), 180 .ctrlbit = (1 << 25),
191 }, { 181 }, {
192 .name = "lcd", 182 .name = "lcd",
193 .id = -1,
194 .parent = &clk_hclk_low.clk, 183 .parent = &clk_hclk_low.clk,
195 .enable = s5p64x0_hclk1_ctrl, 184 .enable = s5p64x0_hclk1_ctrl,
196 .ctrlbit = (1 << 1), 185 .ctrlbit = (1 << 1),
197 }, { 186 }, {
198 .name = "hclk_fimgvg", 187 .name = "hclk_fimgvg",
199 .id = -1,
200 .parent = &clk_hclk.clk, 188 .parent = &clk_hclk.clk,
201 .enable = s5p64x0_hclk1_ctrl, 189 .enable = s5p64x0_hclk1_ctrl,
202 .ctrlbit = (1 << 2), 190 .ctrlbit = (1 << 2),
203 }, { 191 }, {
204 .name = "tsi", 192 .name = "tsi",
205 .id = -1,
206 .parent = &clk_hclk_low.clk, 193 .parent = &clk_hclk_low.clk,
207 .enable = s5p64x0_hclk1_ctrl, 194 .enable = s5p64x0_hclk1_ctrl,
208 .ctrlbit = (1 << 0), 195 .ctrlbit = (1 << 0),
209 }, { 196 }, {
210 .name = "watchdog", 197 .name = "watchdog",
211 .id = -1,
212 .parent = &clk_pclk_low.clk, 198 .parent = &clk_pclk_low.clk,
213 .enable = s5p64x0_pclk_ctrl, 199 .enable = s5p64x0_pclk_ctrl,
214 .ctrlbit = (1 << 5), 200 .ctrlbit = (1 << 5),
215 }, { 201 }, {
216 .name = "rtc", 202 .name = "rtc",
217 .id = -1,
218 .parent = &clk_pclk_low.clk, 203 .parent = &clk_pclk_low.clk,
219 .enable = s5p64x0_pclk_ctrl, 204 .enable = s5p64x0_pclk_ctrl,
220 .ctrlbit = (1 << 6), 205 .ctrlbit = (1 << 6),
221 }, { 206 }, {
222 .name = "timers", 207 .name = "timers",
223 .id = -1,
224 .parent = &clk_pclk_low.clk, 208 .parent = &clk_pclk_low.clk,
225 .enable = s5p64x0_pclk_ctrl, 209 .enable = s5p64x0_pclk_ctrl,
226 .ctrlbit = (1 << 7), 210 .ctrlbit = (1 << 7),
227 }, { 211 }, {
228 .name = "pcm", 212 .name = "pcm",
229 .id = -1,
230 .parent = &clk_pclk_low.clk, 213 .parent = &clk_pclk_low.clk,
231 .enable = s5p64x0_pclk_ctrl, 214 .enable = s5p64x0_pclk_ctrl,
232 .ctrlbit = (1 << 8), 215 .ctrlbit = (1 << 8),
233 }, { 216 }, {
234 .name = "adc", 217 .name = "adc",
235 .id = -1,
236 .parent = &clk_pclk_low.clk, 218 .parent = &clk_pclk_low.clk,
237 .enable = s5p64x0_pclk_ctrl, 219 .enable = s5p64x0_pclk_ctrl,
238 .ctrlbit = (1 << 12), 220 .ctrlbit = (1 << 12),
239 }, { 221 }, {
240 .name = "i2c", 222 .name = "i2c",
241 .id = -1,
242 .parent = &clk_pclk_low.clk, 223 .parent = &clk_pclk_low.clk,
243 .enable = s5p64x0_pclk_ctrl, 224 .enable = s5p64x0_pclk_ctrl,
244 .ctrlbit = (1 << 17), 225 .ctrlbit = (1 << 17),
245 }, { 226 }, {
246 .name = "spi", 227 .name = "spi",
247 .id = 0, 228 .devname = "s3c64xx-spi.0",
248 .parent = &clk_pclk_low.clk, 229 .parent = &clk_pclk_low.clk,
249 .enable = s5p64x0_pclk_ctrl, 230 .enable = s5p64x0_pclk_ctrl,
250 .ctrlbit = (1 << 21), 231 .ctrlbit = (1 << 21),
251 }, { 232 }, {
252 .name = "spi", 233 .name = "spi",
253 .id = 1, 234 .devname = "s3c64xx-spi.1",
254 .parent = &clk_pclk_low.clk, 235 .parent = &clk_pclk_low.clk,
255 .enable = s5p64x0_pclk_ctrl, 236 .enable = s5p64x0_pclk_ctrl,
256 .ctrlbit = (1 << 22), 237 .ctrlbit = (1 << 22),
257 }, { 238 }, {
258 .name = "gps", 239 .name = "gps",
259 .id = -1,
260 .parent = &clk_pclk_low.clk, 240 .parent = &clk_pclk_low.clk,
261 .enable = s5p64x0_pclk_ctrl, 241 .enable = s5p64x0_pclk_ctrl,
262 .ctrlbit = (1 << 25), 242 .ctrlbit = (1 << 25),
263 }, { 243 }, {
264 .name = "iis", 244 .name = "iis",
265 .id = 0, 245 .devname = "samsung-i2s.0",
266 .parent = &clk_pclk_low.clk, 246 .parent = &clk_pclk_low.clk,
267 .enable = s5p64x0_pclk_ctrl, 247 .enable = s5p64x0_pclk_ctrl,
268 .ctrlbit = (1 << 26), 248 .ctrlbit = (1 << 26),
269 }, { 249 }, {
270 .name = "dsim", 250 .name = "dsim",
271 .id = -1,
272 .parent = &clk_pclk_low.clk, 251 .parent = &clk_pclk_low.clk,
273 .enable = s5p64x0_pclk_ctrl, 252 .enable = s5p64x0_pclk_ctrl,
274 .ctrlbit = (1 << 28), 253 .ctrlbit = (1 << 28),
275 }, { 254 }, {
276 .name = "etm", 255 .name = "etm",
277 .id = -1,
278 .parent = &clk_pclk.clk, 256 .parent = &clk_pclk.clk,
279 .enable = s5p64x0_pclk_ctrl, 257 .enable = s5p64x0_pclk_ctrl,
280 .ctrlbit = (1 << 29), 258 .ctrlbit = (1 << 29),
281 }, { 259 }, {
282 .name = "dmc0", 260 .name = "dmc0",
283 .id = -1,
284 .parent = &clk_pclk.clk, 261 .parent = &clk_pclk.clk,
285 .enable = s5p64x0_pclk_ctrl, 262 .enable = s5p64x0_pclk_ctrl,
286 .ctrlbit = (1 << 30), 263 .ctrlbit = (1 << 30),
287 }, { 264 }, {
288 .name = "pclk_fimgvg", 265 .name = "pclk_fimgvg",
289 .id = -1,
290 .parent = &clk_pclk.clk, 266 .parent = &clk_pclk.clk,
291 .enable = s5p64x0_pclk_ctrl, 267 .enable = s5p64x0_pclk_ctrl,
292 .ctrlbit = (1 << 31), 268 .ctrlbit = (1 << 31),
293 }, { 269 }, {
294 .name = "sclk_spi_48", 270 .name = "sclk_spi_48",
295 .id = 0, 271 .devname = "s3c64xx-spi.0",
296 .parent = &clk_48m, 272 .parent = &clk_48m,
297 .enable = s5p64x0_sclk_ctrl, 273 .enable = s5p64x0_sclk_ctrl,
298 .ctrlbit = (1 << 22), 274 .ctrlbit = (1 << 22),
299 }, { 275 }, {
300 .name = "sclk_spi_48", 276 .name = "sclk_spi_48",
301 .id = 1, 277 .devname = "s3c64xx-spi.1",
302 .parent = &clk_48m, 278 .parent = &clk_48m,
303 .enable = s5p64x0_sclk_ctrl, 279 .enable = s5p64x0_sclk_ctrl,
304 .ctrlbit = (1 << 23), 280 .ctrlbit = (1 << 23),
305 }, { 281 }, {
306 .name = "mmc_48m", 282 .name = "mmc_48m",
307 .id = 0, 283 .devname = "s3c-sdhci.0",
308 .parent = &clk_48m, 284 .parent = &clk_48m,
309 .enable = s5p64x0_sclk_ctrl, 285 .enable = s5p64x0_sclk_ctrl,
310 .ctrlbit = (1 << 27), 286 .ctrlbit = (1 << 27),
311 }, { 287 }, {
312 .name = "mmc_48m", 288 .name = "mmc_48m",
313 .id = 1, 289 .devname = "s3c-sdhci.1",
314 .parent = &clk_48m, 290 .parent = &clk_48m,
315 .enable = s5p64x0_sclk_ctrl, 291 .enable = s5p64x0_sclk_ctrl,
316 .ctrlbit = (1 << 28), 292 .ctrlbit = (1 << 28),
317 }, { 293 }, {
318 .name = "mmc_48m", 294 .name = "mmc_48m",
319 .id = 2, 295 .devname = "s3c-sdhci.2",
320 .parent = &clk_48m, 296 .parent = &clk_48m,
321 .enable = s5p64x0_sclk_ctrl, 297 .enable = s5p64x0_sclk_ctrl,
322 .ctrlbit = (1 << 29), 298 .ctrlbit = (1 << 29),
@@ -329,43 +305,40 @@ static struct clk init_clocks_off[] = {
329static struct clk init_clocks[] = { 305static struct clk init_clocks[] = {
330 { 306 {
331 .name = "intc", 307 .name = "intc",
332 .id = -1,
333 .parent = &clk_hclk.clk, 308 .parent = &clk_hclk.clk,
334 .enable = s5p64x0_hclk0_ctrl, 309 .enable = s5p64x0_hclk0_ctrl,
335 .ctrlbit = (1 << 1), 310 .ctrlbit = (1 << 1),
336 }, { 311 }, {
337 .name = "mem", 312 .name = "mem",
338 .id = -1,
339 .parent = &clk_hclk.clk, 313 .parent = &clk_hclk.clk,
340 .enable = s5p64x0_hclk0_ctrl, 314 .enable = s5p64x0_hclk0_ctrl,
341 .ctrlbit = (1 << 21), 315 .ctrlbit = (1 << 21),
342 }, { 316 }, {
343 .name = "uart", 317 .name = "uart",
344 .id = 0, 318 .devname = "s3c6400-uart.0",
345 .parent = &clk_pclk_low.clk, 319 .parent = &clk_pclk_low.clk,
346 .enable = s5p64x0_pclk_ctrl, 320 .enable = s5p64x0_pclk_ctrl,
347 .ctrlbit = (1 << 1), 321 .ctrlbit = (1 << 1),
348 }, { 322 }, {
349 .name = "uart", 323 .name = "uart",
350 .id = 1, 324 .devname = "s3c6400-uart.1",
351 .parent = &clk_pclk_low.clk, 325 .parent = &clk_pclk_low.clk,
352 .enable = s5p64x0_pclk_ctrl, 326 .enable = s5p64x0_pclk_ctrl,
353 .ctrlbit = (1 << 2), 327 .ctrlbit = (1 << 2),
354 }, { 328 }, {
355 .name = "uart", 329 .name = "uart",
356 .id = 2, 330 .devname = "s3c6400-uart.2",
357 .parent = &clk_pclk_low.clk, 331 .parent = &clk_pclk_low.clk,
358 .enable = s5p64x0_pclk_ctrl, 332 .enable = s5p64x0_pclk_ctrl,
359 .ctrlbit = (1 << 3), 333 .ctrlbit = (1 << 3),
360 }, { 334 }, {
361 .name = "uart", 335 .name = "uart",
362 .id = 3, 336 .devname = "s3c6400-uart.3",
363 .parent = &clk_pclk_low.clk, 337 .parent = &clk_pclk_low.clk,
364 .enable = s5p64x0_pclk_ctrl, 338 .enable = s5p64x0_pclk_ctrl,
365 .ctrlbit = (1 << 4), 339 .ctrlbit = (1 << 4),
366 }, { 340 }, {
367 .name = "gpio", 341 .name = "gpio",
368 .id = -1,
369 .parent = &clk_pclk_low.clk, 342 .parent = &clk_pclk_low.clk,
370 .enable = s5p64x0_pclk_ctrl, 343 .enable = s5p64x0_pclk_ctrl,
371 .ctrlbit = (1 << 18), 344 .ctrlbit = (1 << 18),
@@ -374,12 +347,10 @@ static struct clk init_clocks[] = {
374 347
375static struct clk clk_iis_cd_v40 = { 348static struct clk clk_iis_cd_v40 = {
376 .name = "iis_cdclk_v40", 349 .name = "iis_cdclk_v40",
377 .id = -1,
378}; 350};
379 351
380static struct clk clk_pcm_cd = { 352static struct clk clk_pcm_cd = {
381 .name = "pcm_cdclk", 353 .name = "pcm_cdclk",
382 .id = -1,
383}; 354};
384 355
385static struct clk *clkset_group1_list[] = { 356static struct clk *clkset_group1_list[] = {
@@ -420,7 +391,7 @@ static struct clksrc_clk clksrcs[] = {
420 { 391 {
421 .clk = { 392 .clk = {
422 .name = "sclk_mmc", 393 .name = "sclk_mmc",
423 .id = 0, 394 .devname = "s3c-sdhci.0",
424 .ctrlbit = (1 << 24), 395 .ctrlbit = (1 << 24),
425 .enable = s5p64x0_sclk_ctrl, 396 .enable = s5p64x0_sclk_ctrl,
426 }, 397 },
@@ -430,7 +401,7 @@ static struct clksrc_clk clksrcs[] = {
430 }, { 401 }, {
431 .clk = { 402 .clk = {
432 .name = "sclk_mmc", 403 .name = "sclk_mmc",
433 .id = 1, 404 .devname = "s3c-sdhci.1",
434 .ctrlbit = (1 << 25), 405 .ctrlbit = (1 << 25),
435 .enable = s5p64x0_sclk_ctrl, 406 .enable = s5p64x0_sclk_ctrl,
436 }, 407 },
@@ -440,7 +411,7 @@ static struct clksrc_clk clksrcs[] = {
440 }, { 411 }, {
441 .clk = { 412 .clk = {
442 .name = "sclk_mmc", 413 .name = "sclk_mmc",
443 .id = 2, 414 .devname = "s3c-sdhci.2",
444 .ctrlbit = (1 << 26), 415 .ctrlbit = (1 << 26),
445 .enable = s5p64x0_sclk_ctrl, 416 .enable = s5p64x0_sclk_ctrl,
446 }, 417 },
@@ -450,7 +421,6 @@ static struct clksrc_clk clksrcs[] = {
450 }, { 421 }, {
451 .clk = { 422 .clk = {
452 .name = "uclk1", 423 .name = "uclk1",
453 .id = -1,
454 .ctrlbit = (1 << 5), 424 .ctrlbit = (1 << 5),
455 .enable = s5p64x0_sclk_ctrl, 425 .enable = s5p64x0_sclk_ctrl,
456 }, 426 },
@@ -460,7 +430,7 @@ static struct clksrc_clk clksrcs[] = {
460 }, { 430 }, {
461 .clk = { 431 .clk = {
462 .name = "sclk_spi", 432 .name = "sclk_spi",
463 .id = 0, 433 .devname = "s3c64xx-spi.0",
464 .ctrlbit = (1 << 20), 434 .ctrlbit = (1 << 20),
465 .enable = s5p64x0_sclk_ctrl, 435 .enable = s5p64x0_sclk_ctrl,
466 }, 436 },
@@ -470,7 +440,7 @@ static struct clksrc_clk clksrcs[] = {
470 }, { 440 }, {
471 .clk = { 441 .clk = {
472 .name = "sclk_spi", 442 .name = "sclk_spi",
473 .id = 1, 443 .devname = "s3c64xx-spi.1",
474 .ctrlbit = (1 << 21), 444 .ctrlbit = (1 << 21),
475 .enable = s5p64x0_sclk_ctrl, 445 .enable = s5p64x0_sclk_ctrl,
476 }, 446 },
@@ -480,7 +450,6 @@ static struct clksrc_clk clksrcs[] = {
480 }, { 450 }, {
481 .clk = { 451 .clk = {
482 .name = "sclk_post", 452 .name = "sclk_post",
483 .id = -1,
484 .ctrlbit = (1 << 10), 453 .ctrlbit = (1 << 10),
485 .enable = s5p64x0_sclk_ctrl, 454 .enable = s5p64x0_sclk_ctrl,
486 }, 455 },
@@ -490,7 +459,6 @@ static struct clksrc_clk clksrcs[] = {
490 }, { 459 }, {
491 .clk = { 460 .clk = {
492 .name = "sclk_dispcon", 461 .name = "sclk_dispcon",
493 .id = -1,
494 .ctrlbit = (1 << 1), 462 .ctrlbit = (1 << 1),
495 .enable = s5p64x0_sclk1_ctrl, 463 .enable = s5p64x0_sclk1_ctrl,
496 }, 464 },
@@ -500,7 +468,6 @@ static struct clksrc_clk clksrcs[] = {
500 }, { 468 }, {
501 .clk = { 469 .clk = {
502 .name = "sclk_fimgvg", 470 .name = "sclk_fimgvg",
503 .id = -1,
504 .ctrlbit = (1 << 2), 471 .ctrlbit = (1 << 2),
505 .enable = s5p64x0_sclk1_ctrl, 472 .enable = s5p64x0_sclk1_ctrl,
506 }, 473 },
@@ -510,7 +477,6 @@ static struct clksrc_clk clksrcs[] = {
510 }, { 477 }, {
511 .clk = { 478 .clk = {
512 .name = "sclk_audio2", 479 .name = "sclk_audio2",
513 .id = -1,
514 .ctrlbit = (1 << 11), 480 .ctrlbit = (1 << 11),
515 .enable = s5p64x0_sclk_ctrl, 481 .enable = s5p64x0_sclk_ctrl,
516 }, 482 },
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 4eec457ddccc..d9dc16cde109 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -36,7 +36,6 @@
36static struct clksrc_clk clk_mout_dpll = { 36static struct clksrc_clk clk_mout_dpll = {
37 .clk = { 37 .clk = {
38 .name = "mout_dpll", 38 .name = "mout_dpll",
39 .id = -1,
40 }, 39 },
41 .sources = &clk_src_dpll, 40 .sources = &clk_src_dpll,
42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 }, 41 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
@@ -96,7 +95,6 @@ static struct clk_ops s5p6450_epll_ops = {
96static struct clksrc_clk clk_dout_epll = { 95static struct clksrc_clk clk_dout_epll = {
97 .clk = { 96 .clk = {
98 .name = "dout_epll", 97 .name = "dout_epll",
99 .id = -1,
100 .parent = &clk_mout_epll.clk, 98 .parent = &clk_mout_epll.clk,
101 }, 99 },
102 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 }, 100 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
@@ -105,7 +103,6 @@ static struct clksrc_clk clk_dout_epll = {
105static struct clksrc_clk clk_mout_hclk_sel = { 103static struct clksrc_clk clk_mout_hclk_sel = {
106 .clk = { 104 .clk = {
107 .name = "mout_hclk_sel", 105 .name = "mout_hclk_sel",
108 .id = -1,
109 }, 106 },
110 .sources = &clkset_hclk_low, 107 .sources = &clkset_hclk_low,
111 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 }, 108 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
@@ -124,7 +121,6 @@ static struct clksrc_sources clkset_hclk = {
124static struct clksrc_clk clk_hclk = { 121static struct clksrc_clk clk_hclk = {
125 .clk = { 122 .clk = {
126 .name = "clk_hclk", 123 .name = "clk_hclk",
127 .id = -1,
128 }, 124 },
129 .sources = &clkset_hclk, 125 .sources = &clkset_hclk,
130 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 }, 126 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
@@ -134,7 +130,6 @@ static struct clksrc_clk clk_hclk = {
134static struct clksrc_clk clk_pclk = { 130static struct clksrc_clk clk_pclk = {
135 .clk = { 131 .clk = {
136 .name = "clk_pclk", 132 .name = "clk_pclk",
137 .id = -1,
138 .parent = &clk_hclk.clk, 133 .parent = &clk_hclk.clk,
139 }, 134 },
140 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, 135 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
@@ -142,7 +137,6 @@ static struct clksrc_clk clk_pclk = {
142static struct clksrc_clk clk_dout_pwm_ratio0 = { 137static struct clksrc_clk clk_dout_pwm_ratio0 = {
143 .clk = { 138 .clk = {
144 .name = "clk_dout_pwm_ratio0", 139 .name = "clk_dout_pwm_ratio0",
145 .id = -1,
146 .parent = &clk_mout_hclk_sel.clk, 140 .parent = &clk_mout_hclk_sel.clk,
147 }, 141 },
148 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 }, 142 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
@@ -151,7 +145,6 @@ static struct clksrc_clk clk_dout_pwm_ratio0 = {
151static struct clksrc_clk clk_pclk_to_wdt_pwm = { 145static struct clksrc_clk clk_pclk_to_wdt_pwm = {
152 .clk = { 146 .clk = {
153 .name = "clk_pclk_to_wdt_pwm", 147 .name = "clk_pclk_to_wdt_pwm",
154 .id = -1,
155 .parent = &clk_dout_pwm_ratio0.clk, 148 .parent = &clk_dout_pwm_ratio0.clk,
156 }, 149 },
157 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 }, 150 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
@@ -160,7 +153,6 @@ static struct clksrc_clk clk_pclk_to_wdt_pwm = {
160static struct clksrc_clk clk_hclk_low = { 153static struct clksrc_clk clk_hclk_low = {
161 .clk = { 154 .clk = {
162 .name = "clk_hclk_low", 155 .name = "clk_hclk_low",
163 .id = -1,
164 }, 156 },
165 .sources = &clkset_hclk_low, 157 .sources = &clkset_hclk_low,
166 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 }, 158 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
@@ -170,7 +162,6 @@ static struct clksrc_clk clk_hclk_low = {
170static struct clksrc_clk clk_pclk_low = { 162static struct clksrc_clk clk_pclk_low = {
171 .clk = { 163 .clk = {
172 .name = "clk_pclk_low", 164 .name = "clk_pclk_low",
173 .id = -1,
174 .parent = &clk_hclk_low.clk, 165 .parent = &clk_hclk_low.clk,
175 }, 166 },
176 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, 167 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
@@ -184,109 +175,101 @@ static struct clksrc_clk clk_pclk_low = {
184static struct clk init_clocks_off[] = { 175static struct clk init_clocks_off[] = {
185 { 176 {
186 .name = "usbhost", 177 .name = "usbhost",
187 .id = -1,
188 .parent = &clk_hclk_low.clk, 178 .parent = &clk_hclk_low.clk,
189 .enable = s5p64x0_hclk0_ctrl, 179 .enable = s5p64x0_hclk0_ctrl,
190 .ctrlbit = (1 << 3), 180 .ctrlbit = (1 << 3),
191 }, { 181 }, {
192 .name = "pdma", 182 .name = "pdma",
193 .id = -1,
194 .parent = &clk_hclk_low.clk, 183 .parent = &clk_hclk_low.clk,
195 .enable = s5p64x0_hclk0_ctrl, 184 .enable = s5p64x0_hclk0_ctrl,
196 .ctrlbit = (1 << 12), 185 .ctrlbit = (1 << 12),
197 }, { 186 }, {
198 .name = "hsmmc", 187 .name = "hsmmc",
199 .id = 0, 188 .devname = "s3c-sdhci.0",
200 .parent = &clk_hclk_low.clk, 189 .parent = &clk_hclk_low.clk,
201 .enable = s5p64x0_hclk0_ctrl, 190 .enable = s5p64x0_hclk0_ctrl,
202 .ctrlbit = (1 << 17), 191 .ctrlbit = (1 << 17),
203 }, { 192 }, {
204 .name = "hsmmc", 193 .name = "hsmmc",
205 .id = 1, 194 .devname = "s3c-sdhci.1",
206 .parent = &clk_hclk_low.clk, 195 .parent = &clk_hclk_low.clk,
207 .enable = s5p64x0_hclk0_ctrl, 196 .enable = s5p64x0_hclk0_ctrl,
208 .ctrlbit = (1 << 18), 197 .ctrlbit = (1 << 18),
209 }, { 198 }, {
210 .name = "hsmmc", 199 .name = "hsmmc",
211 .id = 2, 200 .devname = "s3c-sdhci.2",
212 .parent = &clk_hclk_low.clk, 201 .parent = &clk_hclk_low.clk,
213 .enable = s5p64x0_hclk0_ctrl, 202 .enable = s5p64x0_hclk0_ctrl,
214 .ctrlbit = (1 << 19), 203 .ctrlbit = (1 << 19),
215 }, { 204 }, {
216 .name = "usbotg", 205 .name = "usbotg",
217 .id = -1,
218 .parent = &clk_hclk_low.clk, 206 .parent = &clk_hclk_low.clk,
219 .enable = s5p64x0_hclk0_ctrl, 207 .enable = s5p64x0_hclk0_ctrl,
220 .ctrlbit = (1 << 20), 208 .ctrlbit = (1 << 20),
221 }, { 209 }, {
222 .name = "lcd", 210 .name = "lcd",
223 .id = -1,
224 .parent = &clk_h, 211 .parent = &clk_h,
225 .enable = s5p64x0_hclk1_ctrl, 212 .enable = s5p64x0_hclk1_ctrl,
226 .ctrlbit = (1 << 1), 213 .ctrlbit = (1 << 1),
227 }, { 214 }, {
228 .name = "watchdog", 215 .name = "watchdog",
229 .id = -1,
230 .parent = &clk_pclk_low.clk, 216 .parent = &clk_pclk_low.clk,
231 .enable = s5p64x0_pclk_ctrl, 217 .enable = s5p64x0_pclk_ctrl,
232 .ctrlbit = (1 << 5), 218 .ctrlbit = (1 << 5),
233 }, { 219 }, {
234 .name = "rtc", 220 .name = "rtc",
235 .id = -1,
236 .parent = &clk_pclk_low.clk, 221 .parent = &clk_pclk_low.clk,
237 .enable = s5p64x0_pclk_ctrl, 222 .enable = s5p64x0_pclk_ctrl,
238 .ctrlbit = (1 << 6), 223 .ctrlbit = (1 << 6),
239 }, { 224 }, {
240 .name = "adc", 225 .name = "adc",
241 .id = -1,
242 .parent = &clk_pclk_low.clk, 226 .parent = &clk_pclk_low.clk,
243 .enable = s5p64x0_pclk_ctrl, 227 .enable = s5p64x0_pclk_ctrl,
244 .ctrlbit = (1 << 12), 228 .ctrlbit = (1 << 12),
245 }, { 229 }, {
246 .name = "i2c", 230 .name = "i2c",
247 .id = 0, 231 .devname = "s3c2440-i2c.0",
248 .parent = &clk_pclk_low.clk, 232 .parent = &clk_pclk_low.clk,
249 .enable = s5p64x0_pclk_ctrl, 233 .enable = s5p64x0_pclk_ctrl,
250 .ctrlbit = (1 << 17), 234 .ctrlbit = (1 << 17),
251 }, { 235 }, {
252 .name = "spi", 236 .name = "spi",
253 .id = 0, 237 .devname = "s3c64xx-spi.0",
254 .parent = &clk_pclk_low.clk, 238 .parent = &clk_pclk_low.clk,
255 .enable = s5p64x0_pclk_ctrl, 239 .enable = s5p64x0_pclk_ctrl,
256 .ctrlbit = (1 << 21), 240 .ctrlbit = (1 << 21),
257 }, { 241 }, {
258 .name = "spi", 242 .name = "spi",
259 .id = 1, 243 .devname = "s3c64xx-spi.1",
260 .parent = &clk_pclk_low.clk, 244 .parent = &clk_pclk_low.clk,
261 .enable = s5p64x0_pclk_ctrl, 245 .enable = s5p64x0_pclk_ctrl,
262 .ctrlbit = (1 << 22), 246 .ctrlbit = (1 << 22),
263 }, { 247 }, {
264 .name = "iis", 248 .name = "iis",
265 .id = 0, 249 .devname = "samsung-i2s.0",
266 .parent = &clk_pclk_low.clk, 250 .parent = &clk_pclk_low.clk,
267 .enable = s5p64x0_pclk_ctrl, 251 .enable = s5p64x0_pclk_ctrl,
268 .ctrlbit = (1 << 26), 252 .ctrlbit = (1 << 26),
269 }, { 253 }, {
270 .name = "iis", 254 .name = "iis",
271 .id = 1, 255 .devname = "samsung-i2s.1",
272 .parent = &clk_pclk_low.clk, 256 .parent = &clk_pclk_low.clk,
273 .enable = s5p64x0_pclk_ctrl, 257 .enable = s5p64x0_pclk_ctrl,
274 .ctrlbit = (1 << 15), 258 .ctrlbit = (1 << 15),
275 }, { 259 }, {
276 .name = "iis", 260 .name = "iis",
277 .id = 2, 261 .devname = "samsung-i2s.2",
278 .parent = &clk_pclk_low.clk, 262 .parent = &clk_pclk_low.clk,
279 .enable = s5p64x0_pclk_ctrl, 263 .enable = s5p64x0_pclk_ctrl,
280 .ctrlbit = (1 << 16), 264 .ctrlbit = (1 << 16),
281 }, { 265 }, {
282 .name = "i2c", 266 .name = "i2c",
283 .id = 1, 267 .devname = "s3c2440-i2c.1",
284 .parent = &clk_pclk_low.clk, 268 .parent = &clk_pclk_low.clk,
285 .enable = s5p64x0_pclk_ctrl, 269 .enable = s5p64x0_pclk_ctrl,
286 .ctrlbit = (1 << 27), 270 .ctrlbit = (1 << 27),
287 }, { 271 }, {
288 .name = "dmc0", 272 .name = "dmc0",
289 .id = -1,
290 .parent = &clk_pclk.clk, 273 .parent = &clk_pclk.clk,
291 .enable = s5p64x0_pclk_ctrl, 274 .enable = s5p64x0_pclk_ctrl,
292 .ctrlbit = (1 << 30), 275 .ctrlbit = (1 << 30),
@@ -299,49 +282,45 @@ static struct clk init_clocks_off[] = {
299static struct clk init_clocks[] = { 282static struct clk init_clocks[] = {
300 { 283 {
301 .name = "intc", 284 .name = "intc",
302 .id = -1,
303 .parent = &clk_hclk.clk, 285 .parent = &clk_hclk.clk,
304 .enable = s5p64x0_hclk0_ctrl, 286 .enable = s5p64x0_hclk0_ctrl,
305 .ctrlbit = (1 << 1), 287 .ctrlbit = (1 << 1),
306 }, { 288 }, {
307 .name = "mem", 289 .name = "mem",
308 .id = -1,
309 .parent = &clk_hclk.clk, 290 .parent = &clk_hclk.clk,
310 .enable = s5p64x0_hclk0_ctrl, 291 .enable = s5p64x0_hclk0_ctrl,
311 .ctrlbit = (1 << 21), 292 .ctrlbit = (1 << 21),
312 }, { 293 }, {
313 .name = "uart", 294 .name = "uart",
314 .id = 0, 295 .devname = "s3c6400-uart.0",
315 .parent = &clk_pclk_low.clk, 296 .parent = &clk_pclk_low.clk,
316 .enable = s5p64x0_pclk_ctrl, 297 .enable = s5p64x0_pclk_ctrl,
317 .ctrlbit = (1 << 1), 298 .ctrlbit = (1 << 1),
318 }, { 299 }, {
319 .name = "uart", 300 .name = "uart",
320 .id = 1, 301 .devname = "s3c6400-uart.1",
321 .parent = &clk_pclk_low.clk, 302 .parent = &clk_pclk_low.clk,
322 .enable = s5p64x0_pclk_ctrl, 303 .enable = s5p64x0_pclk_ctrl,
323 .ctrlbit = (1 << 2), 304 .ctrlbit = (1 << 2),
324 }, { 305 }, {
325 .name = "uart", 306 .name = "uart",
326 .id = 2, 307 .devname = "s3c6400-uart.2",
327 .parent = &clk_pclk_low.clk, 308 .parent = &clk_pclk_low.clk,
328 .enable = s5p64x0_pclk_ctrl, 309 .enable = s5p64x0_pclk_ctrl,
329 .ctrlbit = (1 << 3), 310 .ctrlbit = (1 << 3),
330 }, { 311 }, {
331 .name = "uart", 312 .name = "uart",
332 .id = 3, 313 .devname = "s3c6400-uart.3",
333 .parent = &clk_pclk_low.clk, 314 .parent = &clk_pclk_low.clk,
334 .enable = s5p64x0_pclk_ctrl, 315 .enable = s5p64x0_pclk_ctrl,
335 .ctrlbit = (1 << 4), 316 .ctrlbit = (1 << 4),
336 }, { 317 }, {
337 .name = "timers", 318 .name = "timers",
338 .id = -1,
339 .parent = &clk_pclk_to_wdt_pwm.clk, 319 .parent = &clk_pclk_to_wdt_pwm.clk,
340 .enable = s5p64x0_pclk_ctrl, 320 .enable = s5p64x0_pclk_ctrl,
341 .ctrlbit = (1 << 7), 321 .ctrlbit = (1 << 7),
342 }, { 322 }, {
343 .name = "gpio", 323 .name = "gpio",
344 .id = -1,
345 .parent = &clk_pclk_low.clk, 324 .parent = &clk_pclk_low.clk,
346 .enable = s5p64x0_pclk_ctrl, 325 .enable = s5p64x0_pclk_ctrl,
347 .ctrlbit = (1 << 18), 326 .ctrlbit = (1 << 18),
@@ -421,7 +400,6 @@ static struct clksrc_sources clkset_sclk_audio0 = {
421static struct clksrc_clk clk_sclk_audio0 = { 400static struct clksrc_clk clk_sclk_audio0 = {
422 .clk = { 401 .clk = {
423 .name = "audio-bus", 402 .name = "audio-bus",
424 .id = -1,
425 .enable = s5p64x0_sclk_ctrl, 403 .enable = s5p64x0_sclk_ctrl,
426 .ctrlbit = (1 << 8), 404 .ctrlbit = (1 << 8),
427 .parent = &clk_dout_epll.clk, 405 .parent = &clk_dout_epll.clk,
@@ -435,7 +413,7 @@ static struct clksrc_clk clksrcs[] = {
435 { 413 {
436 .clk = { 414 .clk = {
437 .name = "sclk_mmc", 415 .name = "sclk_mmc",
438 .id = 0, 416 .devname = "s3c-sdhci.0",
439 .ctrlbit = (1 << 24), 417 .ctrlbit = (1 << 24),
440 .enable = s5p64x0_sclk_ctrl, 418 .enable = s5p64x0_sclk_ctrl,
441 }, 419 },
@@ -445,7 +423,7 @@ static struct clksrc_clk clksrcs[] = {
445 }, { 423 }, {
446 .clk = { 424 .clk = {
447 .name = "sclk_mmc", 425 .name = "sclk_mmc",
448 .id = 1, 426 .devname = "s3c-sdhci.1",
449 .ctrlbit = (1 << 25), 427 .ctrlbit = (1 << 25),
450 .enable = s5p64x0_sclk_ctrl, 428 .enable = s5p64x0_sclk_ctrl,
451 }, 429 },
@@ -455,7 +433,7 @@ static struct clksrc_clk clksrcs[] = {
455 }, { 433 }, {
456 .clk = { 434 .clk = {
457 .name = "sclk_mmc", 435 .name = "sclk_mmc",
458 .id = 2, 436 .devname = "s3c-sdhci.2",
459 .ctrlbit = (1 << 26), 437 .ctrlbit = (1 << 26),
460 .enable = s5p64x0_sclk_ctrl, 438 .enable = s5p64x0_sclk_ctrl,
461 }, 439 },
@@ -465,7 +443,6 @@ static struct clksrc_clk clksrcs[] = {
465 }, { 443 }, {
466 .clk = { 444 .clk = {
467 .name = "uclk1", 445 .name = "uclk1",
468 .id = -1,
469 .ctrlbit = (1 << 5), 446 .ctrlbit = (1 << 5),
470 .enable = s5p64x0_sclk_ctrl, 447 .enable = s5p64x0_sclk_ctrl,
471 }, 448 },
@@ -475,7 +452,7 @@ static struct clksrc_clk clksrcs[] = {
475 }, { 452 }, {
476 .clk = { 453 .clk = {
477 .name = "sclk_spi", 454 .name = "sclk_spi",
478 .id = 0, 455 .devname = "s3c64xx-spi.0",
479 .ctrlbit = (1 << 20), 456 .ctrlbit = (1 << 20),
480 .enable = s5p64x0_sclk_ctrl, 457 .enable = s5p64x0_sclk_ctrl,
481 }, 458 },
@@ -485,7 +462,7 @@ static struct clksrc_clk clksrcs[] = {
485 }, { 462 }, {
486 .clk = { 463 .clk = {
487 .name = "sclk_spi", 464 .name = "sclk_spi",
488 .id = 1, 465 .devname = "s3c64xx-spi.1",
489 .ctrlbit = (1 << 21), 466 .ctrlbit = (1 << 21),
490 .enable = s5p64x0_sclk_ctrl, 467 .enable = s5p64x0_sclk_ctrl,
491 }, 468 },
@@ -495,7 +472,6 @@ static struct clksrc_clk clksrcs[] = {
495 }, { 472 }, {
496 .clk = { 473 .clk = {
497 .name = "sclk_fimc", 474 .name = "sclk_fimc",
498 .id = -1,
499 .ctrlbit = (1 << 10), 475 .ctrlbit = (1 << 10),
500 .enable = s5p64x0_sclk_ctrl, 476 .enable = s5p64x0_sclk_ctrl,
501 }, 477 },
@@ -505,7 +481,6 @@ static struct clksrc_clk clksrcs[] = {
505 }, { 481 }, {
506 .clk = { 482 .clk = {
507 .name = "aclk_mali", 483 .name = "aclk_mali",
508 .id = -1,
509 .ctrlbit = (1 << 2), 484 .ctrlbit = (1 << 2),
510 .enable = s5p64x0_sclk1_ctrl, 485 .enable = s5p64x0_sclk1_ctrl,
511 }, 486 },
@@ -515,7 +490,6 @@ static struct clksrc_clk clksrcs[] = {
515 }, { 490 }, {
516 .clk = { 491 .clk = {
517 .name = "sclk_2d", 492 .name = "sclk_2d",
518 .id = -1,
519 .ctrlbit = (1 << 12), 493 .ctrlbit = (1 << 12),
520 .enable = s5p64x0_sclk_ctrl, 494 .enable = s5p64x0_sclk_ctrl,
521 }, 495 },
@@ -525,7 +499,6 @@ static struct clksrc_clk clksrcs[] = {
525 }, { 499 }, {
526 .clk = { 500 .clk = {
527 .name = "sclk_usi", 501 .name = "sclk_usi",
528 .id = -1,
529 .ctrlbit = (1 << 7), 502 .ctrlbit = (1 << 7),
530 .enable = s5p64x0_sclk_ctrl, 503 .enable = s5p64x0_sclk_ctrl,
531 }, 504 },
@@ -535,7 +508,6 @@ static struct clksrc_clk clksrcs[] = {
535 }, { 508 }, {
536 .clk = { 509 .clk = {
537 .name = "sclk_camif", 510 .name = "sclk_camif",
538 .id = -1,
539 .ctrlbit = (1 << 6), 511 .ctrlbit = (1 << 6),
540 .enable = s5p64x0_sclk_ctrl, 512 .enable = s5p64x0_sclk_ctrl,
541 }, 513 },
@@ -545,7 +517,6 @@ static struct clksrc_clk clksrcs[] = {
545 }, { 517 }, {
546 .clk = { 518 .clk = {
547 .name = "sclk_dispcon", 519 .name = "sclk_dispcon",
548 .id = -1,
549 .ctrlbit = (1 << 1), 520 .ctrlbit = (1 << 1),
550 .enable = s5p64x0_sclk1_ctrl, 521 .enable = s5p64x0_sclk1_ctrl,
551 }, 522 },
@@ -555,7 +526,6 @@ static struct clksrc_clk clksrcs[] = {
555 }, { 526 }, {
556 .clk = { 527 .clk = {
557 .name = "sclk_hsmmc44", 528 .name = "sclk_hsmmc44",
558 .id = -1,
559 .ctrlbit = (1 << 30), 529 .ctrlbit = (1 << 30),
560 .enable = s5p64x0_sclk_ctrl, 530 .enable = s5p64x0_sclk_ctrl,
561 }, 531 },
diff --git a/arch/arm/mach-s5p64x0/include/mach/clkdev.h b/arch/arm/mach-s5p64x0/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 0305e9b8282d..cd248e681377 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -31,7 +31,6 @@
31 31
32static struct clk s5p_clk_otgphy = { 32static struct clk s5p_clk_otgphy = {
33 .name = "otg_phy", 33 .name = "otg_phy",
34 .id = -1,
35}; 34};
36 35
37static struct clk *clk_src_mout_href_list[] = { 36static struct clk *clk_src_mout_href_list[] = {
@@ -47,7 +46,6 @@ static struct clksrc_sources clk_src_mout_href = {
47static struct clksrc_clk clk_mout_href = { 46static struct clksrc_clk clk_mout_href = {
48 .clk = { 47 .clk = {
49 .name = "mout_href", 48 .name = "mout_href",
50 .id = -1,
51 }, 49 },
52 .sources = &clk_src_mout_href, 50 .sources = &clk_src_mout_href,
53 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, 51 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@@ -66,7 +64,6 @@ static struct clksrc_sources clk_src_mout_48m = {
66static struct clksrc_clk clk_mout_48m = { 64static struct clksrc_clk clk_mout_48m = {
67 .clk = { 65 .clk = {
68 .name = "mout_48m", 66 .name = "mout_48m",
69 .id = -1,
70 }, 67 },
71 .sources = &clk_src_mout_48m, 68 .sources = &clk_src_mout_48m,
72 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 }, 69 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
@@ -75,7 +72,6 @@ static struct clksrc_clk clk_mout_48m = {
75static struct clksrc_clk clk_mout_mpll = { 72static struct clksrc_clk clk_mout_mpll = {
76 .clk = { 73 .clk = {
77 .name = "mout_mpll", 74 .name = "mout_mpll",
78 .id = -1,
79 }, 75 },
80 .sources = &clk_src_mpll, 76 .sources = &clk_src_mpll,
81 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, 77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@@ -85,7 +81,6 @@ static struct clksrc_clk clk_mout_mpll = {
85static struct clksrc_clk clk_mout_apll = { 81static struct clksrc_clk clk_mout_apll = {
86 .clk = { 82 .clk = {
87 .name = "mout_apll", 83 .name = "mout_apll",
88 .id = -1,
89 }, 84 },
90 .sources = &clk_src_apll, 85 .sources = &clk_src_apll,
91 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, 86 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@@ -94,7 +89,6 @@ static struct clksrc_clk clk_mout_apll = {
94static struct clksrc_clk clk_mout_epll = { 89static struct clksrc_clk clk_mout_epll = {
95 .clk = { 90 .clk = {
96 .name = "mout_epll", 91 .name = "mout_epll",
97 .id = -1,
98 }, 92 },
99 .sources = &clk_src_epll, 93 .sources = &clk_src_epll,
100 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, 94 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@@ -112,7 +106,6 @@ static struct clksrc_sources clk_src_mout_hpll = {
112static struct clksrc_clk clk_mout_hpll = { 106static struct clksrc_clk clk_mout_hpll = {
113 .clk = { 107 .clk = {
114 .name = "mout_hpll", 108 .name = "mout_hpll",
115 .id = -1,
116 }, 109 },
117 .sources = &clk_src_mout_hpll, 110 .sources = &clk_src_mout_hpll,
118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, 111 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@@ -121,7 +114,6 @@ static struct clksrc_clk clk_mout_hpll = {
121static struct clksrc_clk clk_div_apll = { 114static struct clksrc_clk clk_div_apll = {
122 .clk = { 115 .clk = {
123 .name = "div_apll", 116 .name = "div_apll",
124 .id = -1,
125 .parent = &clk_mout_apll.clk, 117 .parent = &clk_mout_apll.clk,
126 }, 118 },
127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 }, 119 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
@@ -130,7 +122,6 @@ static struct clksrc_clk clk_div_apll = {
130static struct clksrc_clk clk_div_arm = { 122static struct clksrc_clk clk_div_arm = {
131 .clk = { 123 .clk = {
132 .name = "div_arm", 124 .name = "div_arm",
133 .id = -1,
134 .parent = &clk_div_apll.clk, 125 .parent = &clk_div_apll.clk,
135 }, 126 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, 127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@@ -139,7 +130,6 @@ static struct clksrc_clk clk_div_arm = {
139static struct clksrc_clk clk_div_d0_bus = { 130static struct clksrc_clk clk_div_d0_bus = {
140 .clk = { 131 .clk = {
141 .name = "div_d0_bus", 132 .name = "div_d0_bus",
142 .id = -1,
143 .parent = &clk_div_arm.clk, 133 .parent = &clk_div_arm.clk,
144 }, 134 },
145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, 135 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@@ -148,7 +138,6 @@ static struct clksrc_clk clk_div_d0_bus = {
148static struct clksrc_clk clk_div_pclkd0 = { 138static struct clksrc_clk clk_div_pclkd0 = {
149 .clk = { 139 .clk = {
150 .name = "div_pclkd0", 140 .name = "div_pclkd0",
151 .id = -1,
152 .parent = &clk_div_d0_bus.clk, 141 .parent = &clk_div_d0_bus.clk,
153 }, 142 },
154 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, 143 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@@ -157,7 +146,6 @@ static struct clksrc_clk clk_div_pclkd0 = {
157static struct clksrc_clk clk_div_secss = { 146static struct clksrc_clk clk_div_secss = {
158 .clk = { 147 .clk = {
159 .name = "div_secss", 148 .name = "div_secss",
160 .id = -1,
161 .parent = &clk_div_d0_bus.clk, 149 .parent = &clk_div_d0_bus.clk,
162 }, 150 },
163 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 }, 151 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
@@ -166,7 +154,6 @@ static struct clksrc_clk clk_div_secss = {
166static struct clksrc_clk clk_div_apll2 = { 154static struct clksrc_clk clk_div_apll2 = {
167 .clk = { 155 .clk = {
168 .name = "div_apll2", 156 .name = "div_apll2",
169 .id = -1,
170 .parent = &clk_mout_apll.clk, 157 .parent = &clk_mout_apll.clk,
171 }, 158 },
172 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 }, 159 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
@@ -185,7 +172,6 @@ struct clksrc_sources clk_src_mout_am = {
185static struct clksrc_clk clk_mout_am = { 172static struct clksrc_clk clk_mout_am = {
186 .clk = { 173 .clk = {
187 .name = "mout_am", 174 .name = "mout_am",
188 .id = -1,
189 }, 175 },
190 .sources = &clk_src_mout_am, 176 .sources = &clk_src_mout_am,
191 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, 177 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@@ -194,7 +180,6 @@ static struct clksrc_clk clk_mout_am = {
194static struct clksrc_clk clk_div_d1_bus = { 180static struct clksrc_clk clk_div_d1_bus = {
195 .clk = { 181 .clk = {
196 .name = "div_d1_bus", 182 .name = "div_d1_bus",
197 .id = -1,
198 .parent = &clk_mout_am.clk, 183 .parent = &clk_mout_am.clk,
199 }, 184 },
200 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 }, 185 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
@@ -203,7 +188,6 @@ static struct clksrc_clk clk_div_d1_bus = {
203static struct clksrc_clk clk_div_mpll2 = { 188static struct clksrc_clk clk_div_mpll2 = {
204 .clk = { 189 .clk = {
205 .name = "div_mpll2", 190 .name = "div_mpll2",
206 .id = -1,
207 .parent = &clk_mout_am.clk, 191 .parent = &clk_mout_am.clk,
208 }, 192 },
209 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 }, 193 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
@@ -212,7 +196,6 @@ static struct clksrc_clk clk_div_mpll2 = {
212static struct clksrc_clk clk_div_mpll = { 196static struct clksrc_clk clk_div_mpll = {
213 .clk = { 197 .clk = {
214 .name = "div_mpll", 198 .name = "div_mpll",
215 .id = -1,
216 .parent = &clk_mout_am.clk, 199 .parent = &clk_mout_am.clk,
217 }, 200 },
218 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 }, 201 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
@@ -231,7 +214,6 @@ struct clksrc_sources clk_src_mout_onenand = {
231static struct clksrc_clk clk_mout_onenand = { 214static struct clksrc_clk clk_mout_onenand = {
232 .clk = { 215 .clk = {
233 .name = "mout_onenand", 216 .name = "mout_onenand",
234 .id = -1,
235 }, 217 },
236 .sources = &clk_src_mout_onenand, 218 .sources = &clk_src_mout_onenand,
237 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, 219 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@@ -240,7 +222,6 @@ static struct clksrc_clk clk_mout_onenand = {
240static struct clksrc_clk clk_div_onenand = { 222static struct clksrc_clk clk_div_onenand = {
241 .clk = { 223 .clk = {
242 .name = "div_onenand", 224 .name = "div_onenand",
243 .id = -1,
244 .parent = &clk_mout_onenand.clk, 225 .parent = &clk_mout_onenand.clk,
245 }, 226 },
246 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 }, 227 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
@@ -249,7 +230,6 @@ static struct clksrc_clk clk_div_onenand = {
249static struct clksrc_clk clk_div_pclkd1 = { 230static struct clksrc_clk clk_div_pclkd1 = {
250 .clk = { 231 .clk = {
251 .name = "div_pclkd1", 232 .name = "div_pclkd1",
252 .id = -1,
253 .parent = &clk_div_d1_bus.clk, 233 .parent = &clk_div_d1_bus.clk,
254 }, 234 },
255 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 }, 235 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
@@ -258,7 +238,6 @@ static struct clksrc_clk clk_div_pclkd1 = {
258static struct clksrc_clk clk_div_cam = { 238static struct clksrc_clk clk_div_cam = {
259 .clk = { 239 .clk = {
260 .name = "div_cam", 240 .name = "div_cam",
261 .id = -1,
262 .parent = &clk_div_mpll2.clk, 241 .parent = &clk_div_mpll2.clk,
263 }, 242 },
264 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 }, 243 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
@@ -267,7 +246,6 @@ static struct clksrc_clk clk_div_cam = {
267static struct clksrc_clk clk_div_hdmi = { 246static struct clksrc_clk clk_div_hdmi = {
268 .clk = { 247 .clk = {
269 .name = "div_hdmi", 248 .name = "div_hdmi",
270 .id = -1,
271 .parent = &clk_mout_hpll.clk, 249 .parent = &clk_mout_hpll.clk,
272 }, 250 },
273 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, 251 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
@@ -399,367 +377,329 @@ static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
399static struct clk init_clocks_off[] = { 377static struct clk init_clocks_off[] = {
400 { 378 {
401 .name = "cssys", 379 .name = "cssys",
402 .id = -1,
403 .parent = &clk_div_d0_bus.clk, 380 .parent = &clk_div_d0_bus.clk,
404 .enable = s5pc100_d0_0_ctrl, 381 .enable = s5pc100_d0_0_ctrl,
405 .ctrlbit = (1 << 6), 382 .ctrlbit = (1 << 6),
406 }, { 383 }, {
407 .name = "secss", 384 .name = "secss",
408 .id = -1,
409 .parent = &clk_div_d0_bus.clk, 385 .parent = &clk_div_d0_bus.clk,
410 .enable = s5pc100_d0_0_ctrl, 386 .enable = s5pc100_d0_0_ctrl,
411 .ctrlbit = (1 << 5), 387 .ctrlbit = (1 << 5),
412 }, { 388 }, {
413 .name = "g2d", 389 .name = "g2d",
414 .id = -1,
415 .parent = &clk_div_d0_bus.clk, 390 .parent = &clk_div_d0_bus.clk,
416 .enable = s5pc100_d0_0_ctrl, 391 .enable = s5pc100_d0_0_ctrl,
417 .ctrlbit = (1 << 4), 392 .ctrlbit = (1 << 4),
418 }, { 393 }, {
419 .name = "mdma", 394 .name = "mdma",
420 .id = -1,
421 .parent = &clk_div_d0_bus.clk, 395 .parent = &clk_div_d0_bus.clk,
422 .enable = s5pc100_d0_0_ctrl, 396 .enable = s5pc100_d0_0_ctrl,
423 .ctrlbit = (1 << 3), 397 .ctrlbit = (1 << 3),
424 }, { 398 }, {
425 .name = "cfcon", 399 .name = "cfcon",
426 .id = -1,
427 .parent = &clk_div_d0_bus.clk, 400 .parent = &clk_div_d0_bus.clk,
428 .enable = s5pc100_d0_0_ctrl, 401 .enable = s5pc100_d0_0_ctrl,
429 .ctrlbit = (1 << 2), 402 .ctrlbit = (1 << 2),
430 }, { 403 }, {
431 .name = "nfcon", 404 .name = "nfcon",
432 .id = -1,
433 .parent = &clk_div_d0_bus.clk, 405 .parent = &clk_div_d0_bus.clk,
434 .enable = s5pc100_d0_1_ctrl, 406 .enable = s5pc100_d0_1_ctrl,
435 .ctrlbit = (1 << 3), 407 .ctrlbit = (1 << 3),
436 }, { 408 }, {
437 .name = "onenandc", 409 .name = "onenandc",
438 .id = -1,
439 .parent = &clk_div_d0_bus.clk, 410 .parent = &clk_div_d0_bus.clk,
440 .enable = s5pc100_d0_1_ctrl, 411 .enable = s5pc100_d0_1_ctrl,
441 .ctrlbit = (1 << 2), 412 .ctrlbit = (1 << 2),
442 }, { 413 }, {
443 .name = "sdm", 414 .name = "sdm",
444 .id = -1,
445 .parent = &clk_div_d0_bus.clk, 415 .parent = &clk_div_d0_bus.clk,
446 .enable = s5pc100_d0_2_ctrl, 416 .enable = s5pc100_d0_2_ctrl,
447 .ctrlbit = (1 << 2), 417 .ctrlbit = (1 << 2),
448 }, { 418 }, {
449 .name = "seckey", 419 .name = "seckey",
450 .id = -1,
451 .parent = &clk_div_d0_bus.clk, 420 .parent = &clk_div_d0_bus.clk,
452 .enable = s5pc100_d0_2_ctrl, 421 .enable = s5pc100_d0_2_ctrl,
453 .ctrlbit = (1 << 1), 422 .ctrlbit = (1 << 1),
454 }, { 423 }, {
455 .name = "hsmmc", 424 .name = "hsmmc",
456 .id = 2, 425 .devname = "s3c-sdhci.2",
457 .parent = &clk_div_d1_bus.clk, 426 .parent = &clk_div_d1_bus.clk,
458 .enable = s5pc100_d1_0_ctrl, 427 .enable = s5pc100_d1_0_ctrl,
459 .ctrlbit = (1 << 7), 428 .ctrlbit = (1 << 7),
460 }, { 429 }, {
461 .name = "hsmmc", 430 .name = "hsmmc",
462 .id = 1, 431 .devname = "s3c-sdhci.1",
463 .parent = &clk_div_d1_bus.clk, 432 .parent = &clk_div_d1_bus.clk,
464 .enable = s5pc100_d1_0_ctrl, 433 .enable = s5pc100_d1_0_ctrl,
465 .ctrlbit = (1 << 6), 434 .ctrlbit = (1 << 6),
466 }, { 435 }, {
467 .name = "hsmmc", 436 .name = "hsmmc",
468 .id = 0, 437 .devname = "s3c-sdhci.0",
469 .parent = &clk_div_d1_bus.clk, 438 .parent = &clk_div_d1_bus.clk,
470 .enable = s5pc100_d1_0_ctrl, 439 .enable = s5pc100_d1_0_ctrl,
471 .ctrlbit = (1 << 5), 440 .ctrlbit = (1 << 5),
472 }, { 441 }, {
473 .name = "modemif", 442 .name = "modemif",
474 .id = -1,
475 .parent = &clk_div_d1_bus.clk, 443 .parent = &clk_div_d1_bus.clk,
476 .enable = s5pc100_d1_0_ctrl, 444 .enable = s5pc100_d1_0_ctrl,
477 .ctrlbit = (1 << 4), 445 .ctrlbit = (1 << 4),
478 }, { 446 }, {
479 .name = "otg", 447 .name = "otg",
480 .id = -1,
481 .parent = &clk_div_d1_bus.clk, 448 .parent = &clk_div_d1_bus.clk,
482 .enable = s5pc100_d1_0_ctrl, 449 .enable = s5pc100_d1_0_ctrl,
483 .ctrlbit = (1 << 3), 450 .ctrlbit = (1 << 3),
484 }, { 451 }, {
485 .name = "usbhost", 452 .name = "usbhost",
486 .id = -1,
487 .parent = &clk_div_d1_bus.clk, 453 .parent = &clk_div_d1_bus.clk,
488 .enable = s5pc100_d1_0_ctrl, 454 .enable = s5pc100_d1_0_ctrl,
489 .ctrlbit = (1 << 2), 455 .ctrlbit = (1 << 2),
490 }, { 456 }, {
491 .name = "pdma", 457 .name = "pdma",
492 .id = 1, 458 .devname = "s3c-pl330.1",
493 .parent = &clk_div_d1_bus.clk, 459 .parent = &clk_div_d1_bus.clk,
494 .enable = s5pc100_d1_0_ctrl, 460 .enable = s5pc100_d1_0_ctrl,
495 .ctrlbit = (1 << 1), 461 .ctrlbit = (1 << 1),
496 }, { 462 }, {
497 .name = "pdma", 463 .name = "pdma",
498 .id = 0, 464 .devname = "s3c-pl330.0",
499 .parent = &clk_div_d1_bus.clk, 465 .parent = &clk_div_d1_bus.clk,
500 .enable = s5pc100_d1_0_ctrl, 466 .enable = s5pc100_d1_0_ctrl,
501 .ctrlbit = (1 << 0), 467 .ctrlbit = (1 << 0),
502 }, { 468 }, {
503 .name = "lcd", 469 .name = "lcd",
504 .id = -1,
505 .parent = &clk_div_d1_bus.clk, 470 .parent = &clk_div_d1_bus.clk,
506 .enable = s5pc100_d1_1_ctrl, 471 .enable = s5pc100_d1_1_ctrl,
507 .ctrlbit = (1 << 0), 472 .ctrlbit = (1 << 0),
508 }, { 473 }, {
509 .name = "rotator", 474 .name = "rotator",
510 .id = -1,
511 .parent = &clk_div_d1_bus.clk, 475 .parent = &clk_div_d1_bus.clk,
512 .enable = s5pc100_d1_1_ctrl, 476 .enable = s5pc100_d1_1_ctrl,
513 .ctrlbit = (1 << 1), 477 .ctrlbit = (1 << 1),
514 }, { 478 }, {
515 .name = "fimc", 479 .name = "fimc",
516 .id = 0, 480 .devname = "s5p-fimc.0",
517 .parent = &clk_div_d1_bus.clk, 481 .parent = &clk_div_d1_bus.clk,
518 .enable = s5pc100_d1_1_ctrl, 482 .enable = s5pc100_d1_1_ctrl,
519 .ctrlbit = (1 << 2), 483 .ctrlbit = (1 << 2),
520 }, { 484 }, {
521 .name = "fimc", 485 .name = "fimc",
522 .id = 1, 486 .devname = "s5p-fimc.1",
523 .parent = &clk_div_d1_bus.clk, 487 .parent = &clk_div_d1_bus.clk,
524 .enable = s5pc100_d1_1_ctrl, 488 .enable = s5pc100_d1_1_ctrl,
525 .ctrlbit = (1 << 3), 489 .ctrlbit = (1 << 3),
526 }, { 490 }, {
527 .name = "fimc", 491 .name = "fimc",
528 .id = 2, 492 .devname = "s5p-fimc.2",
529 .parent = &clk_div_d1_bus.clk,
530 .enable = s5pc100_d1_1_ctrl, 493 .enable = s5pc100_d1_1_ctrl,
531 .ctrlbit = (1 << 4), 494 .ctrlbit = (1 << 4),
532 }, { 495 }, {
533 .name = "jpeg", 496 .name = "jpeg",
534 .id = -1,
535 .parent = &clk_div_d1_bus.clk, 497 .parent = &clk_div_d1_bus.clk,
536 .enable = s5pc100_d1_1_ctrl, 498 .enable = s5pc100_d1_1_ctrl,
537 .ctrlbit = (1 << 5), 499 .ctrlbit = (1 << 5),
538 }, { 500 }, {
539 .name = "mipi-dsim", 501 .name = "mipi-dsim",
540 .id = -1,
541 .parent = &clk_div_d1_bus.clk, 502 .parent = &clk_div_d1_bus.clk,
542 .enable = s5pc100_d1_1_ctrl, 503 .enable = s5pc100_d1_1_ctrl,
543 .ctrlbit = (1 << 6), 504 .ctrlbit = (1 << 6),
544 }, { 505 }, {
545 .name = "mipi-csis", 506 .name = "mipi-csis",
546 .id = -1,
547 .parent = &clk_div_d1_bus.clk, 507 .parent = &clk_div_d1_bus.clk,
548 .enable = s5pc100_d1_1_ctrl, 508 .enable = s5pc100_d1_1_ctrl,
549 .ctrlbit = (1 << 7), 509 .ctrlbit = (1 << 7),
550 }, { 510 }, {
551 .name = "g3d", 511 .name = "g3d",
552 .id = 0,
553 .parent = &clk_div_d1_bus.clk, 512 .parent = &clk_div_d1_bus.clk,
554 .enable = s5pc100_d1_0_ctrl, 513 .enable = s5pc100_d1_0_ctrl,
555 .ctrlbit = (1 << 8), 514 .ctrlbit = (1 << 8),
556 }, { 515 }, {
557 .name = "tv", 516 .name = "tv",
558 .id = -1,
559 .parent = &clk_div_d1_bus.clk, 517 .parent = &clk_div_d1_bus.clk,
560 .enable = s5pc100_d1_2_ctrl, 518 .enable = s5pc100_d1_2_ctrl,
561 .ctrlbit = (1 << 0), 519 .ctrlbit = (1 << 0),
562 }, { 520 }, {
563 .name = "vp", 521 .name = "vp",
564 .id = -1,
565 .parent = &clk_div_d1_bus.clk, 522 .parent = &clk_div_d1_bus.clk,
566 .enable = s5pc100_d1_2_ctrl, 523 .enable = s5pc100_d1_2_ctrl,
567 .ctrlbit = (1 << 1), 524 .ctrlbit = (1 << 1),
568 }, { 525 }, {
569 .name = "mixer", 526 .name = "mixer",
570 .id = -1,
571 .parent = &clk_div_d1_bus.clk, 527 .parent = &clk_div_d1_bus.clk,
572 .enable = s5pc100_d1_2_ctrl, 528 .enable = s5pc100_d1_2_ctrl,
573 .ctrlbit = (1 << 2), 529 .ctrlbit = (1 << 2),
574 }, { 530 }, {
575 .name = "hdmi", 531 .name = "hdmi",
576 .id = -1,
577 .parent = &clk_div_d1_bus.clk, 532 .parent = &clk_div_d1_bus.clk,
578 .enable = s5pc100_d1_2_ctrl, 533 .enable = s5pc100_d1_2_ctrl,
579 .ctrlbit = (1 << 3), 534 .ctrlbit = (1 << 3),
580 }, { 535 }, {
581 .name = "mfc", 536 .name = "mfc",
582 .id = -1,
583 .parent = &clk_div_d1_bus.clk, 537 .parent = &clk_div_d1_bus.clk,
584 .enable = s5pc100_d1_2_ctrl, 538 .enable = s5pc100_d1_2_ctrl,
585 .ctrlbit = (1 << 4), 539 .ctrlbit = (1 << 4),
586 }, { 540 }, {
587 .name = "apc", 541 .name = "apc",
588 .id = -1,
589 .parent = &clk_div_d1_bus.clk, 542 .parent = &clk_div_d1_bus.clk,
590 .enable = s5pc100_d1_3_ctrl, 543 .enable = s5pc100_d1_3_ctrl,
591 .ctrlbit = (1 << 2), 544 .ctrlbit = (1 << 2),
592 }, { 545 }, {
593 .name = "iec", 546 .name = "iec",
594 .id = -1,
595 .parent = &clk_div_d1_bus.clk, 547 .parent = &clk_div_d1_bus.clk,
596 .enable = s5pc100_d1_3_ctrl, 548 .enable = s5pc100_d1_3_ctrl,
597 .ctrlbit = (1 << 3), 549 .ctrlbit = (1 << 3),
598 }, { 550 }, {
599 .name = "systimer", 551 .name = "systimer",
600 .id = -1,
601 .parent = &clk_div_d1_bus.clk, 552 .parent = &clk_div_d1_bus.clk,
602 .enable = s5pc100_d1_3_ctrl, 553 .enable = s5pc100_d1_3_ctrl,
603 .ctrlbit = (1 << 7), 554 .ctrlbit = (1 << 7),
604 }, { 555 }, {
605 .name = "watchdog", 556 .name = "watchdog",
606 .id = -1,
607 .parent = &clk_div_d1_bus.clk, 557 .parent = &clk_div_d1_bus.clk,
608 .enable = s5pc100_d1_3_ctrl, 558 .enable = s5pc100_d1_3_ctrl,
609 .ctrlbit = (1 << 8), 559 .ctrlbit = (1 << 8),
610 }, { 560 }, {
611 .name = "rtc", 561 .name = "rtc",
612 .id = -1,
613 .parent = &clk_div_d1_bus.clk, 562 .parent = &clk_div_d1_bus.clk,
614 .enable = s5pc100_d1_3_ctrl, 563 .enable = s5pc100_d1_3_ctrl,
615 .ctrlbit = (1 << 9), 564 .ctrlbit = (1 << 9),
616 }, { 565 }, {
617 .name = "i2c", 566 .name = "i2c",
618 .id = 0, 567 .devname = "s3c2440-i2c.0",
619 .parent = &clk_div_d1_bus.clk, 568 .parent = &clk_div_d1_bus.clk,
620 .enable = s5pc100_d1_4_ctrl, 569 .enable = s5pc100_d1_4_ctrl,
621 .ctrlbit = (1 << 4), 570 .ctrlbit = (1 << 4),
622 }, { 571 }, {
623 .name = "i2c", 572 .name = "i2c",
624 .id = 1, 573 .devname = "s3c2440-i2c.1",
625 .parent = &clk_div_d1_bus.clk, 574 .parent = &clk_div_d1_bus.clk,
626 .enable = s5pc100_d1_4_ctrl, 575 .enable = s5pc100_d1_4_ctrl,
627 .ctrlbit = (1 << 5), 576 .ctrlbit = (1 << 5),
628 }, { 577 }, {
629 .name = "spi", 578 .name = "spi",
630 .id = 0, 579 .devname = "s3c64xx-spi.0",
631 .parent = &clk_div_d1_bus.clk, 580 .parent = &clk_div_d1_bus.clk,
632 .enable = s5pc100_d1_4_ctrl, 581 .enable = s5pc100_d1_4_ctrl,
633 .ctrlbit = (1 << 6), 582 .ctrlbit = (1 << 6),
634 }, { 583 }, {
635 .name = "spi", 584 .name = "spi",
636 .id = 1, 585 .devname = "s3c64xx-spi.1",
637 .parent = &clk_div_d1_bus.clk, 586 .parent = &clk_div_d1_bus.clk,
638 .enable = s5pc100_d1_4_ctrl, 587 .enable = s5pc100_d1_4_ctrl,
639 .ctrlbit = (1 << 7), 588 .ctrlbit = (1 << 7),
640 }, { 589 }, {
641 .name = "spi", 590 .name = "spi",
642 .id = 2, 591 .devname = "s3c64xx-spi.2",
643 .parent = &clk_div_d1_bus.clk, 592 .parent = &clk_div_d1_bus.clk,
644 .enable = s5pc100_d1_4_ctrl, 593 .enable = s5pc100_d1_4_ctrl,
645 .ctrlbit = (1 << 8), 594 .ctrlbit = (1 << 8),
646 }, { 595 }, {
647 .name = "irda", 596 .name = "irda",
648 .id = -1,
649 .parent = &clk_div_d1_bus.clk, 597 .parent = &clk_div_d1_bus.clk,
650 .enable = s5pc100_d1_4_ctrl, 598 .enable = s5pc100_d1_4_ctrl,
651 .ctrlbit = (1 << 9), 599 .ctrlbit = (1 << 9),
652 }, { 600 }, {
653 .name = "ccan", 601 .name = "ccan",
654 .id = 0,
655 .parent = &clk_div_d1_bus.clk, 602 .parent = &clk_div_d1_bus.clk,
656 .enable = s5pc100_d1_4_ctrl, 603 .enable = s5pc100_d1_4_ctrl,
657 .ctrlbit = (1 << 10), 604 .ctrlbit = (1 << 10),
658 }, { 605 }, {
659 .name = "ccan", 606 .name = "ccan",
660 .id = 1,
661 .parent = &clk_div_d1_bus.clk, 607 .parent = &clk_div_d1_bus.clk,
662 .enable = s5pc100_d1_4_ctrl, 608 .enable = s5pc100_d1_4_ctrl,
663 .ctrlbit = (1 << 11), 609 .ctrlbit = (1 << 11),
664 }, { 610 }, {
665 .name = "hsitx", 611 .name = "hsitx",
666 .id = -1,
667 .parent = &clk_div_d1_bus.clk, 612 .parent = &clk_div_d1_bus.clk,
668 .enable = s5pc100_d1_4_ctrl, 613 .enable = s5pc100_d1_4_ctrl,
669 .ctrlbit = (1 << 12), 614 .ctrlbit = (1 << 12),
670 }, { 615 }, {
671 .name = "hsirx", 616 .name = "hsirx",
672 .id = -1,
673 .parent = &clk_div_d1_bus.clk, 617 .parent = &clk_div_d1_bus.clk,
674 .enable = s5pc100_d1_4_ctrl, 618 .enable = s5pc100_d1_4_ctrl,
675 .ctrlbit = (1 << 13), 619 .ctrlbit = (1 << 13),
676 }, { 620 }, {
677 .name = "iis", 621 .name = "iis",
678 .id = 0, 622 .devname = "samsung-i2s.0",
679 .parent = &clk_div_pclkd1.clk, 623 .parent = &clk_div_pclkd1.clk,
680 .enable = s5pc100_d1_5_ctrl, 624 .enable = s5pc100_d1_5_ctrl,
681 .ctrlbit = (1 << 0), 625 .ctrlbit = (1 << 0),
682 }, { 626 }, {
683 .name = "iis", 627 .name = "iis",
684 .id = 1, 628 .devname = "samsung-i2s.1",
685 .parent = &clk_div_pclkd1.clk, 629 .parent = &clk_div_pclkd1.clk,
686 .enable = s5pc100_d1_5_ctrl, 630 .enable = s5pc100_d1_5_ctrl,
687 .ctrlbit = (1 << 1), 631 .ctrlbit = (1 << 1),
688 }, { 632 }, {
689 .name = "iis", 633 .name = "iis",
690 .id = 2, 634 .devname = "samsung-i2s.2",
691 .parent = &clk_div_pclkd1.clk, 635 .parent = &clk_div_pclkd1.clk,
692 .enable = s5pc100_d1_5_ctrl, 636 .enable = s5pc100_d1_5_ctrl,
693 .ctrlbit = (1 << 2), 637 .ctrlbit = (1 << 2),
694 }, { 638 }, {
695 .name = "ac97", 639 .name = "ac97",
696 .id = -1,
697 .parent = &clk_div_pclkd1.clk, 640 .parent = &clk_div_pclkd1.clk,
698 .enable = s5pc100_d1_5_ctrl, 641 .enable = s5pc100_d1_5_ctrl,
699 .ctrlbit = (1 << 3), 642 .ctrlbit = (1 << 3),
700 }, { 643 }, {
701 .name = "pcm", 644 .name = "pcm",
702 .id = 0, 645 .devname = "samsung-pcm.0",
703 .parent = &clk_div_pclkd1.clk, 646 .parent = &clk_div_pclkd1.clk,
704 .enable = s5pc100_d1_5_ctrl, 647 .enable = s5pc100_d1_5_ctrl,
705 .ctrlbit = (1 << 4), 648 .ctrlbit = (1 << 4),
706 }, { 649 }, {
707 .name = "pcm", 650 .name = "pcm",
708 .id = 1, 651 .devname = "samsung-pcm.1",
709 .parent = &clk_div_pclkd1.clk, 652 .parent = &clk_div_pclkd1.clk,
710 .enable = s5pc100_d1_5_ctrl, 653 .enable = s5pc100_d1_5_ctrl,
711 .ctrlbit = (1 << 5), 654 .ctrlbit = (1 << 5),
712 }, { 655 }, {
713 .name = "spdif", 656 .name = "spdif",
714 .id = -1,
715 .parent = &clk_div_pclkd1.clk, 657 .parent = &clk_div_pclkd1.clk,
716 .enable = s5pc100_d1_5_ctrl, 658 .enable = s5pc100_d1_5_ctrl,
717 .ctrlbit = (1 << 6), 659 .ctrlbit = (1 << 6),
718 }, { 660 }, {
719 .name = "adc", 661 .name = "adc",
720 .id = -1,
721 .parent = &clk_div_pclkd1.clk, 662 .parent = &clk_div_pclkd1.clk,
722 .enable = s5pc100_d1_5_ctrl, 663 .enable = s5pc100_d1_5_ctrl,
723 .ctrlbit = (1 << 7), 664 .ctrlbit = (1 << 7),
724 }, { 665 }, {
725 .name = "keypad", 666 .name = "keypad",
726 .id = -1,
727 .parent = &clk_div_pclkd1.clk, 667 .parent = &clk_div_pclkd1.clk,
728 .enable = s5pc100_d1_5_ctrl, 668 .enable = s5pc100_d1_5_ctrl,
729 .ctrlbit = (1 << 8), 669 .ctrlbit = (1 << 8),
730 }, { 670 }, {
731 .name = "spi_48m", 671 .name = "spi_48m",
732 .id = 0, 672 .devname = "s3c64xx-spi.0",
733 .parent = &clk_mout_48m.clk, 673 .parent = &clk_mout_48m.clk,
734 .enable = s5pc100_sclk0_ctrl, 674 .enable = s5pc100_sclk0_ctrl,
735 .ctrlbit = (1 << 7), 675 .ctrlbit = (1 << 7),
736 }, { 676 }, {
737 .name = "spi_48m", 677 .name = "spi_48m",
738 .id = 1, 678 .devname = "s3c64xx-spi.1",
739 .parent = &clk_mout_48m.clk, 679 .parent = &clk_mout_48m.clk,
740 .enable = s5pc100_sclk0_ctrl, 680 .enable = s5pc100_sclk0_ctrl,
741 .ctrlbit = (1 << 8), 681 .ctrlbit = (1 << 8),
742 }, { 682 }, {
743 .name = "spi_48m", 683 .name = "spi_48m",
744 .id = 2, 684 .devname = "s3c64xx-spi.2",
745 .parent = &clk_mout_48m.clk, 685 .parent = &clk_mout_48m.clk,
746 .enable = s5pc100_sclk0_ctrl, 686 .enable = s5pc100_sclk0_ctrl,
747 .ctrlbit = (1 << 9), 687 .ctrlbit = (1 << 9),
748 }, { 688 }, {
749 .name = "mmc_48m", 689 .name = "mmc_48m",
750 .id = 0, 690 .devname = "s3c-sdhci.0",
751 .parent = &clk_mout_48m.clk, 691 .parent = &clk_mout_48m.clk,
752 .enable = s5pc100_sclk0_ctrl, 692 .enable = s5pc100_sclk0_ctrl,
753 .ctrlbit = (1 << 15), 693 .ctrlbit = (1 << 15),
754 }, { 694 }, {
755 .name = "mmc_48m", 695 .name = "mmc_48m",
756 .id = 1, 696 .devname = "s3c-sdhci.1",
757 .parent = &clk_mout_48m.clk, 697 .parent = &clk_mout_48m.clk,
758 .enable = s5pc100_sclk0_ctrl, 698 .enable = s5pc100_sclk0_ctrl,
759 .ctrlbit = (1 << 16), 699 .ctrlbit = (1 << 16),
760 }, { 700 }, {
761 .name = "mmc_48m", 701 .name = "mmc_48m",
762 .id = 2, 702 .devname = "s3c-sdhci.2",
763 .parent = &clk_mout_48m.clk, 703 .parent = &clk_mout_48m.clk,
764 .enable = s5pc100_sclk0_ctrl, 704 .enable = s5pc100_sclk0_ctrl,
765 .ctrlbit = (1 << 17), 705 .ctrlbit = (1 << 17),
@@ -768,33 +708,27 @@ static struct clk init_clocks_off[] = {
768 708
769static struct clk clk_vclk54m = { 709static struct clk clk_vclk54m = {
770 .name = "vclk_54m", 710 .name = "vclk_54m",
771 .id = -1,
772 .rate = 54000000, 711 .rate = 54000000,
773}; 712};
774 713
775static struct clk clk_i2scdclk0 = { 714static struct clk clk_i2scdclk0 = {
776 .name = "i2s_cdclk0", 715 .name = "i2s_cdclk0",
777 .id = -1,
778}; 716};
779 717
780static struct clk clk_i2scdclk1 = { 718static struct clk clk_i2scdclk1 = {
781 .name = "i2s_cdclk1", 719 .name = "i2s_cdclk1",
782 .id = -1,
783}; 720};
784 721
785static struct clk clk_i2scdclk2 = { 722static struct clk clk_i2scdclk2 = {
786 .name = "i2s_cdclk2", 723 .name = "i2s_cdclk2",
787 .id = -1,
788}; 724};
789 725
790static struct clk clk_pcmcdclk0 = { 726static struct clk clk_pcmcdclk0 = {
791 .name = "pcm_cdclk0", 727 .name = "pcm_cdclk0",
792 .id = -1,
793}; 728};
794 729
795static struct clk clk_pcmcdclk1 = { 730static struct clk clk_pcmcdclk1 = {
796 .name = "pcm_cdclk1", 731 .name = "pcm_cdclk1",
797 .id = -1,
798}; 732};
799 733
800static struct clk *clk_src_group1_list[] = { 734static struct clk *clk_src_group1_list[] = {
@@ -836,7 +770,7 @@ struct clksrc_sources clk_src_group3 = {
836static struct clksrc_clk clk_sclk_audio0 = { 770static struct clksrc_clk clk_sclk_audio0 = {
837 .clk = { 771 .clk = {
838 .name = "sclk_audio", 772 .name = "sclk_audio",
839 .id = 0, 773 .devname = "samsung-pcm.0",
840 .ctrlbit = (1 << 8), 774 .ctrlbit = (1 << 8),
841 .enable = s5pc100_sclk1_ctrl, 775 .enable = s5pc100_sclk1_ctrl,
842 }, 776 },
@@ -862,7 +796,7 @@ struct clksrc_sources clk_src_group4 = {
862static struct clksrc_clk clk_sclk_audio1 = { 796static struct clksrc_clk clk_sclk_audio1 = {
863 .clk = { 797 .clk = {
864 .name = "sclk_audio", 798 .name = "sclk_audio",
865 .id = 1, 799 .devname = "samsung-pcm.1",
866 .ctrlbit = (1 << 9), 800 .ctrlbit = (1 << 9),
867 .enable = s5pc100_sclk1_ctrl, 801 .enable = s5pc100_sclk1_ctrl,
868 }, 802 },
@@ -887,7 +821,7 @@ struct clksrc_sources clk_src_group5 = {
887static struct clksrc_clk clk_sclk_audio2 = { 821static struct clksrc_clk clk_sclk_audio2 = {
888 .clk = { 822 .clk = {
889 .name = "sclk_audio", 823 .name = "sclk_audio",
890 .id = 2, 824 .devname = "samsung-pcm.2",
891 .ctrlbit = (1 << 10), 825 .ctrlbit = (1 << 10),
892 .enable = s5pc100_sclk1_ctrl, 826 .enable = s5pc100_sclk1_ctrl,
893 }, 827 },
@@ -1014,7 +948,6 @@ static struct clk_ops s5pc100_sclk_spdif_ops = {
1014static struct clksrc_clk clk_sclk_spdif = { 948static struct clksrc_clk clk_sclk_spdif = {
1015 .clk = { 949 .clk = {
1016 .name = "sclk_spdif", 950 .name = "sclk_spdif",
1017 .id = -1,
1018 .ctrlbit = (1 << 11), 951 .ctrlbit = (1 << 11),
1019 .enable = s5pc100_sclk1_ctrl, 952 .enable = s5pc100_sclk1_ctrl,
1020 .ops = &s5pc100_sclk_spdif_ops, 953 .ops = &s5pc100_sclk_spdif_ops,
@@ -1027,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
1027 { 960 {
1028 .clk = { 961 .clk = {
1029 .name = "sclk_spi", 962 .name = "sclk_spi",
1030 .id = 0, 963 .devname = "s3c64xx-spi.0",
1031 .ctrlbit = (1 << 4), 964 .ctrlbit = (1 << 4),
1032 .enable = s5pc100_sclk0_ctrl, 965 .enable = s5pc100_sclk0_ctrl,
1033 966
@@ -1038,7 +971,7 @@ static struct clksrc_clk clksrcs[] = {
1038 }, { 971 }, {
1039 .clk = { 972 .clk = {
1040 .name = "sclk_spi", 973 .name = "sclk_spi",
1041 .id = 1, 974 .devname = "s3c64xx-spi.1",
1042 .ctrlbit = (1 << 5), 975 .ctrlbit = (1 << 5),
1043 .enable = s5pc100_sclk0_ctrl, 976 .enable = s5pc100_sclk0_ctrl,
1044 977
@@ -1049,7 +982,7 @@ static struct clksrc_clk clksrcs[] = {
1049 }, { 982 }, {
1050 .clk = { 983 .clk = {
1051 .name = "sclk_spi", 984 .name = "sclk_spi",
1052 .id = 2, 985 .devname = "s3c64xx-spi.2",
1053 .ctrlbit = (1 << 6), 986 .ctrlbit = (1 << 6),
1054 .enable = s5pc100_sclk0_ctrl, 987 .enable = s5pc100_sclk0_ctrl,
1055 988
@@ -1060,7 +993,6 @@ static struct clksrc_clk clksrcs[] = {
1060 }, { 993 }, {
1061 .clk = { 994 .clk = {
1062 .name = "uclk1", 995 .name = "uclk1",
1063 .id = -1,
1064 .ctrlbit = (1 << 3), 996 .ctrlbit = (1 << 3),
1065 .enable = s5pc100_sclk0_ctrl, 997 .enable = s5pc100_sclk0_ctrl,
1066 998
@@ -1071,7 +1003,6 @@ static struct clksrc_clk clksrcs[] = {
1071 }, { 1003 }, {
1072 .clk = { 1004 .clk = {
1073 .name = "sclk_mixer", 1005 .name = "sclk_mixer",
1074 .id = -1,
1075 .ctrlbit = (1 << 6), 1006 .ctrlbit = (1 << 6),
1076 .enable = s5pc100_sclk0_ctrl, 1007 .enable = s5pc100_sclk0_ctrl,
1077 1008
@@ -1081,7 +1012,6 @@ static struct clksrc_clk clksrcs[] = {
1081 }, { 1012 }, {
1082 .clk = { 1013 .clk = {
1083 .name = "sclk_lcd", 1014 .name = "sclk_lcd",
1084 .id = -1,
1085 .ctrlbit = (1 << 0), 1015 .ctrlbit = (1 << 0),
1086 .enable = s5pc100_sclk1_ctrl, 1016 .enable = s5pc100_sclk1_ctrl,
1087 1017
@@ -1092,7 +1022,7 @@ static struct clksrc_clk clksrcs[] = {
1092 }, { 1022 }, {
1093 .clk = { 1023 .clk = {
1094 .name = "sclk_fimc", 1024 .name = "sclk_fimc",
1095 .id = 0, 1025 .devname = "s5p-fimc.0",
1096 .ctrlbit = (1 << 1), 1026 .ctrlbit = (1 << 1),
1097 .enable = s5pc100_sclk1_ctrl, 1027 .enable = s5pc100_sclk1_ctrl,
1098 1028
@@ -1103,7 +1033,7 @@ static struct clksrc_clk clksrcs[] = {
1103 }, { 1033 }, {
1104 .clk = { 1034 .clk = {
1105 .name = "sclk_fimc", 1035 .name = "sclk_fimc",
1106 .id = 1, 1036 .devname = "s5p-fimc.1",
1107 .ctrlbit = (1 << 2), 1037 .ctrlbit = (1 << 2),
1108 .enable = s5pc100_sclk1_ctrl, 1038 .enable = s5pc100_sclk1_ctrl,
1109 1039
@@ -1114,7 +1044,7 @@ static struct clksrc_clk clksrcs[] = {
1114 }, { 1044 }, {
1115 .clk = { 1045 .clk = {
1116 .name = "sclk_fimc", 1046 .name = "sclk_fimc",
1117 .id = 2, 1047 .devname = "s5p-fimc.2",
1118 .ctrlbit = (1 << 3), 1048 .ctrlbit = (1 << 3),
1119 .enable = s5pc100_sclk1_ctrl, 1049 .enable = s5pc100_sclk1_ctrl,
1120 1050
@@ -1125,7 +1055,7 @@ static struct clksrc_clk clksrcs[] = {
1125 }, { 1055 }, {
1126 .clk = { 1056 .clk = {
1127 .name = "sclk_mmc", 1057 .name = "sclk_mmc",
1128 .id = 0, 1058 .devname = "s3c-sdhci.0",
1129 .ctrlbit = (1 << 12), 1059 .ctrlbit = (1 << 12),
1130 .enable = s5pc100_sclk1_ctrl, 1060 .enable = s5pc100_sclk1_ctrl,
1131 1061
@@ -1136,7 +1066,7 @@ static struct clksrc_clk clksrcs[] = {
1136 }, { 1066 }, {
1137 .clk = { 1067 .clk = {
1138 .name = "sclk_mmc", 1068 .name = "sclk_mmc",
1139 .id = 1, 1069 .devname = "s3c-sdhci.1",
1140 .ctrlbit = (1 << 13), 1070 .ctrlbit = (1 << 13),
1141 .enable = s5pc100_sclk1_ctrl, 1071 .enable = s5pc100_sclk1_ctrl,
1142 1072
@@ -1147,7 +1077,7 @@ static struct clksrc_clk clksrcs[] = {
1147 }, { 1077 }, {
1148 .clk = { 1078 .clk = {
1149 .name = "sclk_mmc", 1079 .name = "sclk_mmc",
1150 .id = 2, 1080 .devname = "s3c-sdhci.2",
1151 .ctrlbit = (1 << 14), 1081 .ctrlbit = (1 << 14),
1152 .enable = s5pc100_sclk1_ctrl, 1082 .enable = s5pc100_sclk1_ctrl,
1153 1083
@@ -1158,7 +1088,6 @@ static struct clksrc_clk clksrcs[] = {
1158 }, { 1088 }, {
1159 .clk = { 1089 .clk = {
1160 .name = "sclk_irda", 1090 .name = "sclk_irda",
1161 .id = 2,
1162 .ctrlbit = (1 << 10), 1091 .ctrlbit = (1 << 10),
1163 .enable = s5pc100_sclk0_ctrl, 1092 .enable = s5pc100_sclk0_ctrl,
1164 1093
@@ -1169,7 +1098,6 @@ static struct clksrc_clk clksrcs[] = {
1169 }, { 1098 }, {
1170 .clk = { 1099 .clk = {
1171 .name = "sclk_irda", 1100 .name = "sclk_irda",
1172 .id = -1,
1173 .ctrlbit = (1 << 10), 1101 .ctrlbit = (1 << 10),
1174 .enable = s5pc100_sclk0_ctrl, 1102 .enable = s5pc100_sclk0_ctrl,
1175 1103
@@ -1180,7 +1108,6 @@ static struct clksrc_clk clksrcs[] = {
1180 }, { 1108 }, {
1181 .clk = { 1109 .clk = {
1182 .name = "sclk_pwi", 1110 .name = "sclk_pwi",
1183 .id = -1,
1184 .ctrlbit = (1 << 1), 1111 .ctrlbit = (1 << 1),
1185 .enable = s5pc100_sclk0_ctrl, 1112 .enable = s5pc100_sclk0_ctrl,
1186 1113
@@ -1191,7 +1118,6 @@ static struct clksrc_clk clksrcs[] = {
1191 }, { 1118 }, {
1192 .clk = { 1119 .clk = {
1193 .name = "sclk_uhost", 1120 .name = "sclk_uhost",
1194 .id = -1,
1195 .ctrlbit = (1 << 11), 1121 .ctrlbit = (1 << 11),
1196 .enable = s5pc100_sclk0_ctrl, 1122 .enable = s5pc100_sclk0_ctrl,
1197 1123
@@ -1291,79 +1217,70 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
1291static struct clk init_clocks[] = { 1217static struct clk init_clocks[] = {
1292 { 1218 {
1293 .name = "tzic", 1219 .name = "tzic",
1294 .id = -1,
1295 .parent = &clk_div_d0_bus.clk, 1220 .parent = &clk_div_d0_bus.clk,
1296 .enable = s5pc100_d0_0_ctrl, 1221 .enable = s5pc100_d0_0_ctrl,
1297 .ctrlbit = (1 << 1), 1222 .ctrlbit = (1 << 1),
1298 }, { 1223 }, {
1299 .name = "intc", 1224 .name = "intc",
1300 .id = -1,
1301 .parent = &clk_div_d0_bus.clk, 1225 .parent = &clk_div_d0_bus.clk,
1302 .enable = s5pc100_d0_0_ctrl, 1226 .enable = s5pc100_d0_0_ctrl,
1303 .ctrlbit = (1 << 0), 1227 .ctrlbit = (1 << 0),
1304 }, { 1228 }, {
1305 .name = "ebi", 1229 .name = "ebi",
1306 .id = -1,
1307 .parent = &clk_div_d0_bus.clk, 1230 .parent = &clk_div_d0_bus.clk,
1308 .enable = s5pc100_d0_1_ctrl, 1231 .enable = s5pc100_d0_1_ctrl,
1309 .ctrlbit = (1 << 5), 1232 .ctrlbit = (1 << 5),
1310 }, { 1233 }, {
1311 .name = "intmem", 1234 .name = "intmem",
1312 .id = -1,
1313 .parent = &clk_div_d0_bus.clk, 1235 .parent = &clk_div_d0_bus.clk,
1314 .enable = s5pc100_d0_1_ctrl, 1236 .enable = s5pc100_d0_1_ctrl,
1315 .ctrlbit = (1 << 4), 1237 .ctrlbit = (1 << 4),
1316 }, { 1238 }, {
1317 .name = "sromc", 1239 .name = "sromc",
1318 .id = -1,
1319 .parent = &clk_div_d0_bus.clk, 1240 .parent = &clk_div_d0_bus.clk,
1320 .enable = s5pc100_d0_1_ctrl, 1241 .enable = s5pc100_d0_1_ctrl,
1321 .ctrlbit = (1 << 1), 1242 .ctrlbit = (1 << 1),
1322 }, { 1243 }, {
1323 .name = "dmc", 1244 .name = "dmc",
1324 .id = -1,
1325 .parent = &clk_div_d0_bus.clk, 1245 .parent = &clk_div_d0_bus.clk,
1326 .enable = s5pc100_d0_1_ctrl, 1246 .enable = s5pc100_d0_1_ctrl,
1327 .ctrlbit = (1 << 0), 1247 .ctrlbit = (1 << 0),
1328 }, { 1248 }, {
1329 .name = "chipid", 1249 .name = "chipid",
1330 .id = -1,
1331 .parent = &clk_div_d0_bus.clk, 1250 .parent = &clk_div_d0_bus.clk,
1332 .enable = s5pc100_d0_1_ctrl, 1251 .enable = s5pc100_d0_1_ctrl,
1333 .ctrlbit = (1 << 0), 1252 .ctrlbit = (1 << 0),
1334 }, { 1253 }, {
1335 .name = "gpio", 1254 .name = "gpio",
1336 .id = -1,
1337 .parent = &clk_div_d1_bus.clk, 1255 .parent = &clk_div_d1_bus.clk,
1338 .enable = s5pc100_d1_3_ctrl, 1256 .enable = s5pc100_d1_3_ctrl,
1339 .ctrlbit = (1 << 1), 1257 .ctrlbit = (1 << 1),
1340 }, { 1258 }, {
1341 .name = "uart", 1259 .name = "uart",
1342 .id = 0, 1260 .devname = "s3c6400-uart.0",
1343 .parent = &clk_div_d1_bus.clk, 1261 .parent = &clk_div_d1_bus.clk,
1344 .enable = s5pc100_d1_4_ctrl, 1262 .enable = s5pc100_d1_4_ctrl,
1345 .ctrlbit = (1 << 0), 1263 .ctrlbit = (1 << 0),
1346 }, { 1264 }, {
1347 .name = "uart", 1265 .name = "uart",
1348 .id = 1, 1266 .devname = "s3c6400-uart.1",
1349 .parent = &clk_div_d1_bus.clk, 1267 .parent = &clk_div_d1_bus.clk,
1350 .enable = s5pc100_d1_4_ctrl, 1268 .enable = s5pc100_d1_4_ctrl,
1351 .ctrlbit = (1 << 1), 1269 .ctrlbit = (1 << 1),
1352 }, { 1270 }, {
1353 .name = "uart", 1271 .name = "uart",
1354 .id = 2, 1272 .devname = "s3c6400-uart.2",
1355 .parent = &clk_div_d1_bus.clk, 1273 .parent = &clk_div_d1_bus.clk,
1356 .enable = s5pc100_d1_4_ctrl, 1274 .enable = s5pc100_d1_4_ctrl,
1357 .ctrlbit = (1 << 2), 1275 .ctrlbit = (1 << 2),
1358 }, { 1276 }, {
1359 .name = "uart", 1277 .name = "uart",
1360 .id = 3, 1278 .devname = "s3c6400-uart.3",
1361 .parent = &clk_div_d1_bus.clk, 1279 .parent = &clk_div_d1_bus.clk,
1362 .enable = s5pc100_d1_4_ctrl, 1280 .enable = s5pc100_d1_4_ctrl,
1363 .ctrlbit = (1 << 3), 1281 .ctrlbit = (1 << 3),
1364 }, { 1282 }, {
1365 .name = "timers", 1283 .name = "timers",
1366 .id = -1,
1367 .parent = &clk_div_d1_bus.clk, 1284 .parent = &clk_div_d1_bus.clk,
1368 .enable = s5pc100_d1_3_ctrl, 1285 .enable = s5pc100_d1_3_ctrl,
1369 .ctrlbit = (1 << 6), 1286 .ctrlbit = (1 << 6),
diff --git a/arch/arm/mach-s5pc100/include/mach/clkdev.h b/arch/arm/mach-s5pc100/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 2d599499cefe..b5c95e663c53 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -36,7 +36,6 @@ static unsigned long xtal;
36static struct clksrc_clk clk_mout_apll = { 36static struct clksrc_clk clk_mout_apll = {
37 .clk = { 37 .clk = {
38 .name = "mout_apll", 38 .name = "mout_apll",
39 .id = -1,
40 }, 39 },
41 .sources = &clk_src_apll, 40 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, 41 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@@ -45,7 +44,6 @@ static struct clksrc_clk clk_mout_apll = {
45static struct clksrc_clk clk_mout_epll = { 44static struct clksrc_clk clk_mout_epll = {
46 .clk = { 45 .clk = {
47 .name = "mout_epll", 46 .name = "mout_epll",
48 .id = -1,
49 }, 47 },
50 .sources = &clk_src_epll, 48 .sources = &clk_src_epll,
51 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, 49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@@ -54,7 +52,6 @@ static struct clksrc_clk clk_mout_epll = {
54static struct clksrc_clk clk_mout_mpll = { 52static struct clksrc_clk clk_mout_mpll = {
55 .clk = { 53 .clk = {
56 .name = "mout_mpll", 54 .name = "mout_mpll",
57 .id = -1,
58 }, 55 },
59 .sources = &clk_src_mpll, 56 .sources = &clk_src_mpll,
60 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, 57 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@@ -73,7 +70,6 @@ static struct clksrc_sources clkset_armclk = {
73static struct clksrc_clk clk_armclk = { 70static struct clksrc_clk clk_armclk = {
74 .clk = { 71 .clk = {
75 .name = "armclk", 72 .name = "armclk",
76 .id = -1,
77 }, 73 },
78 .sources = &clkset_armclk, 74 .sources = &clkset_armclk,
79 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, 75 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@@ -83,7 +79,6 @@ static struct clksrc_clk clk_armclk = {
83static struct clksrc_clk clk_hclk_msys = { 79static struct clksrc_clk clk_hclk_msys = {
84 .clk = { 80 .clk = {
85 .name = "hclk_msys", 81 .name = "hclk_msys",
86 .id = -1,
87 .parent = &clk_armclk.clk, 82 .parent = &clk_armclk.clk,
88 }, 83 },
89 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, 84 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@@ -92,7 +87,6 @@ static struct clksrc_clk clk_hclk_msys = {
92static struct clksrc_clk clk_pclk_msys = { 87static struct clksrc_clk clk_pclk_msys = {
93 .clk = { 88 .clk = {
94 .name = "pclk_msys", 89 .name = "pclk_msys",
95 .id = -1,
96 .parent = &clk_hclk_msys.clk, 90 .parent = &clk_hclk_msys.clk,
97 }, 91 },
98 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, 92 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@@ -101,7 +95,6 @@ static struct clksrc_clk clk_pclk_msys = {
101static struct clksrc_clk clk_sclk_a2m = { 95static struct clksrc_clk clk_sclk_a2m = {
102 .clk = { 96 .clk = {
103 .name = "sclk_a2m", 97 .name = "sclk_a2m",
104 .id = -1,
105 .parent = &clk_mout_apll.clk, 98 .parent = &clk_mout_apll.clk,
106 }, 99 },
107 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, 100 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@@ -120,7 +113,6 @@ static struct clksrc_sources clkset_hclk_sys = {
120static struct clksrc_clk clk_hclk_dsys = { 113static struct clksrc_clk clk_hclk_dsys = {
121 .clk = { 114 .clk = {
122 .name = "hclk_dsys", 115 .name = "hclk_dsys",
123 .id = -1,
124 }, 116 },
125 .sources = &clkset_hclk_sys, 117 .sources = &clkset_hclk_sys,
126 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, 118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@@ -130,7 +122,6 @@ static struct clksrc_clk clk_hclk_dsys = {
130static struct clksrc_clk clk_pclk_dsys = { 122static struct clksrc_clk clk_pclk_dsys = {
131 .clk = { 123 .clk = {
132 .name = "pclk_dsys", 124 .name = "pclk_dsys",
133 .id = -1,
134 .parent = &clk_hclk_dsys.clk, 125 .parent = &clk_hclk_dsys.clk,
135 }, 126 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, 127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
@@ -139,7 +130,6 @@ static struct clksrc_clk clk_pclk_dsys = {
139static struct clksrc_clk clk_hclk_psys = { 130static struct clksrc_clk clk_hclk_psys = {
140 .clk = { 131 .clk = {
141 .name = "hclk_psys", 132 .name = "hclk_psys",
142 .id = -1,
143 }, 133 },
144 .sources = &clkset_hclk_sys, 134 .sources = &clkset_hclk_sys,
145 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, 135 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@@ -149,7 +139,6 @@ static struct clksrc_clk clk_hclk_psys = {
149static struct clksrc_clk clk_pclk_psys = { 139static struct clksrc_clk clk_pclk_psys = {
150 .clk = { 140 .clk = {
151 .name = "pclk_psys", 141 .name = "pclk_psys",
152 .id = -1,
153 .parent = &clk_hclk_psys.clk, 142 .parent = &clk_hclk_psys.clk,
154 }, 143 },
155 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, 144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
@@ -187,38 +176,31 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
187 176
188static struct clk clk_sclk_hdmi27m = { 177static struct clk clk_sclk_hdmi27m = {
189 .name = "sclk_hdmi27m", 178 .name = "sclk_hdmi27m",
190 .id = -1,
191 .rate = 27000000, 179 .rate = 27000000,
192}; 180};
193 181
194static struct clk clk_sclk_hdmiphy = { 182static struct clk clk_sclk_hdmiphy = {
195 .name = "sclk_hdmiphy", 183 .name = "sclk_hdmiphy",
196 .id = -1,
197}; 184};
198 185
199static struct clk clk_sclk_usbphy0 = { 186static struct clk clk_sclk_usbphy0 = {
200 .name = "sclk_usbphy0", 187 .name = "sclk_usbphy0",
201 .id = -1,
202}; 188};
203 189
204static struct clk clk_sclk_usbphy1 = { 190static struct clk clk_sclk_usbphy1 = {
205 .name = "sclk_usbphy1", 191 .name = "sclk_usbphy1",
206 .id = -1,
207}; 192};
208 193
209static struct clk clk_pcmcdclk0 = { 194static struct clk clk_pcmcdclk0 = {
210 .name = "pcmcdclk", 195 .name = "pcmcdclk",
211 .id = -1,
212}; 196};
213 197
214static struct clk clk_pcmcdclk1 = { 198static struct clk clk_pcmcdclk1 = {
215 .name = "pcmcdclk", 199 .name = "pcmcdclk",
216 .id = -1,
217}; 200};
218 201
219static struct clk clk_pcmcdclk2 = { 202static struct clk clk_pcmcdclk2 = {
220 .name = "pcmcdclk", 203 .name = "pcmcdclk",
221 .id = -1,
222}; 204};
223 205
224static struct clk *clkset_vpllsrc_list[] = { 206static struct clk *clkset_vpllsrc_list[] = {
@@ -234,7 +216,6 @@ static struct clksrc_sources clkset_vpllsrc = {
234static struct clksrc_clk clk_vpllsrc = { 216static struct clksrc_clk clk_vpllsrc = {
235 .clk = { 217 .clk = {
236 .name = "vpll_src", 218 .name = "vpll_src",
237 .id = -1,
238 .enable = s5pv210_clk_mask0_ctrl, 219 .enable = s5pv210_clk_mask0_ctrl,
239 .ctrlbit = (1 << 7), 220 .ctrlbit = (1 << 7),
240 }, 221 },
@@ -255,7 +236,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
255static struct clksrc_clk clk_sclk_vpll = { 236static struct clksrc_clk clk_sclk_vpll = {
256 .clk = { 237 .clk = {
257 .name = "sclk_vpll", 238 .name = "sclk_vpll",
258 .id = -1,
259 }, 239 },
260 .sources = &clkset_sclk_vpll, 240 .sources = &clkset_sclk_vpll,
261 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, 241 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@@ -276,7 +256,6 @@ static struct clksrc_sources clkset_moutdmc0src = {
276static struct clksrc_clk clk_mout_dmc0 = { 256static struct clksrc_clk clk_mout_dmc0 = {
277 .clk = { 257 .clk = {
278 .name = "mout_dmc0", 258 .name = "mout_dmc0",
279 .id = -1,
280 }, 259 },
281 .sources = &clkset_moutdmc0src, 260 .sources = &clkset_moutdmc0src,
282 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, 261 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@@ -285,7 +264,6 @@ static struct clksrc_clk clk_mout_dmc0 = {
285static struct clksrc_clk clk_sclk_dmc0 = { 264static struct clksrc_clk clk_sclk_dmc0 = {
286 .clk = { 265 .clk = {
287 .name = "sclk_dmc0", 266 .name = "sclk_dmc0",
288 .id = -1,
289 .parent = &clk_mout_dmc0.clk, 267 .parent = &clk_mout_dmc0.clk,
290 }, 268 },
291 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, 269 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
@@ -312,181 +290,169 @@ static struct clk_ops clk_fout_apll_ops = {
312static struct clk init_clocks_off[] = { 290static struct clk init_clocks_off[] = {
313 { 291 {
314 .name = "pdma", 292 .name = "pdma",
315 .id = 0, 293 .devname = "s3c-pl330.0",
316 .parent = &clk_hclk_psys.clk, 294 .parent = &clk_hclk_psys.clk,
317 .enable = s5pv210_clk_ip0_ctrl, 295 .enable = s5pv210_clk_ip0_ctrl,
318 .ctrlbit = (1 << 3), 296 .ctrlbit = (1 << 3),
319 }, { 297 }, {
320 .name = "pdma", 298 .name = "pdma",
321 .id = 1, 299 .devname = "s3c-pl330.1",
322 .parent = &clk_hclk_psys.clk, 300 .parent = &clk_hclk_psys.clk,
323 .enable = s5pv210_clk_ip0_ctrl, 301 .enable = s5pv210_clk_ip0_ctrl,
324 .ctrlbit = (1 << 4), 302 .ctrlbit = (1 << 4),
325 }, { 303 }, {
326 .name = "rot", 304 .name = "rot",
327 .id = -1,
328 .parent = &clk_hclk_dsys.clk, 305 .parent = &clk_hclk_dsys.clk,
329 .enable = s5pv210_clk_ip0_ctrl, 306 .enable = s5pv210_clk_ip0_ctrl,
330 .ctrlbit = (1<<29), 307 .ctrlbit = (1<<29),
331 }, { 308 }, {
332 .name = "fimc", 309 .name = "fimc",
333 .id = 0, 310 .devname = "s5pv210-fimc.0",
334 .parent = &clk_hclk_dsys.clk, 311 .parent = &clk_hclk_dsys.clk,
335 .enable = s5pv210_clk_ip0_ctrl, 312 .enable = s5pv210_clk_ip0_ctrl,
336 .ctrlbit = (1 << 24), 313 .ctrlbit = (1 << 24),
337 }, { 314 }, {
338 .name = "fimc", 315 .name = "fimc",
339 .id = 1, 316 .devname = "s5pv210-fimc.1",
340 .parent = &clk_hclk_dsys.clk, 317 .parent = &clk_hclk_dsys.clk,
341 .enable = s5pv210_clk_ip0_ctrl, 318 .enable = s5pv210_clk_ip0_ctrl,
342 .ctrlbit = (1 << 25), 319 .ctrlbit = (1 << 25),
343 }, { 320 }, {
344 .name = "fimc", 321 .name = "fimc",
345 .id = 2, 322 .devname = "s5pv210-fimc.2",
346 .parent = &clk_hclk_dsys.clk, 323 .parent = &clk_hclk_dsys.clk,
347 .enable = s5pv210_clk_ip0_ctrl, 324 .enable = s5pv210_clk_ip0_ctrl,
348 .ctrlbit = (1 << 26), 325 .ctrlbit = (1 << 26),
349 }, { 326 }, {
350 .name = "otg", 327 .name = "otg",
351 .id = -1,
352 .parent = &clk_hclk_psys.clk, 328 .parent = &clk_hclk_psys.clk,
353 .enable = s5pv210_clk_ip1_ctrl, 329 .enable = s5pv210_clk_ip1_ctrl,
354 .ctrlbit = (1<<16), 330 .ctrlbit = (1<<16),
355 }, { 331 }, {
356 .name = "usb-host", 332 .name = "usb-host",
357 .id = -1,
358 .parent = &clk_hclk_psys.clk, 333 .parent = &clk_hclk_psys.clk,
359 .enable = s5pv210_clk_ip1_ctrl, 334 .enable = s5pv210_clk_ip1_ctrl,
360 .ctrlbit = (1<<17), 335 .ctrlbit = (1<<17),
361 }, { 336 }, {
362 .name = "lcd", 337 .name = "lcd",
363 .id = -1,
364 .parent = &clk_hclk_dsys.clk, 338 .parent = &clk_hclk_dsys.clk,
365 .enable = s5pv210_clk_ip1_ctrl, 339 .enable = s5pv210_clk_ip1_ctrl,
366 .ctrlbit = (1<<0), 340 .ctrlbit = (1<<0),
367 }, { 341 }, {
368 .name = "cfcon", 342 .name = "cfcon",
369 .id = 0,
370 .parent = &clk_hclk_psys.clk, 343 .parent = &clk_hclk_psys.clk,
371 .enable = s5pv210_clk_ip1_ctrl, 344 .enable = s5pv210_clk_ip1_ctrl,
372 .ctrlbit = (1<<25), 345 .ctrlbit = (1<<25),
373 }, { 346 }, {
374 .name = "hsmmc", 347 .name = "hsmmc",
375 .id = 0, 348 .devname = "s3c-sdhci.0",
376 .parent = &clk_hclk_psys.clk, 349 .parent = &clk_hclk_psys.clk,
377 .enable = s5pv210_clk_ip2_ctrl, 350 .enable = s5pv210_clk_ip2_ctrl,
378 .ctrlbit = (1<<16), 351 .ctrlbit = (1<<16),
379 }, { 352 }, {
380 .name = "hsmmc", 353 .name = "hsmmc",
381 .id = 1, 354 .devname = "s3c-sdhci.1",
382 .parent = &clk_hclk_psys.clk, 355 .parent = &clk_hclk_psys.clk,
383 .enable = s5pv210_clk_ip2_ctrl, 356 .enable = s5pv210_clk_ip2_ctrl,
384 .ctrlbit = (1<<17), 357 .ctrlbit = (1<<17),
385 }, { 358 }, {
386 .name = "hsmmc", 359 .name = "hsmmc",
387 .id = 2, 360 .devname = "s3c-sdhci.2",
388 .parent = &clk_hclk_psys.clk, 361 .parent = &clk_hclk_psys.clk,
389 .enable = s5pv210_clk_ip2_ctrl, 362 .enable = s5pv210_clk_ip2_ctrl,
390 .ctrlbit = (1<<18), 363 .ctrlbit = (1<<18),
391 }, { 364 }, {
392 .name = "hsmmc", 365 .name = "hsmmc",
393 .id = 3, 366 .devname = "s3c-sdhci.3",
394 .parent = &clk_hclk_psys.clk, 367 .parent = &clk_hclk_psys.clk,
395 .enable = s5pv210_clk_ip2_ctrl, 368 .enable = s5pv210_clk_ip2_ctrl,
396 .ctrlbit = (1<<19), 369 .ctrlbit = (1<<19),
397 }, { 370 }, {
398 .name = "systimer", 371 .name = "systimer",
399 .id = -1,
400 .parent = &clk_pclk_psys.clk, 372 .parent = &clk_pclk_psys.clk,
401 .enable = s5pv210_clk_ip3_ctrl, 373 .enable = s5pv210_clk_ip3_ctrl,
402 .ctrlbit = (1<<16), 374 .ctrlbit = (1<<16),
403 }, { 375 }, {
404 .name = "watchdog", 376 .name = "watchdog",
405 .id = -1,
406 .parent = &clk_pclk_psys.clk, 377 .parent = &clk_pclk_psys.clk,
407 .enable = s5pv210_clk_ip3_ctrl, 378 .enable = s5pv210_clk_ip3_ctrl,
408 .ctrlbit = (1<<22), 379 .ctrlbit = (1<<22),
409 }, { 380 }, {
410 .name = "rtc", 381 .name = "rtc",
411 .id = -1,
412 .parent = &clk_pclk_psys.clk, 382 .parent = &clk_pclk_psys.clk,
413 .enable = s5pv210_clk_ip3_ctrl, 383 .enable = s5pv210_clk_ip3_ctrl,
414 .ctrlbit = (1<<15), 384 .ctrlbit = (1<<15),
415 }, { 385 }, {
416 .name = "i2c", 386 .name = "i2c",
417 .id = 0, 387 .devname = "s3c2440-i2c.0",
418 .parent = &clk_pclk_psys.clk, 388 .parent = &clk_pclk_psys.clk,
419 .enable = s5pv210_clk_ip3_ctrl, 389 .enable = s5pv210_clk_ip3_ctrl,
420 .ctrlbit = (1<<7), 390 .ctrlbit = (1<<7),
421 }, { 391 }, {
422 .name = "i2c", 392 .name = "i2c",
423 .id = 1, 393 .devname = "s3c2440-i2c.1",
424 .parent = &clk_pclk_psys.clk, 394 .parent = &clk_pclk_psys.clk,
425 .enable = s5pv210_clk_ip3_ctrl, 395 .enable = s5pv210_clk_ip3_ctrl,
426 .ctrlbit = (1 << 10), 396 .ctrlbit = (1 << 10),
427 }, { 397 }, {
428 .name = "i2c", 398 .name = "i2c",
429 .id = 2, 399 .devname = "s3c2440-i2c.2",
430 .parent = &clk_pclk_psys.clk, 400 .parent = &clk_pclk_psys.clk,
431 .enable = s5pv210_clk_ip3_ctrl, 401 .enable = s5pv210_clk_ip3_ctrl,
432 .ctrlbit = (1<<9), 402 .ctrlbit = (1<<9),
433 }, { 403 }, {
434 .name = "spi", 404 .name = "spi",
435 .id = 0, 405 .devname = "s3c64xx-spi.0",
436 .parent = &clk_pclk_psys.clk, 406 .parent = &clk_pclk_psys.clk,
437 .enable = s5pv210_clk_ip3_ctrl, 407 .enable = s5pv210_clk_ip3_ctrl,
438 .ctrlbit = (1<<12), 408 .ctrlbit = (1<<12),
439 }, { 409 }, {
440 .name = "spi", 410 .name = "spi",
441 .id = 1, 411 .devname = "s3c64xx-spi.1",
442 .parent = &clk_pclk_psys.clk, 412 .parent = &clk_pclk_psys.clk,
443 .enable = s5pv210_clk_ip3_ctrl, 413 .enable = s5pv210_clk_ip3_ctrl,
444 .ctrlbit = (1<<13), 414 .ctrlbit = (1<<13),
445 }, { 415 }, {
446 .name = "spi", 416 .name = "spi",
447 .id = 2, 417 .devname = "s3c64xx-spi.2",
448 .parent = &clk_pclk_psys.clk, 418 .parent = &clk_pclk_psys.clk,
449 .enable = s5pv210_clk_ip3_ctrl, 419 .enable = s5pv210_clk_ip3_ctrl,
450 .ctrlbit = (1<<14), 420 .ctrlbit = (1<<14),
451 }, { 421 }, {
452 .name = "timers", 422 .name = "timers",
453 .id = -1,
454 .parent = &clk_pclk_psys.clk, 423 .parent = &clk_pclk_psys.clk,
455 .enable = s5pv210_clk_ip3_ctrl, 424 .enable = s5pv210_clk_ip3_ctrl,
456 .ctrlbit = (1<<23), 425 .ctrlbit = (1<<23),
457 }, { 426 }, {
458 .name = "adc", 427 .name = "adc",
459 .id = -1,
460 .parent = &clk_pclk_psys.clk, 428 .parent = &clk_pclk_psys.clk,
461 .enable = s5pv210_clk_ip3_ctrl, 429 .enable = s5pv210_clk_ip3_ctrl,
462 .ctrlbit = (1<<24), 430 .ctrlbit = (1<<24),
463 }, { 431 }, {
464 .name = "keypad", 432 .name = "keypad",
465 .id = -1,
466 .parent = &clk_pclk_psys.clk, 433 .parent = &clk_pclk_psys.clk,
467 .enable = s5pv210_clk_ip3_ctrl, 434 .enable = s5pv210_clk_ip3_ctrl,
468 .ctrlbit = (1<<21), 435 .ctrlbit = (1<<21),
469 }, { 436 }, {
470 .name = "iis", 437 .name = "iis",
471 .id = 0, 438 .devname = "samsung-i2s.0",
472 .parent = &clk_p, 439 .parent = &clk_p,
473 .enable = s5pv210_clk_ip3_ctrl, 440 .enable = s5pv210_clk_ip3_ctrl,
474 .ctrlbit = (1<<4), 441 .ctrlbit = (1<<4),
475 }, { 442 }, {
476 .name = "iis", 443 .name = "iis",
477 .id = 1, 444 .devname = "samsung-i2s.1",
478 .parent = &clk_p, 445 .parent = &clk_p,
479 .enable = s5pv210_clk_ip3_ctrl, 446 .enable = s5pv210_clk_ip3_ctrl,
480 .ctrlbit = (1 << 5), 447 .ctrlbit = (1 << 5),
481 }, { 448 }, {
482 .name = "iis", 449 .name = "iis",
483 .id = 2, 450 .devname = "samsung-i2s.2",
484 .parent = &clk_p, 451 .parent = &clk_p,
485 .enable = s5pv210_clk_ip3_ctrl, 452 .enable = s5pv210_clk_ip3_ctrl,
486 .ctrlbit = (1 << 6), 453 .ctrlbit = (1 << 6),
487 }, { 454 }, {
488 .name = "spdif", 455 .name = "spdif",
489 .id = -1,
490 .parent = &clk_p, 456 .parent = &clk_p,
491 .enable = s5pv210_clk_ip3_ctrl, 457 .enable = s5pv210_clk_ip3_ctrl,
492 .ctrlbit = (1 << 0), 458 .ctrlbit = (1 << 0),
@@ -496,38 +462,36 @@ static struct clk init_clocks_off[] = {
496static struct clk init_clocks[] = { 462static struct clk init_clocks[] = {
497 { 463 {
498 .name = "hclk_imem", 464 .name = "hclk_imem",
499 .id = -1,
500 .parent = &clk_hclk_msys.clk, 465 .parent = &clk_hclk_msys.clk,
501 .ctrlbit = (1 << 5), 466 .ctrlbit = (1 << 5),
502 .enable = s5pv210_clk_ip0_ctrl, 467 .enable = s5pv210_clk_ip0_ctrl,
503 .ops = &clk_hclk_imem_ops, 468 .ops = &clk_hclk_imem_ops,
504 }, { 469 }, {
505 .name = "uart", 470 .name = "uart",
506 .id = 0, 471 .devname = "s5pv210-uart.0",
507 .parent = &clk_pclk_psys.clk, 472 .parent = &clk_pclk_psys.clk,
508 .enable = s5pv210_clk_ip3_ctrl, 473 .enable = s5pv210_clk_ip3_ctrl,
509 .ctrlbit = (1 << 17), 474 .ctrlbit = (1 << 17),
510 }, { 475 }, {
511 .name = "uart", 476 .name = "uart",
512 .id = 1, 477 .devname = "s5pv210-uart.1",
513 .parent = &clk_pclk_psys.clk, 478 .parent = &clk_pclk_psys.clk,
514 .enable = s5pv210_clk_ip3_ctrl, 479 .enable = s5pv210_clk_ip3_ctrl,
515 .ctrlbit = (1 << 18), 480 .ctrlbit = (1 << 18),
516 }, { 481 }, {
517 .name = "uart", 482 .name = "uart",
518 .id = 2, 483 .devname = "s5pv210-uart.2",
519 .parent = &clk_pclk_psys.clk, 484 .parent = &clk_pclk_psys.clk,
520 .enable = s5pv210_clk_ip3_ctrl, 485 .enable = s5pv210_clk_ip3_ctrl,
521 .ctrlbit = (1 << 19), 486 .ctrlbit = (1 << 19),
522 }, { 487 }, {
523 .name = "uart", 488 .name = "uart",
524 .id = 3, 489 .devname = "s5pv210-uart.3",
525 .parent = &clk_pclk_psys.clk, 490 .parent = &clk_pclk_psys.clk,
526 .enable = s5pv210_clk_ip3_ctrl, 491 .enable = s5pv210_clk_ip3_ctrl,
527 .ctrlbit = (1 << 20), 492 .ctrlbit = (1 << 20),
528 }, { 493 }, {
529 .name = "sromc", 494 .name = "sromc",
530 .id = -1,
531 .parent = &clk_hclk_psys.clk, 495 .parent = &clk_hclk_psys.clk,
532 .enable = s5pv210_clk_ip1_ctrl, 496 .enable = s5pv210_clk_ip1_ctrl,
533 .ctrlbit = (1 << 26), 497 .ctrlbit = (1 << 26),
@@ -579,7 +543,6 @@ static struct clksrc_sources clkset_sclk_dac = {
579static struct clksrc_clk clk_sclk_dac = { 543static struct clksrc_clk clk_sclk_dac = {
580 .clk = { 544 .clk = {
581 .name = "sclk_dac", 545 .name = "sclk_dac",
582 .id = -1,
583 .enable = s5pv210_clk_mask0_ctrl, 546 .enable = s5pv210_clk_mask0_ctrl,
584 .ctrlbit = (1 << 2), 547 .ctrlbit = (1 << 2),
585 }, 548 },
@@ -590,7 +553,6 @@ static struct clksrc_clk clk_sclk_dac = {
590static struct clksrc_clk clk_sclk_pixel = { 553static struct clksrc_clk clk_sclk_pixel = {
591 .clk = { 554 .clk = {
592 .name = "sclk_pixel", 555 .name = "sclk_pixel",
593 .id = -1,
594 .parent = &clk_sclk_vpll.clk, 556 .parent = &clk_sclk_vpll.clk,
595 }, 557 },
596 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, 558 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
@@ -609,7 +571,6 @@ static struct clksrc_sources clkset_sclk_hdmi = {
609static struct clksrc_clk clk_sclk_hdmi = { 571static struct clksrc_clk clk_sclk_hdmi = {
610 .clk = { 572 .clk = {
611 .name = "sclk_hdmi", 573 .name = "sclk_hdmi",
612 .id = -1,
613 .enable = s5pv210_clk_mask0_ctrl, 574 .enable = s5pv210_clk_mask0_ctrl,
614 .ctrlbit = (1 << 0), 575 .ctrlbit = (1 << 0),
615 }, 576 },
@@ -647,7 +608,7 @@ static struct clksrc_sources clkset_sclk_audio0 = {
647static struct clksrc_clk clk_sclk_audio0 = { 608static struct clksrc_clk clk_sclk_audio0 = {
648 .clk = { 609 .clk = {
649 .name = "sclk_audio", 610 .name = "sclk_audio",
650 .id = 0, 611 .devname = "soc-audio.0",
651 .enable = s5pv210_clk_mask0_ctrl, 612 .enable = s5pv210_clk_mask0_ctrl,
652 .ctrlbit = (1 << 24), 613 .ctrlbit = (1 << 24),
653 }, 614 },
@@ -676,7 +637,7 @@ static struct clksrc_sources clkset_sclk_audio1 = {
676static struct clksrc_clk clk_sclk_audio1 = { 637static struct clksrc_clk clk_sclk_audio1 = {
677 .clk = { 638 .clk = {
678 .name = "sclk_audio", 639 .name = "sclk_audio",
679 .id = 1, 640 .devname = "soc-audio.1",
680 .enable = s5pv210_clk_mask0_ctrl, 641 .enable = s5pv210_clk_mask0_ctrl,
681 .ctrlbit = (1 << 25), 642 .ctrlbit = (1 << 25),
682 }, 643 },
@@ -705,7 +666,7 @@ static struct clksrc_sources clkset_sclk_audio2 = {
705static struct clksrc_clk clk_sclk_audio2 = { 666static struct clksrc_clk clk_sclk_audio2 = {
706 .clk = { 667 .clk = {
707 .name = "sclk_audio", 668 .name = "sclk_audio",
708 .id = 2, 669 .devname = "soc-audio.2",
709 .enable = s5pv210_clk_mask0_ctrl, 670 .enable = s5pv210_clk_mask0_ctrl,
710 .ctrlbit = (1 << 26), 671 .ctrlbit = (1 << 26),
711 }, 672 },
@@ -763,7 +724,6 @@ static struct clk_ops s5pv210_sclk_spdif_ops = {
763static struct clksrc_clk clk_sclk_spdif = { 724static struct clksrc_clk clk_sclk_spdif = {
764 .clk = { 725 .clk = {
765 .name = "sclk_spdif", 726 .name = "sclk_spdif",
766 .id = -1,
767 .enable = s5pv210_clk_mask0_ctrl, 727 .enable = s5pv210_clk_mask0_ctrl,
768 .ctrlbit = (1 << 27), 728 .ctrlbit = (1 << 27),
769 .ops = &s5pv210_sclk_spdif_ops, 729 .ops = &s5pv210_sclk_spdif_ops,
@@ -793,7 +753,6 @@ static struct clksrc_clk clksrcs[] = {
793 { 753 {
794 .clk = { 754 .clk = {
795 .name = "sclk_dmc", 755 .name = "sclk_dmc",
796 .id = -1,
797 }, 756 },
798 .sources = &clkset_group1, 757 .sources = &clkset_group1,
799 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, 758 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@@ -801,7 +760,6 @@ static struct clksrc_clk clksrcs[] = {
801 }, { 760 }, {
802 .clk = { 761 .clk = {
803 .name = "sclk_onenand", 762 .name = "sclk_onenand",
804 .id = -1,
805 }, 763 },
806 .sources = &clkset_sclk_onenand, 764 .sources = &clkset_sclk_onenand,
807 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, 765 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
@@ -809,7 +767,7 @@ static struct clksrc_clk clksrcs[] = {
809 }, { 767 }, {
810 .clk = { 768 .clk = {
811 .name = "uclk1", 769 .name = "uclk1",
812 .id = 0, 770 .devname = "s5pv210-uart.0",
813 .enable = s5pv210_clk_mask0_ctrl, 771 .enable = s5pv210_clk_mask0_ctrl,
814 .ctrlbit = (1 << 12), 772 .ctrlbit = (1 << 12),
815 }, 773 },
@@ -819,7 +777,7 @@ static struct clksrc_clk clksrcs[] = {
819 }, { 777 }, {
820 .clk = { 778 .clk = {
821 .name = "uclk1", 779 .name = "uclk1",
822 .id = 1, 780 .devname = "s5pv210-uart.1",
823 .enable = s5pv210_clk_mask0_ctrl, 781 .enable = s5pv210_clk_mask0_ctrl,
824 .ctrlbit = (1 << 13), 782 .ctrlbit = (1 << 13),
825 }, 783 },
@@ -829,7 +787,7 @@ static struct clksrc_clk clksrcs[] = {
829 }, { 787 }, {
830 .clk = { 788 .clk = {
831 .name = "uclk1", 789 .name = "uclk1",
832 .id = 2, 790 .devname = "s5pv210-uart.2",
833 .enable = s5pv210_clk_mask0_ctrl, 791 .enable = s5pv210_clk_mask0_ctrl,
834 .ctrlbit = (1 << 14), 792 .ctrlbit = (1 << 14),
835 }, 793 },
@@ -839,7 +797,7 @@ static struct clksrc_clk clksrcs[] = {
839 }, { 797 }, {
840 .clk = { 798 .clk = {
841 .name = "uclk1", 799 .name = "uclk1",
842 .id = 3, 800 .devname = "s5pv210-uart.3",
843 .enable = s5pv210_clk_mask0_ctrl, 801 .enable = s5pv210_clk_mask0_ctrl,
844 .ctrlbit = (1 << 15), 802 .ctrlbit = (1 << 15),
845 }, 803 },
@@ -849,7 +807,6 @@ static struct clksrc_clk clksrcs[] = {
849 }, { 807 }, {
850 .clk = { 808 .clk = {
851 .name = "sclk_mixer", 809 .name = "sclk_mixer",
852 .id = -1,
853 .enable = s5pv210_clk_mask0_ctrl, 810 .enable = s5pv210_clk_mask0_ctrl,
854 .ctrlbit = (1 << 1), 811 .ctrlbit = (1 << 1),
855 }, 812 },
@@ -858,7 +815,7 @@ static struct clksrc_clk clksrcs[] = {
858 }, { 815 }, {
859 .clk = { 816 .clk = {
860 .name = "sclk_fimc", 817 .name = "sclk_fimc",
861 .id = 0, 818 .devname = "s5pv210-fimc.0",
862 .enable = s5pv210_clk_mask1_ctrl, 819 .enable = s5pv210_clk_mask1_ctrl,
863 .ctrlbit = (1 << 2), 820 .ctrlbit = (1 << 2),
864 }, 821 },
@@ -868,7 +825,7 @@ static struct clksrc_clk clksrcs[] = {
868 }, { 825 }, {
869 .clk = { 826 .clk = {
870 .name = "sclk_fimc", 827 .name = "sclk_fimc",
871 .id = 1, 828 .devname = "s5pv210-fimc.1",
872 .enable = s5pv210_clk_mask1_ctrl, 829 .enable = s5pv210_clk_mask1_ctrl,
873 .ctrlbit = (1 << 3), 830 .ctrlbit = (1 << 3),
874 }, 831 },
@@ -878,7 +835,7 @@ static struct clksrc_clk clksrcs[] = {
878 }, { 835 }, {
879 .clk = { 836 .clk = {
880 .name = "sclk_fimc", 837 .name = "sclk_fimc",
881 .id = 2, 838 .devname = "s5pv210-fimc.2",
882 .enable = s5pv210_clk_mask1_ctrl, 839 .enable = s5pv210_clk_mask1_ctrl,
883 .ctrlbit = (1 << 4), 840 .ctrlbit = (1 << 4),
884 }, 841 },
@@ -888,7 +845,7 @@ static struct clksrc_clk clksrcs[] = {
888 }, { 845 }, {
889 .clk = { 846 .clk = {
890 .name = "sclk_cam", 847 .name = "sclk_cam",
891 .id = 0, 848 .devname = "s5pv210-fimc.0",
892 .enable = s5pv210_clk_mask0_ctrl, 849 .enable = s5pv210_clk_mask0_ctrl,
893 .ctrlbit = (1 << 3), 850 .ctrlbit = (1 << 3),
894 }, 851 },
@@ -898,7 +855,7 @@ static struct clksrc_clk clksrcs[] = {
898 }, { 855 }, {
899 .clk = { 856 .clk = {
900 .name = "sclk_cam", 857 .name = "sclk_cam",
901 .id = 1, 858 .devname = "s5pv210-fimc.1",
902 .enable = s5pv210_clk_mask0_ctrl, 859 .enable = s5pv210_clk_mask0_ctrl,
903 .ctrlbit = (1 << 4), 860 .ctrlbit = (1 << 4),
904 }, 861 },
@@ -908,7 +865,6 @@ static struct clksrc_clk clksrcs[] = {
908 }, { 865 }, {
909 .clk = { 866 .clk = {
910 .name = "sclk_fimd", 867 .name = "sclk_fimd",
911 .id = -1,
912 .enable = s5pv210_clk_mask0_ctrl, 868 .enable = s5pv210_clk_mask0_ctrl,
913 .ctrlbit = (1 << 5), 869 .ctrlbit = (1 << 5),
914 }, 870 },
@@ -918,7 +874,7 @@ static struct clksrc_clk clksrcs[] = {
918 }, { 874 }, {
919 .clk = { 875 .clk = {
920 .name = "sclk_mmc", 876 .name = "sclk_mmc",
921 .id = 0, 877 .devname = "s3c-sdhci.0",
922 .enable = s5pv210_clk_mask0_ctrl, 878 .enable = s5pv210_clk_mask0_ctrl,
923 .ctrlbit = (1 << 8), 879 .ctrlbit = (1 << 8),
924 }, 880 },
@@ -928,7 +884,7 @@ static struct clksrc_clk clksrcs[] = {
928 }, { 884 }, {
929 .clk = { 885 .clk = {
930 .name = "sclk_mmc", 886 .name = "sclk_mmc",
931 .id = 1, 887 .devname = "s3c-sdhci.1",
932 .enable = s5pv210_clk_mask0_ctrl, 888 .enable = s5pv210_clk_mask0_ctrl,
933 .ctrlbit = (1 << 9), 889 .ctrlbit = (1 << 9),
934 }, 890 },
@@ -938,7 +894,7 @@ static struct clksrc_clk clksrcs[] = {
938 }, { 894 }, {
939 .clk = { 895 .clk = {
940 .name = "sclk_mmc", 896 .name = "sclk_mmc",
941 .id = 2, 897 .devname = "s3c-sdhci.2",
942 .enable = s5pv210_clk_mask0_ctrl, 898 .enable = s5pv210_clk_mask0_ctrl,
943 .ctrlbit = (1 << 10), 899 .ctrlbit = (1 << 10),
944 }, 900 },
@@ -948,7 +904,7 @@ static struct clksrc_clk clksrcs[] = {
948 }, { 904 }, {
949 .clk = { 905 .clk = {
950 .name = "sclk_mmc", 906 .name = "sclk_mmc",
951 .id = 3, 907 .devname = "s3c-sdhci.3",
952 .enable = s5pv210_clk_mask0_ctrl, 908 .enable = s5pv210_clk_mask0_ctrl,
953 .ctrlbit = (1 << 11), 909 .ctrlbit = (1 << 11),
954 }, 910 },
@@ -958,7 +914,6 @@ static struct clksrc_clk clksrcs[] = {
958 }, { 914 }, {
959 .clk = { 915 .clk = {
960 .name = "sclk_mfc", 916 .name = "sclk_mfc",
961 .id = -1,
962 .enable = s5pv210_clk_ip0_ctrl, 917 .enable = s5pv210_clk_ip0_ctrl,
963 .ctrlbit = (1 << 16), 918 .ctrlbit = (1 << 16),
964 }, 919 },
@@ -968,7 +923,6 @@ static struct clksrc_clk clksrcs[] = {
968 }, { 923 }, {
969 .clk = { 924 .clk = {
970 .name = "sclk_g2d", 925 .name = "sclk_g2d",
971 .id = -1,
972 .enable = s5pv210_clk_ip0_ctrl, 926 .enable = s5pv210_clk_ip0_ctrl,
973 .ctrlbit = (1 << 12), 927 .ctrlbit = (1 << 12),
974 }, 928 },
@@ -978,7 +932,6 @@ static struct clksrc_clk clksrcs[] = {
978 }, { 932 }, {
979 .clk = { 933 .clk = {
980 .name = "sclk_g3d", 934 .name = "sclk_g3d",
981 .id = -1,
982 .enable = s5pv210_clk_ip0_ctrl, 935 .enable = s5pv210_clk_ip0_ctrl,
983 .ctrlbit = (1 << 8), 936 .ctrlbit = (1 << 8),
984 }, 937 },
@@ -988,7 +941,6 @@ static struct clksrc_clk clksrcs[] = {
988 }, { 941 }, {
989 .clk = { 942 .clk = {
990 .name = "sclk_csis", 943 .name = "sclk_csis",
991 .id = -1,
992 .enable = s5pv210_clk_mask0_ctrl, 944 .enable = s5pv210_clk_mask0_ctrl,
993 .ctrlbit = (1 << 6), 945 .ctrlbit = (1 << 6),
994 }, 946 },
@@ -998,7 +950,7 @@ static struct clksrc_clk clksrcs[] = {
998 }, { 950 }, {
999 .clk = { 951 .clk = {
1000 .name = "sclk_spi", 952 .name = "sclk_spi",
1001 .id = 0, 953 .devname = "s3c64xx-spi.0",
1002 .enable = s5pv210_clk_mask0_ctrl, 954 .enable = s5pv210_clk_mask0_ctrl,
1003 .ctrlbit = (1 << 16), 955 .ctrlbit = (1 << 16),
1004 }, 956 },
@@ -1008,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
1008 }, { 960 }, {
1009 .clk = { 961 .clk = {
1010 .name = "sclk_spi", 962 .name = "sclk_spi",
1011 .id = 1, 963 .devname = "s3c64xx-spi.1",
1012 .enable = s5pv210_clk_mask0_ctrl, 964 .enable = s5pv210_clk_mask0_ctrl,
1013 .ctrlbit = (1 << 17), 965 .ctrlbit = (1 << 17),
1014 }, 966 },
@@ -1018,7 +970,6 @@ static struct clksrc_clk clksrcs[] = {
1018 }, { 970 }, {
1019 .clk = { 971 .clk = {
1020 .name = "sclk_pwi", 972 .name = "sclk_pwi",
1021 .id = -1,
1022 .enable = s5pv210_clk_mask0_ctrl, 973 .enable = s5pv210_clk_mask0_ctrl,
1023 .ctrlbit = (1 << 29), 974 .ctrlbit = (1 << 29),
1024 }, 975 },
@@ -1028,7 +979,6 @@ static struct clksrc_clk clksrcs[] = {
1028 }, { 979 }, {
1029 .clk = { 980 .clk = {
1030 .name = "sclk_pwm", 981 .name = "sclk_pwm",
1031 .id = -1,
1032 .enable = s5pv210_clk_mask0_ctrl, 982 .enable = s5pv210_clk_mask0_ctrl,
1033 .ctrlbit = (1 << 19), 983 .ctrlbit = (1 << 19),
1034 }, 984 },
diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h b/arch/arm/mach-s5pv210/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index cf97caafe56b..f95d3268ae1f 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -169,7 +169,6 @@ static struct clk_ops dclk_ops = {
169 169
170struct clk s3c24xx_dclk0 = { 170struct clk s3c24xx_dclk0 = {
171 .name = "dclk0", 171 .name = "dclk0",
172 .id = -1,
173 .ctrlbit = S3C2410_DCLKCON_DCLK0EN, 172 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
174 .enable = s3c24xx_dclk_enable, 173 .enable = s3c24xx_dclk_enable,
175 .ops = &dclk_ops, 174 .ops = &dclk_ops,
@@ -177,7 +176,6 @@ struct clk s3c24xx_dclk0 = {
177 176
178struct clk s3c24xx_dclk1 = { 177struct clk s3c24xx_dclk1 = {
179 .name = "dclk1", 178 .name = "dclk1",
180 .id = -1,
181 .ctrlbit = S3C2410_DCLKCON_DCLK1EN, 179 .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
182 .enable = s3c24xx_dclk_enable, 180 .enable = s3c24xx_dclk_enable,
183 .ops = &dclk_ops, 181 .ops = &dclk_ops,
@@ -189,12 +187,10 @@ static struct clk_ops clkout_ops = {
189 187
190struct clk s3c24xx_clkout0 = { 188struct clk s3c24xx_clkout0 = {
191 .name = "clkout0", 189 .name = "clkout0",
192 .id = -1,
193 .ops = &clkout_ops, 190 .ops = &clkout_ops,
194}; 191};
195 192
196struct clk s3c24xx_clkout1 = { 193struct clk s3c24xx_clkout1 = {
197 .name = "clkout1", 194 .name = "clkout1",
198 .id = -1,
199 .ops = &clkout_ops, 195 .ops = &clkout_ops,
200}; 196};
diff --git a/arch/arm/plat-s3c24xx/include/mach/clkdev.h b/arch/arm/plat-s3c24xx/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c
index 9ecc5d913679..def76aa3825a 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c
@@ -90,37 +90,31 @@ static int s3c2410_upll_enable(struct clk *clk, int enable)
90static struct clk init_clocks_off[] = { 90static struct clk init_clocks_off[] = {
91 { 91 {
92 .name = "nand", 92 .name = "nand",
93 .id = -1,
94 .parent = &clk_h, 93 .parent = &clk_h,
95 .enable = s3c2410_clkcon_enable, 94 .enable = s3c2410_clkcon_enable,
96 .ctrlbit = S3C2410_CLKCON_NAND, 95 .ctrlbit = S3C2410_CLKCON_NAND,
97 }, { 96 }, {
98 .name = "sdi", 97 .name = "sdi",
99 .id = -1,
100 .parent = &clk_p, 98 .parent = &clk_p,
101 .enable = s3c2410_clkcon_enable, 99 .enable = s3c2410_clkcon_enable,
102 .ctrlbit = S3C2410_CLKCON_SDI, 100 .ctrlbit = S3C2410_CLKCON_SDI,
103 }, { 101 }, {
104 .name = "adc", 102 .name = "adc",
105 .id = -1,
106 .parent = &clk_p, 103 .parent = &clk_p,
107 .enable = s3c2410_clkcon_enable, 104 .enable = s3c2410_clkcon_enable,
108 .ctrlbit = S3C2410_CLKCON_ADC, 105 .ctrlbit = S3C2410_CLKCON_ADC,
109 }, { 106 }, {
110 .name = "i2c", 107 .name = "i2c",
111 .id = -1,
112 .parent = &clk_p, 108 .parent = &clk_p,
113 .enable = s3c2410_clkcon_enable, 109 .enable = s3c2410_clkcon_enable,
114 .ctrlbit = S3C2410_CLKCON_IIC, 110 .ctrlbit = S3C2410_CLKCON_IIC,
115 }, { 111 }, {
116 .name = "iis", 112 .name = "iis",
117 .id = -1,
118 .parent = &clk_p, 113 .parent = &clk_p,
119 .enable = s3c2410_clkcon_enable, 114 .enable = s3c2410_clkcon_enable,
120 .ctrlbit = S3C2410_CLKCON_IIS, 115 .ctrlbit = S3C2410_CLKCON_IIS,
121 }, { 116 }, {
122 .name = "spi", 117 .name = "spi",
123 .id = -1,
124 .parent = &clk_p, 118 .parent = &clk_p,
125 .enable = s3c2410_clkcon_enable, 119 .enable = s3c2410_clkcon_enable,
126 .ctrlbit = S3C2410_CLKCON_SPI, 120 .ctrlbit = S3C2410_CLKCON_SPI,
@@ -130,70 +124,61 @@ static struct clk init_clocks_off[] = {
130static struct clk init_clocks[] = { 124static struct clk init_clocks[] = {
131 { 125 {
132 .name = "lcd", 126 .name = "lcd",
133 .id = -1,
134 .parent = &clk_h, 127 .parent = &clk_h,
135 .enable = s3c2410_clkcon_enable, 128 .enable = s3c2410_clkcon_enable,
136 .ctrlbit = S3C2410_CLKCON_LCDC, 129 .ctrlbit = S3C2410_CLKCON_LCDC,
137 }, { 130 }, {
138 .name = "gpio", 131 .name = "gpio",
139 .id = -1,
140 .parent = &clk_p, 132 .parent = &clk_p,
141 .enable = s3c2410_clkcon_enable, 133 .enable = s3c2410_clkcon_enable,
142 .ctrlbit = S3C2410_CLKCON_GPIO, 134 .ctrlbit = S3C2410_CLKCON_GPIO,
143 }, { 135 }, {
144 .name = "usb-host", 136 .name = "usb-host",
145 .id = -1,
146 .parent = &clk_h, 137 .parent = &clk_h,
147 .enable = s3c2410_clkcon_enable, 138 .enable = s3c2410_clkcon_enable,
148 .ctrlbit = S3C2410_CLKCON_USBH, 139 .ctrlbit = S3C2410_CLKCON_USBH,
149 }, { 140 }, {
150 .name = "usb-device", 141 .name = "usb-device",
151 .id = -1,
152 .parent = &clk_h, 142 .parent = &clk_h,
153 .enable = s3c2410_clkcon_enable, 143 .enable = s3c2410_clkcon_enable,
154 .ctrlbit = S3C2410_CLKCON_USBD, 144 .ctrlbit = S3C2410_CLKCON_USBD,
155 }, { 145 }, {
156 .name = "timers", 146 .name = "timers",
157 .id = -1,
158 .parent = &clk_p, 147 .parent = &clk_p,
159 .enable = s3c2410_clkcon_enable, 148 .enable = s3c2410_clkcon_enable,
160 .ctrlbit = S3C2410_CLKCON_PWMT, 149 .ctrlbit = S3C2410_CLKCON_PWMT,
161 }, { 150 }, {
162 .name = "uart", 151 .name = "uart",
163 .id = 0, 152 .devname = "s3c2410-uart.0",
164 .parent = &clk_p, 153 .parent = &clk_p,
165 .enable = s3c2410_clkcon_enable, 154 .enable = s3c2410_clkcon_enable,
166 .ctrlbit = S3C2410_CLKCON_UART0, 155 .ctrlbit = S3C2410_CLKCON_UART0,
167 }, { 156 }, {
168 .name = "uart", 157 .name = "uart",
169 .id = 1, 158 .devname = "s3c2410-uart.1",
170 .parent = &clk_p, 159 .parent = &clk_p,
171 .enable = s3c2410_clkcon_enable, 160 .enable = s3c2410_clkcon_enable,
172 .ctrlbit = S3C2410_CLKCON_UART1, 161 .ctrlbit = S3C2410_CLKCON_UART1,
173 }, { 162 }, {
174 .name = "uart", 163 .name = "uart",
175 .id = 2, 164 .devname = "s3c2410-uart.2",
176 .parent = &clk_p, 165 .parent = &clk_p,
177 .enable = s3c2410_clkcon_enable, 166 .enable = s3c2410_clkcon_enable,
178 .ctrlbit = S3C2410_CLKCON_UART2, 167 .ctrlbit = S3C2410_CLKCON_UART2,
179 }, { 168 }, {
180 .name = "rtc", 169 .name = "rtc",
181 .id = -1,
182 .parent = &clk_p, 170 .parent = &clk_p,
183 .enable = s3c2410_clkcon_enable, 171 .enable = s3c2410_clkcon_enable,
184 .ctrlbit = S3C2410_CLKCON_RTC, 172 .ctrlbit = S3C2410_CLKCON_RTC,
185 }, { 173 }, {
186 .name = "watchdog", 174 .name = "watchdog",
187 .id = -1,
188 .parent = &clk_p, 175 .parent = &clk_p,
189 .ctrlbit = 0, 176 .ctrlbit = 0,
190 }, { 177 }, {
191 .name = "usb-bus-host", 178 .name = "usb-bus-host",
192 .id = -1,
193 .parent = &clk_usb_bus, 179 .parent = &clk_usb_bus,
194 }, { 180 }, {
195 .name = "usb-bus-gadget", 181 .name = "usb-bus-gadget",
196 .id = -1,
197 .parent = &clk_usb_bus, 182 .parent = &clk_usb_bus,
198 }, 183 },
199}; 184};
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 82f2d4a39291..59552c0ea5fb 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -56,7 +56,6 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
56struct clk clk_mpllref = { 56struct clk clk_mpllref = {
57 .name = "mpllref", 57 .name = "mpllref",
58 .parent = &clk_xtal, 58 .parent = &clk_xtal,
59 .id = -1,
60}; 59};
61 60
62static struct clk *clk_epllref_sources[] = { 61static struct clk *clk_epllref_sources[] = {
@@ -69,7 +68,6 @@ static struct clk *clk_epllref_sources[] = {
69struct clksrc_clk clk_epllref = { 68struct clksrc_clk clk_epllref = {
70 .clk = { 69 .clk = {
71 .name = "epllref", 70 .name = "epllref",
72 .id = -1,
73 }, 71 },
74 .sources = &(struct clksrc_sources) { 72 .sources = &(struct clksrc_sources) {
75 .sources = clk_epllref_sources, 73 .sources = clk_epllref_sources,
@@ -92,7 +90,6 @@ struct clksrc_clk clk_esysclk = {
92 .clk = { 90 .clk = {
93 .name = "esysclk", 91 .name = "esysclk",
94 .parent = &clk_epll, 92 .parent = &clk_epll,
95 .id = -1,
96 }, 93 },
97 .sources = &(struct clksrc_sources) { 94 .sources = &(struct clksrc_sources) {
98 .sources = clk_sysclk_sources, 95 .sources = clk_sysclk_sources,
@@ -115,7 +112,6 @@ static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
115static struct clk clk_mdivclk = { 112static struct clk clk_mdivclk = {
116 .name = "mdivclk", 113 .name = "mdivclk",
117 .parent = &clk_mpllref, 114 .parent = &clk_mpllref,
118 .id = -1,
119 .ops = &(struct clk_ops) { 115 .ops = &(struct clk_ops) {
120 .get_rate = s3c2443_getrate_mdivclk, 116 .get_rate = s3c2443_getrate_mdivclk,
121 }, 117 },
@@ -132,7 +128,6 @@ struct clksrc_clk clk_msysclk = {
132 .clk = { 128 .clk = {
133 .name = "msysclk", 129 .name = "msysclk",
134 .parent = &clk_xtal, 130 .parent = &clk_xtal,
135 .id = -1,
136 }, 131 },
137 .sources = &(struct clksrc_sources) { 132 .sources = &(struct clksrc_sources) {
138 .sources = clk_msysclk_sources, 133 .sources = clk_msysclk_sources,
@@ -159,7 +154,6 @@ static unsigned long s3c2443_prediv_getrate(struct clk *clk)
159 154
160static struct clk clk_prediv = { 155static struct clk clk_prediv = {
161 .name = "prediv", 156 .name = "prediv",
162 .id = -1,
163 .parent = &clk_msysclk.clk, 157 .parent = &clk_msysclk.clk,
164 .ops = &(struct clk_ops) { 158 .ops = &(struct clk_ops) {
165 .get_rate = s3c2443_prediv_getrate, 159 .get_rate = s3c2443_prediv_getrate,
@@ -174,7 +168,6 @@ static struct clk clk_prediv = {
174static struct clksrc_clk clk_usb_bus_host = { 168static struct clksrc_clk clk_usb_bus_host = {
175 .clk = { 169 .clk = {
176 .name = "usb-bus-host-parent", 170 .name = "usb-bus-host-parent",
177 .id = -1,
178 .parent = &clk_esysclk.clk, 171 .parent = &clk_esysclk.clk,
179 .ctrlbit = S3C2443_SCLKCON_USBHOST, 172 .ctrlbit = S3C2443_SCLKCON_USBHOST,
180 .enable = s3c2443_clkcon_enable_s, 173 .enable = s3c2443_clkcon_enable_s,
@@ -189,7 +182,6 @@ static struct clksrc_clk clksrc_clks[] = {
189 /* ART baud-rate clock sourced from esysclk via a divisor */ 182 /* ART baud-rate clock sourced from esysclk via a divisor */
190 .clk = { 183 .clk = {
191 .name = "uartclk", 184 .name = "uartclk",
192 .id = -1,
193 .parent = &clk_esysclk.clk, 185 .parent = &clk_esysclk.clk,
194 }, 186 },
195 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, 187 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
@@ -197,7 +189,6 @@ static struct clksrc_clk clksrc_clks[] = {
197 /* camera interface bus-clock, divided down from esysclk */ 189 /* camera interface bus-clock, divided down from esysclk */
198 .clk = { 190 .clk = {
199 .name = "camif-upll", /* same as 2440 name */ 191 .name = "camif-upll", /* same as 2440 name */
200 .id = -1,
201 .parent = &clk_esysclk.clk, 192 .parent = &clk_esysclk.clk,
202 .ctrlbit = S3C2443_SCLKCON_CAMCLK, 193 .ctrlbit = S3C2443_SCLKCON_CAMCLK,
203 .enable = s3c2443_clkcon_enable_s, 194 .enable = s3c2443_clkcon_enable_s,
@@ -206,7 +197,6 @@ static struct clksrc_clk clksrc_clks[] = {
206 }, { 197 }, {
207 .clk = { 198 .clk = {
208 .name = "display-if", 199 .name = "display-if",
209 .id = -1,
210 .parent = &clk_esysclk.clk, 200 .parent = &clk_esysclk.clk,
211 .ctrlbit = S3C2443_SCLKCON_DISPCLK, 201 .ctrlbit = S3C2443_SCLKCON_DISPCLK,
212 .enable = s3c2443_clkcon_enable_s, 202 .enable = s3c2443_clkcon_enable_s,
@@ -219,13 +209,11 @@ static struct clksrc_clk clksrc_clks[] = {
219static struct clk init_clocks_off[] = { 209static struct clk init_clocks_off[] = {
220 { 210 {
221 .name = "adc", 211 .name = "adc",
222 .id = -1,
223 .parent = &clk_p, 212 .parent = &clk_p,
224 .enable = s3c2443_clkcon_enable_p, 213 .enable = s3c2443_clkcon_enable_p,
225 .ctrlbit = S3C2443_PCLKCON_ADC, 214 .ctrlbit = S3C2443_PCLKCON_ADC,
226 }, { 215 }, {
227 .name = "i2c", 216 .name = "i2c",
228 .id = -1,
229 .parent = &clk_p, 217 .parent = &clk_p,
230 .enable = s3c2443_clkcon_enable_p, 218 .enable = s3c2443_clkcon_enable_p,
231 .ctrlbit = S3C2443_PCLKCON_IIC, 219 .ctrlbit = S3C2443_PCLKCON_IIC,
@@ -235,136 +223,117 @@ static struct clk init_clocks_off[] = {
235static struct clk init_clocks[] = { 223static struct clk init_clocks[] = {
236 { 224 {
237 .name = "dma", 225 .name = "dma",
238 .id = 0,
239 .parent = &clk_h, 226 .parent = &clk_h,
240 .enable = s3c2443_clkcon_enable_h, 227 .enable = s3c2443_clkcon_enable_h,
241 .ctrlbit = S3C2443_HCLKCON_DMA0, 228 .ctrlbit = S3C2443_HCLKCON_DMA0,
242 }, { 229 }, {
243 .name = "dma", 230 .name = "dma",
244 .id = 1,
245 .parent = &clk_h, 231 .parent = &clk_h,
246 .enable = s3c2443_clkcon_enable_h, 232 .enable = s3c2443_clkcon_enable_h,
247 .ctrlbit = S3C2443_HCLKCON_DMA1, 233 .ctrlbit = S3C2443_HCLKCON_DMA1,
248 }, { 234 }, {
249 .name = "dma", 235 .name = "dma",
250 .id = 2,
251 .parent = &clk_h, 236 .parent = &clk_h,
252 .enable = s3c2443_clkcon_enable_h, 237 .enable = s3c2443_clkcon_enable_h,
253 .ctrlbit = S3C2443_HCLKCON_DMA2, 238 .ctrlbit = S3C2443_HCLKCON_DMA2,
254 }, { 239 }, {
255 .name = "dma", 240 .name = "dma",
256 .id = 3,
257 .parent = &clk_h, 241 .parent = &clk_h,
258 .enable = s3c2443_clkcon_enable_h, 242 .enable = s3c2443_clkcon_enable_h,
259 .ctrlbit = S3C2443_HCLKCON_DMA3, 243 .ctrlbit = S3C2443_HCLKCON_DMA3,
260 }, { 244 }, {
261 .name = "dma", 245 .name = "dma",
262 .id = 4,
263 .parent = &clk_h, 246 .parent = &clk_h,
264 .enable = s3c2443_clkcon_enable_h, 247 .enable = s3c2443_clkcon_enable_h,
265 .ctrlbit = S3C2443_HCLKCON_DMA4, 248 .ctrlbit = S3C2443_HCLKCON_DMA4,
266 }, { 249 }, {
267 .name = "dma", 250 .name = "dma",
268 .id = 5,
269 .parent = &clk_h, 251 .parent = &clk_h,
270 .enable = s3c2443_clkcon_enable_h, 252 .enable = s3c2443_clkcon_enable_h,
271 .ctrlbit = S3C2443_HCLKCON_DMA5, 253 .ctrlbit = S3C2443_HCLKCON_DMA5,
272 }, { 254 }, {
273 .name = "hsmmc", 255 .name = "hsmmc",
274 .id = 1,
275 .parent = &clk_h, 256 .parent = &clk_h,
276 .enable = s3c2443_clkcon_enable_h, 257 .enable = s3c2443_clkcon_enable_h,
277 .ctrlbit = S3C2443_HCLKCON_HSMMC, 258 .ctrlbit = S3C2443_HCLKCON_HSMMC,
278 }, { 259 }, {
279 .name = "gpio", 260 .name = "gpio",
280 .id = -1,
281 .parent = &clk_p, 261 .parent = &clk_p,
282 .enable = s3c2443_clkcon_enable_p, 262 .enable = s3c2443_clkcon_enable_p,
283 .ctrlbit = S3C2443_PCLKCON_GPIO, 263 .ctrlbit = S3C2443_PCLKCON_GPIO,
284 }, { 264 }, {
285 .name = "usb-host", 265 .name = "usb-host",
286 .id = -1,
287 .parent = &clk_h, 266 .parent = &clk_h,
288 .enable = s3c2443_clkcon_enable_h, 267 .enable = s3c2443_clkcon_enable_h,
289 .ctrlbit = S3C2443_HCLKCON_USBH, 268 .ctrlbit = S3C2443_HCLKCON_USBH,
290 }, { 269 }, {
291 .name = "usb-device", 270 .name = "usb-device",
292 .id = -1,
293 .parent = &clk_h, 271 .parent = &clk_h,
294 .enable = s3c2443_clkcon_enable_h, 272 .enable = s3c2443_clkcon_enable_h,
295 .ctrlbit = S3C2443_HCLKCON_USBD, 273 .ctrlbit = S3C2443_HCLKCON_USBD,
296 }, { 274 }, {
297 .name = "lcd", 275 .name = "lcd",
298 .id = -1,
299 .parent = &clk_h, 276 .parent = &clk_h,
300 .enable = s3c2443_clkcon_enable_h, 277 .enable = s3c2443_clkcon_enable_h,
301 .ctrlbit = S3C2443_HCLKCON_LCDC, 278 .ctrlbit = S3C2443_HCLKCON_LCDC,
302 279
303 }, { 280 }, {
304 .name = "timers", 281 .name = "timers",
305 .id = -1,
306 .parent = &clk_p, 282 .parent = &clk_p,
307 .enable = s3c2443_clkcon_enable_p, 283 .enable = s3c2443_clkcon_enable_p,
308 .ctrlbit = S3C2443_PCLKCON_PWMT, 284 .ctrlbit = S3C2443_PCLKCON_PWMT,
309 }, { 285 }, {
310 .name = "cfc", 286 .name = "cfc",
311 .id = -1,
312 .parent = &clk_h, 287 .parent = &clk_h,
313 .enable = s3c2443_clkcon_enable_h, 288 .enable = s3c2443_clkcon_enable_h,
314 .ctrlbit = S3C2443_HCLKCON_CFC, 289 .ctrlbit = S3C2443_HCLKCON_CFC,
315 }, { 290 }, {
316 .name = "ssmc", 291 .name = "ssmc",
317 .id = -1,
318 .parent = &clk_h, 292 .parent = &clk_h,
319 .enable = s3c2443_clkcon_enable_h, 293 .enable = s3c2443_clkcon_enable_h,
320 .ctrlbit = S3C2443_HCLKCON_SSMC, 294 .ctrlbit = S3C2443_HCLKCON_SSMC,
321 }, { 295 }, {
322 .name = "uart", 296 .name = "uart",
323 .id = 0, 297 .devname = "s3c2440-uart.0",
324 .parent = &clk_p, 298 .parent = &clk_p,
325 .enable = s3c2443_clkcon_enable_p, 299 .enable = s3c2443_clkcon_enable_p,
326 .ctrlbit = S3C2443_PCLKCON_UART0, 300 .ctrlbit = S3C2443_PCLKCON_UART0,
327 }, { 301 }, {
328 .name = "uart", 302 .name = "uart",
329 .id = 1, 303 .devname = "s3c2440-uart.1",
330 .parent = &clk_p, 304 .parent = &clk_p,
331 .enable = s3c2443_clkcon_enable_p, 305 .enable = s3c2443_clkcon_enable_p,
332 .ctrlbit = S3C2443_PCLKCON_UART1, 306 .ctrlbit = S3C2443_PCLKCON_UART1,
333 }, { 307 }, {
334 .name = "uart", 308 .name = "uart",
335 .id = 2, 309 .devname = "s3c2440-uart.2",
336 .parent = &clk_p, 310 .parent = &clk_p,
337 .enable = s3c2443_clkcon_enable_p, 311 .enable = s3c2443_clkcon_enable_p,
338 .ctrlbit = S3C2443_PCLKCON_UART2, 312 .ctrlbit = S3C2443_PCLKCON_UART2,
339 }, { 313 }, {
340 .name = "uart", 314 .name = "uart",
341 .id = 3, 315 .devname = "s3c2440-uart.3",
342 .parent = &clk_p, 316 .parent = &clk_p,
343 .enable = s3c2443_clkcon_enable_p, 317 .enable = s3c2443_clkcon_enable_p,
344 .ctrlbit = S3C2443_PCLKCON_UART3, 318 .ctrlbit = S3C2443_PCLKCON_UART3,
345 }, { 319 }, {
346 .name = "rtc", 320 .name = "rtc",
347 .id = -1,
348 .parent = &clk_p, 321 .parent = &clk_p,
349 .enable = s3c2443_clkcon_enable_p, 322 .enable = s3c2443_clkcon_enable_p,
350 .ctrlbit = S3C2443_PCLKCON_RTC, 323 .ctrlbit = S3C2443_PCLKCON_RTC,
351 }, { 324 }, {
352 .name = "watchdog", 325 .name = "watchdog",
353 .id = -1,
354 .parent = &clk_p, 326 .parent = &clk_p,
355 .ctrlbit = S3C2443_PCLKCON_WDT, 327 .ctrlbit = S3C2443_PCLKCON_WDT,
356 }, { 328 }, {
357 .name = "ac97", 329 .name = "ac97",
358 .id = -1,
359 .parent = &clk_p, 330 .parent = &clk_p,
360 .ctrlbit = S3C2443_PCLKCON_AC97, 331 .ctrlbit = S3C2443_PCLKCON_AC97,
361 }, { 332 }, {
362 .name = "nand", 333 .name = "nand",
363 .id = -1,
364 .parent = &clk_h, 334 .parent = &clk_h,
365 }, { 335 }, {
366 .name = "usb-bus-host", 336 .name = "usb-bus-host",
367 .id = -1,
368 .parent = &clk_usb_bus_host.clk, 337 .parent = &clk_usb_bus_host.clk,
369 } 338 }
370}; 339};
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
index 612934c48b0d..7c82f06baf57 100644
--- a/arch/arm/plat-s5p/s5p-time.c
+++ b/arch/arm/plat-s5p/s5p-time.c
@@ -384,6 +384,7 @@ static void __init s5p_timer_resources(void)
384 384
385 unsigned long event_id = timer_source.event_id; 385 unsigned long event_id = timer_source.event_id;
386 unsigned long source_id = timer_source.source_id; 386 unsigned long source_id = timer_source.source_id;
387 char devname[15];
387 388
388 timerclk = clk_get(NULL, "timers"); 389 timerclk = clk_get(NULL, "timers");
389 if (IS_ERR(timerclk)) 390 if (IS_ERR(timerclk))
@@ -391,6 +392,10 @@ static void __init s5p_timer_resources(void)
391 392
392 clk_enable(timerclk); 393 clk_enable(timerclk);
393 394
395 sprintf(devname, "s3c24xx-pwm.%lu", event_id);
396 s3c_device_timer[event_id].id = event_id;
397 s3c_device_timer[event_id].dev.init_name = devname;
398
394 tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin"); 399 tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
395 if (IS_ERR(tin_event)) 400 if (IS_ERR(tin_event))
396 panic("failed to get pwm-tin clock for event timer"); 401 panic("failed to get pwm-tin clock for event timer");
@@ -401,6 +406,10 @@ static void __init s5p_timer_resources(void)
401 406
402 clk_enable(tin_event); 407 clk_enable(tin_event);
403 408
409 sprintf(devname, "s3c24xx-pwm.%lu", source_id);
410 s3c_device_timer[source_id].id = source_id;
411 s3c_device_timer[source_id].dev.init_name = devname;
412
404 tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin"); 413 tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
405 if (IS_ERR(tin_source)) 414 if (IS_ERR(tin_source))
406 panic("failed to get pwm-tin clock for source timer"); 415 panic("failed to get pwm-tin clock for source timer");
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 772892826ffc..aecf9e90d4fc 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -71,74 +71,6 @@ static int clk_null_enable(struct clk *clk, int enable)
71 return 0; 71 return 0;
72} 72}
73 73
74static int dev_is_s3c_uart(struct device *dev)
75{
76 struct platform_device **pdev = s3c24xx_uart_devs;
77 int i;
78 for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++)
79 if (*pdev && dev == &(*pdev)->dev)
80 return 1;
81 return 0;
82}
83
84/*
85 * Serial drivers call get_clock() very early, before platform bus
86 * has been set up, this requires a special check to let them get
87 * a proper clock
88 */
89
90static int dev_is_platform_device(struct device *dev)
91{
92 return dev->bus == &platform_bus_type ||
93 (dev->bus == NULL && dev_is_s3c_uart(dev));
94}
95
96/* Clock API calls */
97
98struct clk *clk_get(struct device *dev, const char *id)
99{
100 struct clk *p;
101 struct clk *clk = ERR_PTR(-ENOENT);
102 int idno;
103
104 if (dev == NULL || !dev_is_platform_device(dev))
105 idno = -1;
106 else
107 idno = to_platform_device(dev)->id;
108
109 spin_lock(&clocks_lock);
110
111 list_for_each_entry(p, &clocks, list) {
112 if (p->id == idno &&
113 strcmp(id, p->name) == 0 &&
114 try_module_get(p->owner)) {
115 clk = p;
116 break;
117 }
118 }
119
120 /* check for the case where a device was supplied, but the
121 * clock that was being searched for is not device specific */
122
123 if (IS_ERR(clk)) {
124 list_for_each_entry(p, &clocks, list) {
125 if (p->id == -1 && strcmp(id, p->name) == 0 &&
126 try_module_get(p->owner)) {
127 clk = p;
128 break;
129 }
130 }
131 }
132
133 spin_unlock(&clocks_lock);
134 return clk;
135}
136
137void clk_put(struct clk *clk)
138{
139 module_put(clk->owner);
140}
141
142int clk_enable(struct clk *clk) 74int clk_enable(struct clk *clk)
143{ 75{
144 if (IS_ERR(clk) || clk == NULL) 76 if (IS_ERR(clk) || clk == NULL)
@@ -241,8 +173,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
241 return ret; 173 return ret;
242} 174}
243 175
244EXPORT_SYMBOL(clk_get);
245EXPORT_SYMBOL(clk_put);
246EXPORT_SYMBOL(clk_enable); 176EXPORT_SYMBOL(clk_enable);
247EXPORT_SYMBOL(clk_disable); 177EXPORT_SYMBOL(clk_disable);
248EXPORT_SYMBOL(clk_get_rate); 178EXPORT_SYMBOL(clk_get_rate);
@@ -265,7 +195,6 @@ struct clk_ops clk_ops_def_setrate = {
265 195
266struct clk clk_xtal = { 196struct clk clk_xtal = {
267 .name = "xtal", 197 .name = "xtal",
268 .id = -1,
269 .rate = 0, 198 .rate = 0,
270 .parent = NULL, 199 .parent = NULL,
271 .ctrlbit = 0, 200 .ctrlbit = 0,
@@ -273,30 +202,25 @@ struct clk clk_xtal = {
273 202
274struct clk clk_ext = { 203struct clk clk_ext = {
275 .name = "ext", 204 .name = "ext",
276 .id = -1,
277}; 205};
278 206
279struct clk clk_epll = { 207struct clk clk_epll = {
280 .name = "epll", 208 .name = "epll",
281 .id = -1,
282}; 209};
283 210
284struct clk clk_mpll = { 211struct clk clk_mpll = {
285 .name = "mpll", 212 .name = "mpll",
286 .id = -1,
287 .ops = &clk_ops_def_setrate, 213 .ops = &clk_ops_def_setrate,
288}; 214};
289 215
290struct clk clk_upll = { 216struct clk clk_upll = {
291 .name = "upll", 217 .name = "upll",
292 .id = -1,
293 .parent = NULL, 218 .parent = NULL,
294 .ctrlbit = 0, 219 .ctrlbit = 0,
295}; 220};
296 221
297struct clk clk_f = { 222struct clk clk_f = {
298 .name = "fclk", 223 .name = "fclk",
299 .id = -1,
300 .rate = 0, 224 .rate = 0,
301 .parent = &clk_mpll, 225 .parent = &clk_mpll,
302 .ctrlbit = 0, 226 .ctrlbit = 0,
@@ -304,7 +228,6 @@ struct clk clk_f = {
304 228
305struct clk clk_h = { 229struct clk clk_h = {
306 .name = "hclk", 230 .name = "hclk",
307 .id = -1,
308 .rate = 0, 231 .rate = 0,
309 .parent = NULL, 232 .parent = NULL,
310 .ctrlbit = 0, 233 .ctrlbit = 0,
@@ -313,7 +236,6 @@ struct clk clk_h = {
313 236
314struct clk clk_p = { 237struct clk clk_p = {
315 .name = "pclk", 238 .name = "pclk",
316 .id = -1,
317 .rate = 0, 239 .rate = 0,
318 .parent = NULL, 240 .parent = NULL,
319 .ctrlbit = 0, 241 .ctrlbit = 0,
@@ -322,7 +244,6 @@ struct clk clk_p = {
322 244
323struct clk clk_usb_bus = { 245struct clk clk_usb_bus = {
324 .name = "usb-bus", 246 .name = "usb-bus",
325 .id = -1,
326 .rate = 0, 247 .rate = 0,
327 .parent = &clk_upll, 248 .parent = &clk_upll,
328}; 249};
@@ -330,7 +251,6 @@ struct clk clk_usb_bus = {
330 251
331struct clk s3c24xx_uclk = { 252struct clk s3c24xx_uclk = {
332 .name = "uclk", 253 .name = "uclk",
333 .id = -1,
334}; 254};
335 255
336/* initialise the clock system */ 256/* initialise the clock system */
@@ -346,14 +266,11 @@ int s3c24xx_register_clock(struct clk *clk)
346 if (clk->enable == NULL) 266 if (clk->enable == NULL)
347 clk->enable = clk_null_enable; 267 clk->enable = clk_null_enable;
348 268
349 /* add to the list of available clocks */ 269 /* fill up the clk_lookup structure and register it*/
350 270 clk->lookup.dev_id = clk->devname;
351 /* Quick check to see if this clock has already been registered. */ 271 clk->lookup.con_id = clk->name;
352 BUG_ON(clk->list.prev != clk->list.next); 272 clk->lookup.clk = clk;
353 273 clkdev_add(&clk->lookup);
354 spin_lock(&clocks_lock);
355 list_add(&clk->list, &clocks);
356 spin_unlock(&clocks_lock);
357 274
358 return 0; 275 return 0;
359} 276}
@@ -463,10 +380,7 @@ static int clk_debugfs_register_one(struct clk *c)
463 char s[255]; 380 char s[255];
464 char *p = s; 381 char *p = s;
465 382
466 p += sprintf(p, "%s", c->name); 383 p += sprintf(p, "%s", c->devname);
467
468 if (c->id >= 0)
469 sprintf(p, ":%d", c->id);
470 384
471 d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); 385 d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
472 if (!d) 386 if (!d)
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 983c578b8276..87d5b38a86fb 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -10,6 +10,7 @@
10*/ 10*/
11 11
12#include <linux/spinlock.h> 12#include <linux/spinlock.h>
13#include <linux/clkdev.h>
13 14
14struct clk; 15struct clk;
15 16
@@ -40,6 +41,7 @@ struct clk {
40 struct module *owner; 41 struct module *owner;
41 struct clk *parent; 42 struct clk *parent;
42 const char *name; 43 const char *name;
44 const char *devname;
43 int id; 45 int id;
44 int usage; 46 int usage;
45 unsigned long rate; 47 unsigned long rate;
@@ -47,6 +49,7 @@ struct clk {
47 49
48 struct clk_ops *ops; 50 struct clk_ops *ops;
49 int (*enable)(struct clk *, int enable); 51 int (*enable)(struct clk *, int enable);
52 struct clk_lookup lookup;
50#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) 53#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
51 struct dentry *dent; /* For visible tree hierarchy */ 54 struct dentry *dent; /* For visible tree hierarchy */
52#endif 55#endif
diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c
index 46c9381e083b..f1bba88ed2f5 100644
--- a/arch/arm/plat-samsung/pwm-clock.c
+++ b/arch/arm/plat-samsung/pwm-clock.c
@@ -268,6 +268,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
268 [0] = { 268 [0] = {
269 .clk = { 269 .clk = {
270 .name = "pwm-tdiv", 270 .name = "pwm-tdiv",
271 .devname = "s3c24xx-pwm.0",
271 .ops = &clk_tdiv_ops, 272 .ops = &clk_tdiv_ops,
272 .parent = &clk_timer_scaler[0], 273 .parent = &clk_timer_scaler[0],
273 }, 274 },
@@ -275,6 +276,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
275 [1] = { 276 [1] = {
276 .clk = { 277 .clk = {
277 .name = "pwm-tdiv", 278 .name = "pwm-tdiv",
279 .devname = "s3c24xx-pwm.1",
278 .ops = &clk_tdiv_ops, 280 .ops = &clk_tdiv_ops,
279 .parent = &clk_timer_scaler[0], 281 .parent = &clk_timer_scaler[0],
280 } 282 }
@@ -282,6 +284,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
282 [2] = { 284 [2] = {
283 .clk = { 285 .clk = {
284 .name = "pwm-tdiv", 286 .name = "pwm-tdiv",
287 .devname = "s3c24xx-pwm.2",
285 .ops = &clk_tdiv_ops, 288 .ops = &clk_tdiv_ops,
286 .parent = &clk_timer_scaler[1], 289 .parent = &clk_timer_scaler[1],
287 }, 290 },
@@ -289,6 +292,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
289 [3] = { 292 [3] = {
290 .clk = { 293 .clk = {
291 .name = "pwm-tdiv", 294 .name = "pwm-tdiv",
295 .devname = "s3c24xx-pwm.3",
292 .ops = &clk_tdiv_ops, 296 .ops = &clk_tdiv_ops,
293 .parent = &clk_timer_scaler[1], 297 .parent = &clk_timer_scaler[1],
294 }, 298 },
@@ -296,6 +300,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
296 [4] = { 300 [4] = {
297 .clk = { 301 .clk = {
298 .name = "pwm-tdiv", 302 .name = "pwm-tdiv",
303 .devname = "s3c24xx-pwm.4",
299 .ops = &clk_tdiv_ops, 304 .ops = &clk_tdiv_ops,
300 .parent = &clk_timer_scaler[1], 305 .parent = &clk_timer_scaler[1],
301 }, 306 },
@@ -361,26 +366,31 @@ static struct clk_ops clk_tin_ops = {
361static struct clk clk_tin[] = { 366static struct clk clk_tin[] = {
362 [0] = { 367 [0] = {
363 .name = "pwm-tin", 368 .name = "pwm-tin",
369 .devname = "s3c24xx-pwm.0",
364 .id = 0, 370 .id = 0,
365 .ops = &clk_tin_ops, 371 .ops = &clk_tin_ops,
366 }, 372 },
367 [1] = { 373 [1] = {
368 .name = "pwm-tin", 374 .name = "pwm-tin",
375 .devname = "s3c24xx-pwm.1",
369 .id = 1, 376 .id = 1,
370 .ops = &clk_tin_ops, 377 .ops = &clk_tin_ops,
371 }, 378 },
372 [2] = { 379 [2] = {
373 .name = "pwm-tin", 380 .name = "pwm-tin",
381 .devname = "s3c24xx-pwm.2",
374 .id = 2, 382 .id = 2,
375 .ops = &clk_tin_ops, 383 .ops = &clk_tin_ops,
376 }, 384 },
377 [3] = { 385 [3] = {
378 .name = "pwm-tin", 386 .name = "pwm-tin",
387 .devname = "s3c24xx-pwm.3",
379 .id = 3, 388 .id = 3,
380 .ops = &clk_tin_ops, 389 .ops = &clk_tin_ops,
381 }, 390 },
382 [4] = { 391 [4] = {
383 .name = "pwm-tin", 392 .name = "pwm-tin",
393 .devname = "s3c24xx-pwm.4",
384 .id = 4, 394 .id = 4,
385 .ops = &clk_tin_ops, 395 .ops = &clk_tin_ops,
386 }, 396 },
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
index 2231d80ad817..e3bb806bbafe 100644
--- a/arch/arm/plat-samsung/time.c
+++ b/arch/arm/plat-samsung/time.c
@@ -259,6 +259,8 @@ static void __init s3c2410_timer_resources(void)
259 clk_enable(timerclk); 259 clk_enable(timerclk);
260 260
261 if (!use_tclk1_12()) { 261 if (!use_tclk1_12()) {
262 tmpdev.id = 4;
263 tmpdev.dev.init_name = "s3c24xx-pwm.4";
262 tin = clk_get(&tmpdev.dev, "pwm-tin"); 264 tin = clk_get(&tmpdev.dev, "pwm-tin");
263 if (IS_ERR(tin)) 265 if (IS_ERR(tin))
264 panic("failed to get pwm-tin clock for system timer"); 266 panic("failed to get pwm-tin clock for system timer");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 15:48:32 -0500