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authorKukjin Kim <kgene.kim@samsung.com>2011-01-04 04:27:18 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-01-04 04:27:18 -0500
commitcdb216de6e3291493f6bd033f2eec49c80dc8015 (patch)
treea0904726b94fdfed6faf137d15d355f3a0ff92af /arch/arm
parent387c31c7e5c9805b0aef8833d1731a5fe7bdea14 (diff)
ARM: S3C64XX: Tidy register and disable clock usage
This patch changes the clock registration code to use the s3c_register_clocks() followed by s3c_disable_clocks() instead of the loops it was using. Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-s3c64xx/clock.c19
1 files changed, 3 insertions, 16 deletions
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 7e03f0ae2fc8..487dfb95d609 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -127,7 +127,7 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
127 return s3c64xx_gate(S3C_SCLK_GATE, clk, enable); 127 return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
128} 128}
129 129
130static struct clk init_clocks_disable[] = { 130static struct clk init_clocks_off[] = {
131 { 131 {
132 .name = "nand", 132 .name = "nand",
133 .id = -1, 133 .id = -1,
@@ -834,10 +834,6 @@ static struct clk *clks[] __initdata = {
834void __init s3c64xx_register_clocks(unsigned long xtal, 834void __init s3c64xx_register_clocks(unsigned long xtal,
835 unsigned armclk_divlimit) 835 unsigned armclk_divlimit)
836{ 836{
837 struct clk *clkp;
838 int ret;
839 int ptr;
840
841 armclk_mask = armclk_divlimit; 837 armclk_mask = armclk_divlimit;
842 838
843 s3c24xx_register_baseclocks(xtal); 839 s3c24xx_register_baseclocks(xtal);
@@ -845,17 +841,8 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
845 841
846 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 842 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
847 843
848 clkp = init_clocks_disable; 844 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
849 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { 845 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
850
851 ret = s3c24xx_register_clock(clkp);
852 if (ret < 0) {
853 printk(KERN_ERR "Failed to register clock %s (%d)\n",
854 clkp->name, ret);
855 }
856
857 (clkp->enable)(clkp, 0);
858 }
859 846
860 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); 847 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
861 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 848 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));