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authorRajendra Nayak <rnayak@ti.com>2008-09-26 08:18:31 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2009-11-11 17:40:13 -0500
commitc171a2586161c623253186c394ca456947ec6a66 (patch)
treeda1436fddd64c7a4f0aaeaa6da2a0aab8a648745 /arch/arm
parent0addd61bc2028842bdcbd92c622d1110fc29c5a3 (diff)
OMAP3: PM: PRCM context save/restore
Add context save and restore for PRCM module to support off-mode. Additional registers (CM_CLKSEL4, CM_CLKEN, CM_CLKEN2) added by Tero Kristo. Missing CM_CLKEN_PLL_IVA2 register added by Kalle Jokiniemi. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/prcm.c389
-rw-r--r--arch/arm/plat-omap/include/plat/control.h2
-rw-r--r--arch/arm/plat-omap/include/plat/prcm.h6
3 files changed, 396 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index b0d3ad05be2e..56f77df1ffac 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -7,6 +7,9 @@
7 * 7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 * 9 *
10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
10 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc. 13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
11 * 14 *
12 * This program is free software; you can redistribute it and/or modify 15 * This program is free software; you can redistribute it and/or modify
@@ -21,8 +24,11 @@
21 24
22#include <plat/common.h> 25#include <plat/common.h>
23#include <plat/prcm.h> 26#include <plat/prcm.h>
27#include <plat/irqs.h>
28#include <plat/control.h>
24 29
25#include "clock.h" 30#include "clock.h"
31#include "cm.h"
26#include "prm.h" 32#include "prm.h"
27#include "prm-regbits-24xx.h" 33#include "prm-regbits-24xx.h"
28 34
@@ -31,6 +37,88 @@ static void __iomem *cm_base;
31 37
32#define MAX_MODULE_ENABLE_WAIT 100000 38#define MAX_MODULE_ENABLE_WAIT 100000
33 39
40struct omap3_prcm_regs {
41 u32 control_padconf_sys_nirq;
42 u32 iva2_cm_clksel2;
43 u32 cm_sysconfig;
44 u32 sgx_cm_clksel;
45 u32 wkup_cm_clksel;
46 u32 dss_cm_clksel;
47 u32 cam_cm_clksel;
48 u32 per_cm_clksel;
49 u32 emu_cm_clksel;
50 u32 emu_cm_clkstctrl;
51 u32 pll_cm_autoidle2;
52 u32 pll_cm_clksel4;
53 u32 pll_cm_clksel5;
54 u32 pll_cm_clken;
55 u32 pll_cm_clken2;
56 u32 cm_polctrl;
57 u32 iva2_cm_fclken;
58 u32 iva2_cm_clken_pll;
59 u32 core_cm_fclken1;
60 u32 core_cm_fclken3;
61 u32 sgx_cm_fclken;
62 u32 wkup_cm_fclken;
63 u32 dss_cm_fclken;
64 u32 cam_cm_fclken;
65 u32 per_cm_fclken;
66 u32 usbhost_cm_fclken;
67 u32 core_cm_iclken1;
68 u32 core_cm_iclken2;
69 u32 core_cm_iclken3;
70 u32 sgx_cm_iclken;
71 u32 wkup_cm_iclken;
72 u32 dss_cm_iclken;
73 u32 cam_cm_iclken;
74 u32 per_cm_iclken;
75 u32 usbhost_cm_iclken;
76 u32 iva2_cm_autiidle2;
77 u32 mpu_cm_autoidle2;
78 u32 pll_cm_autoidle;
79 u32 iva2_cm_clkstctrl;
80 u32 mpu_cm_clkstctrl;
81 u32 core_cm_clkstctrl;
82 u32 sgx_cm_clkstctrl;
83 u32 dss_cm_clkstctrl;
84 u32 cam_cm_clkstctrl;
85 u32 per_cm_clkstctrl;
86 u32 neon_cm_clkstctrl;
87 u32 usbhost_cm_clkstctrl;
88 u32 core_cm_autoidle1;
89 u32 core_cm_autoidle2;
90 u32 core_cm_autoidle3;
91 u32 wkup_cm_autoidle;
92 u32 dss_cm_autoidle;
93 u32 cam_cm_autoidle;
94 u32 per_cm_autoidle;
95 u32 usbhost_cm_autoidle;
96 u32 sgx_cm_sleepdep;
97 u32 dss_cm_sleepdep;
98 u32 cam_cm_sleepdep;
99 u32 per_cm_sleepdep;
100 u32 usbhost_cm_sleepdep;
101 u32 cm_clkout_ctrl;
102 u32 prm_clkout_ctrl;
103 u32 sgx_pm_wkdep;
104 u32 dss_pm_wkdep;
105 u32 cam_pm_wkdep;
106 u32 per_pm_wkdep;
107 u32 neon_pm_wkdep;
108 u32 usbhost_pm_wkdep;
109 u32 core_pm_mpugrpsel1;
110 u32 iva2_pm_ivagrpsel1;
111 u32 core_pm_mpugrpsel3;
112 u32 core_pm_ivagrpsel3;
113 u32 wkup_pm_mpugrpsel;
114 u32 wkup_pm_ivagrpsel;
115 u32 per_pm_mpugrpsel;
116 u32 per_pm_ivagrpsel;
117 u32 wkup_pm_wken;
118};
119
120struct omap3_prcm_regs prcm_context;
121
34u32 omap_prcm_get_reset_sources(void) 122u32 omap_prcm_get_reset_sources(void)
35{ 123{
36 /* XXX This presumably needs modification for 34XX */ 124 /* XXX This presumably needs modification for 34XX */
@@ -168,3 +256,304 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
168 prm_base = omap2_globals->prm; 256 prm_base = omap2_globals->prm;
169 cm_base = omap2_globals->cm; 257 cm_base = omap2_globals->cm;
170} 258}
259
260#ifdef CONFIG_ARCH_OMAP3
261void omap3_prcm_save_context(void)
262{
263 prcm_context.control_padconf_sys_nirq =
264 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
265 prcm_context.iva2_cm_clksel2 =
266 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
267 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
268 prcm_context.sgx_cm_clksel =
269 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
270 prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
271 prcm_context.dss_cm_clksel =
272 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
273 prcm_context.cam_cm_clksel =
274 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
275 prcm_context.per_cm_clksel =
276 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
277 prcm_context.emu_cm_clksel =
278 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
279 prcm_context.emu_cm_clkstctrl =
280 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL);
281 prcm_context.pll_cm_autoidle2 =
282 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
283 prcm_context.pll_cm_clksel4 =
284 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
285 prcm_context.pll_cm_clksel5 =
286 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
287 prcm_context.pll_cm_clken =
288 cm_read_mod_reg(PLL_MOD, CM_CLKEN);
289 prcm_context.pll_cm_clken2 =
290 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
291 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
292 prcm_context.iva2_cm_fclken =
293 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
294 prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
295 OMAP3430_CM_CLKEN_PLL);
296 prcm_context.core_cm_fclken1 =
297 cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
298 prcm_context.core_cm_fclken3 =
299 cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
300 prcm_context.sgx_cm_fclken =
301 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
302 prcm_context.wkup_cm_fclken =
303 cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
304 prcm_context.dss_cm_fclken =
305 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
306 prcm_context.cam_cm_fclken =
307 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
308 prcm_context.per_cm_fclken =
309 cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
310 prcm_context.usbhost_cm_fclken =
311 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
312 prcm_context.core_cm_iclken1 =
313 cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
314 prcm_context.core_cm_iclken2 =
315 cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
316 prcm_context.core_cm_iclken3 =
317 cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
318 prcm_context.sgx_cm_iclken =
319 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
320 prcm_context.wkup_cm_iclken =
321 cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
322 prcm_context.dss_cm_iclken =
323 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
324 prcm_context.cam_cm_iclken =
325 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
326 prcm_context.per_cm_iclken =
327 cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
328 prcm_context.usbhost_cm_iclken =
329 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
330 prcm_context.iva2_cm_autiidle2 =
331 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
332 prcm_context.mpu_cm_autoidle2 =
333 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
334 prcm_context.pll_cm_autoidle =
335 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
336 prcm_context.iva2_cm_clkstctrl =
337 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
338 prcm_context.mpu_cm_clkstctrl =
339 cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL);
340 prcm_context.core_cm_clkstctrl =
341 cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL);
342 prcm_context.sgx_cm_clkstctrl =
343 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL);
344 prcm_context.dss_cm_clkstctrl =
345 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL);
346 prcm_context.cam_cm_clkstctrl =
347 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL);
348 prcm_context.per_cm_clkstctrl =
349 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL);
350 prcm_context.neon_cm_clkstctrl =
351 cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL);
352 prcm_context.usbhost_cm_clkstctrl =
353 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
354 prcm_context.core_cm_autoidle1 =
355 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
356 prcm_context.core_cm_autoidle2 =
357 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
358 prcm_context.core_cm_autoidle3 =
359 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
360 prcm_context.wkup_cm_autoidle =
361 cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
362 prcm_context.dss_cm_autoidle =
363 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
364 prcm_context.cam_cm_autoidle =
365 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
366 prcm_context.per_cm_autoidle =
367 cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
368 prcm_context.usbhost_cm_autoidle =
369 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
370 prcm_context.sgx_cm_sleepdep =
371 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
372 prcm_context.dss_cm_sleepdep =
373 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
374 prcm_context.cam_cm_sleepdep =
375 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
376 prcm_context.per_cm_sleepdep =
377 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
378 prcm_context.usbhost_cm_sleepdep =
379 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
380 prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
381 OMAP3_CM_CLKOUT_CTRL_OFFSET);
382 prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
383 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
384 prcm_context.sgx_pm_wkdep =
385 prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
386 prcm_context.dss_pm_wkdep =
387 prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
388 prcm_context.cam_pm_wkdep =
389 prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
390 prcm_context.per_pm_wkdep =
391 prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
392 prcm_context.neon_pm_wkdep =
393 prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
394 prcm_context.usbhost_pm_wkdep =
395 prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
396 prcm_context.core_pm_mpugrpsel1 =
397 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
398 prcm_context.iva2_pm_ivagrpsel1 =
399 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
400 prcm_context.core_pm_mpugrpsel3 =
401 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
402 prcm_context.core_pm_ivagrpsel3 =
403 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
404 prcm_context.wkup_pm_mpugrpsel =
405 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
406 prcm_context.wkup_pm_ivagrpsel =
407 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
408 prcm_context.per_pm_mpugrpsel =
409 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
410 prcm_context.per_pm_ivagrpsel =
411 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
412 prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
413 return;
414}
415
416void omap3_prcm_restore_context(void)
417{
418 omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
419 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
420 cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
421 CM_CLKSEL2);
422 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
423 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
424 CM_CLKSEL);
425 cm_write_mod_reg(prcm_context.wkup_cm_clksel, WKUP_MOD, CM_CLKSEL);
426 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
427 CM_CLKSEL);
428 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
429 CM_CLKSEL);
430 cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
431 CM_CLKSEL);
432 cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
433 CM_CLKSEL1);
434 cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
435 CM_CLKSTCTRL);
436 cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
437 CM_AUTOIDLE2);
438 cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
439 OMAP3430ES2_CM_CLKSEL4);
440 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
441 OMAP3430ES2_CM_CLKSEL5);
442 cm_write_mod_reg(prcm_context.pll_cm_clken, PLL_MOD, CM_CLKEN);
443 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
444 OMAP3430ES2_CM_CLKEN2);
445 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
446 cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
447 CM_FCLKEN);
448 cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
449 OMAP3430_CM_CLKEN_PLL);
450 cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
451 cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
452 OMAP3430ES2_CM_FCLKEN3);
453 cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
454 CM_FCLKEN);
455 cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
456 cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
457 CM_FCLKEN);
458 cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
459 CM_FCLKEN);
460 cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
461 CM_FCLKEN);
462 cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
463 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
464 cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
465 cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
466 cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
467 cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
468 CM_ICLKEN);
469 cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
470 cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
471 CM_ICLKEN);
472 cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
473 CM_ICLKEN);
474 cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
475 CM_ICLKEN);
476 cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
477 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
478 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
479 CM_AUTOIDLE2);
480 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
481 cm_write_mod_reg(prcm_context.pll_cm_autoidle, PLL_MOD, CM_AUTOIDLE);
482 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
483 CM_CLKSTCTRL);
484 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
485 cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
486 CM_CLKSTCTRL);
487 cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
488 CM_CLKSTCTRL);
489 cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
490 CM_CLKSTCTRL);
491 cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
492 CM_CLKSTCTRL);
493 cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
494 CM_CLKSTCTRL);
495 cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
496 CM_CLKSTCTRL);
497 cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
498 OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
499 cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
500 CM_AUTOIDLE1);
501 cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
502 CM_AUTOIDLE2);
503 cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
504 CM_AUTOIDLE3);
505 cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
506 cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
507 CM_AUTOIDLE);
508 cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
509 CM_AUTOIDLE);
510 cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
511 CM_AUTOIDLE);
512 cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
513 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
514 cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
515 OMAP3430_CM_SLEEPDEP);
516 cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
517 OMAP3430_CM_SLEEPDEP);
518 cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
519 OMAP3430_CM_SLEEPDEP);
520 cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
521 OMAP3430_CM_SLEEPDEP);
522 cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
523 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
524 cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
525 OMAP3_CM_CLKOUT_CTRL_OFFSET);
526 prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
527 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
528 prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
529 PM_WKDEP);
530 prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
531 PM_WKDEP);
532 prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
533 PM_WKDEP);
534 prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
535 PM_WKDEP);
536 prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
537 PM_WKDEP);
538 prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
539 OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
540 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
541 OMAP3430_PM_MPUGRPSEL1);
542 prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
543 OMAP3430_PM_IVAGRPSEL1);
544 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
545 OMAP3430ES2_PM_MPUGRPSEL3);
546 prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
547 OMAP3430ES2_PM_IVAGRPSEL3);
548 prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
549 OMAP3430_PM_MPUGRPSEL);
550 prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
551 OMAP3430_PM_IVAGRPSEL);
552 prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
553 OMAP3430_PM_MPUGRPSEL);
554 prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
555 OMAP3430_PM_IVAGRPSEL);
556 prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
557 return;
558}
559#endif
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 805819f3a868..835f5b7aa4b6 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -112,6 +112,8 @@
112#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) 112#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
113#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) 113#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
114 114
115#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
116
115/* 34xx-only CONTROL_GENERAL register offsets */ 117/* 34xx-only CONTROL_GENERAL register offsets */
116#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) 118#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
117#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) 119#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index cda2a70397b4..e63e94e18975 100644
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -27,9 +27,13 @@ u32 omap_prcm_get_reset_sources(void);
27void omap_prcm_arch_reset(char mode); 27void omap_prcm_arch_reset(char mode);
28int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name); 28int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
29 29
30#endif 30#define START_PADCONF_SAVE 0x2
31#define PADCONF_SAVE_DONE 0x1
31 32
33void omap3_prcm_save_context(void);
34void omap3_prcm_restore_context(void);
32 35
36#endif
33 37
34 38
35 39
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 13:15:25 -0400