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authorSascha Hauer <s.hauer@pengutronix.de>2009-02-02 08:11:54 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2009-03-13 05:34:25 -0400
commitc0a5f85523132dc893916d6059370233fac1cb11 (patch)
tree463817508d7fd36af4f7bed7285826f08569bd9d /arch/arm
parent7e8549bcee00d92040904361cb1840c7a5eda615 (diff)
[ARM] MX35: Add register definitions for the i.MX35
This patch moves the stuff common to i.MX31 and i.MX35 to mx3x.h and the specifics to mx31.h/mx35.h. We can build a kernel which runs on i.MX31 and i.MX35, so always include mx31.h and mx35.h Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h329
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h29
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h290
4 files changed, 329 insertions, 323 deletions
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 11f5727ea445..42e4ee37ca1f 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -23,7 +23,9 @@
23#include <asm/sizes.h> 23#include <asm/sizes.h>
24 24
25#ifdef CONFIG_ARCH_MX3 25#ifdef CONFIG_ARCH_MX3
26# include <mach/mx31.h> 26#include <mach/mx3x.h>
27#include <mach/mx31.h>
28#include <mach/mx35.h>
27#endif 29#endif
28 30
29#ifdef CONFIG_ARCH_MX2 31#ifdef CONFIG_ARCH_MX2
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index de026654b00e..0b06941b6139 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -1,360 +1,45 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_MX31_H__
12#define __ASM_ARCH_MXC_MX31_H__
13
14#ifndef __ASM_ARCH_MXC_HARDWARE_H__
15#error "Do not include directly."
16#endif
17
18/*
19 * MX31 memory map:
20 *
21 * Virt Phys Size What
22 * ---------------------------------------------------------------------------
23 * F8000000 1FFC0000 16K IRAM
24 * F9000000 30000000 256M L2CC
25 * FC000000 43F00000 1M AIPS 1
26 * FC100000 50000000 1M SPBA
27 * FC200000 53F00000 1M AIPS 2
28 * FC500000 60000000 128M ROMPATCH
29 * FC400000 68000000 128M AVIC
30 * 70000000 256M IPU (MAX M2)
31 * 80000000 256M CSD0 SDRAM/DDR
32 * 90000000 256M CSD1 SDRAM/DDR
33 * A0000000 128M CS0 Flash
34 * A8000000 128M CS1 Flash
35 * B0000000 32M CS2
36 * B2000000 32M CS3
37 * F4000000 B4000000 32M CS4
38 * B6000000 32M CS5
39 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
40 * C0000000 64M PCMCIA/CF
41 */
42
43#define CS0_BASE_ADDR 0xA0000000
44#define CS1_BASE_ADDR 0xA8000000
45#define CS2_BASE_ADDR 0xB0000000
46#define CS3_BASE_ADDR 0xB2000000
47
48#define CS4_BASE_ADDR 0xB4000000
49#define CS4_BASE_ADDR_VIRT 0xF4000000
50#define CS4_SIZE SZ_32M
51
52#define CS5_BASE_ADDR 0xB6000000
53#define PCMCIA_MEM_BASE_ADDR 0xBC000000
54
55/*
56 * IRAM 2 * IRAM
57 */ 3 */
58#define IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ 4#define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
59#define IRAM_BASE_ADDR_VIRT 0xF8000000 5#define MX31_IRAM_SIZE SZ_16K
60#define IRAM_SIZE SZ_16K
61
62/*
63 * L2CC
64 */
65#define L2CC_BASE_ADDR 0x30000000
66#define L2CC_BASE_ADDR_VIRT 0xF9000000
67#define L2CC_SIZE SZ_1M
68
69/*
70 * AIPS 1
71 */
72#define AIPS1_BASE_ADDR 0x43F00000
73#define AIPS1_BASE_ADDR_VIRT 0xFC000000
74#define AIPS1_SIZE SZ_1M
75 6
76#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
77#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
78#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
79#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
80#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
81#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
82#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
83#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
84#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) 7#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
85#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) 8#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
86#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
87#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
88#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
89#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
90#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
91#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
92#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
93#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
94#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) 9#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
95#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) 10#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
96#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
97#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
98
99/*
100 * SPBA global module enabled #0
101 */
102#define SPBA0_BASE_ADDR 0x50000000
103#define SPBA0_BASE_ADDR_VIRT 0xFC100000
104#define SPBA0_SIZE SZ_1M
105 11
106#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) 12#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
107#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) 13#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
108#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
109#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
110#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
111#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) 14#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
112#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000) 15#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000)
113#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
114#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
115#define MSHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
116#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
117 16
118/*
119 * AIPS 2
120 */
121#define AIPS2_BASE_ADDR 0x53F00000
122#define AIPS2_BASE_ADDR_VIRT 0xFC200000
123#define AIPS2_SIZE SZ_1M
124#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
125#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) 17#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
126#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) 18#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
127#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
128#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
129#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
130#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
131#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
132#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000) 19#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000)
133#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000) 20#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000)
134#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
135#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
136#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
137#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) 21#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
138#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
139#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
140#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
141#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
142#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
143#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
144#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
145
146/*
147 * ROMP and AVIC
148 */
149#define ROMP_BASE_ADDR 0x60000000
150#define ROMP_BASE_ADDR_VIRT 0xFC500000
151#define ROMP_SIZE SZ_1M
152
153#define AVIC_BASE_ADDR 0x68000000
154#define AVIC_BASE_ADDR_VIRT 0xFC400000
155#define AVIC_SIZE SZ_1M
156
157/*
158 * NAND, SDRAM, WEIM, M3IF, EMI controllers
159 */
160#define X_MEMC_BASE_ADDR 0xB8000000
161#define X_MEMC_BASE_ADDR_VIRT 0xFC320000
162#define X_MEMC_SIZE SZ_64K
163 22
164#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) 23#define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
165#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
166#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
167#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
168#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
169#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
170 24
171/*
172 * Memory regions and CS
173 */
174#define IPU_MEM_BASE_ADDR 0x70000000
175#define CSD0_BASE_ADDR 0x80000000
176#define CSD1_BASE_ADDR 0x90000000
177#define CS0_BASE_ADDR 0xA0000000
178#define CS1_BASE_ADDR 0xA8000000
179#define CS2_BASE_ADDR 0xB0000000
180#define CS3_BASE_ADDR 0xB2000000
181
182#define CS4_BASE_ADDR 0xB4000000
183#define CS4_BASE_ADDR_VIRT 0xF4000000
184#define CS4_SIZE SZ_32M
185
186#define CS5_BASE_ADDR 0xB6000000
187#define PCMCIA_MEM_BASE_ADDR 0xBC000000
188
189/*!
190 * This macro defines the physical to virtual address mapping for all the
191 * peripheral modules. It is used by passing in the physical address as x
192 * and returning the virtual address. If the physical address is not mapped,
193 * it returns 0xDEADBEEF
194 */
195#define IO_ADDRESS(x) \
196 (void __iomem *) \
197 (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
198 ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
199 ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
200 ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
201 ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
202 ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
203 ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
204 ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
205 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
206 0xDEADBEEF)
207
208/*
209 * define the address mapping macros: in physical address order
210 */
211
212#define IRAM_IO_ADDRESS(x) \
213 (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT)
214
215#define L2CC_IO_ADDRESS(x) \
216 (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
217
218#define AIPS1_IO_ADDRESS(x) \
219 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
220
221#define SPBA0_IO_ADDRESS(x) \
222 (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
223
224#define AIPS2_IO_ADDRESS(x) \
225 (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
226
227#define ROMP_IO_ADDRESS(x) \
228 (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
229
230#define AVIC_IO_ADDRESS(x) \
231 (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
232
233#define CS4_IO_ADDRESS(x) \
234 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
235
236#define X_MEMC_IO_ADDRESS(x) \
237 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
238
239#define PCMCIA_IO_ADDRESS(x) \
240 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
241
242/*
243 * Interrupt numbers
244 */
245#define MXC_INT_PEN_ADS7843 0
246#define MXC_INT_RESV1 1
247#define MXC_INT_CS8900A 2
248#define MXC_INT_I2C3 3
249#define MXC_INT_I2C2 4
250#define MXC_INT_MPEG4_ENCODER 5 25#define MXC_INT_MPEG4_ENCODER 5
251#define MXC_INT_RTIC 6
252#define MXC_INT_FIRI 7 26#define MXC_INT_FIRI 7
253#define MXC_INT_MMC_SDHC2 8 27#define MX31_INT_MMC_SDHC2 8
254#define MXC_INT_MMC_SDHC1 9 28#define MXC_INT_MMC_SDHC1 9
255#define MXC_INT_I2C 10 29#define MX31_INT_SSI2 11
256#define MXC_INT_SSI2 11 30#define MX31_INT_SSI1 12
257#define MXC_INT_SSI1 12
258#define MXC_INT_CSPI2 13
259#define MXC_INT_CSPI1 14
260#define MXC_INT_ATA 15
261#define MXC_INT_MBX 16 31#define MXC_INT_MBX 16
262#define MXC_INT_CSPI3 17 32#define MXC_INT_CSPI3 17
263#define MXC_INT_UART3 18
264#define MXC_INT_IIM 19
265#define MXC_INT_SIM2 20 33#define MXC_INT_SIM2 20
266#define MXC_INT_SIM1 21 34#define MXC_INT_SIM1 21
267#define MXC_INT_RNGA 22 35#define MXC_INT_CCM_DVFS 31
268#define MXC_INT_EVTMON 23
269#define MXC_INT_KPP 24
270#define MXC_INT_RTC 25
271#define MXC_INT_PWM 26
272#define MXC_INT_EPIT2 27
273#define MXC_INT_EPIT1 28
274#define MXC_INT_GPT 29
275#define MXC_INT_RESV30 30
276#define MXC_INT_RESV31 31
277#define MXC_INT_UART2 32
278#define MXC_INT_NANDFC 33
279#define MXC_INT_SDMA 34
280#define MXC_INT_USB1 35 36#define MXC_INT_USB1 35
281#define MXC_INT_USB2 36 37#define MXC_INT_USB2 36
282#define MXC_INT_USB3 37 38#define MXC_INT_USB3 37
283#define MXC_INT_USB4 38 39#define MXC_INT_USB4 38
284#define MXC_INT_MSHC1 39
285#define MXC_INT_MSHC2 40 40#define MXC_INT_MSHC2 40
286#define MXC_INT_IPU_ERR 41
287#define MXC_INT_IPU_SYN 42
288#define MXC_INT_RESV43 43
289#define MXC_INT_RESV44 44
290#define MXC_INT_UART1 45
291#define MXC_INT_UART4 46 41#define MXC_INT_UART4 46
292#define MXC_INT_UART5 47 42#define MXC_INT_UART5 47
293#define MXC_INT_ECT 48
294#define MXC_INT_SCC_SCM 49
295#define MXC_INT_SCC_SMN 50
296#define MXC_INT_GPIO2 51
297#define MXC_INT_GPIO1 52
298#define MXC_INT_CCM 53 43#define MXC_INT_CCM 53
299#define MXC_INT_PCMCIA 54 44#define MXC_INT_PCMCIA 54
300#define MXC_INT_WDOG 55
301#define MXC_INT_GPIO3 56
302#define MXC_INT_RESV57 57
303#define MXC_INT_EXT_POWER 58
304#define MXC_INT_EXT_TEMPER 59
305#define MXC_INT_EXT_SENSOR60 60
306#define MXC_INT_EXT_SENSOR61 61
307#define MXC_INT_EXT_WDOG 62
308#define MXC_INT_EXT_TV 63
309
310#define PROD_SIGNATURE 0x1 /* For MX31 */
311
312/* silicon revisions specific to i.MX31 */
313#define CHIP_REV_1_0 0x10
314#define CHIP_REV_1_1 0x11
315#define CHIP_REV_1_2 0x12
316#define CHIP_REV_1_3 0x13
317#define CHIP_REV_2_0 0x20
318#define CHIP_REV_2_1 0x21
319#define CHIP_REV_2_2 0x22
320#define CHIP_REV_2_3 0x23
321#define CHIP_REV_3_0 0x30
322#define CHIP_REV_3_1 0x31
323#define CHIP_REV_3_2 0x32
324
325#define SYSTEM_REV_MIN CHIP_REV_1_0
326#define SYSTEM_REV_NUM 3
327
328/* gpio and gpio based interrupt handling */
329#define GPIO_DR 0x00
330#define GPIO_GDIR 0x04
331#define GPIO_PSR 0x08
332#define GPIO_ICR1 0x0C
333#define GPIO_ICR2 0x10
334#define GPIO_IMR 0x14
335#define GPIO_ISR 0x18
336#define GPIO_INT_LOW_LEV 0x0
337#define GPIO_INT_HIGH_LEV 0x1
338#define GPIO_INT_RISE_EDGE 0x2
339#define GPIO_INT_FALL_EDGE 0x3
340#define GPIO_INT_NONE 0x4
341
342/* Mandatory defines used globally */
343
344/* this CPU supports up to 96 GPIOs */
345#define ARCH_NR_GPIOS 96
346
347#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
348
349/* this is a i.MX31 CPU */
350#define cpu_is_mx31() (1)
351
352extern unsigned int system_rev;
353
354static inline int mx31_revision(void)
355{
356 return system_rev;
357}
358#endif
359 45
360#endif /* __ASM_ARCH_MXC_MX31_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
new file mode 100644
index 000000000000..6465fefb42e3
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -0,0 +1,29 @@
1/*
2 * IRAM
3 */
4#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
5#define MX35_IRAM_SIZE SZ_128K
6
7#define MXC_FEC_BASE_ADDR 0x50038000
8#define MX35_NFC_BASE_ADDR 0xBB000000
9
10/*
11 * Interrupt numbers
12 */
13#define MXC_INT_OWIRE 2
14#define MX35_INT_MMC_SDHC1 7
15#define MXC_INT_MMC_SDHC2 8
16#define MXC_INT_MMC_SDHC3 9
17#define MX35_INT_SSI1 11
18#define MX35_INT_SSI2 12
19#define MXC_INT_GPU2D 16
20#define MXC_INT_ASRC 17
21#define MXC_INT_USBHS 35
22#define MXC_INT_USBOTG 37
23#define MXC_INT_ESAI 40
24#define MXC_INT_CAN1 43
25#define MXC_INT_CAN2 44
26#define MXC_INT_MLB 46
27#define MXC_INT_SPDIF 47
28#define MXC_INT_FEC 57
29
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
new file mode 100644
index 000000000000..83a172b51b05
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -0,0 +1,290 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_MX31_H__
12#define __ASM_ARCH_MXC_MX31_H__
13
14#ifndef __ASM_ARCH_MXC_HARDWARE_H__
15#error "Do not include directly."
16#endif
17
18/*
19 * MX31 memory map:
20 *
21 * Virt Phys Size What
22 * ---------------------------------------------------------------------------
23 * FC000000 43F00000 1M AIPS 1
24 * FC100000 50000000 1M SPBA
25 * FC200000 53F00000 1M AIPS 2
26 * FC500000 60000000 128M ROMPATCH
27 * FC400000 68000000 128M AVIC
28 * 70000000 256M IPU (MAX M2)
29 * 80000000 256M CSD0 SDRAM/DDR
30 * 90000000 256M CSD1 SDRAM/DDR
31 * A0000000 128M CS0 Flash
32 * A8000000 128M CS1 Flash
33 * B0000000 32M CS2
34 * B2000000 32M CS3
35 * F4000000 B4000000 32M CS4
36 * B6000000 32M CS5
37 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
38 * C0000000 64M PCMCIA/CF
39 */
40
41#define CS0_BASE_ADDR 0xA0000000
42#define CS1_BASE_ADDR 0xA8000000
43#define CS2_BASE_ADDR 0xB0000000
44#define CS3_BASE_ADDR 0xB2000000
45
46#define CS4_BASE_ADDR 0xB4000000
47#define CS4_BASE_ADDR_VIRT 0xF4000000
48#define CS4_SIZE SZ_32M
49
50#define CS5_BASE_ADDR 0xB6000000
51#define PCMCIA_MEM_BASE_ADDR 0xBC000000
52
53/*
54 * L2CC
55 */
56#define L2CC_BASE_ADDR 0x30000000
57#define L2CC_SIZE SZ_1M
58
59/*
60 * AIPS 1
61 */
62#define AIPS1_BASE_ADDR 0x43F00000
63#define AIPS1_BASE_ADDR_VIRT 0xFC000000
64#define AIPS1_SIZE SZ_1M
65
66#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
67#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
68#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
69#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
70#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
71#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
72#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
73#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
74#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
75#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
76#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
77#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
78#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
79#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
80#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
81#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
82#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
83#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
84
85/*
86 * SPBA global module enabled #0
87 */
88#define SPBA0_BASE_ADDR 0x50000000
89#define SPBA0_BASE_ADDR_VIRT 0xFC100000
90#define SPBA0_SIZE SZ_1M
91
92#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
93#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
94#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
95#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
96#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
97#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
98
99/*
100 * AIPS 2
101 */
102#define AIPS2_BASE_ADDR 0x53F00000
103#define AIPS2_BASE_ADDR_VIRT 0xFC200000
104#define AIPS2_SIZE SZ_1M
105#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
106#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
107#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
108#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
109#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
110#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
111#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
112#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
113#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
114#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
115#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
116#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
117#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
118#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
119#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
120#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
121
122/*
123 * ROMP and AVIC
124 */
125#define ROMP_BASE_ADDR 0x60000000
126#define ROMP_BASE_ADDR_VIRT 0xFC500000
127#define ROMP_SIZE SZ_1M
128
129#define AVIC_BASE_ADDR 0x68000000
130#define AVIC_BASE_ADDR_VIRT 0xFC400000
131#define AVIC_SIZE SZ_1M
132
133/*
134 * NAND, SDRAM, WEIM, M3IF, EMI controllers
135 */
136#define X_MEMC_BASE_ADDR 0xB8000000
137#define X_MEMC_BASE_ADDR_VIRT 0xFC320000
138#define X_MEMC_SIZE SZ_64K
139
140#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
141#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
142#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
143#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
144#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
145
146/*
147 * Memory regions and CS
148 */
149#define IPU_MEM_BASE_ADDR 0x70000000
150#define CSD0_BASE_ADDR 0x80000000
151#define CSD1_BASE_ADDR 0x90000000
152
153/*!
154 * This macro defines the physical to virtual address mapping for all the
155 * peripheral modules. It is used by passing in the physical address as x
156 * and returning the virtual address. If the physical address is not mapped,
157 * it returns 0xDEADBEEF
158 */
159#define IO_ADDRESS(x) \
160 (void __iomem *) \
161 (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
162 ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
163 ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
164 ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
165 ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
166 ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
167 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
168 0xDEADBEEF)
169
170/*
171 * define the address mapping macros: in physical address order
172 */
173#define L2CC_IO_ADDRESS(x) \
174 (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
175
176#define AIPS1_IO_ADDRESS(x) \
177 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
178
179#define SPBA0_IO_ADDRESS(x) \
180 (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
181
182#define AIPS2_IO_ADDRESS(x) \
183 (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
184
185#define ROMP_IO_ADDRESS(x) \
186 (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
187
188#define AVIC_IO_ADDRESS(x) \
189 (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
190
191#define CS4_IO_ADDRESS(x) \
192 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
193
194#define X_MEMC_IO_ADDRESS(x) \
195 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
196
197#define PCMCIA_IO_ADDRESS(x) \
198 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
199
200/*
201 * Interrupt numbers
202 */
203#define MXC_INT_I2C3 3
204#define MXC_INT_I2C2 4
205#define MXC_INT_RTIC 6
206#define MXC_INT_I2C 10
207#define MXC_INT_CSPI2 13
208#define MXC_INT_CSPI1 14
209#define MXC_INT_ATA 15
210#define MXC_INT_UART3 18
211#define MXC_INT_IIM 19
212#define MXC_INT_RNGA 22
213#define MXC_INT_EVTMON 23
214#define MXC_INT_KPP 24
215#define MXC_INT_RTC 25
216#define MXC_INT_PWM 26
217#define MXC_INT_EPIT2 27
218#define MXC_INT_EPIT1 28
219#define MXC_INT_GPT 29
220#define MXC_INT_POWER_FAIL 30
221#define MXC_INT_UART2 32
222#define MXC_INT_NANDFC 33
223#define MXC_INT_SDMA 34
224#define MXC_INT_MSHC1 39
225#define MXC_INT_IPU_ERR 41
226#define MXC_INT_IPU_SYN 42
227#define MXC_INT_UART1 45
228#define MXC_INT_ECT 48
229#define MXC_INT_SCC_SCM 49
230#define MXC_INT_SCC_SMN 50
231#define MXC_INT_GPIO2 51
232#define MXC_INT_GPIO1 52
233#define MXC_INT_WDOG 55
234#define MXC_INT_GPIO3 56
235#define MXC_INT_EXT_POWER 58
236#define MXC_INT_EXT_TEMPER 59
237#define MXC_INT_EXT_SENSOR60 60
238#define MXC_INT_EXT_SENSOR61 61
239#define MXC_INT_EXT_WDOG 62
240#define MXC_INT_EXT_TV 63
241
242#define PROD_SIGNATURE 0x1 /* For MX31 */
243
244/* silicon revisions specific to i.MX31 */
245#define CHIP_REV_1_0 0x10
246#define CHIP_REV_1_1 0x11
247#define CHIP_REV_1_2 0x12
248#define CHIP_REV_1_3 0x13
249#define CHIP_REV_2_0 0x20
250#define CHIP_REV_2_1 0x21
251#define CHIP_REV_2_2 0x22
252#define CHIP_REV_2_3 0x23
253#define CHIP_REV_3_0 0x30
254#define CHIP_REV_3_1 0x31
255#define CHIP_REV_3_2 0x32
256
257#define SYSTEM_REV_MIN CHIP_REV_1_0
258#define SYSTEM_REV_NUM 3
259
260/* gpio and gpio based interrupt handling */
261#define GPIO_DR 0x00
262#define GPIO_GDIR 0x04
263#define GPIO_PSR 0x08
264#define GPIO_ICR1 0x0C
265#define GPIO_ICR2 0x10
266#define GPIO_IMR 0x14
267#define GPIO_ISR 0x18
268#define GPIO_INT_LOW_LEV 0x0
269#define GPIO_INT_HIGH_LEV 0x1
270#define GPIO_INT_RISE_EDGE 0x2
271#define GPIO_INT_FALL_EDGE 0x3
272#define GPIO_INT_NONE 0x4
273
274/* Mandatory defines used globally */
275
276/* this CPU supports up to 96 GPIOs */
277#define ARCH_NR_GPIOS 96
278
279#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
280
281extern unsigned int system_rev;
282
283static inline int mx31_revision(void)
284{
285 return system_rev;
286}
287#endif
288
289#endif /* __ASM_ARCH_MXC_MX31_H__ */
290
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