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authorNicolas Ferre <nicolas.ferre@atmel.com>2014-11-26 11:25:24 -0500
committerNicolas Ferre <nicolas.ferre@atmel.com>2014-11-26 12:43:44 -0500
commitb31706a281c00beb6b49be90795dfcace51e734d (patch)
tree432875d4054fb68774e3854a86d27bc489e8554f /arch/arm
parentef7eda2cfed7b415b9872e8507ca4fde83dee53a (diff)
ARM: at91: remove clock data in at91sam9n12.c and at91sam9x5.c files
As the CONFIG_OLD_CLK_AT91 option is gone, let's completely remove the AT91 old clock driver related data. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-at91/at91sam9n12.c213
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c311
2 files changed, 4 insertions, 520 deletions
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index c8988fe5ff70..dee569b1987e 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -6,219 +6,11 @@
6 * Licensed under GPLv2 or later. 6 * Licensed under GPLv2 or later.
7 */ 7 */
8 8
9#include <linux/module.h> 9#include <asm/system_misc.h>
10#include <linux/dma-mapping.h> 10#include <mach/hardware.h>
11#include <linux/clk/at91_pmc.h>
12 11
13#include <asm/irq.h>
14#include <asm/mach/arch.h>
15#include <asm/mach/map.h>
16#include <mach/at91sam9n12.h>
17#include <mach/cpu.h>
18
19#include "board.h"
20#include "soc.h" 12#include "soc.h"
21#include "generic.h" 13#include "generic.h"
22#include "sam9_smc.h"
23
24#if defined(CONFIG_OLD_CLK_AT91)
25#include "clock.h"
26/* --------------------------------------------------------------------
27 * Clocks
28 * -------------------------------------------------------------------- */
29
30/*
31 * The peripheral clocks.
32 */
33static struct clk pioAB_clk = {
34 .name = "pioAB_clk",
35 .pmc_mask = 1 << AT91SAM9N12_ID_PIOAB,
36 .type = CLK_TYPE_PERIPHERAL,
37};
38static struct clk pioCD_clk = {
39 .name = "pioCD_clk",
40 .pmc_mask = 1 << AT91SAM9N12_ID_PIOCD,
41 .type = CLK_TYPE_PERIPHERAL,
42};
43static struct clk usart0_clk = {
44 .name = "usart0_clk",
45 .pmc_mask = 1 << AT91SAM9N12_ID_USART0,
46 .type = CLK_TYPE_PERIPHERAL,
47};
48static struct clk usart1_clk = {
49 .name = "usart1_clk",
50 .pmc_mask = 1 << AT91SAM9N12_ID_USART1,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk usart2_clk = {
54 .name = "usart2_clk",
55 .pmc_mask = 1 << AT91SAM9N12_ID_USART2,
56 .type = CLK_TYPE_PERIPHERAL,
57};
58static struct clk usart3_clk = {
59 .name = "usart3_clk",
60 .pmc_mask = 1 << AT91SAM9N12_ID_USART3,
61 .type = CLK_TYPE_PERIPHERAL,
62};
63static struct clk twi0_clk = {
64 .name = "twi0_clk",
65 .pmc_mask = 1 << AT91SAM9N12_ID_TWI0,
66 .type = CLK_TYPE_PERIPHERAL,
67};
68static struct clk twi1_clk = {
69 .name = "twi1_clk",
70 .pmc_mask = 1 << AT91SAM9N12_ID_TWI1,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk mmc_clk = {
74 .name = "mci_clk",
75 .pmc_mask = 1 << AT91SAM9N12_ID_MCI,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk spi0_clk = {
79 .name = "spi0_clk",
80 .pmc_mask = 1 << AT91SAM9N12_ID_SPI0,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk spi1_clk = {
84 .name = "spi1_clk",
85 .pmc_mask = 1 << AT91SAM9N12_ID_SPI1,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk uart0_clk = {
89 .name = "uart0_clk",
90 .pmc_mask = 1 << AT91SAM9N12_ID_UART0,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk uart1_clk = {
94 .name = "uart1_clk",
95 .pmc_mask = 1 << AT91SAM9N12_ID_UART1,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk tcb_clk = {
99 .name = "tcb_clk",
100 .pmc_mask = 1 << AT91SAM9N12_ID_TCB,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk pwm_clk = {
104 .name = "pwm_clk",
105 .pmc_mask = 1 << AT91SAM9N12_ID_PWM,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk adc_clk = {
109 .name = "adc_clk",
110 .pmc_mask = 1 << AT91SAM9N12_ID_ADC,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk dma_clk = {
114 .name = "dma_clk",
115 .pmc_mask = 1 << AT91SAM9N12_ID_DMA,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk uhp_clk = {
119 .name = "uhp",
120 .pmc_mask = 1 << AT91SAM9N12_ID_UHP,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk udp_clk = {
124 .name = "udp_clk",
125 .pmc_mask = 1 << AT91SAM9N12_ID_UDP,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk lcdc_clk = {
129 .name = "lcdc_clk",
130 .pmc_mask = 1 << AT91SAM9N12_ID_LCDC,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk ssc_clk = {
134 .name = "ssc_clk",
135 .pmc_mask = 1 << AT91SAM9N12_ID_SSC,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138
139static struct clk *periph_clocks[] __initdata = {
140 &pioAB_clk,
141 &pioCD_clk,
142 &usart0_clk,
143 &usart1_clk,
144 &usart2_clk,
145 &usart3_clk,
146 &twi0_clk,
147 &twi1_clk,
148 &mmc_clk,
149 &spi0_clk,
150 &spi1_clk,
151 &lcdc_clk,
152 &uart0_clk,
153 &uart1_clk,
154 &tcb_clk,
155 &pwm_clk,
156 &adc_clk,
157 &dma_clk,
158 &uhp_clk,
159 &udp_clk,
160 &ssc_clk,
161};
162
163static struct clk_lookup periph_clocks_lookups[] = {
164 /* lookup table for DT entries */
165 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
166 CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
167 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
168 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
169 CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
170 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
171 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
172 CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk),
173 CLKDEV_CON_DEV_ID(NULL, "f0010000.ssc", &ssc_clk),
174 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
175 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
176 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
177 CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
178 CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
179 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
180 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
181 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
182 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
183 /* additional fake clock for macb_hclk */
184 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
185 CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
186 CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
187};
188
189/*
190 * The two programmable clocks.
191 * You must configure pin multiplexing to bring these signals out.
192 */
193static struct clk pck0 = {
194 .name = "pck0",
195 .pmc_mask = AT91_PMC_PCK0,
196 .type = CLK_TYPE_PROGRAMMABLE,
197 .id = 0,
198};
199static struct clk pck1 = {
200 .name = "pck1",
201 .pmc_mask = AT91_PMC_PCK1,
202 .type = CLK_TYPE_PROGRAMMABLE,
203 .id = 1,
204};
205
206static void __init at91sam9n12_register_clocks(void)
207{
208 int i;
209
210 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
211 clk_register(periph_clocks[i]);
212 clk_register(&pck0);
213 clk_register(&pck1);
214
215 clkdev_add_table(periph_clocks_lookups,
216 ARRAY_SIZE(periph_clocks_lookups));
217
218}
219#else
220#define at91sam9n12_register_clocks NULL
221#endif
222 14
223/* -------------------------------------------------------------------- 15/* --------------------------------------------------------------------
224 * AT91SAM9N12 processor initialization 16 * AT91SAM9N12 processor initialization
@@ -236,6 +28,5 @@ static void __init at91sam9n12_initialize(void)
236 28
237AT91_SOC_START(at91sam9n12) 29AT91_SOC_START(at91sam9n12)
238 .map_io = at91sam9n12_map_io, 30 .map_io = at91sam9n12_map_io,
239 .register_clocks = at91sam9n12_register_clocks,
240 .init = at91sam9n12_initialize, 31 .init = at91sam9n12_initialize,
241AT91_SOC_END 32AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 028268ff3722..f0d5a69a7237 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -6,317 +6,11 @@
6 * Licensed under GPLv2 or later. 6 * Licensed under GPLv2 or later.
7 */ 7 */
8 8
9#include <linux/module.h> 9#include <asm/system_misc.h>
10#include <linux/dma-mapping.h> 10#include <mach/hardware.h>
11#include <linux/clk/at91_pmc.h>
12 11
13#include <asm/irq.h>
14#include <asm/mach/arch.h>
15#include <asm/mach/map.h>
16#include <mach/at91sam9x5.h>
17#include <mach/cpu.h>
18
19#include "board.h"
20#include "soc.h" 12#include "soc.h"
21#include "generic.h" 13#include "generic.h"
22#include "sam9_smc.h"
23
24#if defined(CONFIG_OLD_CLK_AT91)
25#include "clock.h"
26/* --------------------------------------------------------------------
27 * Clocks
28 * -------------------------------------------------------------------- */
29
30/*
31 * The peripheral clocks.
32 */
33static struct clk pioAB_clk = {
34 .name = "pioAB_clk",
35 .pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
36 .type = CLK_TYPE_PERIPHERAL,
37};
38static struct clk pioCD_clk = {
39 .name = "pioCD_clk",
40 .pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
41 .type = CLK_TYPE_PERIPHERAL,
42};
43static struct clk smd_clk = {
44 .name = "smd_clk",
45 .pmc_mask = 1 << AT91SAM9X5_ID_SMD,
46 .type = CLK_TYPE_PERIPHERAL,
47};
48static struct clk usart0_clk = {
49 .name = "usart0_clk",
50 .pmc_mask = 1 << AT91SAM9X5_ID_USART0,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk usart1_clk = {
54 .name = "usart1_clk",
55 .pmc_mask = 1 << AT91SAM9X5_ID_USART1,
56 .type = CLK_TYPE_PERIPHERAL,
57};
58static struct clk usart2_clk = {
59 .name = "usart2_clk",
60 .pmc_mask = 1 << AT91SAM9X5_ID_USART2,
61 .type = CLK_TYPE_PERIPHERAL,
62};
63/* USART3 clock - Only for sam9g25/sam9x25 */
64static struct clk usart3_clk = {
65 .name = "usart3_clk",
66 .pmc_mask = 1 << AT91SAM9X5_ID_USART3,
67 .type = CLK_TYPE_PERIPHERAL,
68};
69static struct clk twi0_clk = {
70 .name = "twi0_clk",
71 .pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
72 .type = CLK_TYPE_PERIPHERAL,
73};
74static struct clk twi1_clk = {
75 .name = "twi1_clk",
76 .pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
77 .type = CLK_TYPE_PERIPHERAL,
78};
79static struct clk twi2_clk = {
80 .name = "twi2_clk",
81 .pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
82 .type = CLK_TYPE_PERIPHERAL,
83};
84static struct clk mmc0_clk = {
85 .name = "mci0_clk",
86 .pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
87 .type = CLK_TYPE_PERIPHERAL,
88};
89static struct clk spi0_clk = {
90 .name = "spi0_clk",
91 .pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
92 .type = CLK_TYPE_PERIPHERAL,
93};
94static struct clk spi1_clk = {
95 .name = "spi1_clk",
96 .pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
97 .type = CLK_TYPE_PERIPHERAL,
98};
99static struct clk uart0_clk = {
100 .name = "uart0_clk",
101 .pmc_mask = 1 << AT91SAM9X5_ID_UART0,
102 .type = CLK_TYPE_PERIPHERAL,
103};
104static struct clk uart1_clk = {
105 .name = "uart1_clk",
106 .pmc_mask = 1 << AT91SAM9X5_ID_UART1,
107 .type = CLK_TYPE_PERIPHERAL,
108};
109static struct clk tcb0_clk = {
110 .name = "tcb0_clk",
111 .pmc_mask = 1 << AT91SAM9X5_ID_TCB,
112 .type = CLK_TYPE_PERIPHERAL,
113};
114static struct clk pwm_clk = {
115 .name = "pwm_clk",
116 .pmc_mask = 1 << AT91SAM9X5_ID_PWM,
117 .type = CLK_TYPE_PERIPHERAL,
118};
119static struct clk adc_clk = {
120 .name = "adc_clk",
121 .pmc_mask = 1 << AT91SAM9X5_ID_ADC,
122 .type = CLK_TYPE_PERIPHERAL,
123};
124static struct clk adc_op_clk = {
125 .name = "adc_op_clk",
126 .type = CLK_TYPE_PERIPHERAL,
127 .rate_hz = 5000000,
128};
129static struct clk dma0_clk = {
130 .name = "dma0_clk",
131 .pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
132 .type = CLK_TYPE_PERIPHERAL,
133};
134static struct clk dma1_clk = {
135 .name = "dma1_clk",
136 .pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
137 .type = CLK_TYPE_PERIPHERAL,
138};
139static struct clk uhphs_clk = {
140 .name = "uhphs",
141 .pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
142 .type = CLK_TYPE_PERIPHERAL,
143};
144static struct clk udphs_clk = {
145 .name = "udphs_clk",
146 .pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
147 .type = CLK_TYPE_PERIPHERAL,
148};
149/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
150static struct clk macb0_clk = {
151 .name = "pclk",
152 .pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
153 .type = CLK_TYPE_PERIPHERAL,
154};
155/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
156static struct clk lcdc_clk = {
157 .name = "lcdc_clk",
158 .pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
159 .type = CLK_TYPE_PERIPHERAL,
160};
161/* isi clock - Only for sam9g25 */
162static struct clk isi_clk = {
163 .name = "isi_clk",
164 .pmc_mask = 1 << AT91SAM9X5_ID_ISI,
165 .type = CLK_TYPE_PERIPHERAL,
166};
167static struct clk mmc1_clk = {
168 .name = "mci1_clk",
169 .pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
170 .type = CLK_TYPE_PERIPHERAL,
171};
172/* emac1 clock - Only for sam9x25 */
173static struct clk macb1_clk = {
174 .name = "pclk",
175 .pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
176 .type = CLK_TYPE_PERIPHERAL,
177};
178static struct clk ssc_clk = {
179 .name = "ssc_clk",
180 .pmc_mask = 1 << AT91SAM9X5_ID_SSC,
181 .type = CLK_TYPE_PERIPHERAL,
182};
183/* can0 clock - Only for sam9x35 */
184static struct clk can0_clk = {
185 .name = "can0_clk",
186 .pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
187 .type = CLK_TYPE_PERIPHERAL,
188};
189/* can1 clock - Only for sam9x35 */
190static struct clk can1_clk = {
191 .name = "can1_clk",
192 .pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
193 .type = CLK_TYPE_PERIPHERAL,
194};
195
196static struct clk *periph_clocks[] __initdata = {
197 &pioAB_clk,
198 &pioCD_clk,
199 &smd_clk,
200 &usart0_clk,
201 &usart1_clk,
202 &usart2_clk,
203 &twi0_clk,
204 &twi1_clk,
205 &twi2_clk,
206 &mmc0_clk,
207 &spi0_clk,
208 &spi1_clk,
209 &uart0_clk,
210 &uart1_clk,
211 &tcb0_clk,
212 &pwm_clk,
213 &adc_clk,
214 &adc_op_clk,
215 &dma0_clk,
216 &dma1_clk,
217 &uhphs_clk,
218 &udphs_clk,
219 &mmc1_clk,
220 &ssc_clk,
221 // irq0
222};
223
224static struct clk_lookup periph_clocks_lookups[] = {
225 /* lookup table for DT entries */
226 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
227 CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
228 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
229 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
230 CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
231 CLKDEV_CON_DEV_ID("usart", "f8040000.serial", &uart0_clk),
232 CLKDEV_CON_DEV_ID("usart", "f8044000.serial", &uart1_clk),
233 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
234 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
235 CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
236 CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
237 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
238 CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
239 CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
240 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
241 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
242 CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
243 CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
244 CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
245 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
246 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
247 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
248 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
249 /* additional fake clock for macb_hclk */
250 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
251 CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
252 CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
253 CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
254 CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
255 CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
256 CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
257 CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
258};
259
260/*
261 * The two programmable clocks.
262 * You must configure pin multiplexing to bring these signals out.
263 */
264static struct clk pck0 = {
265 .name = "pck0",
266 .pmc_mask = AT91_PMC_PCK0,
267 .type = CLK_TYPE_PROGRAMMABLE,
268 .id = 0,
269};
270static struct clk pck1 = {
271 .name = "pck1",
272 .pmc_mask = AT91_PMC_PCK1,
273 .type = CLK_TYPE_PROGRAMMABLE,
274 .id = 1,
275};
276
277static void __init at91sam9x5_register_clocks(void)
278{
279 int i;
280
281 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
282 clk_register(periph_clocks[i]);
283
284 clkdev_add_table(periph_clocks_lookups,
285 ARRAY_SIZE(periph_clocks_lookups));
286
287 if (cpu_is_at91sam9g25()
288 || cpu_is_at91sam9x25())
289 clk_register(&usart3_clk);
290
291 if (cpu_is_at91sam9g25()
292 || cpu_is_at91sam9x25()
293 || cpu_is_at91sam9g35()
294 || cpu_is_at91sam9x35())
295 clk_register(&macb0_clk);
296
297 if (cpu_is_at91sam9g15()
298 || cpu_is_at91sam9g35()
299 || cpu_is_at91sam9x35())
300 clk_register(&lcdc_clk);
301
302 if (cpu_is_at91sam9g25())
303 clk_register(&isi_clk);
304
305 if (cpu_is_at91sam9x25())
306 clk_register(&macb1_clk);
307
308 if (cpu_is_at91sam9x25()
309 || cpu_is_at91sam9x35()) {
310 clk_register(&can0_clk);
311 clk_register(&can1_clk);
312 }
313
314 clk_register(&pck0);
315 clk_register(&pck1);
316}
317#else
318#define at91sam9x5_register_clocks NULL
319#endif
320 14
321/* -------------------------------------------------------------------- 15/* --------------------------------------------------------------------
322 * AT91SAM9x5 processor initialization 16 * AT91SAM9x5 processor initialization
@@ -338,6 +32,5 @@ static void __init at91sam9x5_initialize(void)
338 32
339AT91_SOC_START(at91sam9x5) 33AT91_SOC_START(at91sam9x5)
340 .map_io = at91sam9x5_map_io, 34 .map_io = at91sam9x5_map_io,
341 .register_clocks = at91sam9x5_register_clocks,
342 .init = at91sam9x5_initialize, 35 .init = at91sam9x5_initialize,
343AT91_SOC_END 36AT91_SOC_END
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-07 19:26:58 -0400