diff options
author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2014-12-30 15:20:34 -0500 |
---|---|---|
committer | Simon Horman <horms+renesas@verge.net.au> | 2015-02-23 16:30:57 -0500 |
commit | ae65a8ae4c25c7ea01204c9d033cd47da3000cf8 (patch) | |
tree | 85f605de80e767fbe96ce542a3d2173589003306 /arch/arm | |
parent | 457acc4a6ce8fe821aed4f254e72a76c88673712 (diff) |
ARM: shmobile: r8a7791: add ADSP clocks
Add the ADSP clocks to the CPG and MSTP5 nodes of the R8A7791 device tree.
Based on the original patch by Konstantin Kozhevnikov
<konstantin.kozhevnikov@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/boot/dts/r8a7791.dtsi | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index ff49b95df0ec..1e593a2b55fa 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi | |||
@@ -909,7 +909,7 @@ | |||
909 | #clock-cells = <1>; | 909 | #clock-cells = <1>; |
910 | clock-output-names = "main", "pll0", "pll1", "pll3", | 910 | clock-output-names = "main", "pll0", "pll1", "pll3", |
911 | "lb", "qspi", "sdh", "sd0", "z", | 911 | "lb", "qspi", "sdh", "sd0", "z", |
912 | "rcan"; | 912 | "rcan", "adsp"; |
913 | }; | 913 | }; |
914 | 914 | ||
915 | /* Variable factor clocks */ | 915 | /* Variable factor clocks */ |
@@ -1164,13 +1164,16 @@ | |||
1164 | mstp5_clks: mstp5_clks@e6150144 { | 1164 | mstp5_clks: mstp5_clks@e6150144 { |
1165 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | 1165 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
1166 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; | 1166 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; |
1167 | clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; | 1167 | clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>, |
1168 | <&extal_clk>, <&p_clk>; | ||
1168 | #clock-cells = <1>; | 1169 | #clock-cells = <1>; |
1169 | clock-indices = < | 1170 | clock-indices = < |
1170 | R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 | 1171 | R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 |
1171 | R8A7791_CLK_THERMAL R8A7791_CLK_PWM | 1172 | R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL |
1173 | R8A7791_CLK_PWM | ||
1172 | >; | 1174 | >; |
1173 | clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; | 1175 | clock-output-names = "audmac0", "audmac1", "adsp_mod", |
1176 | "thermal", "pwm"; | ||
1174 | }; | 1177 | }; |
1175 | mstp7_clks: mstp7_clks@e615014c { | 1178 | mstp7_clks: mstp7_clks@e615014c { |
1176 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | 1179 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |