Merge branch 'devel-stable' into devel

Conflicts:
	arch/arm/Kconfig
	arch/arm/include/asm/system.h
	arch/arm/mm/Kconfig

366 files changed, 8686 insertions, 3346 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2b3157b5089a..492f81344900 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -241,6 +241,7 @@ config ARCH_REALVIEW
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select PLAT_VERSATILE
         select ARM_TIMER_SP804
+        select GPIO_PL061 if GPIOLIB
         help
           This enables support for ARM Ltd RealView boards.
 
@@ -300,6 +301,15 @@ config ARCH_CLPS711X
         help
           Support for Cirrus Logic 711x/721x based boards.
 
+config ARCH_CNS3XXX
+        bool "Cavium Networks CNS3XXX family"
+        select CPU_V6
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select ARM_GIC
+        help
+          Support for Cavium Networks CNS3XXX platform.
+
 config ARCH_GEMINI
         bool "Cortina Systems Gemini"
         select CPU_FA526
@@ -593,14 +603,15 @@ config ARCH_PXA
 
 config ARCH_MSM
         bool "Qualcomm MSM"
-        select CPU_V6
+        select HAVE_CLK
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         help
-          Support for Qualcomm MSM7K based systems.  This runs on the ARM11
-          apps processor of the MSM7K and depends on a shared memory
-          interface to the ARM9 modem processor which runs the baseband stack
-          and controls some vital subsystems (clock and power control, etc).
+          Support for Qualcomm MSM/QSD based systems.  This runs on the
+          apps processor of the MSM/QSD and depends on a shared memory
+          interface to the modem processor which runs the baseband
+          stack and controls some vital subsystems
+          (clock and power control, etc).
 
 config ARCH_SHMOBILE
         bool "Renesas SH-Mobile"
@@ -639,7 +650,7 @@ config ARCH_SA1100
           Support for StrongARM 11x0 based boards.
 
 config ARCH_S3C2410
-        bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
+        bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
         select GENERIC_GPIO
         select ARCH_HAS_CPUFREQ
         select HAVE_CLK
@@ -649,6 +660,10 @@ config ARCH_S3C2410
           BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
           the Samsung SMDK2410 development board (and derivatives).
 
+          Note, the S3C2416 and the S3C2450 are so close that they even share
+          the same SoC ID code. This means that there is no seperate machine
+          directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
+
 config ARCH_S3C64XX
         bool "Samsung S3C64XX"
         select PLAT_SAMSUNG
@@ -818,6 +833,8 @@ source "arch/arm/mach-bcmring/Kconfig"
 
 source "arch/arm/mach-clps711x/Kconfig"
 
+source "arch/arm/mach-cns3xxx/Kconfig"
+
 source "arch/arm/mach-davinci/Kconfig"
 
 source "arch/arm/mach-dove/Kconfig"
@@ -894,6 +911,7 @@ if ARCH_S3C2410
 source "arch/arm/mach-s3c2400/Kconfig"
 source "arch/arm/mach-s3c2410/Kconfig"
 source "arch/arm/mach-s3c2412/Kconfig"
+source "arch/arm/mach-s3c2416/Kconfig"
 source "arch/arm/mach-s3c2440/Kconfig"
 source "arch/arm/mach-s3c2443/Kconfig"
 endif
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 219cb4ee7e32..d5af3b024300 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -121,6 +121,7 @@ machine-$(CONFIG_ARCH_AAEC2000)		:= aaec2000
 machine-$(CONFIG_ARCH_AT91)             := at91
 machine-$(CONFIG_ARCH_BCMRING)          := bcmring
 machine-$(CONFIG_ARCH_CLPS711X)         := clps711x
+machine-$(CONFIG_ARCH_CNS3XXX)          := cns3xxx
 machine-$(CONFIG_ARCH_DAVINCI)          := davinci
 machine-$(CONFIG_ARCH_DOVE)             := dove
 machine-$(CONFIG_ARCH_EBSA110)          := ebsa110
@@ -160,7 +161,7 @@ machine-$(CONFIG_ARCH_PNX4008)		:= pnx4008
 machine-$(CONFIG_ARCH_PXA)              := pxa
 machine-$(CONFIG_ARCH_REALVIEW)         := realview
 machine-$(CONFIG_ARCH_RPC)              := rpc
-machine-$(CONFIG_ARCH_S3C2410)          := s3c2410 s3c2400 s3c2412 s3c2440 s3c2443
+machine-$(CONFIG_ARCH_S3C2410)          := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
 machine-$(CONFIG_ARCH_S3C24A0)          := s3c24a0
 machine-$(CONFIG_ARCH_S3C64XX)          := s3c64xx
 machine-$(CONFIG_ARCH_S5P6440)          := s5p6440
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 0f23009170a1..c5191b1532e8 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -172,7 +172,7 @@ not_angel:
                 adr     r0, LC0
  ARM(           ldmia   r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
  THUMB(         ldmia   r0, {r1, r2, r3, r4, r5, r6, r11, ip}   )
- THUMB(         ldr     sp, [r0, #28]                           )
+ THUMB(         ldr     sp, [r0, #32]                           )
                 subs    r0, r0, r1              @ calculate the delta offset
 
                                                 @ if delta is zero, we are
@@ -685,8 +685,8 @@ proc_types:
                 W(b)    __armv4_mmu_cache_off
                 W(b)    __armv4_mmu_cache_flush
 
-                .word   0x56056930
-                .word   0xff0ffff0              @ PXA935
+                .word   0x56056900
+                .word   0xffffff00              @ PXA9xx
                 W(b)    __armv4_mmu_cache_on
                 W(b)    __armv4_mmu_cache_off
                 W(b)    __armv4_mmu_cache_flush
@@ -697,12 +697,6 @@ proc_types:
                 W(b)    __armv4_mmu_cache_off
                 W(b)    __armv5tej_mmu_cache_flush
 
-                .word   0x56056930
-                .word   0xff0ffff0              @ PXA935
-                W(b)    __armv4_mmu_cache_on
-                W(b)    __armv4_mmu_cache_off
-                W(b)    __armv4_mmu_cache_flush
-
                 .word   0x56050000              @ Feroceon
                 .word   0xff0f0000
                 W(b)    __armv4_mmu_cache_on
diff --git a/arch/arm/common/clkdev.c b/arch/arm/common/clkdev.c
index 4f8390dd6cac..e2b2bb66e094 100644
--- a/arch/arm/common/clkdev.c
+++ b/arch/arm/common/clkdev.c
@@ -18,6 +18,7 @@
 #include <linux/string.h>
 #include <linux/mutex.h>
 #include <linux/clk.h>
+#include <linux/slab.h>
 
 #include <asm/clkdev.h>
 #include <mach/clkdev.h>
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index ee1d3b85eb65..7974baacafce 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -21,7 +21,6 @@
 #include <linux/ptrace.h>
 #include <linux/interrupt.h>
 #include <linux/mm.h>
-#include <linux/slab.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/irq.h>
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index 90ae00b631c2..9dff07c80ddb 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -290,7 +290,7 @@ static int locomo_suspend(struct platform_device *dev, pm_message_t state)
         save->LCM_GPO     = locomo_readl(lchip->base + LOCOMO_GPO);     /* GPIO */
         locomo_writel(0x00, lchip->base + LOCOMO_GPO);
         save->LCM_SPICT   = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPICT);      /* SPI */
-        locomo_writel(0x40, lchip->base + LOCOMO_SPICT);
+        locomo_writel(0x40, lchip->base + LOCOMO_SPI + LOCOMO_SPICT);
         save->LCM_GPE     = locomo_readl(lchip->base + LOCOMO_GPE);     /* GPIO */
         locomo_writel(0x00, lchip->base + LOCOMO_GPE);
         save->LCM_ASD     = locomo_readl(lchip->base + LOCOMO_ASD);     /* ADSTART */
@@ -418,7 +418,7 @@ __locomo_probe(struct device *me, struct resource *mem, int irq)
         /* Longtime timer */
         locomo_writel(0, lchip->base + LOCOMO_LTINT);
         /* SPI */
-        locomo_writel(0, lchip->base + LOCOMO_SPIIE);
+        locomo_writel(0, lchip->base + LOCOMO_SPI + LOCOMO_SPIIE);
 
         locomo_writel(6 + 8 + 320 + 30 - 10, lchip->base + LOCOMO_ASD);
         r = locomo_readl(lchip->base + LOCOMO_ASD);
@@ -707,7 +707,7 @@ void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int
         udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4.7 usec */
         if (locomo_readl(mapbase + LOCOMO_DAC) & LOCOMO_DAC_SDAOEB) {   /* High is error */
                 printk(KERN_WARNING "locomo: m62332_senddata Error 1\n");
-                return;
+                goto out;
         }
 
         /* Send Sub address (LSB is channel select) */
@@ -735,7 +735,7 @@ void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int
         udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4.7 usec */
         if (locomo_readl(mapbase + LOCOMO_DAC) & LOCOMO_DAC_SDAOEB) {   /* High is error */
                 printk(KERN_WARNING "locomo: m62332_senddata Error 2\n");
-                return;
+                goto out;
         }
 
         /* Send DAC data */
@@ -760,9 +760,9 @@ void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int
         udelay(DAC_SCL_HIGH_HOLD_TIME); /* 4.7 usec */
         if (locomo_readl(mapbase + LOCOMO_DAC) & LOCOMO_DAC_SDAOEB) {   /* High is error */
                 printk(KERN_WARNING "locomo: m62332_senddata Error 3\n");
-                return;
         }
 
+out:
         /* stop */
         r = locomo_readl(mapbase + LOCOMO_DAC);
         r &=  ~(LOCOMO_DAC_SCLOEB);
diff --git a/arch/arm/configs/bcmring_defconfig b/arch/arm/configs/bcmring_defconfig
index 1e12167c89b7..6ac6693299bc 100644
--- a/arch/arm/configs/bcmring_defconfig
+++ b/arch/arm/configs/bcmring_defconfig
@@ -1,13 +1,13 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc3
-# Fri Jul 17 12:07:28 2009
+# Linux kernel version: 2.6.34-rc2
+# Mon Mar 29 12:01:41 2010
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
+CONFIG_HAVE_PROC_CPU=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -18,6 +18,7 @@ CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -32,6 +33,12 @@ CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
@@ -43,21 +50,22 @@ CONFIG_SYSVIPC_SYSCTL=y
 #
 # RCU Subsystem
 #
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
 # CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_GROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
 # CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 # CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
@@ -75,19 +83,21 @@ CONFIG_FUTEX=y
 # CONFIG_EVENTFD is not set
 CONFIG_SHMEM=y
 # CONFIG_AIO is not set
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
 
 #
-# Performance Counters
+# Kernel Performance Events And Counters
 #
+CONFIG_PERF_EVENTS=y
+CONFIG_PERF_COUNTERS=y
 # CONFIG_VM_EVENT_COUNTERS is not set
 # CONFIG_SLUB_DEBUG is not set
-# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_COMPAT_BRK is not set
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_KPROBES=y
@@ -115,24 +125,53 @@ CONFIG_LBDAF=y
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-# CONFIG_DEFAULT_AS is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
 # CONFIG_FREEZER is not set
 
 #
 # System Type
 #
+CONFIG_MMU=y
 # CONFIG_ARCH_AAEC2000 is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
+CONFIG_ARCH_BCMRING=y
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
@@ -149,6 +188,7 @@ CONFIG_DEFAULT_IOSCHED="noop"
 # CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_DOVE is not set
 # CONFIG_ARCH_KIRKWOOD is not set
 # CONFIG_ARCH_LOKI is not set
 # CONFIG_ARCH_MV78XX0 is not set
@@ -157,19 +197,26 @@ CONFIG_DEFAULT_IOSCHED="noop"
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_S5PV210 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-CONFIG_ARCH_BCMRING=y
 # CONFIG_ARCH_FPGA11107 is not set
 CONFIG_ARCH_BCM11107=y
 
@@ -185,7 +232,7 @@ CONFIG_CPU_V6=y
 CONFIG_CPU_32v6K=y
 CONFIG_CPU_32v6=y
 CONFIG_CPU_ABRT_EV6=y
-CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_PABRT_V6=y
 CONFIG_CPU_CACHE_V6=y
 CONFIG_CPU_CACHE_VIPT=y
 CONFIG_CPU_COPY_V6=y
@@ -201,6 +248,8 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_CPU_HAS_PMU=y
 # CONFIG_ARM_ERRATA_411920 is not set
 CONFIG_COMMON_CLKDEV=y
 
@@ -222,6 +271,8 @@ CONFIG_VMSPLIT_3G=y
 # CONFIG_VMSPLIT_2G is not set
 # CONFIG_VMSPLIT_1G is not set
 CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
 CONFIG_PREEMPT=y
 CONFIG_HZ=100
 CONFIG_AEABI=y
@@ -229,6 +280,7 @@ CONFIG_AEABI=y
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 # CONFIG_HIGHMEM is not set
+CONFIG_HW_PERF_EVENTS=y
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -240,8 +292,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_ALIGNMENT_TRAP=y
 CONFIG_UACCESS_WITH_MEMCPY=y
@@ -335,9 +386,9 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 CONFIG_MTD_CONCAT=y
 CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AFS_PARTS is not set
@@ -433,6 +484,10 @@ CONFIG_MTD_NAND_BCM_UMI_HWCS=y
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
@@ -444,6 +499,7 @@ CONFIG_HAVE_IDE=y
 #
 # SCSI device support
 #
+CONFIG_SCSI_MOD=y
 # CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
 # CONFIG_SCSI_DMA is not set
@@ -452,6 +508,7 @@ CONFIG_HAVE_IDE=y
 # CONFIG_MD is not set
 # CONFIG_NETDEVICES is not set
 # CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
 
 #
 # Input device support
@@ -459,6 +516,7 @@ CONFIG_HAVE_IDE=y
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
 # CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
@@ -508,6 +566,7 @@ CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
@@ -519,13 +578,17 @@ CONFIG_LEGACY_PTY_COUNT=64
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
 # CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 # CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 
@@ -541,6 +604,7 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
 # CONFIG_MEDIA_SUPPORT is not set
 
 #
@@ -566,14 +630,17 @@ CONFIG_DUMMY_CONSOLE=y
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
-# CONFIG_REGULATOR is not set
 # CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 
 #
@@ -589,9 +656,12 @@ CONFIG_FS_POSIX_ACL=y
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 # CONFIG_FILE_LOCKING is not set
 # CONFIG_FSNOTIFY is not set
+# CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
 # CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
@@ -647,6 +717,7 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+# CONFIG_LOGFS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -657,7 +728,6 @@ CONFIG_JFFS2_RTIME=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NILFS2_FS is not set
 # CONFIG_NETWORK_FILESYSTEMS is not set
 
 #
@@ -675,11 +745,12 @@ CONFIG_MSDOS_PARTITION=y
 CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 CONFIG_HEADERS_CHECK=y
 # CONFIG_DEBUG_KERNEL is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_MEMORY_INIT is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
@@ -693,6 +764,7 @@ CONFIG_TRACING_SUPPORT=y
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_ARM_UNWIND is not set
 # CONFIG_DEBUG_USER is not set
+# CONFIG_OC_ETM is not set
 
 #
 # Security options
@@ -700,7 +772,11 @@ CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
 # CONFIG_CRYPTO is not set
 # CONFIG_BINARY_PRINTF is not set
 
diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig
new file mode 100644
index 000000000000..d5c088149e46
--- /dev/null
+++ b/arch/arm/configs/cns3420vb_defconfig
@@ -0,0 +1,831 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.34-rc6
+# Sun May  2 21:58:08 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_OPROFILE_ARMV6=y
+CONFIG_OPROFILE_ARM11_CORE=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_NS is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CPUSETS is not set
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_RESOURCE_COUNTERS is not set
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=m
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
+# CONFIG_SLOW_WORK_DEBUG is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=m
+# CONFIG_CFQ_GROUP_IOSCHED is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+CONFIG_ARCH_CNS3XXX=y
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# CNS3XXX platform type
+#
+CONFIG_MACH_CNS3420VB=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_V6=y
+# CONFIG_CPU_32v6K is not set
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_V6=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_CPU_HAS_PMU=y
+# CONFIG_ARM_ERRATA_411920 is not set
+CONFIG_ARM_GIC=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,38400 mem=128M root=/dev/mmcblk0p1 ro rootwait"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=20000
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_SATA_PMP is not set
+# CONFIG_ATA_SFF is not set
+# CONFIG_MD is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+CONFIG_FSCACHE=y
+# CONFIG_FSCACHE_STATS is not set
+# CONFIG_FSCACHE_HISTOGRAM is not set
+# CONFIG_FSCACHE_DEBUG is not set
+# CONFIG_FSCACHE_OBJECT_LIST is not set
+# CONFIG_CACHEFILES is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LKDTM is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_ARM_UNWIND is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig
index 95d2becfc664..21f2bff8a363 100644
--- a/arch/arm/configs/imote2_defconfig
+++ b/arch/arm/configs/imote2_defconfig
@@ -1,13 +1,14 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.33-rc8
-# Sat Feb 13 21:48:53 2010
+# Linux kernel version: 2.6.34-rc2
+# Thu Apr  8 14:49:08 2010
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_HAVE_PROC_CPU=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -19,6 +20,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_ARCH_HAS_CPUFREQ=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_ARCH_MTD_XIP=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
@@ -60,11 +62,6 @@ CONFIG_RCU_FANOUT=32
 # CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_GROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_USER_SCHED=y
-# CONFIG_CGROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
@@ -97,10 +94,14 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
 
 #
 # Kernel Performance Events And Counters
 #
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
@@ -184,6 +185,7 @@ CONFIG_MMU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
@@ -193,7 +195,6 @@ CONFIG_MMU=y
 # CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -210,21 +211,26 @@ CONFIG_MMU=y
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
 # CONFIG_ARCH_PNX4008 is not set
 CONFIG_ARCH_PXA=y
 # CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
 # CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_S5PV210 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_U8500 is not set
 
 #
 # Intel PXA2xx/PXA3xx Implementations
@@ -253,6 +259,7 @@ CONFIG_ARCH_PXA=y
 # CONFIG_MACH_EM_X270 is not set
 # CONFIG_MACH_EXEDA is not set
 # CONFIG_MACH_CM_X300 is not set
+# CONFIG_MACH_CAPC7117 is not set
 # CONFIG_ARCH_GUMSTIX is not set
 CONFIG_MACH_INTELMOTE2=y
 # CONFIG_MACH_STARGATE2 is not set
@@ -275,7 +282,11 @@ CONFIG_MACH_INTELMOTE2=y
 # CONFIG_PXA_EZX is not set
 # CONFIG_MACH_MP900C is not set
 # CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_MACH_RAUMFELD_RC is not set
+# CONFIG_MACH_RAUMFELD_CONNECTOR is not set
+# CONFIG_MACH_RAUMFELD_SPEAKER is not set
 # CONFIG_PXA_SHARPSL is not set
+# CONFIG_MACH_ICONTROL is not set
 # CONFIG_ARCH_PXA_ESERIES is not set
 CONFIG_PXA27x=y
 CONFIG_PXA_SSP=y
@@ -302,6 +313,7 @@ CONFIG_ARM_THUMB=y
 CONFIG_ARM_L1_CACHE_SHIFT=5
 CONFIG_IWMMXT=y
 CONFIG_XSCALE_PMU=y
+CONFIG_CPU_HAS_PMU=y
 CONFIG_COMMON_CLKDEV=y
 
 #
@@ -352,7 +364,7 @@ CONFIG_ALIGNMENT_TRAP=y
 #
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=3 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug"
+CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS2,115200 mem=32M"
 # CONFIG_XIP_KERNEL is not set
 CONFIG_KEXEC=y
 CONFIG_ATAGS_PROC=y
@@ -360,24 +372,8 @@ CONFIG_ATAGS_PROC=y
 #
 # CPU Power Management
 #
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-CONFIG_CPU_FREQ_DEBUG=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=m
-CONFIG_CPU_FREQ_GOV_USERSPACE=m
-CONFIG_CPU_FREQ_GOV_ONDEMAND=m
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
 
 #
 # Floating point emulation
@@ -409,6 +405,7 @@ CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
 CONFIG_APM_EMULATION=y
 CONFIG_PM_RUNTIME=y
+CONFIG_PM_OPS=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_NET=y
 
@@ -416,7 +413,6 @@ CONFIG_NET=y
 # Networking options
 #
 CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
@@ -506,6 +502,7 @@ CONFIG_NF_CT_NETLINK=m
 CONFIG_NETFILTER_XTABLES=m
 CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 # CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_CT is not set
 # CONFIG_NETFILTER_XT_TARGET_DSCP is not set
 CONFIG_NETFILTER_XT_TARGET_HL=m
 CONFIG_NETFILTER_XT_TARGET_LED=m
@@ -622,6 +619,7 @@ CONFIG_IP6_NF_RAW=m
 # CONFIG_ATM is not set
 CONFIG_STP=m
 CONFIG_BRIDGE=m
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
 # CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
@@ -646,32 +644,7 @@ CONFIG_NET_CLS_ROUTE=y
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=y
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIBTUSB=m
-CONFIG_BT_HCIBTSDIO=m
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-# CONFIG_BT_HCIUART_BCSP is not set
-# CONFIG_BT_HCIUART_LL is not set
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_BT_MRVL=m
-CONFIG_BT_MRVL_SDIO=m
-# CONFIG_BT_ATH3K is not set
+# CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
 CONFIG_FIB_RULES=y
 # CONFIG_WIRELESS is not set
@@ -687,7 +660,8 @@ CONFIG_FIB_RULES=y
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_DEVTMPFS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=m
@@ -703,9 +677,9 @@ CONFIG_MTD=y
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_AFS_PARTS=y
+CONFIG_MTD_AR7_PARTS=y
 
 #
 # User Modules And Translation Layers
@@ -812,6 +786,7 @@ CONFIG_HAVE_IDE=y
 #
 # SCSI device support
 #
+CONFIG_SCSI_MOD=y
 # CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
 # CONFIG_SCSI_DMA is not set
@@ -965,6 +940,7 @@ CONFIG_SERIAL_PXA=y
 CONFIG_SERIAL_PXA_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
@@ -993,6 +969,7 @@ CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_PXA=y
 # CONFIG_I2C_PXA_SLAVE is not set
 # CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
 
 #
 # External I2C/SMBus adapter drivers
@@ -1006,15 +983,9 @@ CONFIG_I2C_PXA=y
 #
 # CONFIG_I2C_PCA_PLATFORM is not set
 # CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
 CONFIG_SPI=y
 # CONFIG_SPI_DEBUG is not set
 CONFIG_SPI_MASTER=y
@@ -1046,10 +1017,12 @@ CONFIG_GPIO_SYSFS=y
 #
 # Memory mapped GPIO expanders:
 #
+# CONFIG_GPIO_IT8761E is not set
 
 #
 # I2C GPIO expanders:
 #
+# CONFIG_GPIO_MAX7300 is not set
 # CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
@@ -1093,10 +1066,12 @@ CONFIG_SSB_POSSIBLE=y
 # Multifunction device drivers
 #
 # CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_MFD_ASIC3 is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
 # CONFIG_TPS65010 is not set
 # CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
@@ -1105,22 +1080,25 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_TC6393XB is not set
 CONFIG_PMIC_DA903X=y
 # CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM831X is not set
 # CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
 # CONFIG_MFD_PCF50633 is not set
 # CONFIG_MFD_MC13783 is not set
 # CONFIG_AB3100_CORE is not set
 # CONFIG_EZX_PCAP is not set
-# CONFIG_MFD_88PM8607 is not set
 # CONFIG_AB4500_CORE is not set
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_DEBUG=y
+# CONFIG_REGULATOR_DUMMY is not set
 # CONFIG_REGULATOR_FIXED_VOLTAGE is not set
 CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_USERSPACE_CONSUMER=y
 # CONFIG_REGULATOR_BQ24022 is not set
 # CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
 # CONFIG_REGULATOR_MAX8660 is not set
 CONFIG_REGULATOR_DA903X=y
 # CONFIG_REGULATOR_LP3971 is not set
@@ -1218,6 +1196,7 @@ CONFIG_VIDEO_IR_I2C=y
 # CONFIG_VIDEO_SAA7191 is not set
 # CONFIG_VIDEO_TVP514X is not set
 # CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
 # CONFIG_VIDEO_VPX3220 is not set
 
 #
@@ -1264,15 +1243,7 @@ CONFIG_SOC_CAMERA_MT9M111=y
 CONFIG_VIDEO_PXA27x=y
 # CONFIG_VIDEO_SH_MOBILE_CEU is not set
 # CONFIG_V4L_USB_DRIVERS is not set
-CONFIG_RADIO_ADAPTERS=y
-# CONFIG_I2C_SI4713 is not set
-# CONFIG_RADIO_SI4713 is not set
-# CONFIG_USB_DSBR is not set
-# CONFIG_RADIO_SI470X is not set
-# CONFIG_USB_MR800 is not set
-CONFIG_RADIO_TEA5764=y
-CONFIG_RADIO_TEA5764_XTAL=y
-# CONFIG_RADIO_TEF6862 is not set
+# CONFIG_RADIO_ADAPTERS is not set
 # CONFIG_DAB is not set
 
 #
@@ -1398,8 +1369,6 @@ CONFIG_HID=y
 #
 # Special HID drivers
 #
-CONFIG_HID_APPLE=m
-# CONFIG_HID_WACOM is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1477,7 +1446,6 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
@@ -1489,7 +1457,6 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 # CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
 CONFIG_USB_GADGET=y
 # CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
@@ -1529,6 +1496,7 @@ CONFIG_USB_ETH=y
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_G_PRINTER is not set
 # CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_NOKIA is not set
 # CONFIG_USB_G_MULTI is not set
 
 #
@@ -1555,8 +1523,6 @@ CONFIG_SDIO_UART=m
 #
 CONFIG_MMC_PXA=y
 # CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_AT91 is not set
-# CONFIG_MMC_ATMELMCI is not set
 CONFIG_MMC_SPI=y
 # CONFIG_MEMSTICK is not set
 CONFIG_NEW_LEDS=y
@@ -1574,11 +1540,11 @@ CONFIG_LEDS_LP3944=y
 # CONFIG_LEDS_REGULATOR is not set
 # CONFIG_LEDS_BD2802 is not set
 # CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
 
 #
 # LED Triggers
 #
-CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_BACKLIGHT=y
@@ -1656,7 +1622,7 @@ CONFIG_RTC_INTF_DEV=y
 # on-CPU RTC drivers
 #
 # CONFIG_RTC_DRV_SA1100 is not set
-# CONFIG_RTC_DRV_PXA is not set
+CONFIG_RTC_DRV_PXA=y
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
@@ -1681,19 +1647,10 @@ CONFIG_EXT3_FS_XATTR=y
 CONFIG_JBD=m
 # CONFIG_JBD_DEBUG is not set
 CONFIG_FS_MBCACHE=m
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
-CONFIG_XFS_FS=m
-# CONFIG_XFS_QUOTA is not set
-# CONFIG_XFS_POSIX_ACL is not set
-# CONFIG_XFS_RT is not set
-# CONFIG_XFS_DEBUG is not set
+# CONFIG_XFS_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
 # CONFIG_NILFS2_FS is not set
@@ -1716,9 +1673,7 @@ CONFIG_CUSE=m
 #
 # CD-ROM/DVD Filesystems
 #
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
+# CONFIG_ISO9660_FS is not set
 # CONFIG_UDF_FS is not set
 
 #
@@ -1750,12 +1705,14 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
 CONFIG_JFFS2_COMPRESSION_OPTIONS=y
 CONFIG_JFFS2_ZLIB=y
 CONFIG_JFFS2_LZO=y
@@ -1765,6 +1722,7 @@ CONFIG_JFFS2_RUBIN=y
 CONFIG_JFFS2_CMODE_PRIORITY=y
 # CONFIG_JFFS2_CMODE_SIZE is not set
 # CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_LOGFS is not set
 CONFIG_CRAMFS=m
 CONFIG_SQUASHFS=m
 # CONFIG_SQUASHFS_EMBEDDED is not set
@@ -1802,6 +1760,7 @@ CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
 # CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_CEPH_FS is not set
 CONFIG_CIFS=m
 CONFIG_CIFS_STATS=y
 # CONFIG_CIFS_STATS2 is not set
@@ -1895,6 +1854,7 @@ CONFIG_DEBUG_SPINLOCK=y
 CONFIG_DEBUG_MUTEXES=y
 CONFIG_DEBUG_LOCK_ALLOC=y
 CONFIG_PROVE_LOCKING=y
+# CONFIG_PROVE_RCU is not set
 CONFIG_LOCKDEP=y
 # CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_LOCKDEP is not set
@@ -1918,6 +1878,7 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 # CONFIG_SYSCTL_SYSCALL_CHECK is not set
@@ -2061,9 +2022,9 @@ CONFIG_CRC32=y
 CONFIG_CRC7=y
 CONFIG_LIBCRC32C=m
 CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=m
-CONFIG_LZO_COMPRESS=m
-CONFIG_LZO_DECOMPRESS=m
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_DECOMPRESS_GZIP=y
 CONFIG_DECOMPRESS_BZIP2=y
 CONFIG_DECOMPRESS_LZMA=y
@@ -2075,3 +2036,4 @@ CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 03f76cfc941c..4b55dcb60029 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -1,13 +1,14 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.33-rc2
-# Tue Jan  5 13:55:22 2010
+# Linux kernel version: 2.6.34-rc5
+# Wed Apr 28 11:23:19 2010
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_HAVE_PROC_CPU=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -18,6 +19,7 @@ CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -32,6 +34,12 @@ CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
@@ -52,7 +60,6 @@ CONFIG_RCU_FANOUT=32
 # CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_GROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
@@ -85,10 +92,14 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
 
 #
 # Kernel Performance Events And Counters
 #
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
@@ -104,6 +115,7 @@ CONFIG_HAVE_CLK=y
 #
 # GCOV-based kernel profiling
 #
+# CONFIG_GCOV_KERNEL is not set
 # CONFIG_SLOW_WORK is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
@@ -170,6 +182,7 @@ CONFIG_MMU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
@@ -179,7 +192,6 @@ CONFIG_MMU=y
 # CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -196,21 +208,26 @@ CONFIG_ARCH_MMP=y
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
 # CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_S5PV210 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_U8500 is not set
 # CONFIG_MACH_TAVOREVB is not set
 
 #
@@ -218,8 +235,10 @@ CONFIG_ARCH_MMP=y
 #
 # CONFIG_MACH_ASPENITE is not set
 # CONFIG_MACH_ZYLONITE2 is not set
+# CONFIG_MACH_AVENGERS_LITE is not set
 # CONFIG_MACH_TTC_DKB is not set
 CONFIG_MACH_FLINT=y
+CONFIG_MACH_MARVELL_JASPER=y
 CONFIG_CPU_MMP2=y
 CONFIG_PLAT_PXA=y
 
@@ -246,7 +265,10 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_TAUROS2=y
 CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_CPU_HAS_PMU=y
 # CONFIG_ARM_ERRATA_411920 is not set
 CONFIG_COMMON_CLKDEV=y
 
@@ -298,7 +320,7 @@ CONFIG_ALIGNMENT_TRAP=y
 #
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M user_debug=255"
+CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=128M user_debug=255"
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
 
@@ -338,7 +360,6 @@ CONFIG_NET=y
 # Networking options
 #
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
@@ -532,6 +553,7 @@ CONFIG_HAVE_IDE=y
 #
 # SCSI device support
 #
+CONFIG_SCSI_MOD=y
 # CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
 # CONFIG_SCSI_DMA is not set
@@ -640,6 +662,7 @@ CONFIG_SERIAL_PXA=y
 CONFIG_SERIAL_PXA_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
@@ -667,6 +690,7 @@ CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_PXA=y
 # CONFIG_I2C_PXA_SLAVE is not set
 # CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
 
 #
 # External I2C/SMBus adapter drivers
@@ -679,15 +703,9 @@ CONFIG_I2C_PXA=y
 #
 # CONFIG_I2C_PCA_PLATFORM is not set
 # CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
 # CONFIG_SPI is not set
 
 #
@@ -702,13 +720,16 @@ CONFIG_GPIOLIB=y
 #
 # Memory mapped GPIO expanders:
 #
+# CONFIG_GPIO_IT8761E is not set
 
 #
 # I2C GPIO expanders:
 #
+# CONFIG_GPIO_MAX7300 is not set
 # CONFIG_GPIO_MAX732X is not set
 # CONFIG_GPIO_PCA953X is not set
 # CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_ADP5588 is not set
 
 #
 # PCI GPIO expanders:
@@ -737,10 +758,12 @@ CONFIG_SSB_POSSIBLE=y
 # Multifunction device drivers
 #
 CONFIG_MFD_CORE=y
+# CONFIG_MFD_88PM860X is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_MFD_ASIC3 is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
 # CONFIG_TPS65010 is not set
 # CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
@@ -749,24 +772,27 @@ CONFIG_MFD_CORE=y
 # CONFIG_MFD_TC6393XB is not set
 # CONFIG_PMIC_DA903X is not set
 # CONFIG_PMIC_ADP5520 is not set
+CONFIG_MFD_MAX8925=y
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM831X is not set
 # CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
 # CONFIG_MFD_PCF50633 is not set
 # CONFIG_AB3100_CORE is not set
-CONFIG_MFD_88PM8607=y
 CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_DUMMY is not set
 # CONFIG_REGULATOR_FIXED_VOLTAGE is not set
 # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
 # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
 # CONFIG_REGULATOR_BQ24022 is not set
 # CONFIG_REGULATOR_MAX1586 is not set
-CONFIG_REGULATOR_MAX8660=y
+CONFIG_REGULATOR_MAX8649=y
+# CONFIG_REGULATOR_MAX8660 is not set
+CONFIG_REGULATOR_MAX8925=y
 # CONFIG_REGULATOR_LP3971 is not set
 # CONFIG_REGULATOR_TPS65023 is not set
 # CONFIG_REGULATOR_TPS6507X is not set
-CONFIG_REGULATOR_88PM8607=y
 # CONFIG_MEDIA_SUPPORT is not set
 
 #
@@ -781,6 +807,7 @@ CONFIG_LCD_CLASS_DEVICE=y
 # CONFIG_LCD_PLATFORM is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_BACKLIGHT_MAX8925=y
 
 #
 # Display device support
@@ -821,6 +848,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_DS1374 is not set
 # CONFIG_RTC_DRV_DS1672 is not set
 # CONFIG_RTC_DRV_MAX6900 is not set
+CONFIG_RTC_DRV_MAX8925=y
 # CONFIG_RTC_DRV_RS5C372 is not set
 # CONFIG_RTC_DRV_ISL1208 is not set
 # CONFIG_RTC_DRV_X1205 is not set
@@ -872,7 +900,6 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_EXT2_FS is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_EXT4_FS is not set
-CONFIG_EXT4_USE_FOR_EXT23=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
@@ -883,7 +910,7 @@ CONFIG_FS_POSIX_ACL=y
 # CONFIG_NILFS2_FS is not set
 CONFIG_FILE_LOCKING=y
 CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
+# CONFIG_DNOTIFY is not set
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
@@ -940,6 +967,7 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+# CONFIG_LOGFS is not set
 CONFIG_CRAMFS=y
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -967,6 +995,7 @@ CONFIG_SUNRPC_GSS=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
@@ -990,7 +1019,7 @@ CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
@@ -1032,6 +1061,7 @@ CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 # CONFIG_SYSCTL_SYSCALL_CHECK is not set
@@ -1052,6 +1082,7 @@ CONFIG_BRANCH_PROFILE_NONE=y
 # CONFIG_KMEMTRACE is not set
 # CONFIG_WORKQUEUE_TRACER is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_DYNAMIC_DEBUG=y
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
@@ -1059,9 +1090,7 @@ CONFIG_ARM_UNWIND=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_STACK_USAGE is not set
-CONFIG_DEBUG_LL=y
-# CONFIG_EARLY_PRINTK is not set
-# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_LL is not set
 # CONFIG_OC_ETM is not set
 
 #
diff --git a/arch/arm/configs/n8x0_defconfig b/arch/arm/configs/n8x0_defconfig
index 216ad00948af..9405e32783de 100644
--- a/arch/arm/configs/n8x0_defconfig
+++ b/arch/arm/configs/n8x0_defconfig
@@ -1058,7 +1058,6 @@ CONFIG_JFFS2_CMODE_PRIORITY=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 # CONFIG_NFS_FS is not set
 # CONFIG_NFSD is not set
diff --git a/arch/arm/configs/omap_zoom2_defconfig b/arch/arm/configs/omap_zoom2_defconfig
index f5c6e11cf189..881faea03d79 100644
--- a/arch/arm/configs/omap_zoom2_defconfig
+++ b/arch/arm/configs/omap_zoom2_defconfig
@@ -661,7 +661,7 @@ CONFIG_DEVKMEM=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
 CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_MANY_PORTS=y
 CONFIG_SERIAL_8250_SHARE_IRQ=y
diff --git a/arch/arm/configs/omap_zoom3_defconfig b/arch/arm/configs/omap_zoom3_defconfig
index ea9a5012d332..5e55b550a408 100644
--- a/arch/arm/configs/omap_zoom3_defconfig
+++ b/arch/arm/configs/omap_zoom3_defconfig
@@ -680,7 +680,7 @@ CONFIG_DEVKMEM=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
 CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_MANY_PORTS=y
 CONFIG_SERIAL_8250_SHARE_IRQ=y
diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig
index 45135ffadc57..473f9e13f08b 100644
--- a/arch/arm/configs/rx51_defconfig
+++ b/arch/arm/configs/rx51_defconfig
@@ -59,8 +59,6 @@ CONFIG_FAIR_GROUP_SCHED=y
 CONFIG_USER_SCHED=y
 # CONFIG_CGROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
@@ -480,7 +478,6 @@ CONFIG_BT_HIDP=m
 # CONFIG_BT_HCIBFUSB is not set
 # CONFIG_BT_HCIVHCI is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
 CONFIG_WIRELESS=y
 CONFIG_CFG80211=y
 # CONFIG_CFG80211_REG_DEBUG is not set
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 00f46d9ce299..6e8f05c8a1c8 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -149,10 +149,10 @@
 
 #define USER(x...)                              \
 9999:   x;                                      \
-        .section __ex_table,"a";                \
+        .pushsection __ex_table,"a";            \
         .align  3;                              \
         .long   9999b,9001f;                    \
-        .previous
+        .popsection
 
 /*
  * SMP data memory barrier
@@ -193,10 +193,10 @@
         .error  "Unsupported inc macro argument"
         .endif
 
-        .section __ex_table,"a"
+        .pushsection __ex_table,"a"
         .align  3
         .long   9999b, \abort
-        .previous
+        .popsection
         .endm
 
         .macro  usracc, instr, reg, ptr, inc, cond, rept, abort
@@ -234,10 +234,10 @@
         .error  "Unsupported inc macro argument"
         .endif
 
-        .section __ex_table,"a"
+        .pushsection __ex_table,"a"
         .align  3
         .long   9999b, \abort
-        .previous
+        .popsection
         .endr
         .endm
 
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 72da7e045c6b..0d08d4170b64 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -15,6 +15,7 @@
 #include <asm/glue.h>
 #include <asm/shmparam.h>
 #include <asm/cachetype.h>
+#include <asm/outercache.h>
 
 #define CACHE_COLOUR(vaddr)     ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
 
@@ -219,12 +220,6 @@ struct cpu_cache_fns {
         void (*dma_flush_range)(const void *, const void *);
 };
 
-struct outer_cache_fns {
-        void (*inv_range)(unsigned long, unsigned long);
-        void (*clean_range)(unsigned long, unsigned long);
-        void (*flush_range)(unsigned long, unsigned long);
-};
-
 /*
  * Select the calling method
  */
@@ -281,37 +276,6 @@ extern void dmac_flush_range(const void *, const void *);
 
 #endif
 
-#ifdef CONFIG_OUTER_CACHE
-
-extern struct outer_cache_fns outer_cache;
-
-static inline void outer_inv_range(unsigned long start, unsigned long end)
-{
-        if (outer_cache.inv_range)
-                outer_cache.inv_range(start, end);
-}
-static inline void outer_clean_range(unsigned long start, unsigned long end)
-{
-        if (outer_cache.clean_range)
-                outer_cache.clean_range(start, end);
-}
-static inline void outer_flush_range(unsigned long start, unsigned long end)
-{
-        if (outer_cache.flush_range)
-                outer_cache.flush_range(start, end);
-}
-
-#else
-
-static inline void outer_inv_range(unsigned long start, unsigned long end)
-{ }
-static inline void outer_clean_range(unsigned long start, unsigned long end)
-{ }
-static inline void outer_flush_range(unsigned long start, unsigned long end)
-{ }
-
-#endif
-
 /*
  * Copy user data from/to a page which is mapped into a different
  * processes address space.  Really, we want to allow our "user
diff --git a/arch/arm/include/asm/clkdev.h b/arch/arm/include/asm/clkdev.h
index 7a0690da5e63..b56c1389b6fa 100644
--- a/arch/arm/include/asm/clkdev.h
+++ b/arch/arm/include/asm/clkdev.h
@@ -13,6 +13,7 @@
 #define __ASM_CLKDEV_H
 
 struct clk;
+struct device;
 
 struct clk_lookup {
         struct list_head        node;
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index bff056489cc1..51662feb9f1d 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -9,6 +9,8 @@
 #include <asm/ptrace.h>
 #include <asm/user.h>
 
+struct task_struct;
+
 typedef unsigned long elf_greg_t;
 typedef unsigned long elf_freg_t[3];
 
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index bfcc15929a7f..540a044153a5 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -21,14 +21,14 @@
         "2:     strt    %0, [%2]\n"                             \
         "       mov     %0, #0\n"                               \
         "3:\n"                                                  \
-        "       .section __ex_table,\"a\"\n"                    \
+        "       .pushsection __ex_table,\"a\"\n"                \
         "       .align  3\n"                                    \
         "       .long   1b, 4f, 2b, 4f\n"                       \
-        "       .previous\n"                                    \
-        "       .section .fixup,\"ax\"\n"                       \
+        "       .popsection\n"                                  \
+        "       .pushsection .fixup,\"ax\"\n"                   \
         "4:     mov     %0, %4\n"                               \
         "       b       3b\n"                                   \
-        "       .previous"                                      \
+        "       .popsection"                                    \
         : "=&r" (ret), "=&r" (oldval)                           \
         : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT)              \
         : "cc", "memory")
@@ -102,14 +102,14 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
         "       it      eq      @ explicit IT needed for the 2b label\n"
         "2:     streqt  %2, [%3]\n"
         "3:\n"
-        "       .section __ex_table,\"a\"\n"
+        "       .pushsection __ex_table,\"a\"\n"
         "       .align  3\n"
         "       .long   1b, 4f, 2b, 4f\n"
-        "       .previous\n"
-        "       .section .fixup,\"ax\"\n"
+        "       .popsection\n"
+        "       .pushsection .fixup,\"ax\"\n"
         "4:     mov     %0, %4\n"
         "       b       3b\n"
-        "       .previous"
+        "       .popsection"
         : "=&r" (val)
         : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
         : "cc", "memory");
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
index 7f36d00600b4..feb988a7ec37 100644
--- a/arch/arm/include/asm/highmem.h
+++ b/arch/arm/include/asm/highmem.h
@@ -11,7 +11,11 @@
 
 #define kmap_prot               PAGE_KERNEL
 
-#define flush_cache_kmaps()     flush_cache_all()
+#define flush_cache_kmaps() \
+        do { \
+                if (cache_is_vivt()) \
+                        flush_cache_all(); \
+        } while (0)
 
 extern pte_t *pkmap_page_table;
 
@@ -21,11 +25,20 @@ extern void *kmap_high(struct page *page);
 extern void *kmap_high_get(struct page *page);
 extern void kunmap_high(struct page *page);
 
+extern void *kmap_high_l1_vipt(struct page *page, pte_t *saved_pte);
+extern void kunmap_high_l1_vipt(struct page *page, pte_t saved_pte);
+
+/*
+ * The following functions are already defined by <linux/highmem.h>
+ * when CONFIG_HIGHMEM is not set.
+ */
+#ifdef CONFIG_HIGHMEM
 extern void *kmap(struct page *page);
 extern void kunmap(struct page *page);
 extern void *kmap_atomic(struct page *page, enum km_type type);
 extern void kunmap_atomic(void *kvaddr, enum km_type type);
 extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
 extern struct page *kmap_atomic_to_page(const void *ptr);
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 328f14a8b790..237282f7c762 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -17,6 +17,7 @@
 
 #ifndef __ASSEMBLY__
 struct irqaction;
+struct pt_regs;
 extern void migrate_irqs(void);
 
 extern void asm_do_IRQ(unsigned int, struct pt_regs *);
diff --git a/arch/arm/include/asm/kmap_types.h b/arch/arm/include/asm/kmap_types.h
index c019949a5189..c4b2ea3fbe42 100644
--- a/arch/arm/include/asm/kmap_types.h
+++ b/arch/arm/include/asm/kmap_types.h
@@ -18,6 +18,7 @@ enum km_type {
         KM_IRQ1,
         KM_SOFTIRQ0,
         KM_SOFTIRQ1,
+        KM_L1_CACHE,
         KM_L2_CACHE,
         KM_TYPE_NR
 };
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
new file mode 100644
index 000000000000..25f76bae57ab
--- /dev/null
+++ b/arch/arm/include/asm/outercache.h
@@ -0,0 +1,75 @@
+/*
+ * arch/arm/include/asm/outercache.h
+ *
+ * Copyright (C) 2010 ARM Ltd.
+ * Written by Catalin Marinas <catalin.marinas@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_OUTERCACHE_H
+#define __ASM_OUTERCACHE_H
+
+struct outer_cache_fns {
+        void (*inv_range)(unsigned long, unsigned long);
+        void (*clean_range)(unsigned long, unsigned long);
+        void (*flush_range)(unsigned long, unsigned long);
+#ifdef CONFIG_OUTER_CACHE_SYNC
+        void (*sync)(void);
+#endif
+};
+
+#ifdef CONFIG_OUTER_CACHE
+
+extern struct outer_cache_fns outer_cache;
+
+static inline void outer_inv_range(unsigned long start, unsigned long end)
+{
+        if (outer_cache.inv_range)
+                outer_cache.inv_range(start, end);
+}
+static inline void outer_clean_range(unsigned long start, unsigned long end)
+{
+        if (outer_cache.clean_range)
+                outer_cache.clean_range(start, end);
+}
+static inline void outer_flush_range(unsigned long start, unsigned long end)
+{
+        if (outer_cache.flush_range)
+                outer_cache.flush_range(start, end);
+}
+
+#else
+
+static inline void outer_inv_range(unsigned long start, unsigned long end)
+{ }
+static inline void outer_clean_range(unsigned long start, unsigned long end)
+{ }
+static inline void outer_flush_range(unsigned long start, unsigned long end)
+{ }
+
+#endif
+
+#ifdef CONFIG_OUTER_CACHE_SYNC
+static inline void outer_sync(void)
+{
+        if (outer_cache.sync)
+                outer_cache.sync();
+}
+#else
+static inline void outer_sync(void)
+{ }
+#endif
+
+#endif  /* __ASM_OUTERCACHE_H */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 02f5d99adbc0..5f4f48002734 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -60,6 +60,8 @@
 #include <linux/linkage.h>
 #include <linux/irqflags.h>
 
+#include <asm/outercache.h>
+
 #define __exception     __attribute__((section(".exception.text")))
 
 struct thread_info;
@@ -137,10 +139,12 @@ extern unsigned int user_debug;
 #define dmb() __asm__ __volatile__ ("" : : : "memory")
 #endif
 
-#if defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
-#define mb()            dmb()
+#ifdef CONFIG_ARCH_HAS_BARRIERS
+#include <mach/barriers.h>
+#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
+#define mb()            do { dsb(); outer_sync(); } while (0)
 #define rmb()           dmb()
-#define wmb()           dmb()
+#define wmb()           mb()
 #else
 #define mb()    do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 #define rmb()   do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
@@ -152,9 +156,9 @@ extern unsigned int user_debug;
 #define smp_rmb()       barrier()
 #define smp_wmb()       barrier()
 #else
-#define smp_mb()        mb()
-#define smp_rmb()       rmb()
-#define smp_wmb()       wmb()
+#define smp_mb()        dmb()
+#define smp_rmb()       dmb()
+#define smp_wmb()       dmb()
 #endif
 
 #define read_barrier_depends()          do { } while(0)
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 1d6bd40a4322..33e4a48fe103 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -229,16 +229,16 @@ do {									\
         __asm__ __volatile__(                                   \
         "1:     ldrbt   %1,[%2]\n"                              \
         "2:\n"                                                  \
-        "       .section .fixup,\"ax\"\n"                       \
+        "       .pushsection .fixup,\"ax\"\n"                   \
         "       .align  2\n"                                    \
         "3:     mov     %0, %3\n"                               \
         "       mov     %1, #0\n"                               \
         "       b       2b\n"                                   \
-        "       .previous\n"                                    \
-        "       .section __ex_table,\"a\"\n"                    \
+        "       .popsection\n"                                  \
+        "       .pushsection __ex_table,\"a\"\n"                \
         "       .align  3\n"                                    \
         "       .long   1b, 3b\n"                               \
-        "       .previous"                                      \
+        "       .popsection"                                    \
         : "+r" (err), "=&r" (x)                                 \
         : "r" (addr), "i" (-EFAULT)                             \
         : "cc")
@@ -265,16 +265,16 @@ do {									\
         __asm__ __volatile__(                                   \
         "1:     ldrt    %1,[%2]\n"                              \
         "2:\n"                                                  \
-        "       .section .fixup,\"ax\"\n"                       \
+        "       .pushsection .fixup,\"ax\"\n"                   \
         "       .align  2\n"                                    \
         "3:     mov     %0, %3\n"                               \
         "       mov     %1, #0\n"                               \
         "       b       2b\n"                                   \
-        "       .previous\n"                                    \
-        "       .section __ex_table,\"a\"\n"                    \
+        "       .popsection\n"                                  \
+        "       .pushsection __ex_table,\"a\"\n"                \
         "       .align  3\n"                                    \
         "       .long   1b, 3b\n"                               \
-        "       .previous"                                      \
+        "       .popsection"                                    \
         : "+r" (err), "=&r" (x)                                 \
         : "r" (addr), "i" (-EFAULT)                             \
         : "cc")
@@ -310,15 +310,15 @@ do {									\
         __asm__ __volatile__(                                   \
         "1:     strbt   %1,[%2]\n"                              \
         "2:\n"                                                  \
-        "       .section .fixup,\"ax\"\n"                       \
+        "       .pushsection .fixup,\"ax\"\n"                   \
         "       .align  2\n"                                    \
         "3:     mov     %0, %3\n"                               \
         "       b       2b\n"                                   \
-        "       .previous\n"                                    \
-        "       .section __ex_table,\"a\"\n"                    \
+        "       .popsection\n"                                  \
+        "       .pushsection __ex_table,\"a\"\n"                \
         "       .align  3\n"                                    \
         "       .long   1b, 3b\n"                               \
-        "       .previous"                                      \
+        "       .popsection"                                    \
         : "+r" (err)                                            \
         : "r" (x), "r" (__pu_addr), "i" (-EFAULT)               \
         : "cc")
@@ -343,15 +343,15 @@ do {									\
         __asm__ __volatile__(                                   \
         "1:     strt    %1,[%2]\n"                              \
         "2:\n"                                                  \
-        "       .section .fixup,\"ax\"\n"                       \
+        "       .pushsection .fixup,\"ax\"\n"                   \
         "       .align  2\n"                                    \
         "3:     mov     %0, %3\n"                               \
         "       b       2b\n"                                   \
-        "       .previous\n"                                    \
-        "       .section __ex_table,\"a\"\n"                    \
+        "       .popsection\n"                                  \
+        "       .pushsection __ex_table,\"a\"\n"                \
         "       .align  3\n"                                    \
         "       .long   1b, 3b\n"                               \
-        "       .previous"                                      \
+        "       .popsection"                                    \
         : "+r" (err)                                            \
         : "r" (x), "r" (__pu_addr), "i" (-EFAULT)               \
         : "cc")
@@ -371,16 +371,16 @@ do {									\
  THUMB( "1:     strt    " __reg_oper1 ", [%1]\n"        )       \
  THUMB( "2:     strt    " __reg_oper0 ", [%1, #4]\n"    )       \
         "3:\n"                                                  \
-        "       .section .fixup,\"ax\"\n"                       \
+        "       .pushsection .fixup,\"ax\"\n"                   \
         "       .align  2\n"                                    \
         "4:     mov     %0, %3\n"                               \
         "       b       3b\n"                                   \
-        "       .previous\n"                                    \
-        "       .section __ex_table,\"a\"\n"                    \
+        "       .popsection\n"                                  \
+        "       .pushsection __ex_table,\"a\"\n"                \
         "       .align  3\n"                                    \
         "       .long   1b, 4b\n"                               \
         "       .long   2b, 4b\n"                               \
-        "       .previous"                                      \
+        "       .popsection"                                    \
         : "+r" (err), "+r" (__pu_addr)                          \
         : "r" (x), "i" (-EFAULT)                                \
         : "cc")
diff --git a/arch/arm/include/asm/ucontext.h b/arch/arm/include/asm/ucontext.h
index bf65e9f4525d..47f023aa8495 100644
--- a/arch/arm/include/asm/ucontext.h
+++ b/arch/arm/include/asm/ucontext.h
@@ -59,23 +59,22 @@ struct iwmmxt_sigframe {
 #endif /* CONFIG_IWMMXT */
 
 #ifdef CONFIG_VFP
-#if __LINUX_ARM_ARCH__ < 6
-/* For ARM pre-v6, we use fstmiax and fldmiax.  This adds one extra
- * word after the registers, and a word of padding at the end for
- * alignment.  */
 #define VFP_MAGIC               0x56465001
-#define VFP_STORAGE_SIZE        152
-#else
-#define VFP_MAGIC               0x56465002
-#define VFP_STORAGE_SIZE        144
-#endif
 
 struct vfp_sigframe
 {
         unsigned long           magic;
         unsigned long           size;
-        union vfp_state         storage;
-};
+        struct user_vfp         ufp;
+        struct user_vfp_exc     ufp_exc;
+} __attribute__((__aligned__(8)));
+
+/*
+ *  8 byte for magic and size, 264 byte for ufp, 12 bytes for ufp_exc,
+ *  4 bytes padding.
+ */
+#define VFP_STORAGE_SIZE        sizeof(struct vfp_sigframe)
+
 #endif /* CONFIG_VFP */
 
 /*
@@ -91,7 +90,7 @@ struct aux_sigframe {
 #ifdef CONFIG_IWMMXT
         struct iwmmxt_sigframe  iwmmxt;
 #endif
-#if 0 && defined CONFIG_VFP /* Not yet saved.  */
+#ifdef CONFIG_VFP
         struct vfp_sigframe     vfp;
 #endif
         /* Something that isn't a valid magic number for any coprocessor.  */
diff --git a/arch/arm/include/asm/user.h b/arch/arm/include/asm/user.h
index df95e050f9dd..05ac4b06876a 100644
--- a/arch/arm/include/asm/user.h
+++ b/arch/arm/include/asm/user.h
@@ -83,11 +83,21 @@ struct user{
 
 /*
  * User specific VFP registers. If only VFPv2 is present, registers 16 to 31
- * are ignored by the ptrace system call.
+ * are ignored by the ptrace system call and the signal handler.
  */
 struct user_vfp {
         unsigned long long fpregs[32];
         unsigned long fpscr;
 };
 
+/*
+ * VFP exception registers exposed to user space during signal delivery.
+ * Fields not relavant to the current VFP architecture are ignored.
+ */
+struct user_vfp_exc {
+        unsigned long   fpexc;
+        unsigned long   fpinst;
+        unsigned long   fpinst2;
+};
+
 #endif /* _ARM_USER_H */
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 6c5cf369183b..7ee48e7f8f31 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -523,16 +523,16 @@ ENDPROC(__und_usr)
 /*
  * The out of line fixup for the ldrt above.
  */
-        .section .fixup, "ax"
+        .pushsection .fixup, "ax"
 4:      mov     pc, r9
-        .previous
-        .section __ex_table,"a"
+        .popsection
+        .pushsection __ex_table,"a"
         .long   1b, 4b
 #if __LINUX_ARM_ARCH__ >= 7
         .long   2b, 4b
         .long   3b, 4b
 #endif
-        .previous
+        .popsection
 
 /*
  * Check whether the instruction is a co-processor instruction.
@@ -676,10 +676,10 @@ do_fpe:
  *  lr  = unrecognised FP instruction return address
  */
 
-        .data
+        .pushsection .data
 ENTRY(fp_enter)
         .word   no_fp
-        .previous
+        .popsection
 
 ENTRY(no_fp)
         mov     pc, lr
diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c
index c63842766229..0298286ad4ad 100644
--- a/arch/arm/kernel/ftrace.c
+++ b/arch/arm/kernel/ftrace.c
@@ -62,15 +62,15 @@ int ftrace_modify_code(unsigned long pc, unsigned char *old_code,
                 "    movne  %0, #2    \n"
                 "3:\n"
 
-                ".section .fixup, \"ax\"\n"
+                ".pushsection .fixup, \"ax\"\n"
                 "4:  mov  %0, #1  \n"
                 "    b    3b      \n"
-                ".previous\n"
+                ".popsection\n"
 
-                ".section __ex_table, \"a\"\n"
+                ".pushsection __ex_table, \"a\"\n"
                 "    .long 1b, 4b \n"
                 "    .long 2b, 4b \n"
-                ".previous\n"
+                ".popsection\n"
 
                 : "=r"(err), "=r"(replaced)
                 : "r"(pc), "r"(new), "r"(old), "0"(err), "1"(replaced)
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index b7cb45bb91e8..3b3d2c80509c 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -27,7 +27,6 @@
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/slab.h>
 #include <linux/random.h>
 #include <linux/smp.h>
 #include <linux/init.h>
diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c
index 60c62c377fa9..2ba7deb3072e 100644
--- a/arch/arm/kernel/kprobes.c
+++ b/arch/arm/kernel/kprobes.c
@@ -22,6 +22,7 @@
 #include <linux/kernel.h>
 #include <linux/kprobes.h>
 #include <linux/module.h>
+#include <linux/slab.h>
 #include <linux/stop_machine.h>
 #include <linux/stringify.h>
 #include <asm/traps.h>
@@ -393,6 +394,14 @@ void __kprobes jprobe_return(void)
                 /*
                  * Setup an empty pt_regs. Fill SP and PC fields as
                  * they're needed by longjmp_break_handler.
+                 *
+                 * We allocate some slack between the original SP and start of
+                 * our fabricated regs. To be precise we want to have worst case
+                 * covered which is STMFD with all 16 regs so we allocate 2 *
+                 * sizeof(struct_pt_regs)).
+                 *
+                 * This is to prevent any simulated instruction from writing
+                 * over the regs when they are accessing the stack.
                  */
                 "sub    sp, %0, %1              \n\t"
                 "ldr    r0, ="__stringify(JPROBE_MAGIC_ADDR)"\n\t"
@@ -410,7 +419,7 @@ void __kprobes jprobe_return(void)
                 "ldmia  sp, {r0 - pc}           \n\t"
                 :
                 : "r" (kcb->jprobe_saved_regs.ARM_sp),
-                  "I" (sizeof(struct pt_regs)),
+                  "I" (sizeof(struct pt_regs) * 2),
                   "J" (offsetof(struct pt_regs, ARM_sp)),
                   "J" (offsetof(struct pt_regs, ARM_pc)),
                   "J" (offsetof(struct pt_regs, ARM_cpsr))
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index f28c5e9c51ea..c628bdf6c430 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -16,9 +16,9 @@
 #include <linux/mm.h>
 #include <linux/elf.h>
 #include <linux/vmalloc.h>
-#include <linux/slab.h>
 #include <linux/fs.h>
 #include <linux/string.h>
+#include <linux/gfp.h>
 
 #include <asm/pgtable.h>
 #include <asm/sections.h>
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index ba2adefa53f7..acf5e6fdb6dc 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -16,7 +16,6 @@
 #include <linux/mm.h>
 #include <linux/stddef.h>
 #include <linux/unistd.h>
-#include <linux/slab.h>
 #include <linux/user.h>
 #include <linux/delay.h>
 #include <linux/reboot.h>
@@ -356,7 +355,7 @@ EXPORT_SYMBOL(dump_fpu);
  * the thread function, and r3 points to the exit function.
  */
 extern void kernel_thread_helper(void);
-asm(    ".section .text\n"
+asm(    ".pushsection .text\n"
 "       .align\n"
 "       .type   kernel_thread_helper, #function\n"
 "kernel_thread_helper:\n"
@@ -364,11 +363,11 @@ asm(	".section .text\n"
 "       mov     lr, r3\n"
 "       mov     pc, r2\n"
 "       .size   kernel_thread_helper, . - kernel_thread_helper\n"
-"       .previous");
+"       .popsection");
 
 #ifdef CONFIG_ARM_UNWIND
 extern void kernel_thread_exit(long code);
-asm(    ".section .text\n"
+asm(    ".pushsection .text\n"
 "       .align\n"
 "       .type   kernel_thread_exit, #function\n"
 "kernel_thread_exit:\n"
@@ -378,7 +377,7 @@ asm(	".section .text\n"
 "       nop\n"
 "       .fnend\n"
 "       .size   kernel_thread_exit, . - kernel_thread_exit\n"
-"       .previous");
+"       .popsection");
 #else
 #define kernel_thread_exit      do_exit
 #endif
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index e7714f367eb8..907d5a620bca 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -18,6 +18,7 @@
 #include <asm/cacheflush.h>
 #include <asm/ucontext.h>
 #include <asm/unistd.h>
+#include <asm/vfp.h>
 
 #include "ptrace.h"
 #include "signal.h"
@@ -175,6 +176,90 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame)
 
 #endif
 
+#ifdef CONFIG_VFP
+
+static int preserve_vfp_context(struct vfp_sigframe __user *frame)
+{
+        struct thread_info *thread = current_thread_info();
+        struct vfp_hard_struct *h = &thread->vfpstate.hard;
+        const unsigned long magic = VFP_MAGIC;
+        const unsigned long size = VFP_STORAGE_SIZE;
+        int err = 0;
+
+        vfp_sync_hwstate(thread);
+        __put_user_error(magic, &frame->magic, err);
+        __put_user_error(size, &frame->size, err);
+
+        /*
+         * Copy the floating point registers. There can be unused
+         * registers see asm/hwcap.h for details.
+         */
+        err |= __copy_to_user(&frame->ufp.fpregs, &h->fpregs,
+                              sizeof(h->fpregs));
+        /*
+         * Copy the status and control register.
+         */
+        __put_user_error(h->fpscr, &frame->ufp.fpscr, err);
+
+        /*
+         * Copy the exception registers.
+         */
+        __put_user_error(h->fpexc, &frame->ufp_exc.fpexc, err);
+        __put_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
+        __put_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
+
+        return err ? -EFAULT : 0;
+}
+
+static int restore_vfp_context(struct vfp_sigframe __user *frame)
+{
+        struct thread_info *thread = current_thread_info();
+        struct vfp_hard_struct *h = &thread->vfpstate.hard;
+        unsigned long magic;
+        unsigned long size;
+        unsigned long fpexc;
+        int err = 0;
+
+        __get_user_error(magic, &frame->magic, err);
+        __get_user_error(size, &frame->size, err);
+
+        if (err)
+                return -EFAULT;
+        if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
+                return -EINVAL;
+
+        /*
+         * Copy the floating point registers. There can be unused
+         * registers see asm/hwcap.h for details.
+         */
+        err |= __copy_from_user(&h->fpregs, &frame->ufp.fpregs,
+                                sizeof(h->fpregs));
+        /*
+         * Copy the status and control register.
+         */
+        __get_user_error(h->fpscr, &frame->ufp.fpscr, err);
+
+        /*
+         * Sanitise and restore the exception registers.
+         */
+        __get_user_error(fpexc, &frame->ufp_exc.fpexc, err);
+        /* Ensure the VFP is enabled. */
+        fpexc |= FPEXC_EN;
+        /* Ensure FPINST2 is invalid and the exception flag is cleared. */
+        fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
+        h->fpexc = fpexc;
+
+        __get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
+        __get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
+
+        if (!err)
+                vfp_flush_hwstate(thread);
+
+        return err ? -EFAULT : 0;
+}
+
+#endif
+
 /*
  * Do a signal return; undo the signal stack.  These are aligned to 64-bit.
  */
@@ -233,8 +318,8 @@ static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf)
                 err |= restore_iwmmxt_context(&aux->iwmmxt);
 #endif
 #ifdef CONFIG_VFP
-//      if (err == 0)
-//              err |= vfp_restore_state(&sf->aux.vfp);
+        if (err == 0)
+                err |= restore_vfp_context(&aux->vfp);
 #endif
 
         return err;
@@ -348,8 +433,8 @@ setup_sigframe(struct sigframe __user *sf, struct pt_regs *regs, sigset_t *set)
                 err |= preserve_iwmmxt_context(&aux->iwmmxt);
 #endif
 #ifdef CONFIG_VFP
-//      if (err == 0)
-//              err |= vfp_save_state(&sf->aux.vfp);
+        if (err == 0)
+                err |= preserve_vfp_context(&aux->vfp);
 #endif
         __put_user_error(0, &aux->end_magic, err);
 
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 7a3cc0266934..b8c3d0f689d9 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -86,6 +86,12 @@ int __cpuinit __cpu_up(unsigned int cpu)
                         return PTR_ERR(idle);
                 }
                 ci->idle = idle;
+        } else {
+                /*
+                 * Since this idle thread is being re-used, call
+                 * init_idle() to reinitialize the thread structure.
+                 */
+                init_idle(idle, cpu);
         }
 
         /*
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index 4350f75e578c..c23501842b98 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -15,7 +15,6 @@
 #include <linux/module.h>
 #include <linux/errno.h>
 #include <linux/sched.h>
-#include <linux/slab.h>
 #include <linux/mm.h>
 #include <linux/sem.h>
 #include <linux/msg.h>
@@ -27,6 +26,7 @@
 #include <linux/file.h>
 #include <linux/ipc.h>
 #include <linux/uaccess.h>
+#include <linux/slab.h>
 
 /* Fork a new task - this creates a new program thread.
  * This is called indirectly via a small wrapper
diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S
index aaf7220d9e30..a673297b0cf1 100644
--- a/arch/arm/lib/backtrace.S
+++ b/arch/arm/lib/backtrace.S
@@ -110,13 +110,13 @@ no_frame:	ldmfd	sp!, {r4 - r8, pc}
 ENDPROC(__backtrace)
 ENDPROC(c_backtrace)
                 
-                .section __ex_table,"a"
+                .pushsection __ex_table,"a"
                 .align  3
                 .long   1001b, 1006b
                 .long   1002b, 1006b
                 .long   1003b, 1006b
                 .long   1004b, 1006b
-                .previous
+                .popsection
 
 #define instr r4
 #define reg   r5
diff --git a/arch/arm/lib/clear_user.S b/arch/arm/lib/clear_user.S
index 1279abd8b886..5e3f99620c04 100644
--- a/arch/arm/lib/clear_user.S
+++ b/arch/arm/lib/clear_user.S
@@ -46,8 +46,8 @@ USER(		strnebt	r2, [r0])
                 ldmfd   sp!, {r1, pc}
 ENDPROC(__clear_user)
 
-                .section .fixup,"ax"
+                .pushsection .fixup,"ax"
                 .align  0
 9001:           ldmfd   sp!, {r0, pc}
-                .previous
+                .popsection
 
diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S
index e4fe124acedc..66a477a3e3cc 100644
--- a/arch/arm/lib/copy_from_user.S
+++ b/arch/arm/lib/copy_from_user.S
@@ -90,7 +90,7 @@ ENTRY(__copy_from_user)
 
 ENDPROC(__copy_from_user)
 
-        .section .fixup,"ax"
+        .pushsection .fixup,"ax"
         .align 0
         copy_abort_preamble
         ldmfd   sp!, {r1, r2}
@@ -100,5 +100,5 @@ ENDPROC(__copy_from_user)
         bl      __memzero
         ldr     r0, [sp], #4
         copy_abort_end
-        .previous
+        .popsection
 
diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
index 1a71e1584442..027b69bdbad1 100644
--- a/arch/arm/lib/copy_to_user.S
+++ b/arch/arm/lib/copy_to_user.S
@@ -94,12 +94,12 @@ WEAK(__copy_to_user)
 
 ENDPROC(__copy_to_user)
 
-        .section .fixup,"ax"
+        .pushsection .fixup,"ax"
         .align 0
         copy_abort_preamble
         ldmfd   sp!, {r1, r2, r3}
         sub     r0, r0, r1
         rsb     r0, r0, r2
         copy_abort_end
-        .previous
+        .popsection
 
diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S
index fd0e9dcd9fdc..59ff6fdc1e63 100644
--- a/arch/arm/lib/csumpartialcopyuser.S
+++ b/arch/arm/lib/csumpartialcopyuser.S
@@ -68,7 +68,7 @@
  * so properly, we would have to add in whatever registers were loaded before
  * the fault, which, with the current asm above is not predictable.
  */
-                .section .fixup,"ax"
+                .pushsection .fixup,"ax"
                 .align  4
 9001:           mov     r4, #-EFAULT
                 ldr     r5, [fp, #4]            @ *err_ptr
@@ -80,4 +80,4 @@
                 strneb  r0, [r1], #1
                 bne     9002b
                 load_regs
-                .previous
+                .popsection
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index a1814d927122..b1631a7dbe75 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -64,9 +64,9 @@ __get_user_bad:
         mov     pc, lr
 ENDPROC(__get_user_bad)
 
-.section __ex_table, "a"
+.pushsection __ex_table, "a"
         .long   1b, __get_user_bad
         .long   2b, __get_user_bad
         .long   3b, __get_user_bad
         .long   4b, __get_user_bad
-.previous
+.popsection
diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
index 5025c863713d..938fc14f962d 100644
--- a/arch/arm/lib/memmove.S
+++ b/arch/arm/lib/memmove.S
@@ -74,7 +74,7 @@ ENTRY(memmove)
                 rsb     ip, ip, #32
                 addne   pc, pc, ip              @ C is always clear here
                 b       7f
-6:              nop
+6:              W(nop)
                 W(ldr)  r3, [r1, #-4]!
                 W(ldr)  r4, [r1, #-4]!
                 W(ldr)  r5, [r1, #-4]!
@@ -85,7 +85,7 @@ ENTRY(memmove)
 
                 add     pc, pc, ip
                 nop
-                nop
+                W(nop)
                 W(str)  r3, [r0, #-4]!
                 W(str)  r4, [r0, #-4]!
                 W(str)  r5, [r0, #-4]!
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S
index 02fedbf07c0d..5a01a23c6c06 100644
--- a/arch/arm/lib/putuser.S
+++ b/arch/arm/lib/putuser.S
@@ -81,11 +81,11 @@ __put_user_bad:
         mov     pc, lr
 ENDPROC(__put_user_bad)
 
-.section __ex_table, "a"
+.pushsection __ex_table, "a"
         .long   1b, __put_user_bad
         .long   2b, __put_user_bad
         .long   3b, __put_user_bad
         .long   4b, __put_user_bad
         .long   5b, __put_user_bad
         .long   6b, __put_user_bad
-.previous
+.popsection
diff --git a/arch/arm/lib/strncpy_from_user.S b/arch/arm/lib/strncpy_from_user.S
index 1c9814f346c6..f202d7bd1647 100644
--- a/arch/arm/lib/strncpy_from_user.S
+++ b/arch/arm/lib/strncpy_from_user.S
@@ -33,11 +33,11 @@ ENTRY(__strncpy_from_user)
         mov     pc, lr
 ENDPROC(__strncpy_from_user)
 
-        .section .fixup,"ax"
+        .pushsection .fixup,"ax"
         .align  0
 9001:   mov     r3, #0
         strb    r3, [r0, #0]    @ null terminate
         mov     r0, #-EFAULT
         mov     pc, lr
-        .previous
+        .popsection
 
diff --git a/arch/arm/lib/strnlen_user.S b/arch/arm/lib/strnlen_user.S
index 7855b2906659..0ecbb459c4f1 100644
--- a/arch/arm/lib/strnlen_user.S
+++ b/arch/arm/lib/strnlen_user.S
@@ -33,8 +33,8 @@ ENTRY(__strnlen_user)
         mov     pc, lr
 ENDPROC(__strnlen_user)
 
-        .section .fixup,"ax"
+        .pushsection .fixup,"ax"
         .align  0
 9001:   mov     r0, #0
         mov     pc, lr
-        .previous
+        .popsection
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S
index ffdd27498cee..fee9f6f88adb 100644
--- a/arch/arm/lib/uaccess.S
+++ b/arch/arm/lib/uaccess.S
@@ -279,10 +279,10 @@ USER(		strgtbt	r3, [r0], #1)			@ May fault
                 b       .Lc2u_finished
 ENDPROC(__copy_to_user)
 
-                .section .fixup,"ax"
+                .pushsection .fixup,"ax"
                 .align  0
 9001:           ldmfd   sp!, {r0, r4 - r7, pc}
-                .previous
+                .popsection
 
 /* Prototype: unsigned long __copy_from_user(void *to,const void *from,unsigned long n);
  * Purpose  : copy a block from user memory to kernel memory
@@ -545,7 +545,7 @@ USER(		ldrgtbt	r3, [r1], #1)			@ May fault
                 b       .Lcfu_finished
 ENDPROC(__copy_from_user)
 
-                .section .fixup,"ax"
+                .pushsection .fixup,"ax"
                 .align  0
                 /*
                  * We took an exception.  r0 contains a pointer to
@@ -559,5 +559,5 @@ ENDPROC(__copy_from_user)
                 blne    __memzero
                 mov     r0, r4
                 ldmfd   sp!, {r4 - r7, pc}
-                .previous
+                .popsection
 
diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c
index 6b967ffb6552..e2d2f2cd0c4f 100644
--- a/arch/arm/lib/uaccess_with_memcpy.c
+++ b/arch/arm/lib/uaccess_with_memcpy.c
@@ -16,6 +16,7 @@
 #include <linux/mm.h>
 #include <linux/sched.h>
 #include <linux/hardirq.h> /* for in_atomic() */
+#include <linux/gfp.h>
 #include <asm/current.h>
 #include <asm/page.h>
 
diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c
index b5c5fc6ba3a9..3ef68330452a 100644
--- a/arch/arm/mach-aaec2000/core.c
+++ b/arch/arm/mach-aaec2000/core.c
@@ -20,6 +20,7 @@
 #include <linux/timex.h>
 #include <linux/signal.h>
 #include <linux/clk.h>
+#include <linux/gfp.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 1df9ee1ba040..c1f821e58222 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -16,8 +16,8 @@ obj-$(CONFIG_ARCH_AT91SAM9261)	+= at91sam9261.o at91sam926x_time.o at91sam9261_d
 obj-$(CONFIG_ARCH_AT91SAM9G10)  += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9263)  += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9RL)   += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o  sam9_smc.o
- obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9G45)  += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91CAP9)     += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT572D940HF)  += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 987fab3d846a..9c5b48e68a71 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -175,8 +175,6 @@ ENTRY(at91_slow_clock)
         orr     r3, r3, #(1 << 29)              /* bit 29 always set */
         str     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
 
-        wait_pllalock
-
         /* Save PLLB setting and disable it */
         ldr     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
         str     r3, .saved_pllbr
@@ -184,8 +182,6 @@ ENTRY(at91_slow_clock)
         mov     r3, #AT91_PMC_PLLCOUNT
         str     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
 
-        wait_pllblock
-
         /* Turn off the main oscillator */
         ldr     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
         bic     r3, r3, #AT91_PMC_MOSCEN
@@ -205,13 +201,25 @@ ENTRY(at91_slow_clock)
         ldr     r3, .saved_pllbr
         str     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
 
+        tst     r3, #(AT91_PMC_MUL &  0xff0000)
+        bne     1f
+        tst     r3, #(AT91_PMC_MUL & ~0xff0000)
+        beq     2f
+1:
         wait_pllblock
+2:
 
         /* Restore PLLA setting */
         ldr     r3, .saved_pllar
         str     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
 
+        tst     r3, #(AT91_PMC_MUL &  0xff0000)
+        bne     3f
+        tst     r3, #(AT91_PMC_MUL & ~0xff0000)
+        beq     4f
+3:
         wait_pllalock
+4:
 
 #ifdef SLOWDOWN_MASTER_CLOCK
         /*
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
index 7b20fccb9d4e..29c0a911df26 100644
--- a/arch/arm/mach-bcmring/dma.c
+++ b/arch/arm/mach-bcmring/dma.c
@@ -28,6 +28,7 @@
 #include <linux/interrupt.h>
 #include <linux/irqreturn.h>
 #include <linux/proc_fs.h>
+#include <linux/slab.h>
 
 #include <mach/timer.h>
 
@@ -2220,11 +2221,15 @@ EXPORT_SYMBOL(dma_map_create_descriptor_ring);
 int dma_unmap(DMA_MemMap_t *memMap,     /* Stores state information about the map */
               int dirtied       /* non-zero if any of the pages were modified */
     ) {
+
+        int rc = 0;
         int regionIdx;
         int segmentIdx;
         DMA_Region_t *region;
         DMA_Segment_t *segment;
 
+        down(&memMap->lock);
+
         for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
                 region = &memMap->region[regionIdx];
 
@@ -2238,7 +2243,8 @@ int dma_unmap(DMA_MemMap_t *memMap,	/* Stores state information about the map */
                                         printk(KERN_ERR
                                                "%s: vmalloc'd pages are not yet supported\n",
                                                __func__);
-                                        return -EINVAL;
+                                        rc = -EINVAL;
+                                        goto out;
                                 }
 
                         case DMA_MEM_TYPE_KMALLOC:
@@ -2275,7 +2281,8 @@ int dma_unmap(DMA_MemMap_t *memMap,	/* Stores state information about the map */
                                         printk(KERN_ERR
                                                "%s: Unsupported memory type: %d\n",
                                                __func__, region->memType);
-                                        return -EINVAL;
+                                        rc = -EINVAL;
+                                        goto out;
                                 }
                         }
 
@@ -2313,9 +2320,10 @@ int dma_unmap(DMA_MemMap_t *memMap,	/* Stores state information about the map */
         memMap->numRegionsUsed = 0;
         memMap->inUse = 0;
 
+out:
         up(&memMap->lock);
 
-        return 0;
+        return rc;
 }
 
 EXPORT_SYMBOL(dma_unmap);
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
new file mode 100644
index 000000000000..9ebfcc46feb1
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -0,0 +1,12 @@
+menu "CNS3XXX platform type"
+        depends on ARCH_CNS3XXX
+
+config MACH_CNS3420VB
+        bool "Support for CNS3420 Validation Board"
+        help
+          Include support for the Cavium Networks CNS3420 MPCore Platform
+          Baseboard.
+          This is a platform with an on-board ARM11 MPCore and has support
+          for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
+
+endmenu
diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
new file mode 100644
index 000000000000..427507a2d696
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_ARCH_CNS3XXX)              += core.o pm.o
+obj-$(CONFIG_MACH_CNS3420VB)            += cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/Makefile.boot b/arch/arm/mach-cns3xxx/Makefile.boot
new file mode 100644
index 000000000000..777012865220
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00C00000
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
new file mode 100644
index 000000000000..2e30c8288740
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -0,0 +1,148 @@
+/*
+ * Cavium Networks CNS3420 Validation Board
+ *
+ * Copyright 2000 Deep Blue Solutions Ltd
+ * Copyright 2008 ARM Limited
+ * Copyright 2008 Cavium Networks
+ *                Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ *                Anton Vorontsov <avorontsov@mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/compiler.h>
+#include <linux/io.h>
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/partitions.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <mach/hardware.h>
+#include <mach/cns3xxx.h>
+#include <mach/irqs.h>
+#include "core.h"
+
+/*
+ * NOR Flash
+ */
+static struct mtd_partition cns3420_nor_partitions[] = {
+        {
+                .name           = "uboot",
+                .size           = 0x00040000,
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "kernel",
+                .size           = 0x004C0000,
+                .offset         = MTDPART_OFS_APPEND,
+        }, {
+                .name           = "filesystem",
+                .size           = 0x7000000,
+                .offset         = MTDPART_OFS_APPEND,
+        }, {
+                .name           = "filesystem2",
+                .size           = 0x0AE0000,
+                .offset         = MTDPART_OFS_APPEND,
+        }, {
+                .name           = "ubootenv",
+                .size           = MTDPART_SIZ_FULL,
+                .offset         = MTDPART_OFS_APPEND,
+        },
+};
+
+static struct physmap_flash_data cns3420_nor_pdata = {
+        .width = 2,
+        .parts = cns3420_nor_partitions,
+        .nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
+};
+
+static struct resource cns3420_nor_res = {
+        .start = CNS3XXX_FLASH_BASE,
+        .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
+        .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+};
+
+static struct platform_device cns3420_nor_pdev = {
+        .name = "physmap-flash",
+        .id = 0,
+        .resource = &cns3420_nor_res,
+        .num_resources = 1,
+        .dev = {
+                .platform_data = &cns3420_nor_pdata,
+        },
+};
+
+/*
+ * UART
+ */
+static void __init cns3420_early_serial_setup(void)
+{
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+        static struct uart_port cns3420_serial_port = {
+                .membase        = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
+                .mapbase        = CNS3XXX_UART0_BASE,
+                .irq            = IRQ_CNS3XXX_UART0,
+                .iotype         = UPIO_MEM,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
+                .regshift       = 2,
+                .uartclk        = 24000000,
+                .line           = 0,
+                .type           = PORT_16550A,
+                .fifosize       = 16,
+        };
+
+        early_serial_setup(&cns3420_serial_port);
+#endif
+}
+
+/*
+ * Initialization
+ */
+static struct platform_device *cns3420_pdevs[] __initdata = {
+        &cns3420_nor_pdev,
+};
+
+static void __init cns3420_init(void)
+{
+        platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
+
+        pm_power_off = cns3xxx_power_off;
+}
+
+static struct map_desc cns3420_io_desc[] __initdata = {
+        {
+                .virtual        = CNS3XXX_UART0_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_UART0_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+
+static void __init cns3420_map_io(void)
+{
+        cns3xxx_map_io();
+        iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
+
+        cns3420_early_serial_setup();
+}
+
+MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
+        .phys_io        = CNS3XXX_UART0_BASE,
+        .io_pg_offst    = (CNS3XXX_UART0_BASE_VIRT >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .map_io         = cns3420_map_io,
+        .init_irq       = cns3xxx_init_irq,
+        .timer          = &cns3xxx_timer,
+        .init_machine   = cns3420_init,
+MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
new file mode 100644
index 000000000000..9ca4d581016f
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright 1999 - 2003 ARM Limited
+ * Copyright 2000 Deep Blue Solutions Ltd
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/io.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/mach/irq.h>
+#include <asm/hardware/gic.h>
+#include <mach/cns3xxx.h>
+#include "core.h"
+
+static struct map_desc cns3xxx_io_desc[] __initdata = {
+        {
+                .virtual        = CNS3XXX_TC11MP_TWD_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = CNS3XXX_TIMER1_2_3_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = CNS3XXX_GPIOA_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = CNS3XXX_GPIOB_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = CNS3XXX_MISC_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_MISC_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = CNS3XXX_PM_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_PM_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init cns3xxx_map_io(void)
+{
+        iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
+}
+
+/* used by entry-macro.S */
+void __iomem *gic_cpu_base_addr;
+
+void __init cns3xxx_init_irq(void)
+{
+        gic_cpu_base_addr = __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT);
+        gic_dist_init(0, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), 29);
+        gic_cpu_init(0, gic_cpu_base_addr);
+}
+
+void cns3xxx_power_off(void)
+{
+        u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT);
+        u32 clkctrl;
+
+        printk(KERN_INFO "powering system down...\n");
+
+        clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET);
+        clkctrl &= 0xfffff1ff;
+        clkctrl |= (0x5 << 9);          /* Hibernate */
+        writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET);
+
+}
+
+/*
+ * Timer
+ */
+static void __iomem *cns3xxx_tmr1;
+
+static void cns3xxx_timer_set_mode(enum clock_event_mode mode,
+                                   struct clock_event_device *clk)
+{
+        unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+        int pclk = cns3xxx_cpu_clock() / 8;
+        int reload;
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                reload = pclk * 20 / (3 * HZ) * 0x25000;
+                writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
+                ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* period set, and timer enabled in 'next_event' hook */
+                ctrl |= (1 << 2) | (1 << 9);
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        default:
+                ctrl = 0;
+        }
+
+        writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+}
+
+static int cns3xxx_timer_set_next_event(unsigned long evt,
+                                        struct clock_event_device *unused)
+{
+        unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+
+        writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
+        writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+
+        return 0;
+}
+
+static struct clock_event_device cns3xxx_tmr1_clockevent = {
+        .name           = "cns3xxx timer1",
+        .shift          = 8,
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .set_mode       = cns3xxx_timer_set_mode,
+        .set_next_event = cns3xxx_timer_set_next_event,
+        .rating         = 350,
+        .cpumask        = cpu_all_mask,
+};
+
+static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
+{
+        cns3xxx_tmr1_clockevent.irq = timer_irq;
+        cns3xxx_tmr1_clockevent.mult =
+                div_sc((cns3xxx_cpu_clock() >> 3) * 1000000, NSEC_PER_SEC,
+                       cns3xxx_tmr1_clockevent.shift);
+        cns3xxx_tmr1_clockevent.max_delta_ns =
+                clockevent_delta2ns(0xffffffff, &cns3xxx_tmr1_clockevent);
+        cns3xxx_tmr1_clockevent.min_delta_ns =
+                clockevent_delta2ns(0xf, &cns3xxx_tmr1_clockevent);
+
+        clockevents_register_device(&cns3xxx_tmr1_clockevent);
+}
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = &cns3xxx_tmr1_clockevent;
+        u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET;
+        u32 val;
+
+        /* Clear the interrupt */
+        val = readl(stat);
+        writel(val & ~(1 << 2), stat);
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction cns3xxx_timer_irq = {
+        .name           = "timer",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = cns3xxx_timer_interrupt,
+};
+
+/*
+ * Set up the clock source and clock events devices
+ */
+static void __init __cns3xxx_timer_init(unsigned int timer_irq)
+{
+        u32 val;
+        u32 irq_mask;
+
+        /*
+         * Initialise to a known state (all timers off)
+         */
+
+        /* disable timer1 and timer2 */
+        writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+        /* stop free running timer3 */
+        writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
+
+        /* timer1 */
+        writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
+        writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
+
+        writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
+        writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
+
+        /* mask irq, non-mask timer1 overflow */
+        irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
+        irq_mask &= ~(1 << 2);
+        irq_mask |= 0x03;
+        writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
+
+        /* down counter */
+        val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+        val |= (1 << 9);
+        writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+
+        /* timer2 */
+        writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
+        writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
+
+        /* mask irq */
+        irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
+        irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
+        writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
+
+        /* down counter */
+        val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+        val |= (1 << 10);
+        writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
+
+        /* Make irqs happen for the system timer */
+        setup_irq(timer_irq, &cns3xxx_timer_irq);
+
+        cns3xxx_clockevents_init(timer_irq);
+}
+
+static void __init cns3xxx_timer_init(void)
+{
+        cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT);
+
+        __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
+}
+
+struct sys_timer cns3xxx_timer = {
+        .init = cns3xxx_timer_init,
+};
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
new file mode 100644
index 000000000000..6b33ec11346e
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2000 Deep Blue Solutions Ltd
+ * Copyright 2004 ARM Limited
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __CNS3XXX_CORE_H
+#define __CNS3XXX_CORE_H
+
+extern void __iomem *gic_cpu_base_addr;
+extern struct sys_timer cns3xxx_timer;
+
+void __init cns3xxx_map_io(void);
+void __init cns3xxx_init_irq(void);
+void cns3xxx_power_off(void);
+void cns3xxx_pwr_power_up(unsigned int block);
+void cns3xxx_pwr_power_down(unsigned int block);
+
+#endif /* __CNS3XXX_CORE_H */
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
new file mode 100644
index 000000000000..8a2f5a21d4ee
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -0,0 +1,635 @@
+/*
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_BOARD_CNS3XXXH
+#define __MACH_BOARD_CNS3XXXH
+
+/*
+ * Memory map
+ */
+#define CNS3XXX_FLASH_BASE                      0x10000000      /* Flash/SRAM Memory Bank 0 */
+#define CNS3XXX_FLASH_SIZE                      SZ_256M
+
+#define CNS3XXX_DDR2SDRAM_BASE                  0x20000000      /* DDR2 SDRAM Memory */
+
+#define CNS3XXX_SPI_FLASH_BASE                  0x60000000      /* SPI Serial Flash Memory */
+
+#define CNS3XXX_SWITCH_BASE                     0x70000000      /* Switch and HNAT Control */
+#define CNS3XXX_SWITCH_BASE_VIRT                0xFFF00000
+
+#define CNS3XXX_PPE_BASE                        0x70001000      /* HANT */
+#define CNS3XXX_PPE_BASE_VIRT                   0xFFF50000
+
+#define CNS3XXX_EMBEDDED_SRAM_BASE              0x70002000      /* HANT Embedded SRAM */
+#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT         0xFFF60000
+
+#define CNS3XXX_SSP_BASE                        0x71000000      /* Synchronous Serial Port - SPI/PCM/I2C */
+#define CNS3XXX_SSP_BASE_VIRT                   0xFFF01000
+
+#define CNS3XXX_DMC_BASE                        0x72000000      /* DMC Control (DDR2 SDRAM) */
+#define CNS3XXX_DMC_BASE_VIRT                   0xFFF02000
+
+#define CNS3XXX_SMC_BASE                        0x73000000      /* SMC Control */
+#define CNS3XXX_SMC_BASE_VIRT                   0xFFF03000
+
+#define SMC_MEMC_STATUS_OFFSET                  0x000
+#define SMC_MEMIF_CFG_OFFSET                    0x004
+#define SMC_MEMC_CFG_SET_OFFSET                 0x008
+#define SMC_MEMC_CFG_CLR_OFFSET                 0x00C
+#define SMC_DIRECT_CMD_OFFSET                   0x010
+#define SMC_SET_CYCLES_OFFSET                   0x014
+#define SMC_SET_OPMODE_OFFSET                   0x018
+#define SMC_REFRESH_PERIOD_0_OFFSET             0x020
+#define SMC_REFRESH_PERIOD_1_OFFSET             0x024
+#define SMC_SRAM_CYCLES0_0_OFFSET               0x100
+#define SMC_NAND_CYCLES0_0_OFFSET               0x100
+#define SMC_OPMODE0_0_OFFSET                    0x104
+#define SMC_SRAM_CYCLES0_1_OFFSET               0x120
+#define SMC_NAND_CYCLES0_1_OFFSET               0x120
+#define SMC_OPMODE0_1_OFFSET                    0x124
+#define SMC_USER_STATUS_OFFSET                  0x200
+#define SMC_USER_CONFIG_OFFSET                  0x204
+#define SMC_ECC_STATUS_OFFSET                   0x300
+#define SMC_ECC_MEMCFG_OFFSET                   0x304
+#define SMC_ECC_MEMCOMMAND1_OFFSET              0x308
+#define SMC_ECC_MEMCOMMAND2_OFFSET              0x30C
+#define SMC_ECC_ADDR0_OFFSET                    0x310
+#define SMC_ECC_ADDR1_OFFSET                    0x314
+#define SMC_ECC_VALUE0_OFFSET                   0x318
+#define SMC_ECC_VALUE1_OFFSET                   0x31C
+#define SMC_ECC_VALUE2_OFFSET                   0x320
+#define SMC_ECC_VALUE3_OFFSET                   0x324
+#define SMC_PERIPH_ID_0_OFFSET                  0xFE0
+#define SMC_PERIPH_ID_1_OFFSET                  0xFE4
+#define SMC_PERIPH_ID_2_OFFSET                  0xFE8
+#define SMC_PERIPH_ID_3_OFFSET                  0xFEC
+#define SMC_PCELL_ID_0_OFFSET                   0xFF0
+#define SMC_PCELL_ID_1_OFFSET                   0xFF4
+#define SMC_PCELL_ID_2_OFFSET                   0xFF8
+#define SMC_PCELL_ID_3_OFFSET                   0xFFC
+
+#define CNS3XXX_GPIOA_BASE                      0x74000000      /* GPIO port A */
+#define CNS3XXX_GPIOA_BASE_VIRT                 0xFFF04000
+
+#define CNS3XXX_GPIOB_BASE                      0x74800000      /* GPIO port B */
+#define CNS3XXX_GPIOB_BASE_VIRT                 0xFFF05000
+
+#define CNS3XXX_RTC_BASE                        0x75000000      /* Real Time Clock */
+#define CNS3XXX_RTC_BASE_VIRT                   0xFFF06000
+
+#define RTC_SEC_OFFSET                          0x00
+#define RTC_MIN_OFFSET                          0x04
+#define RTC_HOUR_OFFSET                         0x08
+#define RTC_DAY_OFFSET                          0x0C
+#define RTC_SEC_ALM_OFFSET                      0x10
+#define RTC_MIN_ALM_OFFSET                      0x14
+#define RTC_HOUR_ALM_OFFSET                     0x18
+#define RTC_REC_OFFSET                          0x1C
+#define RTC_CTRL_OFFSET                         0x20
+#define RTC_INTR_STS_OFFSET                     0x34
+
+#define CNS3XXX_MISC_BASE                       0x76000000      /* Misc Control */
+#define CNS3XXX_MISC_BASE_VIRT                  0xFFF07000      /* Misc Control */
+
+#define CNS3XXX_PM_BASE                         0x77000000      /* Power Management Control */
+#define CNS3XXX_PM_BASE_VIRT                    0xFFF08000
+
+#define PM_CLK_GATE_OFFSET                      0x00
+#define PM_SOFT_RST_OFFSET                      0x04
+#define PM_HS_CFG_OFFSET                        0x08
+#define PM_CACTIVE_STA_OFFSET                   0x0C
+#define PM_PWR_STA_OFFSET                       0x10
+#define PM_SYS_CLK_CTRL_OFFSET                  0x14
+#define PM_PLL_LCD_I2S_CTRL_OFFSET              0x18
+#define PM_PLL_HM_PD_OFFSET                     0x1C
+
+#define CNS3XXX_UART0_BASE                      0x78000000      /* UART 0 */
+#define CNS3XXX_UART0_BASE_VIRT                 0xFFF09000
+
+#define CNS3XXX_UART1_BASE                      0x78400000      /* UART 1 */
+#define CNS3XXX_UART1_BASE_VIRT                 0xFFF0A000
+
+#define CNS3XXX_UART2_BASE                      0x78800000      /* UART 2 */
+#define CNS3XXX_UART2_BASE_VIRT                 0xFFF0B000
+
+#define CNS3XXX_DMAC_BASE                       0x79000000      /* Generic DMA Control */
+#define CNS3XXX_DMAC_BASE_VIRT                  0xFFF0D000
+
+#define CNS3XXX_CORESIGHT_BASE                  0x7A000000      /* CoreSight */
+#define CNS3XXX_CORESIGHT_BASE_VIRT             0xFFF0E000
+
+#define CNS3XXX_CRYPTO_BASE                     0x7B000000      /* Crypto */
+#define CNS3XXX_CRYPTO_BASE_VIRT                0xFFF0F000
+
+#define CNS3XXX_I2S_BASE                        0x7C000000      /* I2S */
+#define CNS3XXX_I2S_BASE_VIRT                   0xFFF10000
+
+#define CNS3XXX_TIMER1_2_3_BASE                 0x7C800000      /* Timer */
+#define CNS3XXX_TIMER1_2_3_BASE_VIRT            0xFFF10800
+
+#define TIMER1_COUNTER_OFFSET                   0x00
+#define TIMER1_AUTO_RELOAD_OFFSET               0x04
+#define TIMER1_MATCH_V1_OFFSET                  0x08
+#define TIMER1_MATCH_V2_OFFSET                  0x0C
+
+#define TIMER2_COUNTER_OFFSET                   0x10
+#define TIMER2_AUTO_RELOAD_OFFSET               0x14
+#define TIMER2_MATCH_V1_OFFSET                  0x18
+#define TIMER2_MATCH_V2_OFFSET                  0x1C
+
+#define TIMER1_2_CONTROL_OFFSET                 0x30
+#define TIMER1_2_INTERRUPT_STATUS_OFFSET        0x34
+#define TIMER1_2_INTERRUPT_MASK_OFFSET          0x38
+
+#define TIMER_FREERUN_OFFSET                    0x40
+#define TIMER_FREERUN_CONTROL_OFFSET            0x44
+
+#define CNS3XXX_HCIE_BASE                       0x7D000000      /* HCIE Control */
+#define CNS3XXX_HCIE_BASE_VIRT                  0xFFF30000
+
+#define CNS3XXX_RAID_BASE                       0x7E000000      /* RAID Control */
+#define CNS3XXX_RAID_BASE_VIRT                  0xFFF12000
+
+#define CNS3XXX_AXI_IXC_BASE                    0x7F000000      /* AXI IXC */
+#define CNS3XXX_AXI_IXC_BASE_VIRT               0xFFF13000
+
+#define CNS3XXX_CLCD_BASE                       0x80000000      /* LCD Control */
+#define CNS3XXX_CLCD_BASE_VIRT                  0xFFF14000
+
+#define CNS3XXX_USBOTG_BASE                     0x81000000      /* USB OTG Control */
+#define CNS3XXX_USBOTG_BASE_VIRT                0xFFF15000
+
+#define CNS3XXX_USB_BASE                        0x82000000      /* USB Host Control */
+#define CNS3XXX_USB_BASE_VIRT                   0xFFF16000
+
+#define CNS3XXX_SATA2_BASE                      0x83000000      /* SATA */
+#define CNS3XXX_SATA2_SIZE                      SZ_16M
+#define CNS3XXX_SATA2_BASE_VIRT                 0xFFF17000
+
+#define CNS3XXX_CAMERA_BASE                     0x84000000      /* Camera Interface */
+#define CNS3XXX_CAMERA_BASE_VIRT                0xFFF18000
+
+#define CNS3XXX_SDIO_BASE                       0x85000000      /* SDIO */
+#define CNS3XXX_SDIO_BASE_VIRT                  0xFFF19000
+
+#define CNS3XXX_I2S_TDM_BASE                    0x86000000      /* I2S TDM */
+#define CNS3XXX_I2S_TDM_BASE_VIRT               0xFFF1A000
+
+#define CNS3XXX_2DG_BASE                        0x87000000      /* 2D Graphic Control */
+#define CNS3XXX_2DG_BASE_VIRT                   0xFFF1B000
+
+#define CNS3XXX_USB_OHCI_BASE                   0x88000000      /* USB OHCI */
+#define CNS3XXX_USB_OHCI_BASE_VIRT              0xFFF1C000
+
+#define CNS3XXX_L2C_BASE                        0x92000000      /* L2 Cache Control */
+#define CNS3XXX_L2C_BASE_VIRT                   0xFFF27000
+
+#define CNS3XXX_PCIE0_MEM_BASE                  0xA0000000      /* PCIe Port 0 IO/Memory Space */
+#define CNS3XXX_PCIE0_MEM_BASE_VIRT             0xE0000000
+
+#define CNS3XXX_PCIE0_HOST_BASE                 0xAB000000      /* PCIe Port 0 RC Base */
+#define CNS3XXX_PCIE0_HOST_BASE_VIRT            0xE1000000
+
+#define CNS3XXX_PCIE0_IO_BASE                   0xAC000000      /* PCIe Port 0 */
+#define CNS3XXX_PCIE0_IO_BASE_VIRT              0xE2000000
+
+#define CNS3XXX_PCIE0_CFG0_BASE                 0xAD000000      /* PCIe Port 0 CFG Type 0 */
+#define CNS3XXX_PCIE0_CFG0_BASE_VIRT            0xE3000000
+
+#define CNS3XXX_PCIE0_CFG1_BASE                 0xAE000000      /* PCIe Port 0 CFG Type 1 */
+#define CNS3XXX_PCIE0_CFG1_BASE_VIRT            0xE4000000
+
+#define CNS3XXX_PCIE0_MSG_BASE                  0xAF000000      /* PCIe Port 0 Message Space */
+#define CNS3XXX_PCIE0_MSG_BASE_VIRT             0xE5000000
+
+#define CNS3XXX_PCIE1_MEM_BASE                  0xB0000000      /* PCIe Port 1 IO/Memory Space */
+#define CNS3XXX_PCIE1_MEM_BASE_VIRT             0xE8000000
+
+#define CNS3XXX_PCIE1_HOST_BASE                 0xBB000000      /* PCIe Port 1 RC Base */
+#define CNS3XXX_PCIE1_HOST_BASE_VIRT            0xE9000000
+
+#define CNS3XXX_PCIE1_IO_BASE                   0xBC000000      /* PCIe Port 1 */
+#define CNS3XXX_PCIE1_IO_BASE_VIRT              0xEA000000
+
+#define CNS3XXX_PCIE1_CFG0_BASE                 0xBD000000      /* PCIe Port 1 CFG Type 0 */
+#define CNS3XXX_PCIE1_CFG0_BASE_VIRT            0xEB000000
+
+#define CNS3XXX_PCIE1_CFG1_BASE                 0xBE000000      /* PCIe Port 1 CFG Type 1 */
+#define CNS3XXX_PCIE1_CFG1_BASE_VIRT            0xEC000000
+
+#define CNS3XXX_PCIE1_MSG_BASE                  0xBF000000      /* PCIe Port 1 Message Space */
+#define CNS3XXX_PCIE1_MSG_BASE_VIRT             0xED000000
+
+/*
+ * Testchip peripheral and fpga gic regions
+ */
+#define CNS3XXX_TC11MP_SCU_BASE                 0x90000000      /* IRQ, Test chip */
+#define CNS3XXX_TC11MP_SCU_BASE_VIRT            0xFF000000
+
+#define CNS3XXX_TC11MP_GIC_CPU_BASE             0x90000100      /* Test chip interrupt controller CPU interface */
+#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT        0xFF000100
+
+#define CNS3XXX_TC11MP_TWD_BASE                 0x90000600
+#define CNS3XXX_TC11MP_TWD_BASE_VIRT            0xFF000600
+
+#define CNS3XXX_TC11MP_GIC_DIST_BASE            0x90001000      /* Test chip interrupt controller distributor */
+#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT       0xFF001000
+
+#define CNS3XXX_TC11MP_L220_BASE                0x92002000      /* L220 registers */
+#define CNS3XXX_TC11MP_L220_BASE_VIRT           0xFF002000
+
+/*
+ * Misc block
+ */
+#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
+#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset))))
+
+#define MISC_MEMORY_REMAP_REG                   MISC_MEM_MAP_VALUE(0x00)
+#define MISC_CHIP_CONFIG_REG                    MISC_MEM_MAP_VALUE(0x04)
+#define MISC_DEBUG_PROBE_DATA_REG               MISC_MEM_MAP_VALUE(0x08)
+#define MISC_DEBUG_PROBE_SELECTION_REG          MISC_MEM_MAP_VALUE(0x0C)
+#define MISC_IO_PIN_FUNC_SELECTION_REG          MISC_MEM_MAP_VALUE(0x10)
+#define MISC_GPIOA_PIN_ENABLE_REG               MISC_MEM_MAP_VALUE(0x14)
+#define MISC_GPIOB_PIN_ENABLE_REG               MISC_MEM_MAP_VALUE(0x18)
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A       MISC_MEM_MAP_VALUE(0x1C)
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B       MISC_MEM_MAP_VALUE(0x20)
+#define MISC_GPIOA_15_0_PULL_CTRL_REG           MISC_MEM_MAP_VALUE(0x24)
+#define MISC_GPIOA_16_31_PULL_CTRL_REG          MISC_MEM_MAP_VALUE(0x28)
+#define MISC_GPIOB_15_0_PULL_CTRL_REG           MISC_MEM_MAP_VALUE(0x2C)
+#define MISC_GPIOB_16_31_PULL_CTRL_REG          MISC_MEM_MAP_VALUE(0x30)
+#define MISC_IO_PULL_CTRL_REG                   MISC_MEM_MAP_VALUE(0x34)
+#define MISC_E_FUSE_31_0_REG                    MISC_MEM_MAP_VALUE(0x40)
+#define MISC_E_FUSE_63_32_REG                   MISC_MEM_MAP_VALUE(0x44)
+#define MISC_E_FUSE_95_64_REG                   MISC_MEM_MAP_VALUE(0x48)
+#define MISC_E_FUSE_127_96_REG                  MISC_MEM_MAP_VALUE(0x4C)
+#define MISC_SOFTWARE_TEST_1_REG                MISC_MEM_MAP_VALUE(0x50)
+#define MISC_SOFTWARE_TEST_2_REG                MISC_MEM_MAP_VALUE(0x54)
+
+#define MISC_SATA_POWER_MODE                    MISC_MEM_MAP_VALUE(0x310)
+
+#define MISC_USB_CFG_REG                        MISC_MEM_MAP_VALUE(0x800)
+#define MISC_USB_STS_REG                        MISC_MEM_MAP_VALUE(0x804)
+#define MISC_USBPHY00_CFG_REG                   MISC_MEM_MAP_VALUE(0x808)
+#define MISC_USBPHY01_CFG_REG                   MISC_MEM_MAP_VALUE(0x80c)
+#define MISC_USBPHY10_CFG_REG                   MISC_MEM_MAP_VALUE(0x810)
+#define MISC_USBPHY11_CFG_REG                   MISC_MEM_MAP_VALUE(0x814)
+
+#define MISC_PCIEPHY_CMCTL(x)                   MISC_MEM_MAP(0x900 + (x) * 0x004)
+#define MISC_PCIEPHY_CTL(x)                     MISC_MEM_MAP(0x940 + (x) * 0x100)
+#define MISC_PCIE_AXIS_AWMISC(x)                MISC_MEM_MAP(0x944 + (x) * 0x100)
+#define MISC_PCIE_AXIS_ARMISC(x)                MISC_MEM_MAP(0x948 + (x) * 0x100)
+#define MISC_PCIE_AXIS_RMISC(x)                 MISC_MEM_MAP(0x94C + (x) * 0x100)
+#define MISC_PCIE_AXIS_BMISC(x)                 MISC_MEM_MAP(0x950 + (x) * 0x100)
+#define MISC_PCIE_AXIM_RMISC(x)                 MISC_MEM_MAP(0x954 + (x) * 0x100)
+#define MISC_PCIE_AXIM_BMISC(x)                 MISC_MEM_MAP(0x958 + (x) * 0x100)
+#define MISC_PCIE_CTRL(x)                       MISC_MEM_MAP(0x95C + (x) * 0x100)
+#define MISC_PCIE_PM_DEBUG(x)                   MISC_MEM_MAP(0x960 + (x) * 0x100)
+#define MISC_PCIE_RFC_DEBUG(x)                  MISC_MEM_MAP(0x964 + (x) * 0x100)
+#define MISC_PCIE_CXPL_DEBUGL(x)                MISC_MEM_MAP(0x968 + (x) * 0x100)
+#define MISC_PCIE_CXPL_DEBUGH(x)                MISC_MEM_MAP(0x96C + (x) * 0x100)
+#define MISC_PCIE_DIAG_DEBUGH(x)                MISC_MEM_MAP(0x970 + (x) * 0x100)
+#define MISC_PCIE_W1CLR(x)                      MISC_MEM_MAP(0x974 + (x) * 0x100)
+#define MISC_PCIE_INT_MASK(x)                   MISC_MEM_MAP(0x978 + (x) * 0x100)
+#define MISC_PCIE_INT_STATUS(x)                 MISC_MEM_MAP(0x97C + (x) * 0x100)
+
+/*
+ * Power management and clock control
+ */
+#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset))))
+
+#define PM_CLK_GATE_REG                                 PMU_REG_VALUE(0x000)
+#define PM_SOFT_RST_REG                                 PMU_REG_VALUE(0x004)
+#define PM_HS_CFG_REG                                   PMU_REG_VALUE(0x008)
+#define PM_CACTIVE_STA_REG                              PMU_REG_VALUE(0x00C)
+#define PM_PWR_STA_REG                                  PMU_REG_VALUE(0x010)
+#define PM_CLK_CTRL_REG                                 PMU_REG_VALUE(0x014)
+#define PM_PLL_LCD_I2S_CTRL_REG                         PMU_REG_VALUE(0x018)
+#define PM_PLL_HM_PD_CTRL_REG                           PMU_REG_VALUE(0x01C)
+#define PM_REGULAT_CTRL_REG                             PMU_REG_VALUE(0x020)
+#define PM_WDT_CTRL_REG                                 PMU_REG_VALUE(0x024)
+#define PM_WU_CTRL0_REG                                 PMU_REG_VALUE(0x028)
+#define PM_WU_CTRL1_REG                                 PMU_REG_VALUE(0x02C)
+#define PM_CSR_REG                                      PMU_REG_VALUE(0x030)
+
+/* PM_CLK_GATE_REG */
+#define PM_CLK_GATE_REG_OFFSET_SDIO                     (25)
+#define PM_CLK_GATE_REG_OFFSET_GPU                      (24)
+#define PM_CLK_GATE_REG_OFFSET_CIM                      (23)
+#define PM_CLK_GATE_REG_OFFSET_LCDC                     (22)
+#define PM_CLK_GATE_REG_OFFSET_I2S                      (21)
+#define PM_CLK_GATE_REG_OFFSET_RAID                     (20)
+#define PM_CLK_GATE_REG_OFFSET_SATA                     (19)
+#define PM_CLK_GATE_REG_OFFSET_PCIE(x)                  (17 + (x))
+#define PM_CLK_GATE_REG_OFFSET_USB_HOST                 (16)
+#define PM_CLK_GATE_REG_OFFSET_USB_OTG                  (15)
+#define PM_CLK_GATE_REG_OFFSET_TIMER                    (14)
+#define PM_CLK_GATE_REG_OFFSET_CRYPTO                   (13)
+#define PM_CLK_GATE_REG_OFFSET_HCIE                     (12)
+#define PM_CLK_GATE_REG_OFFSET_SWITCH                   (11)
+#define PM_CLK_GATE_REG_OFFSET_GPIO                     (10)
+#define PM_CLK_GATE_REG_OFFSET_UART3                    (9)
+#define PM_CLK_GATE_REG_OFFSET_UART2                    (8)
+#define PM_CLK_GATE_REG_OFFSET_UART1                    (7)
+#define PM_CLK_GATE_REG_OFFSET_RTC                      (5)
+#define PM_CLK_GATE_REG_OFFSET_GDMA                     (4)
+#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C              (3)
+#define PM_CLK_GATE_REG_OFFSET_SMC_NFI                  (1)
+#define PM_CLK_GATE_REG_MASK                            (0x03FFFFBA)
+
+/* PM_SOFT_RST_REG */
+#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG             (31)
+#define PM_SOFT_RST_REG_OFFST_CPU1                      (29)
+#define PM_SOFT_RST_REG_OFFST_CPU0                      (28)
+#define PM_SOFT_RST_REG_OFFST_SDIO                      (25)
+#define PM_SOFT_RST_REG_OFFST_GPU                       (24)
+#define PM_SOFT_RST_REG_OFFST_CIM                       (23)
+#define PM_SOFT_RST_REG_OFFST_LCDC                      (22)
+#define PM_SOFT_RST_REG_OFFST_I2S                       (21)
+#define PM_SOFT_RST_REG_OFFST_RAID                      (20)
+#define PM_SOFT_RST_REG_OFFST_SATA                      (19)
+#define PM_SOFT_RST_REG_OFFST_PCIE(x)                   (17 + (x))
+#define PM_SOFT_RST_REG_OFFST_USB_HOST                  (16)
+#define PM_SOFT_RST_REG_OFFST_USB_OTG                   (15)
+#define PM_SOFT_RST_REG_OFFST_TIMER                     (14)
+#define PM_SOFT_RST_REG_OFFST_CRYPTO                    (13)
+#define PM_SOFT_RST_REG_OFFST_HCIE                      (12)
+#define PM_SOFT_RST_REG_OFFST_SWITCH                    (11)
+#define PM_SOFT_RST_REG_OFFST_GPIO                      (10)
+#define PM_SOFT_RST_REG_OFFST_UART3                     (9)
+#define PM_SOFT_RST_REG_OFFST_UART2                     (8)
+#define PM_SOFT_RST_REG_OFFST_UART1                     (7)
+#define PM_SOFT_RST_REG_OFFST_RTC                       (5)
+#define PM_SOFT_RST_REG_OFFST_GDMA                      (4)
+#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C               (3)
+#define PM_SOFT_RST_REG_OFFST_DMC                       (2)
+#define PM_SOFT_RST_REG_OFFST_SMC_NFI                   (1)
+#define PM_SOFT_RST_REG_OFFST_GLOBAL                    (0)
+#define PM_SOFT_RST_REG_MASK                            (0xF3FFFFBF)
+
+/* PMHS_CFG_REG */
+#define PM_HS_CFG_REG_OFFSET_SDIO                       (25)
+#define PM_HS_CFG_REG_OFFSET_GPU                        (24)
+#define PM_HS_CFG_REG_OFFSET_CIM                        (23)
+#define PM_HS_CFG_REG_OFFSET_LCDC                       (22)
+#define PM_HS_CFG_REG_OFFSET_I2S                        (21)
+#define PM_HS_CFG_REG_OFFSET_RAID                       (20)
+#define PM_HS_CFG_REG_OFFSET_SATA                       (19)
+#define PM_HS_CFG_REG_OFFSET_PCIE1                      (18)
+#define PM_HS_CFG_REG_OFFSET_PCIE0                      (17)
+#define PM_HS_CFG_REG_OFFSET_USB_HOST                   (16)
+#define PM_HS_CFG_REG_OFFSET_USB_OTG                    (15)
+#define PM_HS_CFG_REG_OFFSET_TIMER                      (14)
+#define PM_HS_CFG_REG_OFFSET_CRYPTO                     (13)
+#define PM_HS_CFG_REG_OFFSET_HCIE                       (12)
+#define PM_HS_CFG_REG_OFFSET_SWITCH                     (11)
+#define PM_HS_CFG_REG_OFFSET_GPIO                       (10)
+#define PM_HS_CFG_REG_OFFSET_UART3                      (9)
+#define PM_HS_CFG_REG_OFFSET_UART2                      (8)
+#define PM_HS_CFG_REG_OFFSET_UART1                      (7)
+#define PM_HS_CFG_REG_OFFSET_RTC                        (5)
+#define PM_HS_CFG_REG_OFFSET_GDMA                       (4)
+#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S                (3)
+#define PM_HS_CFG_REG_OFFSET_DMC                        (2)
+#define PM_HS_CFG_REG_OFFSET_SMC_NFI                    (1)
+#define PM_HS_CFG_REG_MASK                              (0x03FFFFBE)
+#define PM_HS_CFG_REG_MASK_SUPPORT                      (0x01100806)
+
+/* PM_CACTIVE_STA_REG */
+#define PM_CACTIVE_STA_REG_OFFSET_SDIO                  (25)
+#define PM_CACTIVE_STA_REG_OFFSET_GPU                   (24)
+#define PM_CACTIVE_STA_REG_OFFSET_CIM                   (23)
+#define PM_CACTIVE_STA_REG_OFFSET_LCDC                  (22)
+#define PM_CACTIVE_STA_REG_OFFSET_I2S                   (21)
+#define PM_CACTIVE_STA_REG_OFFSET_RAID                  (20)
+#define PM_CACTIVE_STA_REG_OFFSET_SATA                  (19)
+#define PM_CACTIVE_STA_REG_OFFSET_PCIE1                 (18)
+#define PM_CACTIVE_STA_REG_OFFSET_PCIE0                 (17)
+#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST              (16)
+#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG               (15)
+#define PM_CACTIVE_STA_REG_OFFSET_TIMER                 (14)
+#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO                (13)
+#define PM_CACTIVE_STA_REG_OFFSET_HCIE                  (12)
+#define PM_CACTIVE_STA_REG_OFFSET_SWITCH                (11)
+#define PM_CACTIVE_STA_REG_OFFSET_GPIO                  (10)
+#define PM_CACTIVE_STA_REG_OFFSET_UART3                 (9)
+#define PM_CACTIVE_STA_REG_OFFSET_UART2                 (8)
+#define PM_CACTIVE_STA_REG_OFFSET_UART1                 (7)
+#define PM_CACTIVE_STA_REG_OFFSET_RTC                   (5)
+#define PM_CACTIVE_STA_REG_OFFSET_GDMA                  (4)
+#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S           (3)
+#define PM_CACTIVE_STA_REG_OFFSET_DMC                   (2)
+#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI               (1)
+#define PM_CACTIVE_STA_REG_MASK                         (0x03FFFFBE)
+
+/* PM_PWR_STA_REG */
+#define PM_PWR_STA_REG_REG_OFFSET_SDIO                  (25)
+#define PM_PWR_STA_REG_REG_OFFSET_GPU                   (24)
+#define PM_PWR_STA_REG_REG_OFFSET_CIM                   (23)
+#define PM_PWR_STA_REG_REG_OFFSET_LCDC                  (22)
+#define PM_PWR_STA_REG_REG_OFFSET_I2S                   (21)
+#define PM_PWR_STA_REG_REG_OFFSET_RAID                  (20)
+#define PM_PWR_STA_REG_REG_OFFSET_SATA                  (19)
+#define PM_PWR_STA_REG_REG_OFFSET_PCIE1                 (18)
+#define PM_PWR_STA_REG_REG_OFFSET_PCIE0                 (17)
+#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST              (16)
+#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG               (15)
+#define PM_PWR_STA_REG_REG_OFFSET_TIMER                 (14)
+#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO                (13)
+#define PM_PWR_STA_REG_REG_OFFSET_HCIE                  (12)
+#define PM_PWR_STA_REG_REG_OFFSET_SWITCH                (11)
+#define PM_PWR_STA_REG_REG_OFFSET_GPIO                  (10)
+#define PM_PWR_STA_REG_REG_OFFSET_UART3                 (9)
+#define PM_PWR_STA_REG_REG_OFFSET_UART2                 (8)
+#define PM_PWR_STA_REG_REG_OFFSET_UART1                 (7)
+#define PM_PWR_STA_REG_REG_OFFSET_RTC                   (5)
+#define PM_PWR_STA_REG_REG_OFFSET_GDMA                  (4)
+#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S           (3)
+#define PM_PWR_STA_REG_REG_OFFSET_DMC                   (2)
+#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI               (1)
+#define PM_PWR_STA_REG_REG_MASK                         (0x03FFFFBE)
+
+/* PM_CLK_CTRL_REG */
+#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK                 (31)
+#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN              (30)
+#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN             (29)
+#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN             (28)
+#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE           (27)
+#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV               (24)
+#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL               (22)
+#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV               (20)
+#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL               (16)
+#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV                  (14)
+#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL           (12)
+#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE             (9)
+#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL             (7)
+#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE            (6)
+#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV              (4)
+#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL              (0)
+
+#define PM_CPU_CLK_DIV(DIV) { \
+        PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
+        PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
+}
+
+#define PM_PLL_CPU_SEL(CPU) { \
+        PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
+        PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
+}
+
+/* PM_PLL_LCD_I2S_CTRL_REG */
+#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV     (22)
+#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL            (17)
+#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P        (11)
+#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M        (3)
+#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S        (0)
+
+/* PM_PLL_HM_PD_CTRL_REG */
+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1          (11)
+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0          (10)
+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD          (6)
+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S            (5)
+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD            (4)
+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB            (3)
+#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII          (2)
+#define PM_PLL_HM_PD_CTRL_REG_MASK                      (0x00000C7C)
+
+/* PM_WDT_CTRL_REG */
+#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY           (0)
+
+/* PM_CSR_REG - Clock Scaling Register*/
+#define PM_CSR_REG_OFFSET_CSR_EN                        (30)
+#define PM_CSR_REG_OFFSET_CSR_NUM                       (0)
+
+#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK)
+
+/* Software reset*/
+#define CNS3XXX_PWR_SOFTWARE_RST(BLOCK) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK)
+
+/*
+ * CNS3XXX support several power saving mode as following,
+ * DFS, IDLE, HALT, DOZE, SLEEP, Hibernate
+ */
+#define CNS3XXX_PWR_CPU_MODE_DFS                        (0)
+#define CNS3XXX_PWR_CPU_MODE_IDLE                       (1)
+#define CNS3XXX_PWR_CPU_MODE_HALT                       (2)
+#define CNS3XXX_PWR_CPU_MODE_DOZE                       (3)
+#define CNS3XXX_PWR_CPU_MODE_SLEEP                      (4)
+#define CNS3XXX_PWR_CPU_MODE_HIBERNATE                  (5)
+
+#define CNS3XXX_PWR_PLL(BLOCK)  (0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK)
+#define CNS3XXX_PWR_PLL_ALL     PM_PLL_HM_PD_CTRL_REG_MASK
+
+/* Change CPU frequency and divider */
+#define CNS3XXX_PWR_PLL_CPU_300MHZ                      (0)
+#define CNS3XXX_PWR_PLL_CPU_333MHZ                      (1)
+#define CNS3XXX_PWR_PLL_CPU_366MHZ                      (2)
+#define CNS3XXX_PWR_PLL_CPU_400MHZ                      (3)
+#define CNS3XXX_PWR_PLL_CPU_433MHZ                      (4)
+#define CNS3XXX_PWR_PLL_CPU_466MHZ                      (5)
+#define CNS3XXX_PWR_PLL_CPU_500MHZ                      (6)
+#define CNS3XXX_PWR_PLL_CPU_533MHZ                      (7)
+#define CNS3XXX_PWR_PLL_CPU_566MHZ                      (8)
+#define CNS3XXX_PWR_PLL_CPU_600MHZ                      (9)
+#define CNS3XXX_PWR_PLL_CPU_633MHZ                      (10)
+#define CNS3XXX_PWR_PLL_CPU_666MHZ                      (11)
+#define CNS3XXX_PWR_PLL_CPU_700MHZ                      (12)
+
+#define CNS3XXX_PWR_CPU_CLK_DIV_BY1                     (0)
+#define CNS3XXX_PWR_CPU_CLK_DIV_BY2                     (1)
+#define CNS3XXX_PWR_CPU_CLK_DIV_BY4                     (2)
+
+/* Change DDR2 frequency */
+#define CNS3XXX_PWR_PLL_DDR2_200MHZ                     (0)
+#define CNS3XXX_PWR_PLL_DDR2_266MHZ                     (1)
+#define CNS3XXX_PWR_PLL_DDR2_333MHZ                     (2)
+#define CNS3XXX_PWR_PLL_DDR2_400MHZ                     (3)
+
+void cns3xxx_pwr_soft_rst(unsigned int block);
+void cns3xxx_pwr_clk_en(unsigned int block);
+int cns3xxx_cpu_clock(void);
+
+/*
+ * ARM11 MPCore interrupt sources (primary GIC)
+ */
+#define IRQ_CNS3XXX_PMU                 (IRQ_TC11MP_GIC_START + 0)
+#define IRQ_CNS3XXX_SDIO                (IRQ_TC11MP_GIC_START + 1)
+#define IRQ_CNS3XXX_L2CC                (IRQ_TC11MP_GIC_START + 2)
+#define IRQ_CNS3XXX_RTC                 (IRQ_TC11MP_GIC_START + 3)
+#define IRQ_CNS3XXX_I2S                 (IRQ_TC11MP_GIC_START + 4)
+#define IRQ_CNS3XXX_PCM                 (IRQ_TC11MP_GIC_START + 5)
+#define IRQ_CNS3XXX_SPI                 (IRQ_TC11MP_GIC_START + 6)
+#define IRQ_CNS3XXX_I2C                 (IRQ_TC11MP_GIC_START + 7)
+#define IRQ_CNS3XXX_CIM                 (IRQ_TC11MP_GIC_START + 8)
+#define IRQ_CNS3XXX_GPU                 (IRQ_TC11MP_GIC_START + 9)
+#define IRQ_CNS3XXX_LCD                 (IRQ_TC11MP_GIC_START + 10)
+#define IRQ_CNS3XXX_GPIOA               (IRQ_TC11MP_GIC_START + 11)
+#define IRQ_CNS3XXX_GPIOB               (IRQ_TC11MP_GIC_START + 12)
+#define IRQ_CNS3XXX_UART0               (IRQ_TC11MP_GIC_START + 13)
+#define IRQ_CNS3XXX_UART1               (IRQ_TC11MP_GIC_START + 14)
+#define IRQ_CNS3XXX_UART2               (IRQ_TC11MP_GIC_START + 15)
+#define IRQ_CNS3XXX_ARM11               (IRQ_TC11MP_GIC_START + 16)
+
+#define IRQ_CNS3XXX_SW_STATUS           (IRQ_TC11MP_GIC_START + 17)
+#define IRQ_CNS3XXX_SW_R0TXC            (IRQ_TC11MP_GIC_START + 18)
+#define IRQ_CNS3XXX_SW_R0RXC            (IRQ_TC11MP_GIC_START + 19)
+#define IRQ_CNS3XXX_SW_R0QE             (IRQ_TC11MP_GIC_START + 20)
+#define IRQ_CNS3XXX_SW_R0QF             (IRQ_TC11MP_GIC_START + 21)
+#define IRQ_CNS3XXX_SW_R1TXC            (IRQ_TC11MP_GIC_START + 22)
+#define IRQ_CNS3XXX_SW_R1RXC            (IRQ_TC11MP_GIC_START + 23)
+#define IRQ_CNS3XXX_SW_R1QE             (IRQ_TC11MP_GIC_START + 24)
+#define IRQ_CNS3XXX_SW_R1QF             (IRQ_TC11MP_GIC_START + 25)
+#define IRQ_CNS3XXX_SW_PPE              (IRQ_TC11MP_GIC_START + 26)
+
+#define IRQ_CNS3XXX_CRYPTO              (IRQ_TC11MP_GIC_START + 27)
+#define IRQ_CNS3XXX_HCIE                (IRQ_TC11MP_GIC_START + 28)
+#define IRQ_CNS3XXX_PCIE0_DEVICE        (IRQ_TC11MP_GIC_START + 29)
+#define IRQ_CNS3XXX_PCIE1_DEVICE        (IRQ_TC11MP_GIC_START + 30)
+#define IRQ_CNS3XXX_USB_OTG             (IRQ_TC11MP_GIC_START + 31)
+#define IRQ_CNS3XXX_USB_EHCI            (IRQ_TC11MP_GIC_START + 32)
+#define IRQ_CNS3XXX_SATA                (IRQ_TC11MP_GIC_START + 33)
+#define IRQ_CNS3XXX_RAID                (IRQ_TC11MP_GIC_START + 34)
+#define IRQ_CNS3XXX_SMC                 (IRQ_TC11MP_GIC_START + 35)
+
+#define IRQ_CNS3XXX_DMAC_ABORT          (IRQ_TC11MP_GIC_START + 36)
+#define IRQ_CNS3XXX_DMAC0               (IRQ_TC11MP_GIC_START + 37)
+#define IRQ_CNS3XXX_DMAC1               (IRQ_TC11MP_GIC_START + 38)
+#define IRQ_CNS3XXX_DMAC2               (IRQ_TC11MP_GIC_START + 39)
+#define IRQ_CNS3XXX_DMAC3               (IRQ_TC11MP_GIC_START + 40)
+#define IRQ_CNS3XXX_DMAC4               (IRQ_TC11MP_GIC_START + 41)
+#define IRQ_CNS3XXX_DMAC5               (IRQ_TC11MP_GIC_START + 42)
+#define IRQ_CNS3XXX_DMAC6               (IRQ_TC11MP_GIC_START + 43)
+#define IRQ_CNS3XXX_DMAC7               (IRQ_TC11MP_GIC_START + 44)
+#define IRQ_CNS3XXX_DMAC8               (IRQ_TC11MP_GIC_START + 45)
+#define IRQ_CNS3XXX_DMAC9               (IRQ_TC11MP_GIC_START + 46)
+#define IRQ_CNS3XXX_DMAC10              (IRQ_TC11MP_GIC_START + 47)
+#define IRQ_CNS3XXX_DMAC11              (IRQ_TC11MP_GIC_START + 48)
+#define IRQ_CNS3XXX_DMAC12              (IRQ_TC11MP_GIC_START + 49)
+#define IRQ_CNS3XXX_DMAC13              (IRQ_TC11MP_GIC_START + 50)
+#define IRQ_CNS3XXX_DMAC14              (IRQ_TC11MP_GIC_START + 51)
+#define IRQ_CNS3XXX_DMAC15              (IRQ_TC11MP_GIC_START + 52)
+#define IRQ_CNS3XXX_DMAC16              (IRQ_TC11MP_GIC_START + 53)
+#define IRQ_CNS3XXX_DMAC17              (IRQ_TC11MP_GIC_START + 54)
+
+#define IRQ_CNS3XXX_PCIE0_RC            (IRQ_TC11MP_GIC_START + 55)
+#define IRQ_CNS3XXX_PCIE1_RC            (IRQ_TC11MP_GIC_START + 56)
+#define IRQ_CNS3XXX_TIMER0              (IRQ_TC11MP_GIC_START + 57)
+#define IRQ_CNS3XXX_TIMER1              (IRQ_TC11MP_GIC_START + 58)
+#define IRQ_CNS3XXX_USB_OHCI            (IRQ_TC11MP_GIC_START + 59)
+#define IRQ_CNS3XXX_TIMER2              (IRQ_TC11MP_GIC_START + 60)
+#define IRQ_CNS3XXX_EXTERNAL_PIN0       (IRQ_TC11MP_GIC_START + 61)
+#define IRQ_CNS3XXX_EXTERNAL_PIN1       (IRQ_TC11MP_GIC_START + 62)
+#define IRQ_CNS3XXX_EXTERNAL_PIN2       (IRQ_TC11MP_GIC_START + 63)
+
+#define NR_IRQS_CNS3XXX                 (IRQ_TC11MP_GIC_START + 64)
+
+#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
+#undef NR_IRQS
+#define NR_IRQS                         NR_IRQS_CNS3XXX
+#endif
+
+#endif  /* __MACH_BOARD_CNS3XXX_H */
diff --git a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..d16ce7eb00e9
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
@@ -0,0 +1,21 @@
+/*
+ * Debugging macro include header
+ *
+ * Copyright 1994-1999 Russell King
+ * Copyright 2008 Cavium Networks
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx,      #0x10000000
+                movne   \rx,      #0xf0000000   @ virtual base
+                orr     \rx, \rx, #0x00009000
+                .endm
+
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..5e1c5545680f
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
@@ -0,0 +1,82 @@
+/*
+ * Low-level IRQ helper macros for Cavium Networks platforms
+ *
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/hardware.h>
+#include <asm/hardware/gic.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                ldr     \base, =gic_cpu_base_addr
+                ldr     \base, [\base]
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                /*
+                 * The interrupt numbering scheme is defined in the
+                 * interrupt controller spec.  To wit:
+                 *
+                 * Interrupts 0-15 are IPI
+                 * 16-28 are reserved
+                 * 29-31 are local.  We allow 30 to be used for the watchdog.
+                 * 32-1020 are global
+                 * 1021-1022 are reserved
+                 * 1023 is "spurious" (no interrupt)
+                 *
+                 * For now, we ignore all local interrupts so only return an interrupt if it's
+                 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
+                 *
+                 * A simple read from the controller will tell us the number of the highest
+                 * priority enabled interrupt.  We then just need to check whether it is in the
+                 * valid range for an IRQ (30-1020 inclusive).
+                 */
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
+
+                ldr     \tmp, =1021
+
+                bic     \irqnr, \irqstat, #0x1c00
+
+                cmp     \irqnr, #29
+                cmpcc   \irqnr, \irqnr
+                cmpne   \irqnr, \tmp
+                cmpcs   \irqnr, \irqnr
+
+                .endm
+
+                /* We assume that irqstat (the raw value of the IRQ acknowledge
+                 * register) is preserved from the macro above.
+                 * If there is an IPI, we immediately signal end of interrupt on the
+                 * controller, since this requires the original irqstat value which
+                 * we won't easily be able to recreate later.
+                 */
+
+                .macro test_for_ipi, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #16
+                strcc   \irqstat, [\base, #GIC_CPU_EOI]
+                cmpcs   \irqnr, \irqnr
+                .endm
+
+                /* As above, this assumes that irqstat and base are preserved.. */
+
+                .macro test_for_ltirq, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                mov     \tmp, #0
+                cmp     \irqnr, #29
+                moveq   \tmp, #1
+                streq   \irqstat, [\base, #GIC_CPU_EOI]
+                cmp     \tmp, #0
+                .endm
diff --git a/arch/arm/mach-cns3xxx/include/mach/hardware.h b/arch/arm/mach-cns3xxx/include/mach/hardware.h
new file mode 100644
index 000000000000..57e09836f9d7
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/hardware.h
@@ -0,0 +1,22 @@
+/*
+ * This file contains the hardware definitions of the Cavium Networks boards.
+ *
+ * Copyright 2003 ARM Limited.
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_HARDWARE_H
+#define __MACH_HARDWARE_H
+
+#include <asm/sizes.h>
+
+/* macro to get at IO space when running virtually */
+#define PCIBIOS_MIN_IO          0x00000000
+#define PCIBIOS_MIN_MEM         0x00000000
+#define pcibios_assign_all_busses()     1
+
+#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/io.h b/arch/arm/mach-cns3xxx/include/mach/io.h
new file mode 100644
index 000000000000..33b6fc1ece7c
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/io.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2008 Cavium Networks
+ * Copyright 2003 ARM Limited
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+#ifndef __MACH_IO_H
+#define __MACH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)                 __typesafe_io(a)
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/irqs.h b/arch/arm/mach-cns3xxx/include/mach/irqs.h
new file mode 100644
index 000000000000..2ab96f8085c8
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/irqs.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2000 Deep Blue Solutions Ltd.
+ * Copyright 2003 ARM Limited
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define IRQ_LOCALTIMER          29
+#define IRQ_LOCALWDOG           30
+#define IRQ_TC11MP_GIC_START    32
+
+#include <mach/cns3xxx.h>
+
+#ifndef NR_IRQS
+#error "NR_IRQS not defined by the board-specific files"
+#endif
+
+#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/memory.h b/arch/arm/mach-cns3xxx/include/mach/memory.h
new file mode 100644
index 000000000000..3b6b769b7a27
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/memory.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2003 ARM Limited
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_MEMORY_H
+#define __MACH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET             UL(0x00000000)
+
+#define __phys_to_bus(x)        ((x) + PHYS_OFFSET)
+#define __bus_to_phys(x)        ((x) - PHYS_OFFSET)
+
+#define __virt_to_bus(v)        __phys_to_bus(__virt_to_phys(v))
+#define __bus_to_virt(b)        __phys_to_virt(__bus_to_phys(b))
+#define __pfn_to_bus(p)         __phys_to_bus(__pfn_to_phys(p))
+#define __bus_to_pfn(b)         __phys_to_pfn(__bus_to_phys(b))
+
+#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/system.h b/arch/arm/mach-cns3xxx/include/mach/system.h
new file mode 100644
index 000000000000..58bb03ae3cf4
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/system.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2000 Deep Blue Solutions Ltd
+ * Copyright 2003 ARM Limited
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_SYSTEM_H
+#define __MACH_SYSTEM_H
+
+#include <linux/io.h>
+#include <asm/proc-fns.h>
+#include <mach/hardware.h>
+
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+
+void arch_reset(char mode, const char *cmd);
+
+#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/timex.h b/arch/arm/mach-cns3xxx/include/mach/timex.h
new file mode 100644
index 000000000000..1fd04217cacb
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/timex.h
@@ -0,0 +1,12 @@
+/*
+ * Cavium Networks architecture timex specifications
+ *
+ * Copyright 2003 ARM Limited
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
new file mode 100644
index 000000000000..de8ead9b91f7
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2003 ARM Limited
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include <mach/cns3xxx.h>
+
+#define AMBA_UART_DR(base)      (*(volatile unsigned char *)((base) + 0x00))
+#define AMBA_UART_LCRH(base)    (*(volatile unsigned char *)((base) + 0x2c))
+#define AMBA_UART_CR(base)      (*(volatile unsigned char *)((base) + 0x30))
+#define AMBA_UART_FR(base)      (*(volatile unsigned char *)((base) + 0x18))
+
+/*
+ * Return the UART base address
+ */
+static inline unsigned long get_uart_base(void)
+{
+        if (machine_is_cns3420vb())
+                return CNS3XXX_UART0_BASE;
+        else
+                return 0;
+}
+
+/*
+ * This does not append a newline
+ */
+static inline void putc(int c)
+{
+        unsigned long base = get_uart_base();
+
+        while (AMBA_UART_FR(base) & (1 << 5))
+                barrier();
+
+        AMBA_UART_DR(base) = c;
+}
+
+static inline void flush(void)
+{
+        unsigned long base = get_uart_base();
+
+        while (AMBA_UART_FR(base) & (1 << 3))
+                barrier();
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-cns3xxx/include/mach/vmalloc.h b/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..4d381ec05278
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2000 Russell King.
+ * Copyright 2003 ARM Limited
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#define VMALLOC_END             0xd8000000
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
new file mode 100644
index 000000000000..725e1a4fc231
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <mach/system.h>
+#include <mach/cns3xxx.h>
+
+void cns3xxx_pwr_clk_en(unsigned int block)
+{
+        PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
+}
+
+void cns3xxx_pwr_power_up(unsigned int block)
+{
+        PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
+
+        /* Wait for 300us for the PLL output clock locked. */
+        udelay(300);
+};
+
+void cns3xxx_pwr_power_down(unsigned int block)
+{
+        /* write '1' to power down */
+        PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
+};
+
+static void cns3xxx_pwr_soft_rst_force(unsigned int block)
+{
+        /*
+         * bit 0, 28, 29 => program low to reset,
+         * the other else program low and then high
+         */
+        if (block & 0x30000001) {
+                PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
+        } else {
+                PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
+                PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
+        }
+}
+
+void cns3xxx_pwr_soft_rst(unsigned int block)
+{
+        static unsigned int soft_reset;
+
+        if (soft_reset & block) {
+                /* SPI/I2C/GPIO use the same block, reset once. */
+                return;
+        } else {
+                soft_reset |= block;
+        }
+        cns3xxx_pwr_soft_rst_force(block);
+}
+
+void arch_reset(char mode, const char *cmd)
+{
+        /*
+         * To reset, we hit the on-board reset register
+         * in the system FPGA.
+         */
+        cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
+}
+
+/*
+ * cns3xxx_cpu_clock - return CPU/L2 clock
+ *  aclk: cpu clock/2
+ *  hclk: cpu clock/4
+ *  pclk: cpu clock/8
+ */
+int cns3xxx_cpu_clock(void)
+{
+        int cpu;
+        int cpu_sel;
+        int div_sel;
+
+        cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
+        div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
+
+        cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
+
+        return cpu;
+}
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index d15beceb632e..df4ab2105869 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -22,6 +22,7 @@
 #include <linux/leds.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/slab.h>
 #include <linux/mtd/nand.h>
 #include <linux/input.h>
 #include <linux/spi/spi.h>
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 27772e18e45b..0d6ee583f65c 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -758,7 +758,6 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
         [IRQ_MMCINT]                    = 7,
         [IRQ_DM365_MMCINT1]             = 7,
         [IRQ_DM365_PWMINT3]             = 7,
-        [IRQ_DDRINT]                    = 4,
         [IRQ_AEMIFINT]                  = 2,
         [IRQ_DM365_SDIOINT1]            = 2,
         [IRQ_TINT0_TINT12]              = 7,
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 15dd886df04c..53137387aee1 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -23,6 +23,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 
 #include <mach/edma.h>
 
@@ -1266,7 +1267,8 @@ int edma_start(unsigned channel)
                 /* EDMA channel with event association */
                 pr_debug("EDMA: ER%d %08x\n", j,
                         edma_shadow0_read_array(ctlr, SH_ER, j));
-                /* Clear any pending error */
+                /* Clear any pending event or error */
+                edma_write_array(ctlr, EDMA_ECR, j, mask);
                 edma_write_array(ctlr, EDMA_EMCR, j, mask);
                 /* Clear any SER */
                 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index cc9be7fee627..03acfd39042b 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -3,7 +3,7 @@
  *
  * Author: Mark A. Greer <mgreer@mvista.com>
  *
- * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
+ * 2007, 2009-2010 (c) MontaVista Software, Inc. This file is licensed under
  * the terms of the GNU General Public License version 2. This program
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
@@ -13,7 +13,9 @@
 
 #include <video/da8xx-fb.h>
 
+#include <linux/platform_device.h>
 #include <linux/davinci_emac.h>
+
 #include <mach/serial.h>
 #include <mach/edma.h>
 #include <mach/i2c.h>
@@ -144,6 +146,10 @@ extern const short da850_mmcsd0_pins[];
 extern const short da850_nand_pins[];
 extern const short da850_nor_pins[];
 
+#ifdef CONFIG_DAVINCI_MUX
 int da8xx_pinmux_setup(const short pins[]);
+#else
+static inline int da8xx_pinmux_setup(const short pins[]) { return 0; }
+#endif
 
 #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 42d985beece5..9e0b106b4f5f 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -253,8 +253,6 @@ static void __init timer_init(void)
                         irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq;
                         setup_irq(irq, &t->irqaction);
                 }
-
-                timer32_config(&timers[i]);
         }
 }
 
@@ -331,6 +329,7 @@ static void __init davinci_timer_init(void)
         unsigned int clocksource_id;
         static char err[] __initdata = KERN_ERR
                 "%s: can't register clocksource!\n";
+        int i;
 
         clockevent_id = soc_info->timer_info->clockevent_id;
         clocksource_id = soc_info->timer_info->clocksource_id;
@@ -389,6 +388,9 @@ static void __init davinci_timer_init(void)
 
         clockevent_davinci.cpumask = cpumask_of(0);
         clockevents_register_device(&clockevent_davinci);
+
+        for (i=0; i< ARRAY_SIZE(timers); i++)
+                timer32_config(&timers[i]);
 }
 
 struct sys_timer davinci_timer = {
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index cc377ae8c428..cf547ad7ebd4 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -25,7 +25,7 @@
 #include <mach/hardware.h>
 
 /*************************************************************************
- * GPIO handling for EP93xx
+ * Interrupt handling for EP93xx on-chip GPIOs
  *************************************************************************/
 static unsigned char gpio_int_unmasked[3];
 static unsigned char gpio_int_enabled[3];
@@ -40,7 +40,7 @@ static const u8 eoi_register_offset[3]		= { 0x98, 0xb4, 0x54 };
 static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x58 };
 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
 
-void ep93xx_gpio_update_int_params(unsigned port)
+static void ep93xx_gpio_update_int_params(unsigned port)
 {
         BUG_ON(port > 2);
 
@@ -56,7 +56,7 @@ void ep93xx_gpio_update_int_params(unsigned port)
                 EP93XX_GPIO_REG(int_en_register_offset[port]));
 }
 
-void ep93xx_gpio_int_mask(unsigned line)
+static inline void ep93xx_gpio_int_mask(unsigned line)
 {
         gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
 }
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index 7a2614828217..bdb3f6706801 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -14,7 +14,6 @@
  */
 
 #include <linux/sched.h>
-#include <linux/slab.h>
 #include <linux/mman.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
diff --git a/arch/arm/mach-integrator/cpu.c b/arch/arm/mach-integrator/cpu.c
index 1cb222daa06d..a3fbcb3adc29 100644
--- a/arch/arm/mach-integrator/cpu.c
+++ b/arch/arm/mach-integrator/cpu.c
@@ -13,7 +13,6 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/cpufreq.h>
-#include <linux/slab.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/init.h>
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index 1a0ee93e4519..fd684bf205e5 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -21,6 +21,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 
 #include <asm/clkdev.h>
 #include <mach/clkdev.h>
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 54edb6b8504f..cde57b2b83b5 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -13,7 +13,6 @@
 #include <linux/list.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
-#include <linux/slab.h>
 #include <linux/string.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
@@ -21,6 +20,7 @@
 #include <linux/amba/clcd.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
+#include <linux/gfp.h>
 
 #include <asm/clkdev.h>
 #include <mach/clkdev.h>
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index e5491629c6da..9cef0590d5aa 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -22,7 +22,6 @@
  */
 #include <linux/kernel.h>
 #include <linux/pci.h>
-#include <linux/slab.h>
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
 #include <linux/spinlock.h>
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 4873f26a42e1..6d5a90813d31 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -18,6 +18,7 @@
  */
 
 #include <linux/pci.h>
+#include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/jiffies.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index 93370a46b620..10384fc37cb2 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -19,7 +19,6 @@
 #include <linux/pci.h>
 #include <linux/pm.h>
 #include <linux/string.h>
-#include <linux/slab.h>
 #include <linux/serial_core.h>
 #include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index a7a08dda7f33..d6ac85ff109d 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -21,7 +21,6 @@
 #include <linux/pci.h>
 #include <linux/pm.h>
 #include <linux/string.h>
-#include <linux/slab.h>
 #include <linux/serial_core.h>
 #include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index 0200f80c1e17..c6a0e4ee9d91 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -18,7 +18,6 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/string.h>
-#include <linux/slab.h>
 #include <linux/serial_core.h>
 #include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index 266b1f58a784..f108a31afc2b 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -23,7 +23,6 @@
 #include <linux/pci.h>
 #include <linux/pm.h>
 #include <linux/string.h>
-#include <linux/slab.h>
 #include <linux/serial_core.h>
 #include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 394e95a30b75..c6ff5523b380 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -17,7 +17,6 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/string.h>
-#include <linux/slab.h>
 #include <linux/serial_core.h>
 #include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index a40badf126c2..fbf551409394 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -17,7 +17,6 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/string.h>
-#include <linux/slab.h>
 #include <linux/serial_core.h>
 #include <linux/serial_8250.h>
 #include <linux/mtd/physmap.h>
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index c84dfac13882..1a557e0d055b 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -26,7 +26,6 @@
 #include <linux/bitops.h>
 #include <linux/pci.h>
 #include <linux/ioport.h>
-#include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/serial.h>
 #include <linux/tty.h>
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
index 4467c4224d73..55e5c69352ad 100644
--- a/arch/arm/mach-ixp2000/ixdp2400.c
+++ b/arch/arm/mach-ixp2000/ixdp2400.c
@@ -23,7 +23,6 @@
 #include <linux/bitops.h>
 #include <linux/pci.h>
 #include <linux/ioport.h>
-#include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
index 94f68ba9ea50..237b61a85e9a 100644
--- a/arch/arm/mach-ixp2000/ixdp2800.c
+++ b/arch/arm/mach-ixp2000/ixdp2800.c
@@ -23,7 +23,6 @@
 #include <linux/bitops.h>
 #include <linux/pci.h>
 #include <linux/ioport.h>
-#include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index 30451300751b..91fffb9b2084 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -23,7 +23,6 @@
 #include <linux/bitops.h>
 #include <linux/pci.h>
 #include <linux/ioport.h>
-#include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 4a12327a09a3..0369ec4242a6 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -23,7 +23,6 @@
 #include <linux/bitops.h>
 #include <linux/pci.h>
 #include <linux/ioport.h>
-#include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/serial.h>
 #include <linux/tty.h>
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index 60e9fd08ab80..90771cad06f8 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -22,7 +22,6 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
-#include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 
diff --git a/arch/arm/mach-ixp23xx/include/mach/memory.h b/arch/arm/mach-ixp23xx/include/mach/memory.h
index 94a3a86cfeb8..6ef65d813f16 100644
--- a/arch/arm/mach-ixp23xx/include/mach/memory.h
+++ b/arch/arm/mach-ixp23xx/include/mach/memory.h
@@ -19,7 +19,7 @@
  */
 #define PHYS_OFFSET             (0x00000000)
 
-#define IXP23XX_PCI_SDRAM_OFFSET (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0))
+#define IXP23XX_PCI_SDRAM_OFFSET (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0)
 
 #define __phys_to_bus(x)        ((x) + (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET))
 #define __bus_to_phys(x)        ((x) - (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET))
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index 59022becb134..4b0e598a91c9 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -23,7 +23,6 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
-#include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index 6e558a76457d..d8bc86d76f1d 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -17,7 +17,6 @@
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/serial_8250.h>
-#include <linux/slab.h>
 #include <linux/i2c-gpio.h>
 #include <asm/types.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index 25bf5ad770ea..31a47f6a8939 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -14,7 +14,6 @@
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/serial_8250.h>
-#include <linux/slab.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c
index 59b73a0ddfa9..2583b2a13174 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -17,7 +17,6 @@
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/serial_8250.h>
-#include <linux/slab.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index 0bc7185cb6f7..c67586b79400 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -27,7 +27,6 @@
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/serial_8250.h>
-#include <linux/slab.h>
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index bbb768988845..827cbc4402f4 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -14,7 +14,6 @@
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/serial_8250.h>
-#include <linux/slab.h>
 #include <linux/i2c-gpio.h>
 #include <linux/io.h>
 #include <linux/mtd/mtd.h>
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
index e8bb25778166..a17ed79207a4 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
@@ -20,7 +20,6 @@
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/slab.h>
 #include <mach/npe.h>
 
 #define DEBUG_MSG                       0
diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c
index 7ea782021d1f..4dd74863daa9 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
@@ -18,7 +18,6 @@
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/serial_8250.h>
-#include <linux/slab.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 17879a876be6..29b2163b1fe3 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -38,6 +38,12 @@ config MACH_ESATA_SHEEVAPLUG
           Say 'Y' here if you want your kernel to support the
           Marvell eSATA SheevaPlug Reference Board.
 
+config MACH_GURUPLUG
+        bool "Marvell GuruPlug Reference Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell GuruPlug Reference Board.
+
 config MACH_TS219
         bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS"
         help
@@ -81,6 +87,18 @@ config MACH_INETSPACE_V2
           Say 'Y' here if you want your kernel to support the
           LaCie Internet Space v2 NAS.
 
+config MACH_NET2BIG_V2
+        bool "LaCie 2Big Network v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie 2Big Network v2 NAS.
+
+config MACH_NET5BIG_V2
+        bool "LaCie 5Big Network v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie 5Big Network v2 NAS.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index a5530e36ba3e..c0cd5d362002 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -6,10 +6,13 @@ obj-$(CONFIG_MACH_RD88F6281)		+= rd88f6281-setup.o
 obj-$(CONFIG_MACH_MV88F6281GTW_GE)      += mv88f6281gtw_ge-setup.o
 obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
 obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG)     += sheevaplug-setup.o
+obj-$(CONFIG_MACH_GURUPLUG)             += guruplug-setup.o
 obj-$(CONFIG_MACH_TS219)                += ts219-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_OPENRD)               += openrd-setup.o
 obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o
 obj-$(CONFIG_MACH_INETSPACE_V2)         += netspace_v2-setup.o
+obj-$(CONFIG_MACH_NET2BIG_V2)           += netxbig_v2-setup.o
+obj-$(CONFIG_MACH_NET5BIG_V2)           += netxbig_v2-setup.o
 
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
new file mode 100644
index 000000000000..54d07c89d4ff
--- /dev/null
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -0,0 +1,131 @@
+/*
+ * arch/arm/mach-kirkwood/guruplug-setup.c
+ *
+ * Marvell GuruPlug Reference Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mtd_partition guruplug_nand_parts[] = {
+        {
+                .name = "u-boot",
+                .offset = 0,
+                .size = SZ_1M
+        }, {
+                .name = "uImage",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = SZ_4M
+        }, {
+                .name = "root",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = MTDPART_SIZ_FULL
+        },
+};
+
+static struct mv643xx_eth_platform_data guruplug_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static struct mv643xx_eth_platform_data guruplug_ge01_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(1),
+};
+
+static struct mv_sata_platform_data guruplug_sata_data = {
+        .n_ports        = 1,
+};
+
+static struct mvsdio_platform_data guruplug_mvsdio_data = {
+        /* unfortunately the CD signal has not been connected */
+};
+
+static struct gpio_led guruplug_led_pins[] = {
+        {
+                .name                   = "guruplug:red:health",
+                .gpio                   = 46,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "guruplug:green:health",
+                .gpio                   = 47,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "guruplug:red:wmode",
+                .gpio                   = 48,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "guruplug:green:wmode",
+                .gpio                   = 49,
+                .active_low             = 1,
+        },
+};
+
+static struct gpio_led_platform_data guruplug_led_data = {
+        .leds           = guruplug_led_pins,
+        .num_leds       = ARRAY_SIZE(guruplug_led_pins),
+};
+
+static struct platform_device guruplug_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &guruplug_led_data,
+        }
+};
+
+static unsigned int guruplug_mpp_config[] __initdata = {
+        MPP46_GPIO,     /* M_RLED */
+        MPP47_GPIO,     /* M_GLED */
+        MPP48_GPIO,     /* B_RLED */
+        MPP49_GPIO,     /* B_GLED */
+        0
+};
+
+static void __init guruplug_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(guruplug_mpp_config);
+
+        kirkwood_uart0_init();
+        kirkwood_nand_init(ARRAY_AND_SIZE(guruplug_nand_parts), 25);
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&guruplug_ge00_data);
+        kirkwood_ge01_init(&guruplug_ge01_data);
+        kirkwood_sata_init(&guruplug_sata_data);
+        kirkwood_sdio_init(&guruplug_mvsdio_data);
+
+        platform_device_register(&guruplug_leds);
+}
+
+MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board")
+        /* Maintainer: Siddarth Gore <gores@marvell.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = guruplug_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 0358f45766cb..5e6f711b1c67 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -74,9 +74,9 @@ static struct gpio_keys_button mv88f6281gtw_ge_button_pins[] = {
                 .desc           = "SWR Button",
                 .active_low     = 1,
         }, {
-                .code           = KEY_F1,
+                .code           = KEY_WPS_BUTTON,
                 .gpio           = 46,
-                .desc           = "WPS Button(F1)",
+                .desc           = "WPS Button",
                 .active_low     = 1,
         },
 };
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
new file mode 100644
index 000000000000..8a2bb0228e4f
--- /dev/null
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -0,0 +1,415 @@
+/*
+ * arch/arm/mach-kirkwood/netxbig_v2-setup.c
+ *
+ * LaCie 2Big and 5Big Network v2 board setup
+ *
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/input.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/kirkwood.h>
+#include <plat/time.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
+ ****************************************************************************/
+
+static struct mtd_partition netxbig_v2_flash_parts[] = {
+        {
+                .name = "u-boot",
+                .size = MTDPART_SIZ_FULL,
+                .offset = 0,
+                .mask_flags = MTD_WRITEABLE, /* force read-only */
+        },
+};
+
+static const struct flash_platform_data netxbig_v2_flash = {
+        .type           = "mx25l4005a",
+        .name           = "spi_flash",
+        .parts          = netxbig_v2_flash_parts,
+        .nr_parts       = ARRAY_SIZE(netxbig_v2_flash_parts),
+};
+
+static struct spi_board_info __initdata netxbig_v2_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &netxbig_v2_flash,
+                .irq            = -1,
+                .max_speed_hz   = 20000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data netxbig_v2_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+static struct mv643xx_eth_platform_data netxbig_v2_ge01_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+/*****************************************************************************
+ * I2C devices
+ ****************************************************************************/
+
+static struct at24_platform_data at24c04 = {
+        .byte_len       = SZ_4K / 8,
+        .page_size      = 16,
+};
+
+/*
+ * i2c addr | chip         | description
+ * 0x50     | HT24LC04     | eeprom (512B)
+ */
+
+static struct i2c_board_info __initdata netxbig_v2_i2c_info[] = {
+        {
+                I2C_BOARD_INFO("24c04", 0x50),
+                .platform_data  = &at24c04,
+        }
+};
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+
+static struct mv_sata_platform_data netxbig_v2_sata_data = {
+        .n_ports        = 2,
+};
+
+static int __initdata netxbig_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 };
+
+static void __init netxbig_v2_sata_power_init(void)
+{
+        int i;
+        int err;
+        int hdd_nb;
+
+        if (machine_is_net2big_v2())
+                hdd_nb = 2;
+        else
+                hdd_nb = 5;
+
+        /* Power up all hard disks. */
+        for (i = 0; i < hdd_nb; i++) {
+                err = gpio_request(netxbig_v2_gpio_hdd_power[i], NULL);
+                if (err == 0) {
+                        err = gpio_direction_output(
+                                        netxbig_v2_gpio_hdd_power[i], 1);
+                        /* Free the HDD power GPIOs. This allow user-space to
+                         * configure them via the gpiolib sysfs interface. */
+                        gpio_free(netxbig_v2_gpio_hdd_power[i]);
+                }
+                if (err)
+                        pr_err("netxbig_v2: failed to power up HDD%d\n", i + 1);
+        }
+}
+
+/*****************************************************************************
+ * GPIO keys
+ ****************************************************************************/
+
+#define NETXBIG_V2_GPIO_SWITCH_POWER_ON         13
+#define NETXBIG_V2_GPIO_SWITCH_POWER_OFF        15
+#define NETXBIG_V2_GPIO_FUNC_BUTTON             34
+
+#define NETXBIG_V2_SWITCH_POWER_ON              0x1
+#define NETXBIG_V2_SWITCH_POWER_OFF             0x2
+
+static struct gpio_keys_button netxbig_v2_buttons[] = {
+        [0] = {
+                .type           = EV_SW,
+                .code           = NETXBIG_V2_SWITCH_POWER_ON,
+                .gpio           = NETXBIG_V2_GPIO_SWITCH_POWER_ON,
+                .desc           = "Back power switch (on|auto)",
+                .active_low     = 1,
+        },
+        [1] = {
+                .type           = EV_SW,
+                .code           = NETXBIG_V2_SWITCH_POWER_OFF,
+                .gpio           = NETXBIG_V2_GPIO_SWITCH_POWER_OFF,
+                .desc           = "Back power switch (auto|off)",
+                .active_low     = 1,
+        },
+        [2] = {
+                .code           = KEY_OPTION,
+                .gpio           = NETXBIG_V2_GPIO_FUNC_BUTTON,
+                .desc           = "Function button",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data netxbig_v2_button_data = {
+        .buttons        = netxbig_v2_buttons,
+        .nbuttons       = ARRAY_SIZE(netxbig_v2_buttons),
+};
+
+static struct platform_device netxbig_v2_gpio_buttons = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &netxbig_v2_button_data,
+        },
+};
+
+/*****************************************************************************
+ * GPIO LEDs
+ ****************************************************************************/
+
+/*
+ * The LEDs are controlled by a CPLD and can be configured through a GPIO
+ * extension bus:
+ *
+ * - address register : bit [0-2] -> GPIO [47-49]
+ * - data register    : bit [0-2] -> GPIO [44-46]
+ * - enable register  : GPIO 29
+ *
+ * Address register selection:
+ *
+ * addr | register
+ * ----------------------------
+ *   0  | front LED
+ *   1  | front LED brightness
+ *   2  | HDD LED brightness
+ *   3  | HDD1 LED
+ *   4  | HDD2 LED
+ *   5  | HDD3 LED
+ *   6  | HDD4 LED
+ *   7  | HDD5 LED
+ *
+ * Data register configuration:
+ *
+ * data | LED brightness
+ * -------------------------------------------------
+ *   0  | min (off)
+ *   -  | -
+ *   7  | max
+ *
+ * data | front LED mode
+ * -------------------------------------------------
+ *   0  | fix off
+ *   1  | fix blue on
+ *   2  | fix red on
+ *   3  | blink blue on=1 sec and blue off=1 sec
+ *   4  | blink red on=1 sec and red off=1 sec
+ *   5  | blink blue on=2.5 sec and red on=0.5 sec
+ *   6  | blink blue on=1 sec and red on=1 sec
+ *   7  | blink blue on=0.5 sec and blue off=2.5 sec
+ *
+ * data | HDD LED mode
+ * -------------------------------------------------
+ *   0  | fix blue on
+ *   1  | SATA activity blink
+ *   2  | fix red on
+ *   3  | blink blue on=1 sec and blue off=1 sec
+ *   4  | blink red on=1 sec and red off=1 sec
+ *   5  | blink blue on=2.5 sec and red on=0.5 sec
+ *   6  | blink blue on=1 sec and red on=1 sec
+ *   7  | blink blue on=0.5 sec and blue off=2.5 sec
+ */
+
+/*****************************************************************************
+ * Timer
+ ****************************************************************************/
+
+static void netxbig_v2_timer_init(void)
+{
+        kirkwood_tclk = 166666667;
+        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
+}
+
+struct sys_timer netxbig_v2_timer = {
+        .init = netxbig_v2_timer_init,
+};
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+
+static unsigned int net2big_v2_mpp_config[] __initdata = {
+        MPP0_SPI_SCn,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP6_SYSRST_OUTn,
+        MPP7_GPO,               /* Request power-off */
+        MPP8_TW_SDA,
+        MPP9_TW_SCK,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP13_GPIO,             /* Rear power switch (on|auto) */
+        MPP14_GPIO,             /* USB fuse alarm */
+        MPP15_GPIO,             /* Rear power switch (auto|off) */
+        MPP16_GPIO,             /* SATA HDD1 power */
+        MPP17_GPIO,             /* SATA HDD2 power */
+        MPP20_SATA1_ACTn,
+        MPP21_SATA0_ACTn,
+        MPP24_GPIO,             /* USB mode select */
+        MPP26_GPIO,             /* USB device vbus */
+        MPP28_GPIO,             /* USB enable host vbus */
+        MPP29_GPIO,             /* CPLD extension ALE */
+        MPP34_GPIO,             /* Rear Push button */
+        MPP35_GPIO,             /* Inhibit switch power-off */
+        MPP36_GPIO,             /* SATA HDD1 presence */
+        MPP37_GPIO,             /* SATA HDD2 presence */
+        MPP40_GPIO,             /* eSATA presence */
+        MPP44_GPIO,             /* CPLD extension (data 0) */
+        MPP45_GPIO,             /* CPLD extension (data 1) */
+        MPP46_GPIO,             /* CPLD extension (data 2) */
+        MPP47_GPIO,             /* CPLD extension (addr 0) */
+        MPP48_GPIO,             /* CPLD extension (addr 1) */
+        MPP49_GPIO,             /* CPLD extension (addr 2) */
+        0
+};
+
+static unsigned int net5big_v2_mpp_config[] __initdata = {
+        MPP0_SPI_SCn,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP6_SYSRST_OUTn,
+        MPP7_GPO,               /* Request power-off */
+        MPP8_TW_SDA,
+        MPP9_TW_SCK,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP13_GPIO,             /* Rear power switch (on|auto) */
+        MPP14_GPIO,             /* USB fuse alarm */
+        MPP15_GPIO,             /* Rear power switch (auto|off) */
+        MPP16_GPIO,             /* SATA HDD1 power */
+        MPP17_GPIO,             /* SATA HDD2 power */
+        MPP20_GE1_0,
+        MPP21_GE1_1,
+        MPP22_GE1_2,
+        MPP23_GE1_3,
+        MPP24_GE1_4,
+        MPP25_GE1_5,
+        MPP26_GE1_6,
+        MPP27_GE1_7,
+        MPP28_GPIO,             /* USB enable host vbus */
+        MPP29_GPIO,             /* CPLD extension ALE */
+        MPP30_GE1_10,
+        MPP31_GE1_11,
+        MPP32_GE1_12,
+        MPP33_GE1_13,
+        MPP34_GPIO,             /* Rear Push button */
+        MPP35_GPIO,             /* Inhibit switch power-off */
+        MPP36_GPIO,             /* SATA HDD1 presence */
+        MPP37_GPIO,             /* SATA HDD2 presence */
+        MPP38_GPIO,             /* SATA HDD3 presence */
+        MPP39_GPIO,             /* SATA HDD4 presence */
+        MPP40_GPIO,             /* SATA HDD5 presence */
+        MPP41_GPIO,             /* SATA HDD3 power */
+        MPP42_GPIO,             /* SATA HDD4 power */
+        MPP43_GPIO,             /* SATA HDD5 power */
+        MPP44_GPIO,             /* CPLD extension (data 0) */
+        MPP45_GPIO,             /* CPLD extension (data 1) */
+        MPP46_GPIO,             /* CPLD extension (data 2) */
+        MPP47_GPIO,             /* CPLD extension (addr 0) */
+        MPP48_GPIO,             /* CPLD extension (addr 1) */
+        MPP49_GPIO,             /* CPLD extension (addr 2) */
+        0
+};
+
+#define NETXBIG_V2_GPIO_POWER_OFF               7
+
+static void netxbig_v2_power_off(void)
+{
+        gpio_set_value(NETXBIG_V2_GPIO_POWER_OFF, 1);
+}
+
+static void __init netxbig_v2_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        if (machine_is_net2big_v2())
+                kirkwood_mpp_conf(net2big_v2_mpp_config);
+        else
+                kirkwood_mpp_conf(net5big_v2_mpp_config);
+
+        netxbig_v2_sata_power_init();
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&netxbig_v2_ge00_data);
+        if (machine_is_net5big_v2())
+                kirkwood_ge01_init(&netxbig_v2_ge01_data);
+        kirkwood_sata_init(&netxbig_v2_sata_data);
+        kirkwood_uart0_init();
+        spi_register_board_info(netxbig_v2_spi_slave_info,
+                                ARRAY_SIZE(netxbig_v2_spi_slave_info));
+        kirkwood_spi_init();
+        kirkwood_i2c_init();
+        i2c_register_board_info(0, netxbig_v2_i2c_info,
+                                ARRAY_SIZE(netxbig_v2_i2c_info));
+
+        platform_device_register(&netxbig_v2_gpio_buttons);
+
+        if (gpio_request(NETXBIG_V2_GPIO_POWER_OFF, "power-off") == 0 &&
+            gpio_direction_output(NETXBIG_V2_GPIO_POWER_OFF, 0) == 0)
+                pm_power_off = netxbig_v2_power_off;
+        else
+                pr_err("netxbig_v2: failed to configure power-off GPIO\n");
+}
+
+#ifdef CONFIG_MACH_NET2BIG_V2
+MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = netxbig_v2_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &netxbig_v2_timer,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_NET5BIG_V2
+MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = netxbig_v2_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &netxbig_v2_timer,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index a604b2a701aa..dee1eff50d39 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -10,6 +10,7 @@
 
 #include <linux/kernel.h>
 #include <linux/pci.h>
+#include <linux/slab.h>
 #include <linux/mbus.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-lh7a40x/clcd.c b/arch/arm/mach-lh7a40x/clcd.c
index c472b9e8b37c..7fe4fd347c82 100644
--- a/arch/arm/mach-lh7a40x/clcd.c
+++ b/arch/arm/mach-lh7a40x/clcd.c
@@ -10,6 +10,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/gfp.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
 #include <linux/sysdev.h>
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index a2d307ec0420..244655d323ea 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -59,6 +59,13 @@ static unsigned long common_pin_config[] __initdata = {
         /* UART1 */
         GPIO107_UART1_RXD,
         GPIO108_UART1_TXD,
+
+        /* SSP1 */
+        GPIO113_I2S_MCLK,
+        GPIO114_I2S_FRM,
+        GPIO115_I2S_BCLK,
+        GPIO116_I2S_RXD,
+        GPIO117_I2S_TXD,
 };
 
 static struct smc91x_platdata smc91x_info = {
@@ -123,12 +130,18 @@ static struct pxa3xx_nand_platform_data aspenite_nand_info = {
         .nr_parts       = ARRAY_SIZE(aspenite_nand_partitions),
 };
 
+static struct i2c_board_info aspenite_i2c_info[] __initdata = {
+        { I2C_BOARD_INFO("wm8753", 0x1b), },
+};
+
 static void __init common_init(void)
 {
         mfp_config(ARRAY_AND_SIZE(common_pin_config));
 
         /* on-chip devices */
         pxa168_add_uart(1);
+        pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info));
+        pxa168_add_ssp(1);
         pxa168_add_nand(&aspenite_nand_info);
 
         /* off-chip devices */
diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h
index ab26d13295c4..ee8b02ed8011 100644
--- a/arch/arm/mach-mmp/include/mach/gpio.h
+++ b/arch/arm/mach-mmp/include/mach/gpio.h
@@ -10,7 +10,7 @@
 #define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
 #define GPIO_REG(x)     (*((volatile u32 *)(GPIO_REGS_VIRT + (x))))
 
-#define NR_BUILTIN_GPIO (128)
+#define NR_BUILTIN_GPIO (192)
 
 #define gpio_to_bank(gpio)      ((gpio) >> 5)
 #define gpio_to_irq(gpio)       (IRQ_GPIO_START + (gpio))
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index 02701196ea03..b379cdec4d38 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -5,10 +5,10 @@
  * Interrupt numbers for PXA168
  */
 #define IRQ_PXA168_NONE                 (-1)
-#define IRQ_PXA168_SSP3                 0
-#define IRQ_PXA168_SSP2                 1
-#define IRQ_PXA168_SSP1                 2
-#define IRQ_PXA168_SSP0                 3
+#define IRQ_PXA168_SSP4                 0
+#define IRQ_PXA168_SSP3                 1
+#define IRQ_PXA168_SSP2                 2
+#define IRQ_PXA168_SSP1                 3
 #define IRQ_PXA168_PMIC_INT             4
 #define IRQ_PXA168_RTC_INT              5
 #define IRQ_PXA168_RTC_ALARM            6
@@ -20,7 +20,7 @@
 #define IRQ_PXA168_TIMER2               14
 #define IRQ_PXA168_TIMER3               15
 #define IRQ_PXA168_CMU                  16
-#define IRQ_PXA168_SSP4                 17
+#define IRQ_PXA168_SSP5                 17
 #define IRQ_PXA168_MSP_WAKEUP           19
 #define IRQ_PXA168_CF_WAKEUP            20
 #define IRQ_PXA168_XD_WAKEUP            21
diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
index 9f9f8143e272..761c2dacc079 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
@@ -9,6 +9,175 @@
 #define MFP_DRIVE_FAST          (0x8 << 13)
 
 /* GPIO */
+#define GPIO0_GPIO0             MFP_CFG(GPIO0, AF0)
+#define GPIO1_GPIO1             MFP_CFG(GPIO1, AF0)
+#define GPIO2_GPIO2             MFP_CFG(GPIO2, AF0)
+#define GPIO3_GPIO3             MFP_CFG(GPIO3, AF0)
+#define GPIO4_GPIO4             MFP_CFG(GPIO4, AF0)
+#define GPIO5_GPIO5             MFP_CFG(GPIO5, AF0)
+#define GPIO6_GPIO6             MFP_CFG(GPIO6, AF0)
+#define GPIO7_GPIO7             MFP_CFG(GPIO7, AF0)
+#define GPIO8_GPIO8             MFP_CFG(GPIO8, AF0)
+#define GPIO9_GPIO9             MFP_CFG(GPIO9, AF0)
+#define GPIO10_GPIO10           MFP_CFG(GPIO10, AF0)
+#define GPIO11_GPIO11           MFP_CFG(GPIO11, AF0)
+#define GPIO12_GPIO12           MFP_CFG(GPIO12, AF0)
+#define GPIO13_GPIO13           MFP_CFG(GPIO13, AF0)
+#define GPIO14_GPIO14           MFP_CFG(GPIO14, AF0)
+#define GPIO15_GPIO15           MFP_CFG(GPIO15, AF0)
+#define GPIO16_GPIO16           MFP_CFG(GPIO16, AF0)
+#define GPIO17_GPIO17           MFP_CFG(GPIO17, AF0)
+#define GPIO18_GPIO18           MFP_CFG(GPIO18, AF0)
+#define GPIO19_GPIO19           MFP_CFG(GPIO19, AF0)
+#define GPIO20_GPIO20           MFP_CFG(GPIO20, AF0)
+#define GPIO21_GPIO21           MFP_CFG(GPIO21, AF0)
+#define GPIO22_GPIO22           MFP_CFG(GPIO22, AF0)
+#define GPIO23_GPIO23           MFP_CFG(GPIO23, AF0)
+#define GPIO24_GPIO24           MFP_CFG(GPIO24, AF0)
+#define GPIO25_GPIO25           MFP_CFG(GPIO25, AF0)
+#define GPIO26_GPIO26           MFP_CFG(GPIO26, AF0)
+#define GPIO27_GPIO27           MFP_CFG(GPIO27, AF0)
+#define GPIO28_GPIO28           MFP_CFG(GPIO28, AF0)
+#define GPIO29_GPIO29           MFP_CFG(GPIO29, AF0)
+#define GPIO30_GPIO30           MFP_CFG(GPIO30, AF0)
+#define GPIO31_GPIO31           MFP_CFG(GPIO31, AF0)
+#define GPIO32_GPIO32           MFP_CFG(GPIO32, AF0)
+#define GPIO33_GPIO33           MFP_CFG(GPIO33, AF0)
+#define GPIO34_GPIO34           MFP_CFG(GPIO34, AF0)
+#define GPIO35_GPIO35           MFP_CFG(GPIO35, AF0)
+#define GPIO36_GPIO36           MFP_CFG(GPIO36, AF0)
+#define GPIO37_GPIO37           MFP_CFG(GPIO37, AF0)
+#define GPIO38_GPIO38           MFP_CFG(GPIO38, AF0)
+#define GPIO39_GPIO39           MFP_CFG(GPIO39, AF0)
+#define GPIO40_GPIO40           MFP_CFG(GPIO40, AF0)
+#define GPIO41_GPIO41           MFP_CFG(GPIO41, AF0)
+#define GPIO42_GPIO42           MFP_CFG(GPIO42, AF0)
+#define GPIO43_GPIO43           MFP_CFG(GPIO43, AF0)
+#define GPIO44_GPIO44           MFP_CFG(GPIO44, AF0)
+#define GPIO45_GPIO45           MFP_CFG(GPIO45, AF0)
+#define GPIO46_GPIO46           MFP_CFG(GPIO46, AF0)
+#define GPIO47_GPIO47           MFP_CFG(GPIO47, AF0)
+#define GPIO48_GPIO48           MFP_CFG(GPIO48, AF0)
+#define GPIO49_GPIO49           MFP_CFG(GPIO49, AF0)
+#define GPIO50_GPIO50           MFP_CFG(GPIO50, AF0)
+#define GPIO51_GPIO51           MFP_CFG(GPIO51, AF0)
+#define GPIO52_GPIO52           MFP_CFG(GPIO52, AF0)
+#define GPIO53_GPIO53           MFP_CFG(GPIO53, AF0)
+#define GPIO54_GPIO54           MFP_CFG(GPIO54, AF0)
+#define GPIO55_GPIO55           MFP_CFG(GPIO55, AF0)
+#define GPIO56_GPIO56           MFP_CFG(GPIO56, AF0)
+#define GPIO57_GPIO57           MFP_CFG(GPIO57, AF0)
+#define GPIO58_GPIO58           MFP_CFG(GPIO58, AF0)
+#define GPIO59_GPIO59           MFP_CFG(GPIO59, AF0)
+#define GPIO60_GPIO60           MFP_CFG(GPIO60, AF0)
+#define GPIO61_GPIO61           MFP_CFG(GPIO61, AF0)
+#define GPIO62_GPIO62           MFP_CFG(GPIO62, AF0)
+#define GPIO63_GPIO63           MFP_CFG(GPIO63, AF0)
+#define GPIO64_GPIO64           MFP_CFG(GPIO64, AF0)
+#define GPIO65_GPIO65           MFP_CFG(GPIO65, AF0)
+#define GPIO66_GPIO66           MFP_CFG(GPIO66, AF0)
+#define GPIO67_GPIO67           MFP_CFG(GPIO67, AF0)
+#define GPIO68_GPIO68           MFP_CFG(GPIO68, AF0)
+#define GPIO69_GPIO69           MFP_CFG(GPIO69, AF0)
+#define GPIO70_GPIO70           MFP_CFG(GPIO70, AF0)
+#define GPIO71_GPIO71           MFP_CFG(GPIO71, AF0)
+#define GPIO72_GPIO72           MFP_CFG(GPIO72, AF0)
+#define GPIO73_GPIO73           MFP_CFG(GPIO73, AF0)
+#define GPIO74_GPIO74           MFP_CFG(GPIO74, AF0)
+#define GPIO75_GPIO75           MFP_CFG(GPIO75, AF0)
+#define GPIO76_GPIO76           MFP_CFG(GPIO76, AF0)
+#define GPIO77_GPIO77           MFP_CFG(GPIO77, AF0)
+#define GPIO78_GPIO78           MFP_CFG(GPIO78, AF0)
+#define GPIO79_GPIO79           MFP_CFG(GPIO79, AF0)
+#define GPIO80_GPIO80           MFP_CFG(GPIO80, AF0)
+#define GPIO81_GPIO81           MFP_CFG(GPIO81, AF0)
+#define GPIO82_GPIO82           MFP_CFG(GPIO82, AF0)
+#define GPIO83_GPIO83           MFP_CFG(GPIO83, AF0)
+#define GPIO84_GPIO84           MFP_CFG(GPIO84, AF0)
+#define GPIO85_GPIO85           MFP_CFG(GPIO85, AF0)
+#define GPIO86_GPIO86           MFP_CFG(GPIO86, AF0)
+#define GPIO87_GPIO87           MFP_CFG(GPIO87, AF0)
+#define GPIO88_GPIO88           MFP_CFG(GPIO88, AF0)
+#define GPIO89_GPIO89           MFP_CFG(GPIO89, AF0)
+#define GPIO90_GPIO90           MFP_CFG(GPIO90, AF0)
+#define GPIO91_GPIO91           MFP_CFG(GPIO91, AF0)
+#define GPIO92_GPIO92           MFP_CFG(GPIO92, AF0)
+#define GPIO93_GPIO93           MFP_CFG(GPIO93, AF0)
+#define GPIO94_GPIO94           MFP_CFG(GPIO94, AF0)
+#define GPIO95_GPIO95           MFP_CFG(GPIO95, AF0)
+#define GPIO96_GPIO96           MFP_CFG(GPIO96, AF0)
+#define GPIO97_GPIO97           MFP_CFG(GPIO97, AF0)
+#define GPIO98_GPIO98           MFP_CFG(GPIO98, AF0)
+#define GPIO99_GPIO99           MFP_CFG(GPIO99, AF0)
+#define GPIO100_GPIO100         MFP_CFG(GPIO100, AF0)
+#define GPIO101_GPIO101         MFP_CFG(GPIO101, AF0)
+#define GPIO102_GPIO102         MFP_CFG(GPIO102, AF1)
+#define GPIO103_GPIO103         MFP_CFG(GPIO103, AF1)
+#define GPIO104_GPIO104         MFP_CFG(GPIO104, AF1)
+#define GPIO105_GPIO105         MFP_CFG(GPIO105, AF1)
+#define GPIO106_GPIO106         MFP_CFG(GPIO106, AF1)
+#define GPIO107_GPIO107         MFP_CFG(GPIO107, AF1)
+#define GPIO108_GPIO108         MFP_CFG(GPIO108, AF1)
+#define GPIO109_GPIO109         MFP_CFG(GPIO109, AF1)
+#define GPIO110_GPIO110         MFP_CFG(GPIO110, AF1)
+#define GPIO111_GPIO111         MFP_CFG(GPIO111, AF1)
+#define GPIO112_GPIO112         MFP_CFG(GPIO112, AF1)
+#define GPIO113_GPIO113         MFP_CFG(GPIO113, AF1)
+#define GPIO114_GPIO114         MFP_CFG(GPIO114, AF0)
+#define GPIO115_GPIO115         MFP_CFG(GPIO115, AF0)
+#define GPIO116_GPIO116         MFP_CFG(GPIO116, AF0)
+#define GPIO117_GPIO117         MFP_CFG(GPIO117, AF0)
+#define GPIO118_GPIO118         MFP_CFG(GPIO118, AF0)
+#define GPIO119_GPIO119         MFP_CFG(GPIO119, AF0)
+#define GPIO120_GPIO120         MFP_CFG(GPIO120, AF0)
+#define GPIO121_GPIO121         MFP_CFG(GPIO121, AF0)
+#define GPIO122_GPIO122         MFP_CFG(GPIO122, AF0)
+#define GPIO123_GPIO123         MFP_CFG(GPIO123, AF0)
+#define GPIO124_GPIO124         MFP_CFG(GPIO124, AF0)
+#define GPIO125_GPIO125         MFP_CFG(GPIO125, AF0)
+#define GPIO126_GPIO126         MFP_CFG(GPIO126, AF0)
+#define GPIO127_GPIO127         MFP_CFG(GPIO127, AF0)
+#define GPIO128_GPIO128         MFP_CFG(GPIO128, AF0)
+#define GPIO129_GPIO129         MFP_CFG(GPIO129, AF0)
+#define GPIO130_GPIO130         MFP_CFG(GPIO130, AF0)
+#define GPIO131_GPIO131         MFP_CFG(GPIO131, AF0)
+#define GPIO132_GPIO132         MFP_CFG(GPIO132, AF0)
+#define GPIO133_GPIO133         MFP_CFG(GPIO133, AF0)
+#define GPIO134_GPIO134         MFP_CFG(GPIO134, AF0)
+#define GPIO135_GPIO135         MFP_CFG(GPIO135, AF0)
+#define GPIO136_GPIO136         MFP_CFG(GPIO136, AF0)
+#define GPIO137_GPIO137         MFP_CFG(GPIO137, AF0)
+#define GPIO138_GPIO138         MFP_CFG(GPIO138, AF0)
+#define GPIO139_GPIO139         MFP_CFG(GPIO139, AF0)
+#define GPIO140_GPIO140         MFP_CFG(GPIO140, AF0)
+#define GPIO141_GPIO141         MFP_CFG(GPIO141, AF0)
+#define GPIO142_GPIO142         MFP_CFG(GPIO142, AF1)
+#define GPIO143_GPIO143         MFP_CFG(GPIO143, AF1)
+#define GPIO144_GPIO144         MFP_CFG(GPIO144, AF1)
+#define GPIO145_GPIO145         MFP_CFG(GPIO145, AF1)
+#define GPIO146_GPIO146         MFP_CFG(GPIO146, AF1)
+#define GPIO147_GPIO147         MFP_CFG(GPIO147, AF1)
+#define GPIO148_GPIO148         MFP_CFG(GPIO148, AF1)
+#define GPIO149_GPIO149         MFP_CFG(GPIO149, AF1)
+#define GPIO150_GPIO150         MFP_CFG(GPIO150, AF1)
+#define GPIO151_GPIO151         MFP_CFG(GPIO151, AF1)
+#define GPIO152_GPIO152         MFP_CFG(GPIO152, AF1)
+#define GPIO153_GPIO153         MFP_CFG(GPIO153, AF1)
+#define GPIO154_GPIO154         MFP_CFG(GPIO154, AF1)
+#define GPIO155_GPIO155         MFP_CFG(GPIO155, AF1)
+#define GPIO156_GPIO156         MFP_CFG(GPIO156, AF1)
+#define GPIO157_GPIO157         MFP_CFG(GPIO157, AF1)
+#define GPIO158_GPIO158         MFP_CFG(GPIO158, AF1)
+#define GPIO159_GPIO159         MFP_CFG(GPIO159, AF1)
+#define GPIO160_GPIO160         MFP_CFG(GPIO160, AF1)
+#define GPIO161_GPIO161         MFP_CFG(GPIO161, AF1)
+#define GPIO162_GPIO162         MFP_CFG(GPIO162, AF1)
+#define GPIO163_GPIO163         MFP_CFG(GPIO163, AF1)
+#define GPIO164_GPIO164         MFP_CFG(GPIO164, AF1)
+#define GPIO165_GPIO165         MFP_CFG(GPIO165, AF1)
+#define GPIO166_GPIO166         MFP_CFG(GPIO166, AF1)
+#define GPIO167_GPIO167         MFP_CFG(GPIO167, AF1)
+#define GPIO168_GPIO168         MFP_CFG(GPIO168, AF1)
 
 /* DFI */
 #define GPIO108_DFI_D15         MFP_CFG(GPIO108, AF0)
@@ -47,7 +216,6 @@
 
 /* Ethernet */
 #define GPIO155_SM_ADVMUX       MFP_CFG(GPIO155, AF2)
-#define GPIO155_GPIO155         MFP_CFG(GPIO155, AF1)
 
 /* UART1 */
 #define GPIO45_UART1_RXD        MFP_CFG(GPIO45, AF1)
@@ -159,6 +327,8 @@
 #define GPIO44_TWSI2_SDA        MFP_CFG_DRV(GPIO44, AF1, SLOW)
 #define GPIO71_TWSI3_SCL        MFP_CFG_DRV(GPIO71, AF1, SLOW)
 #define GPIO72_TWSI3_SDA        MFP_CFG_DRV(GPIO72, AF1, SLOW)
+#define TWSI4_SCL               MFP_CFG_DRV(TWSI4_SCL, AF0, SLOW)
+#define TWSI4_SDA               MFP_CFG_DRV(TWSI4_SDA, AF0, SLOW)
 #define GPIO99_TWSI5_SCL        MFP_CFG_DRV(GPIO99, AF4, SLOW)
 #define GPIO100_TWSI5_SDA       MFP_CFG_DRV(GPIO100, AF4, SLOW)
 #define GPIO97_TWSI6_SCL        MFP_CFG_DRV(GPIO97, AF2, SLOW)
@@ -218,21 +388,6 @@
 #define GPIO69_CAM_MCLK         MFP_CFG_DRV(GPIO69, AF1, FAST)
 #define GPIO70_CAM_PCLK         MFP_CFG_DRV(GPIO70, AF1, FAST)
 
-/* Wifi */
-#define GPIO45_GPIO45           MFP_CFG(GPIO45, AF0)
-#define GPIO46_GPIO46           MFP_CFG(GPIO46, AF0)
-#define GPIO21_GPIO21           MFP_CFG(GPIO21, AF0)
-#define GPIO22_GPIO22           MFP_CFG(GPIO22, AF0)
-#define GPIO55_GPIO55           MFP_CFG(GPIO55, AF0)
-#define GPIO56_GPIO56           MFP_CFG(GPIO56, AF0)
-#define GPIO57_GPIO57           MFP_CFG(GPIO57, AF0)
-#define GPIO58_GPIO58           MFP_CFG(GPIO58, AF0)
-
-/* Codec*/
-#define GPIO23_GPIO23           MFP_CFG(GPIO23, AF0)
-
-#define GPIO101_GPIO101         MFP_CFG(GPIO101, AF0)
-
 /* PMIC */
 #define PMIC_PMIC_INT           MFP_CFG(PMIC_INT, AF0)
 
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h
index 459f3be9cfb2..fec220bd5046 100644
--- a/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -39,17 +39,17 @@ static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data,
         int ret;
 
         switch (id) {
-        case 0: d = &mmp2_device_twsi1; break;
-        case 1: d = &mmp2_device_twsi2; break;
-        case 2: d = &mmp2_device_twsi3; break;
-        case 3: d = &mmp2_device_twsi4; break;
-        case 4: d = &mmp2_device_twsi5; break;
-        case 5: d = &mmp2_device_twsi6; break;
+        case 1: d = &mmp2_device_twsi1; break;
+        case 2: d = &mmp2_device_twsi2; break;
+        case 3: d = &mmp2_device_twsi3; break;
+        case 4: d = &mmp2_device_twsi4; break;
+        case 5: d = &mmp2_device_twsi5; break;
+        case 6: d = &mmp2_device_twsi6; break;
         default:
                 return -EINVAL;
         }
 
-        ret = i2c_register_board_info(id, info, size);
+        ret = i2c_register_board_info(id - 1, info, size);
         if (ret)
                 return ret;
 
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 3ad612cbdf09..3b2bd5d5eb05 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -14,6 +14,11 @@ extern struct pxa_device_desc pxa168_device_pwm1;
 extern struct pxa_device_desc pxa168_device_pwm2;
 extern struct pxa_device_desc pxa168_device_pwm3;
 extern struct pxa_device_desc pxa168_device_pwm4;
+extern struct pxa_device_desc pxa168_device_ssp1;
+extern struct pxa_device_desc pxa168_device_ssp2;
+extern struct pxa_device_desc pxa168_device_ssp3;
+extern struct pxa_device_desc pxa168_device_ssp4;
+extern struct pxa_device_desc pxa168_device_ssp5;
 extern struct pxa_device_desc pxa168_device_nand;
 
 static inline int pxa168_add_uart(int id)
@@ -67,6 +72,22 @@ static inline int pxa168_add_pwm(int id)
         return pxa_register_device(d, NULL, 0);
 }
 
+static inline int pxa168_add_ssp(int id)
+{
+        struct pxa_device_desc *d = NULL;
+
+        switch (id) {
+        case 1: d = &pxa168_device_ssp1; break;
+        case 2: d = &pxa168_device_ssp2; break;
+        case 3: d = &pxa168_device_ssp3; break;
+        case 4: d = &pxa168_device_ssp4; break;
+        case 5: d = &pxa168_device_ssp5; break;
+        default:
+                return -EINVAL;
+        }
+        return pxa_register_device(d, NULL, 0);
+}
+
 static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info)
 {
         return pxa_register_device(&pxa168_device_nand, info, sizeof(*info));
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 712af03fd1af..1a96585336ba 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -26,8 +26,6 @@
 #define APBC_PXA168_PWM2        APBC_REG(0x010)
 #define APBC_PXA168_PWM3        APBC_REG(0x014)
 #define APBC_PXA168_PWM4        APBC_REG(0x018)
-#define APBC_PXA168_SSP1        APBC_REG(0x01c)
-#define APBC_PXA168_SSP2        APBC_REG(0x020)
 #define APBC_PXA168_RTC         APBC_REG(0x028)
 #define APBC_PXA168_TWSI0       APBC_REG(0x02c)
 #define APBC_PXA168_KPC         APBC_REG(0x030)
@@ -35,14 +33,16 @@
 #define APBC_PXA168_AIB         APBC_REG(0x03c)
 #define APBC_PXA168_SW_JTAG     APBC_REG(0x040)
 #define APBC_PXA168_ONEWIRE     APBC_REG(0x048)
-#define APBC_PXA168_SSP3        APBC_REG(0x04c)
 #define APBC_PXA168_ASFAR       APBC_REG(0x050)
 #define APBC_PXA168_ASSAR       APBC_REG(0x054)
-#define APBC_PXA168_SSP4        APBC_REG(0x058)
-#define APBC_PXA168_SSP5        APBC_REG(0x05c)
 #define APBC_PXA168_TWSI1       APBC_REG(0x06c)
 #define APBC_PXA168_UART3       APBC_REG(0x070)
 #define APBC_PXA168_AC97        APBC_REG(0x084)
+#define APBC_PXA168_SSP1        APBC_REG(0x81c)
+#define APBC_PXA168_SSP2        APBC_REG(0x820)
+#define APBC_PXA168_SSP3        APBC_REG(0x84c)
+#define APBC_PXA168_SSP4        APBC_REG(0x858)
+#define APBC_PXA168_SSP5        APBC_REG(0x85c)
 
 /*
  * APB Clock register offsets for PXA910
diff --git a/arch/arm/mach-mmp/include/mach/regs-smc.h b/arch/arm/mach-mmp/include/mach/regs-smc.h
new file mode 100644
index 000000000000..e484d40d71bd
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-smc.h
@@ -0,0 +1,37 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/regs-smc.h
+ *
+ *  Static Memory Controller Registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_REGS_SMC_H
+#define __ASM_MACH_REGS_SMC_H
+
+#include <mach/addr-map.h>
+
+#define SMC_VIRT_BASE           (AXI_VIRT_BASE + 0x83800)
+#define SMC_REG(x)              (SMC_VIRT_BASE + (x))
+
+#define SMC_MSC0                SMC_REG(0x0020)
+#define SMC_MSC1                SMC_REG(0x0024)
+#define SMC_SXCNFG0             SMC_REG(0x0030)
+#define SMC_SXCNFG1             SMC_REG(0x0034)
+#define SMC_MEMCLKCFG           SMC_REG(0x0068)
+#define SMC_CSDFICFG0           SMC_REG(0x0090)
+#define SMC_CSDFICFG1           SMC_REG(0x0094)
+#define SMC_CLK_RET_DEL         SMC_REG(0x00b0)
+#define SMC_ADV_RET_DEL         SMC_REG(0x00b4)
+#define SMC_CSADRMAP0           SMC_REG(0x00c0)
+#define SMC_CSADRMAP1           SMC_REG(0x00c4)
+#define SMC_WE_AP0              SMC_REG(0x00e0)
+#define SMC_WE_AP1              SMC_REG(0x00e4)
+#define SMC_OE_AP0              SMC_REG(0x00f0)
+#define SMC_OE_AP1              SMC_REG(0x00f4)
+#define SMC_ADV_AP0             SMC_REG(0x0100)
+#define SMC_ADV_AP1             SMC_REG(0x0104)
+
+#endif /* __ASM_MACH_REGS_SMC_H */
diff --git a/arch/arm/mach-mmp/include/mach/timex.h b/arch/arm/mach-mmp/include/mach/timex.h
index 6cebbd0ca8f4..70c9f1d88c02 100644
--- a/arch/arm/mach-mmp/include/mach/timex.h
+++ b/arch/arm/mach-mmp/include/mach/timex.h
@@ -6,4 +6,8 @@
  * published by the Free Software Foundation.
  */
 
+#ifdef CONFIG_CPU_MMP2
+#define CLOCK_TICK_RATE         6500000
+#else
 #define CLOCK_TICK_RATE         3250000
+#endif
diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h
index a7dcc5307216..85bd8a2d84b5 100644
--- a/arch/arm/mach-mmp/include/mach/uncompress.h
+++ b/arch/arm/mach-mmp/include/mach/uncompress.h
@@ -14,7 +14,7 @@
 #define UART2_BASE      (APB_PHYS_BASE + 0x17000)
 #define UART3_BASE      (APB_PHYS_BASE + 0x18000)
 
-static volatile unsigned long *UART = (unsigned long *)UART2_BASE;
+static volatile unsigned long *UART;
 
 static inline void putc(char c)
 {
@@ -37,6 +37,9 @@ static inline void flush(void)
 
 static inline void arch_decomp_setup(void)
 {
+        /* default to UART2 */
+        UART = (unsigned long *)UART2_BASE;
+
         if (machine_is_avengers_lite())
                 UART = (unsigned long *)UART3_BASE;
 }
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index cfd4d66ef800..d77dd41d60e1 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -15,12 +15,16 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/max8649.h>
+#include <linux/mfd/max8925.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/addr-map.h>
 #include <mach/mfp-mmp2.h>
 #include <mach/mmp2.h>
+#include <mach/irqs.h>
 
 #include "common.h"
 
@@ -58,6 +62,63 @@ static unsigned long jasper_pin_config[] __initdata = {
         GPIO149_ND_CLE,
         GPIO112_ND_RDY0,
         GPIO160_ND_RDY1,
+
+        /* PMIC */
+        PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
+};
+
+static struct regulator_consumer_supply max8649_supply[] = {
+        REGULATOR_SUPPLY("vcc_core", NULL),
+};
+
+static struct regulator_init_data max8649_init_data = {
+        .constraints    = {
+                .name           = "vcc_core range",
+                .min_uV         = 1150000,
+                .max_uV         = 1280000,
+                .always_on      = 1,
+                .boot_on        = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &max8649_supply[0],
+};
+
+static struct max8649_platform_data jasper_max8649_info = {
+        .mode           = 2,    /* VID1 = 1, VID0 = 0 */
+        .extclk         = 0,
+        .ramp_timing    = MAX8649_RAMP_32MV,
+        .regulator      = &max8649_init_data,
+};
+
+static struct max8925_backlight_pdata jasper_backlight_data = {
+        .dual_string    = 0,
+};
+
+static struct max8925_power_pdata jasper_power_data = {
+        .batt_detect            = 0,    /* can't detect battery by ID pin */
+        .topoff_threshold       = MAX8925_TOPOFF_THR_10PER,
+        .fast_charge            = MAX8925_FCHG_1000MA,
+};
+
+static struct max8925_platform_data jasper_max8925_info = {
+        .backlight              = &jasper_backlight_data,
+        .power                  = &jasper_power_data,
+        .irq_base               = IRQ_BOARD_START,
+};
+
+static struct i2c_board_info jasper_twsi1_info[] = {
+        [0] = {
+                .type           = "max8649",
+                .addr           = 0x60,
+                .platform_data  = &jasper_max8649_info,
+        },
+        [1] = {
+                .type           = "max8925",
+                .addr           = 0x3c,
+                .irq            = IRQ_MMP2_PMIC,
+                .platform_data  = &jasper_max8925_info,
+        },
 };
 
 static void __init jasper_init(void)
@@ -67,6 +128,9 @@ static void __init jasper_init(void)
         /* on-chip devices */
         mmp2_add_uart(1);
         mmp2_add_uart(3);
+        mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info));
+
+        regulator_has_full_constraints();
 }
 
 MACHINE_START(MARVELL_JASPER, "Jasper Development Platform")
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 72eb9daeea99..7f5eb059bb01 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -15,11 +15,14 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
+#include <asm/hardware/cache-tauros2.h>
+
 #include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
 #include <mach/regs-apmu.h>
 #include <mach/cputype.h>
 #include <mach/irqs.h>
+#include <mach/dma.h>
 #include <mach/mfp.h>
 #include <mach/gpio.h>
 #include <mach/devices.h>
@@ -32,7 +35,50 @@
 #define APMASK(i)       (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c)
 
 static struct mfp_addr_map mmp2_addr_map[] __initdata = {
+
+        MFP_ADDR_X(GPIO0, GPIO58, 0x54),
+        MFP_ADDR_X(GPIO59, GPIO73, 0x280),
+        MFP_ADDR_X(GPIO74, GPIO101, 0x170),
+
+        MFP_ADDR(GPIO102, 0x0),
+        MFP_ADDR(GPIO103, 0x4),
+        MFP_ADDR(GPIO104, 0x1fc),
+        MFP_ADDR(GPIO105, 0x1f8),
+        MFP_ADDR(GPIO106, 0x1f4),
+        MFP_ADDR(GPIO107, 0x1f0),
+        MFP_ADDR(GPIO108, 0x21c),
+        MFP_ADDR(GPIO109, 0x218),
+        MFP_ADDR(GPIO110, 0x214),
+        MFP_ADDR(GPIO111, 0x200),
+        MFP_ADDR(GPIO112, 0x244),
+        MFP_ADDR(GPIO113, 0x25c),
+        MFP_ADDR(GPIO114, 0x164),
+        MFP_ADDR_X(GPIO115, GPIO122, 0x260),
+
+        MFP_ADDR(GPIO123, 0x148),
+        MFP_ADDR_X(GPIO124, GPIO141, 0xc),
+
+        MFP_ADDR(GPIO142, 0x8),
+        MFP_ADDR_X(GPIO143, GPIO151, 0x220),
+        MFP_ADDR_X(GPIO152, GPIO153, 0x248),
+        MFP_ADDR_X(GPIO154, GPIO155, 0x254),
+        MFP_ADDR_X(GPIO156, GPIO159, 0x14c),
+
+        MFP_ADDR(GPIO160, 0x250),
+        MFP_ADDR(GPIO161, 0x210),
+        MFP_ADDR(GPIO162, 0x20c),
+        MFP_ADDR(GPIO163, 0x208),
+        MFP_ADDR(GPIO164, 0x204),
+        MFP_ADDR(GPIO165, 0x1ec),
+        MFP_ADDR(GPIO166, 0x1e8),
+        MFP_ADDR(GPIO167, 0x1e4),
+        MFP_ADDR(GPIO168, 0x1e0),
+
+        MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140),
+        MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc),
+
         MFP_ADDR(PMIC_INT, 0x2c4),
+        MFP_ADDR(CLK_REQ, 0x160),
 
         MFP_ADDR_END,
 };
@@ -99,9 +145,13 @@ static struct clk_lookup mmp2_clkregs[] = {
 static int __init mmp2_init(void)
 {
         if (cpu_is_mmp2()) {
+#ifdef CONFIG_CACHE_TAUROS2
+                tauros2_init();
+#endif
                 mfp_init_base(MFPR_VIRT_BASE);
                 mfp_init_addr(mmp2_addr_map);
-                clks_register(ARRAY_AND_SIZE(mmp2_clkregs));
+                pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16);
+                clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
         }
 
         return 0;
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 1873c821df90..652ae660634c 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -72,6 +72,11 @@ static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
 static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
 static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
 static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
+static APBC_CLK(ssp1, PXA168_SSP1, 4, 0);
+static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
+static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
+static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
+static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
 
 static APMU_CLK(nand, NAND, 0x01db, 208000000);
 
@@ -85,6 +90,11 @@ static struct clk_lookup pxa168_clkregs[] = {
         INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
         INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
         INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
+        INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
+        INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
+        INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
+        INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
+        INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
 };
 
@@ -132,3 +142,8 @@ PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10);
 PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10);
 PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10);
 PXA168_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
+PXA168_DEVICE(ssp1, "pxa168-ssp", 0, SSP1, 0xd401b000, 0x40, 52, 53);
+PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55);
+PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57);
+PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59);
+PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index f780086befd7..b9fd5c528e5b 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -29,12 +29,14 @@ endchoice
 
 config MACH_HALIBUT
         depends on ARCH_MSM
+        select CPU_V6
         default y
         bool "Halibut Board (QCT SURF7201A)"
         help
           Support for the Qualcomm SURF7201A eval board.
 
 config MACH_TROUT
+        select CPU_V6
         default y
         bool "HTC Dream (aka trout)"
         help
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 3872af1cf2c3..170f68e46dd5 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -62,6 +62,15 @@ config MACH_MX31_3DS
           Include support for MX31PDK (3DS) platform. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_MX31_3DS_MXC_NAND_USE_BBT
+        bool "Make the MXC NAND driver use the in flash Bad Block Table"
+        depends on MACH_MX31_3DS
+        depends on MTD_NAND_MXC
+        help
+          Enable this if you want that the MXC NAND driver uses the in flash
+          Bad Block Table to know what blocks are bad instead of scanning the
+          entire flash looking for bad block markers.
+
 config MACH_MX31MOBOARD
         bool "Support mx31moboard platforms (EPFL Mobots group)"
         select ARCH_MX31
@@ -95,6 +104,7 @@ config MACH_PCM043
 config MACH_ARMADILLO5X0
         bool "Support Atmark Armadillo-500 Development Base Board"
         select ARCH_MX31
+        select MXC_ULPI if USB_ULPI
         help
           Include support for Atmark Armadillo-500 platform. This includes
           specific configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c
index 80dba9966b5e..9a9eb6de6127 100644
--- a/arch/arm/mach-mx3/clock-imx31.c
+++ b/arch/arm/mach-mx3/clock-imx31.c
@@ -468,6 +468,7 @@ static struct clk ahb_clk = {
         }
 
 DEFINE_CLOCK(perclk_clk,  0, NULL,          0, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ckil_clk,    0, NULL,          0, clk_ckil_get_rate, NULL, NULL);
 
 DEFINE_CLOCK(sdhc1_clk,   0, MXC_CCM_CGR0,  0, NULL, NULL, &perclk_clk);
 DEFINE_CLOCK(sdhc2_clk,   1, MXC_CCM_CGR0,  2, NULL, NULL, &perclk_clk);
@@ -490,7 +491,7 @@ DEFINE_CLOCK(mpeg4_clk,   0, MXC_CCM_CGR1,  0, NULL, NULL, &ahb_clk);
 DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1,  2, mstick1_get_rate, NULL, &usb_pll_clk);
 DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1,  4, mstick2_get_rate, NULL, &usb_pll_clk);
 DEFINE_CLOCK1(csi_clk,    0, MXC_CCM_CGR1,  6, csi, NULL, &serial_pll_clk);
-DEFINE_CLOCK(rtc_clk,     0, MXC_CCM_CGR1,  8, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(rtc_clk,     0, MXC_CCM_CGR1,  8, NULL, NULL, &ckil_clk);
 DEFINE_CLOCK(wdog_clk,    0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(pwm_clk,     0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
 DEFINE_CLOCK(usb_clk2,    0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
@@ -514,7 +515,6 @@ DEFINE_CLOCK(usb_clk1,    0, NULL,          0, usb_get_rate, NULL, &usb_pll_clk)
 DEFINE_CLOCK(nfc_clk,     0, NULL,          0, nfc_get_rate, NULL, &ahb_clk);
 DEFINE_CLOCK(scc_clk,     0, NULL,          0, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
-DEFINE_CLOCK(ckil_clk,    0, NULL,          0, clk_ckil_get_rate, NULL, NULL);
 
 #define _REGISTER_CLOCK(d, n, c) \
         { \
@@ -572,7 +572,6 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "iim", iim_clk)
         _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
         _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
-        _REGISTER_CLOCK("mxc_rtc", NULL, ckil_clk)
 };
 
 int __init mx31_clocks_init(unsigned long fref)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index 6adb586515ea..f8911154a9fa 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -575,11 +575,26 @@ struct platform_device imx_ssi_device1 = {
         .resource = imx_ssi_resources1,
 };
 
-static int mx3_devices_init(void)
+static struct resource imx_wdt_resources[] = {
+        {
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device imx_wdt_device0 = {
+        .name           = "imx-wdt",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(imx_wdt_resources),
+        .resource       = imx_wdt_resources,
+};
+
+static int __init mx3_devices_init(void)
 {
         if (cpu_is_mx31()) {
                 mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
                 mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
+                imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
+                imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
                 mxc_register_device(&mxc_rnga_device, NULL);
         }
         if (cpu_is_mx35()) {
@@ -597,6 +612,8 @@ static int mx3_devices_init(void)
                 imx_ssi_resources0[1].end = MX35_INT_SSI1;
                 imx_ssi_resources1[1].start = MX35_INT_SSI2;
                 imx_ssi_resources1[1].end = MX35_INT_SSI2;
+                imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
+                imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
         }
 
         return 0;
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 42cf175eac6b..4f77eb501274 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -25,4 +25,5 @@ extern struct platform_device mxc_spi_device1;
 extern struct platform_device mxc_spi_device2;
 extern struct platform_device imx_ssi_device0;
 extern struct platform_device imx_ssi_device1;
-
+extern struct platform_device imx_ssi_device1;
+extern struct platform_device imx_wdt_device0;
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 3d72b0b89705..5f72ec91af2d 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -36,6 +36,9 @@
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
 #include <linux/i2c.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/delay.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -52,6 +55,8 @@
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
 #include <mach/mxc_nand.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
 
 #include "devices.h"
 #include "crm_regs.h"
@@ -103,8 +108,158 @@ static int armadillo5x0_pins[] = {
         /* I2C2 */
         MX31_PIN_CSPI2_MOSI__SCL,
         MX31_PIN_CSPI2_MISO__SDA,
+        /* OTG */
+        MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+        MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
+        MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
+        MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
+        MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
+        MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
+        MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
+        MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
+        MX31_PIN_USBOTG_CLK__USBOTG_CLK,
+        MX31_PIN_USBOTG_DIR__USBOTG_DIR,
+        MX31_PIN_USBOTG_NXT__USBOTG_NXT,
+        MX31_PIN_USBOTG_STP__USBOTG_STP,
+        /* USB host 2 */
+        IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
 };
 
+/* USB */
+#if defined(CONFIG_USB_ULPI)
+
+#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4)
+#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6)
+#define USBH2_CS IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)
+
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+static int usbotg_init(struct platform_device *pdev)
+{
+        int err;
+
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
+
+        /* Chip already enabled by hardware */
+        /* OTG phy reset*/
+        err = gpio_request(OTG_RESET, "USB-OTG-RESET");
+        if (err) {
+                pr_err("Failed to request the usb otg reset gpio\n");
+                return err;
+        }
+
+        err = gpio_direction_output(OTG_RESET, 1/*HIGH*/);
+        if (err) {
+                pr_err("Failed to reset the usb otg phy\n");
+                goto otg_free_reset;
+        }
+
+        gpio_set_value(OTG_RESET, 0/*LOW*/);
+        mdelay(5);
+        gpio_set_value(OTG_RESET, 1/*HIGH*/);
+
+        return 0;
+
+otg_free_reset:
+        gpio_free(OTG_RESET);
+        return err;
+}
+
+static int usbh2_init(struct platform_device *pdev)
+{
+        int err;
+
+        mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
+
+        mxc_iomux_set_gpr(MUX_PGP_UH2, true);
+
+
+        /* Enable the chip */
+        err = gpio_request(USBH2_CS, "USB-H2-CS");
+        if (err) {
+                pr_err("Failed to request the usb host 2 CS gpio\n");
+                return err;
+        }
+
+        err = gpio_direction_output(USBH2_CS, 0/*Enabled*/);
+        if (err) {
+                pr_err("Failed to drive the usb host 2 CS gpio\n");
+                goto h2_free_cs;
+        }
+
+        /* H2 phy reset*/
+        err = gpio_request(USBH2_RESET, "USB-H2-RESET");
+        if (err) {
+                pr_err("Failed to request the usb host 2 reset gpio\n");
+                goto h2_free_cs;
+        }
+
+        err = gpio_direction_output(USBH2_RESET, 1/*HIGH*/);
+        if (err) {
+                pr_err("Failed to reset the usb host 2 phy\n");
+                goto h2_free_reset;
+        }
+
+        gpio_set_value(USBH2_RESET, 0/*LOW*/);
+        mdelay(5);
+        gpio_set_value(USBH2_RESET, 1/*HIGH*/);
+
+        return 0;
+
+h2_free_reset:
+        gpio_free(USBH2_RESET);
+h2_free_cs:
+        gpio_free(USBH2_CS);
+        return err;
+}
+
+static struct mxc_usbh_platform_data usbotg_pdata = {
+        .init   = usbotg_init,
+        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata = {
+        .init   = usbh2_init,
+        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+#endif /* CONFIG_USB_ULPI */
+
 /* RTC over I2C*/
 #define ARMADILLO5X0_RTC_GPIO   IOMUX_TO_GPIO(MX31_PIN_SRXD4)
 
@@ -393,6 +548,17 @@ static void __init armadillo5x0_init(void)
         if (armadillo5x0_i2c_rtc.irq == 0)
                 pr_warning("armadillo5x0_init: failed to get RTC IRQ\n");
         i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
+
+        /* USB */
+#if defined(CONFIG_USB_ULPI)
+        usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                        USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                        USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+        mxc_register_device(&mxc_otg_host, &usbotg_pdata);
+        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+#endif
 }
 
 static void __init armadillo5x0_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index b88c18ad7698..f54af1e29ca4 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -23,6 +23,9 @@
 #include <linux/gpio.h>
 #include <linux/smsc911x.h>
 #include <linux/platform_device.h>
+#include <linux/mfd/mc13783.h>
+#include <linux/spi/spi.h>
+#include <linux/regulator/machine.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -31,26 +34,96 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/board-mx31pdk.h>
+#include <mach/board-mx31_3ds.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
+#include <mach/mxc_nand.h>
+#include <mach/spi.h>
 #include "devices.h"
 
 /*!
- * @file mx31pdk.c
+ * @file mx31_3ds.c
  *
  * @brief This file contains the board-specific initialization routines.
  *
  * @ingroup System
  */
 
-static int mx31pdk_pins[] = {
+static int mx31_3ds_pins[] = {
         /* UART1 */
         MX31_PIN_CTS1__CTS1,
         MX31_PIN_RTS1__RTS1,
         MX31_PIN_TXD1__TXD1,
         MX31_PIN_RXD1__RXD1,
         IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
+        /* SPI 1 */
+        MX31_PIN_CSPI2_SCLK__SCLK,
+        MX31_PIN_CSPI2_MOSI__MOSI,
+        MX31_PIN_CSPI2_MISO__MISO,
+        MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
+        MX31_PIN_CSPI2_SS0__SS0,
+        MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
+        /* MC13783 IRQ */
+        IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
+};
+
+/* Regulators */
+static struct regulator_init_data pwgtx_init = {
+        .constraints = {
+                .boot_on        = 1,
+                .always_on      = 1,
+        },
+};
+
+static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
+        {
+                .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
+                .init_data = &pwgtx_init,
+        }, {
+                .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
+                .init_data = &pwgtx_init,
+        },
+};
+
+/* MC13783 */
+static struct mc13783_platform_data mc13783_pdata __initdata = {
+        .regulators = mx31_3ds_regulators,
+        .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
+        .flags  = MC13783_USE_REGULATOR,
+};
+
+/* SPI */
+static int spi1_internal_chipselect[] = {
+        MXC_SPI_CS(0),
+        MXC_SPI_CS(2),
+};
+
+static struct spi_imx_master spi1_pdata = {
+        .chipselect     = spi1_internal_chipselect,
+        .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
+};
+
+static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
+        {
+                .modalias       = "mc13783",
+                .max_speed_hz   = 1000000,
+                .bus_num        = 1,
+                .chip_select    = 1, /* SS2 */
+                .platform_data  = &mc13783_pdata,
+                .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+                .mode = SPI_CS_HIGH,
+        },
+};
+
+/*
+ * NAND Flash
+ */
+static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
+        .width          = 1,
+        .hw_ecc         = 1,
+#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
+        .flash_bbt      = 1,
+#endif
 };
 
 static struct imxuart_platform_data uart_pdata = {
@@ -95,7 +168,7 @@ static struct platform_device smsc911x_device = {
  * LEDs, switches, interrupts for Ethernet.
  */
 
-static void mx31pdk_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
+static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
 {
         uint32_t imr_val;
         uint32_t int_valid;
@@ -163,7 +236,7 @@ static struct irq_chip expio_irq_chip = {
         .unmask = expio_unmask_irq,
 };
 
-static int __init mx31pdk_init_expio(void)
+static int __init mx31_3ds_init_expio(void)
 {
         int i;
         int ret;
@@ -176,7 +249,7 @@ static int __init mx31pdk_init_expio(void)
                 return -ENODEV;
         }
 
-        pr_info("i.MX31PDK Debug board detected, rev = 0x%04X\n",
+        pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
                 __raw_readw(CPLD_CODE_VER_REG));
 
         /*
@@ -201,7 +274,7 @@ static int __init mx31pdk_init_expio(void)
                 set_irq_flags(i, IRQF_VALID);
         }
         set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
-        set_irq_chained_handler(EXPIO_PARENT_INT, mx31pdk_expio_irq_handler);
+        set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
 
         return 0;
 }
@@ -209,7 +282,7 @@ static int __init mx31pdk_init_expio(void)
 /*
  * This structure defines the MX31 memory map.
  */
-static struct map_desc mx31pdk_io_desc[] __initdata = {
+static struct map_desc mx31_3ds_io_desc[] __initdata = {
         {
                 .virtual = MX31_CS5_BASE_ADDR_VIRT,
                 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
@@ -221,10 +294,10 @@ static struct map_desc mx31pdk_io_desc[] __initdata = {
 /*
  * Set up static virtual mappings.
  */
-static void __init mx31pdk_map_io(void)
+static void __init mx31_3ds_map_io(void)
 {
         mx31_map_io();
-        iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc));
+        iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
 }
 
 /*!
@@ -232,35 +305,40 @@ static void __init mx31pdk_map_io(void)
  */
 static void __init mxc_board_init(void)
 {
-        mxc_iomux_setup_multiple_pins(mx31pdk_pins, ARRAY_SIZE(mx31pdk_pins),
-                                      "mx31pdk");
+        mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
+                                      "mx31_3ds");
 
         mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
+
+        mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+        spi_register_board_info(mx31_3ds_spi_devs,
+                                                ARRAY_SIZE(mx31_3ds_spi_devs));
 
-        if (!mx31pdk_init_expio())
+        if (!mx31_3ds_init_expio())
                 platform_device_register(&smsc911x_device);
 }
 
-static void __init mx31pdk_timer_init(void)
+static void __init mx31_3ds_timer_init(void)
 {
         mx31_clocks_init(26000000);
 }
 
-static struct sys_timer mx31pdk_timer = {
-        .init   = mx31pdk_timer_init,
+static struct sys_timer mx31_3ds_timer = {
+        .init   = mx31_3ds_timer_init,
 };
 
 /*
  * The following uses standard kernel macros defined in arch.h in order to
- * initialize __mach_desc_MX31PDK data structure.
+ * initialize __mach_desc_MX31_3DS data structure.
  */
 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
         /* Maintainer: Freescale Semiconductor, Inc. */
         .phys_io        = MX31_AIPS1_BASE_ADDR,
         .io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX3x_PHYS_OFFSET + 0x100,
-        .map_io         = mx31pdk_map_io,
+        .map_io         = mx31_3ds_map_io,
         .init_irq       = mx31_init_irq,
         .init_machine   = mxc_board_init,
-        .timer          = &mx31pdk_timer,
+        .timer          = &mx31_3ds_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index a7dc5191bf5e..fccb9207b78d 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -19,6 +19,7 @@
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/fsl_devices.h>
+#include <linux/gfp.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 11f531559169..2df1ec55a97e 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -35,7 +35,7 @@
 #include <linux/can/platform/sja1000.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
-#include <linux/fsl_devices.h>
+#include <linux/gfp.h>
 
 #include <media/soc_camera.h>
 
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
index ccd874225c3b..093c595ca581 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -28,7 +28,6 @@
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
 #include <linux/leds.h>
 #include <linux/platform_device.h>
 
@@ -206,5 +205,6 @@ void __init mx31lite_db_init(void)
         mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
         mxc_register_device(&mxc_spi_device0, &spi0_pdata);
         platform_device_register(&litekit_led_device);
+        mxc_register_device(&imx_wdt_device0, NULL);
 }
 
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 9fbad2eb3a49..11b906ce7eae 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -20,6 +20,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 #include <linux/types.h>
 
 #include <linux/usb/otg.h>
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 3958515d75bf..ffb105e14d88 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -22,6 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/i2c.h>
 #include <linux/spi/spi.h>
+#include <linux/slab.h>
 #include <linux/platform_device.h>
 #include <linux/types.h>
 
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index be90c03101cd..1ee6ce4087b8 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -16,6 +16,7 @@
 #include <linux/io.h>
 
 #include <asm/clkdev.h>
+#include <asm/div64.h>
 
 #include <mach/hardware.h>
 #include <mach/common.h>
@@ -757,7 +758,7 @@ DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
 
 /* GPT */
 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
-        NULL,  NULL, &ipg_perclk, NULL);
+        NULL,  NULL, &ipg_clk, NULL);
 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
         NULL,  NULL, &ipg_clk, NULL);
 
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 41c769f08c4d..2d37785e3857 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -14,9 +14,62 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/module.h>
 #include <mach/hardware.h>
 #include <asm/io.h>
 
+static int cpu_silicon_rev = -1;
+
+#define SI_REV 0x48
+
+static void query_silicon_parameter(void)
+{
+        void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);
+        u32 rev;
+
+        if (!rom) {
+                cpu_silicon_rev = -EINVAL;
+                return;
+        }
+
+        rev = readl(rom + SI_REV);
+        switch (rev) {
+        case 0x1:
+                cpu_silicon_rev = MX51_CHIP_REV_1_0;
+                break;
+        case 0x2:
+                cpu_silicon_rev = MX51_CHIP_REV_1_1;
+                break;
+        case 0x10:
+                cpu_silicon_rev = MX51_CHIP_REV_2_0;
+                break;
+        case 0x20:
+                cpu_silicon_rev = MX51_CHIP_REV_3_0;
+                break;
+        default:
+                cpu_silicon_rev = 0;
+        }
+
+        iounmap(rom);
+}
+
+/*
+ * Returns:
+ *      the silicon revision of the cpu
+ *      -EINVAL - not a mx51
+ */
+int mx51_revision(void)
+{
+        if (!cpu_is_mx51())
+                return -EINVAL;
+
+        if (cpu_silicon_rev == -1)
+                query_silicon_parameter();
+
+        return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx51_revision);
+
 static int __init post_cpu_init(void)
 {
         unsigned int reg;
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index c21e18be7af8..b7677ef80cc4 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -35,11 +35,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
                 .length = MX51_DEBUG_SIZE,
                 .type = MT_DEVICE
         }, {
-                .virtual = MX51_TZIC_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR),
-                .length = MX51_TZIC_SIZE,
-                .type = MT_DEVICE
-        }, {
                 .virtual = MX51_AIPS1_BASE_ADDR_VIRT,
                 .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),
                 .length = MX51_AIPS1_SIZE,
@@ -54,11 +49,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
                 .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),
                 .length = MX51_AIPS2_SIZE,
                 .type = MT_DEVICE
-        }, {
-                .virtual = MX51_NFC_AXI_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR),
-                .length = MX51_NFC_AXI_SIZE,
-                .type = MT_DEVICE
         },
 };
 
@@ -69,14 +59,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
  */
 void __init mx51_map_io(void)
 {
-        u32 tzic_addr;
-
-        if (mx51_revision() < MX51_CHIP_REV_2_0)
-                tzic_addr = 0x8FFFC000;
-        else
-                tzic_addr = 0xE0003000;
-        mxc_io_desc[2].pfn =  __phys_to_pfn(tzic_addr);
-
         mxc_set_cpu_type(MXC_CPU_MX51);
         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR));
@@ -85,5 +67,17 @@ void __init mx51_map_io(void)
 
 void __init mx51_init_irq(void)
 {
-        tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
+        unsigned long tzic_addr;
+        void __iomem *tzic_virt;
+
+        if (mx51_revision() < MX51_CHIP_REV_2_0)
+                tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
+        else
+                tzic_addr = MX51_TZIC_BASE_ADDR;
+
+        tzic_virt = ioremap(tzic_addr, SZ_16K);
+        if (!tzic_virt)
+                panic("unable to map TZIC interrupt controller\n");
+
+        tzic_init_irq(tzic_virt);
 }
diff --git a/arch/arm/mach-netx/fb.c b/arch/arm/mach-netx/fb.c
index 1d844e228ea9..5b84bcd30271 100644
--- a/arch/arm/mach-netx/fb.c
+++ b/arch/arm/mach-netx/fb.c
@@ -23,6 +23,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 #include <linux/err.h>
+#include <linux/gfp.h>
 
 #include <asm/irq.h>
 
diff --git a/arch/arm/mach-netx/xc.c b/arch/arm/mach-netx/xc.c
index 181a78ba8165..f009b54e8d20 100644
--- a/arch/arm/mach-netx/xc.c
+++ b/arch/arm/mach-netx/xc.c
@@ -21,6 +21,7 @@
 #include <linux/device.h>
 #include <linux/firmware.h>
 #include <linux/mutex.h>
+#include <linux/slab.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-ns9xxx/plat-serial8250.c b/arch/arm/mach-ns9xxx/plat-serial8250.c
index 795b15e8982a..463e92465fda 100644
--- a/arch/arm/mach-ns9xxx/plat-serial8250.c
+++ b/arch/arm/mach-ns9xxx/plat-serial8250.c
@@ -10,6 +10,7 @@
  */
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
+#include <linux/slab.h>
 
 #include <mach/regs-board-a9m9750dev.h>
 #include <mach/board.h>
diff --git a/arch/arm/mach-ns9xxx/processor-ns9360.c b/arch/arm/mach-ns9xxx/processor-ns9360.c
index abee8338735d..aed1999d24fc 100644
--- a/arch/arm/mach-ns9xxx/processor-ns9360.c
+++ b/arch/arm/mach-ns9xxx/processor-ns9360.c
@@ -10,7 +10,6 @@
  */
 #include <linux/io.h>
 #include <linux/kernel.h>
-#include <linux/slab.h>
 
 #include <asm/page.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index f9a5cf750b59..e9bdff192f82 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -16,6 +16,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 
 #include <mach/irqs.h>
 #include <plat/dma.h>
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 9ad118563f7d..20cfbcc6c60c 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -68,12 +68,6 @@ struct sys_timer omap_timer;
  * ---------------------------------------------------------------------------
  */
 
-#if defined(CONFIG_ARCH_OMAP16XX)
-#define TIMER_32K_SYNCHRONIZED          0xfffbc410
-#else
-#error OMAP 32KHz timer does not currently work on 15XX!
-#endif
-
 /* 16xx specific defines */
 #define OMAP1_32K_TIMER_BASE            0xfffb9000
 #define OMAP1_32K_TIMER_CR              0x08
@@ -150,15 +144,6 @@ static struct clock_event_device clockevent_32k_timer = {
         .set_mode       = omap_32k_timer_set_mode,
 };
 
-/*
- * The 32KHz synchronized timer is an additional timer on 16xx.
- * It is always running.
- */
-static inline unsigned long omap_32k_sync_timer_read(void)
-{
-        return omap_readl(TIMER_32K_SYNCHRONIZED);
-}
-
 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
 {
         struct clock_event_device *evt = &clockevent_32k_timer;
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index a8a3d1e23e26..2455dcc744a0 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -59,8 +59,10 @@ config MACH_OMAP3_BEAGLE
         select OMAP_PACKAGE_CBB
 
 config MACH_DEVKIT8000
-        bool "DEVKIT8000 board"
-        depends on ARCH_OMAP3
+        bool "DEVKIT8000 board"
+        depends on ARCH_OMAP3
+        select OMAP_PACKAGE_CUS
+        select OMAP_MUX
 
 config MACH_OMAP_LDP
         bool "OMAP3 LDP board"
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index a0a2a113465c..504d2bd222fe 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -96,6 +96,7 @@ static struct omap_board_mux board_mux[] __initdata = {
 static void __init omap_sdp_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
+        omap_serial_init();
         zoom_peripherals_init();
         board_smc91x_init();
         enable_board_wakeup_source();
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 6ae880585d54..c1c4389fbd8f 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -294,9 +294,9 @@ static struct omap_board_mux board_mux[] __initdata = {
 
 static void __init am3517_evm_init(void)
 {
-        am3517_evm_i2c_init();
-
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+
+        am3517_evm_i2c_init();
         platform_add_devices(am3517_evm_devices,
                                 ARRAY_SIZE(am3517_evm_devices));
 
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 5bfc13b3176c..47e3af2166d4 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -50,7 +50,6 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
-#include <linux/usb/otg.h>
 #include <linux/dm9000.h>
 #include <linux/interrupt.h>
 
@@ -269,20 +268,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
         devkit8000_vmmc1_supply.dev = mmc[0].dev;
         devkit8000_vsim_supply.dev = mmc[0].dev;
 
-        /* REVISIT: need ehci-omap hooks for external VBUS
-         * power switch and overcurrent detect
-         */
-
-        gpio_request(gpio + 1, "EHCI_nOC");
-        gpio_direction_input(gpio + 1);
-
-        /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
-        gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
-        gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1);
-
-        /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
-        gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
-
         return 0;
 }
 
@@ -303,7 +288,7 @@ static struct regulator_consumer_supply devkit8000_vpll2_supplies[] = {
         .dev            = &devkit8000_lcd_device.dev,
         },
         {
-        .supply         = "vdss_dsi",
+        .supply         = "vdds_dsi",
         .dev            = &devkit8000_dss_device.dev,
         }
 };
@@ -639,17 +624,21 @@ static struct omap_musb_board_data musb_board_data = {
 static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 
         .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
         .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
 
         .phy_reset  = true,
         .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = 147,
+        .reset_gpio_port[1]  = -EINVAL,
         .reset_gpio_port[2]  = -EINVAL
 };
 
 static void __init devkit8000_init(void)
 {
+        omap_serial_init();
+
+        omap_dm9000_init();
+
         devkit8000_i2c_init();
         platform_add_devices(devkit8000_devices,
                         ARRAY_SIZE(devkit8000_devices));
@@ -659,25 +648,15 @@ static void __init devkit8000_init(void)
         spi_register_board_info(devkit8000_spi_board_info,
         ARRAY_SIZE(devkit8000_spi_board_info));
 
-        omap_serial_init();
-
-        omap_dm9000_init();
-
         devkit8000_ads7846_init();
 
-        omap_mux_init_gpio(170, OMAP_PIN_INPUT);
-
-        gpio_request(170, "DVI_nPD");
-        /* REVISIT leave DVI powered down until it's needed ... */
-        gpio_direction_output(170, true);
-
         usb_musb_init(&musb_board_data);
         usb_ehci_init(&ehci_pdata);
         devkit8000_flash_init();
 
         /* Ensure SDRC pins are mux'd for self-refresh */
-        omap_mux_init_signal("sdr_cke0", OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sdr_cke1", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 }
 
 static void __init devkit8000_map_io(void)
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 3c7789d45051..d55c57b761a9 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -458,13 +458,13 @@ static struct omap_musb_board_data musb_board_data = {
 };
 
 static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
-        .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
-        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
         .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
 
         .phy_reset = true,
-        .reset_gpio_port[0] = -EINVAL,
-        .reset_gpio_port[1] = IGEP2_GPIO_USBH_NRESET,
+        .reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET,
+        .reset_gpio_port[1] = -EINVAL,
         .reset_gpio_port[2] = -EINVAL,
 };
 
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index da9bcb898991..3ccc34ebdcc7 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -216,7 +216,7 @@ static void __init n8x0_onenand_init(void) {}
  */
 #define N8X0_SLOT_SWITCH_GPIO   96
 #define N810_EMMC_VSD_GPIO      23
-#define NN810_EMMC_VIO_GPIO     9
+#define N810_EMMC_VIO_GPIO      9
 
 static int n8x0_mmc_switch_slot(struct device *dev, int slot)
 {
@@ -304,10 +304,10 @@ static void n810_set_power_emmc(struct device *dev,
         if (power_on) {
                 gpio_set_value(N810_EMMC_VSD_GPIO, 1);
                 msleep(1);
-                gpio_set_value(NN810_EMMC_VIO_GPIO, 1);
+                gpio_set_value(N810_EMMC_VIO_GPIO, 1);
                 msleep(1);
         } else {
-                gpio_set_value(NN810_EMMC_VIO_GPIO, 0);
+                gpio_set_value(N810_EMMC_VIO_GPIO, 0);
                 msleep(50);
                 gpio_set_value(N810_EMMC_VSD_GPIO, 0);
                 msleep(50);
@@ -468,7 +468,7 @@ static void n8x0_mmc_cleanup(struct device *dev)
 
         if (machine_is_nokia_n810()) {
                 gpio_free(N810_EMMC_VSD_GPIO);
-                gpio_free(NN810_EMMC_VIO_GPIO);
+                gpio_free(N810_EMMC_VIO_GPIO);
         }
 }
 
@@ -529,7 +529,7 @@ void __init n8x0_mmc_init(void)
 
         err = gpio_request(N8X0_SLOT_SWITCH_GPIO, "MMC slot switch");
         if (err)
-                return err;
+                return;
 
         gpio_direction_output(N8X0_SLOT_SWITCH_GPIO, 0);
 
@@ -537,17 +537,17 @@ void __init n8x0_mmc_init(void)
                 err = gpio_request(N810_EMMC_VSD_GPIO, "MMC slot 2 Vddf");
                 if (err) {
                         gpio_free(N8X0_SLOT_SWITCH_GPIO);
-                        return err;
+                        return;
                 }
                 gpio_direction_output(N810_EMMC_VSD_GPIO, 0);
 
-                err = gpio_request(NN810_EMMC_VIO_GPIO, "MMC slot 2 Vdd");
+                err = gpio_request(N810_EMMC_VIO_GPIO, "MMC slot 2 Vdd");
                 if (err) {
                         gpio_free(N8X0_SLOT_SWITCH_GPIO);
                         gpio_free(N810_EMMC_VSD_GPIO);
-                        return err;
+                        return;
                 }
-                gpio_direction_output(NN810_EMMC_VIO_GPIO, 0);
+                gpio_direction_output(N810_EMMC_VIO_GPIO, 0);
         }
 
         mmc_data[0] = &mmc1_data;
diff --git a/arch/arm/mach-omap2/board-sdp-flash.c b/arch/arm/mach-omap2/board-sdp-flash.c
index b1b88deec7f2..2d026328e385 100644
--- a/arch/arm/mach-omap2/board-sdp-flash.c
+++ b/arch/arm/mach-omap2/board-sdp-flash.c
@@ -253,20 +253,20 @@ void __init sdp_flash_init(struct flash_partitions sdp_partition_info[])
         }
 
         if (norcs > GPMC_CS_NUM)
-                printk(KERN_INFO "OneNAND: Unable to find configuration "
-                                " in GPMC\n ");
+                printk(KERN_INFO "NOR: Unable to find configuration "
+                                "in GPMC\n");
         else
                 board_nor_init(sdp_partition_info[0], norcs);
 
         if (onenandcs > GPMC_CS_NUM)
                 printk(KERN_INFO "OneNAND: Unable to find configuration "
-                                " in GPMC\n ");
+                                "in GPMC\n");
         else
                 board_onenand_init(sdp_partition_info[1], onenandcs);
 
         if (nandcs > GPMC_CS_NUM)
                 printk(KERN_INFO "NAND: Unable to find configuration "
-                                " in GPMC\n ");
+                                "in GPMC\n");
         else
                 board_nand_init(sdp_partition_info[2], nandcs);
 }
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index bb4018b60642..e15d2e87cfc1 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -96,7 +96,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
 
 static struct platform_device zoom_debugboard_serial_device = {
         .name                   = "serial8250",
-        .id                     = 3,
+        .id                     = PLAT8250_DEV_PLATFORM,
         .dev                    = {
                 .platform_data  = serial_platform_data,
         },
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index ca95d8d64136..6b3984964cc5 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -280,7 +280,6 @@ static void enable_board_wakeup_source(void)
 void __init zoom_peripherals_init(void)
 {
         omap_i2c_init();
-        omap_serial_init();
         usb_musb_init(&musb_board_data);
         enable_board_wakeup_source();
 }
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 3b1eac4d5390..e60ca4e47bbd 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -31,6 +31,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/cpufreq.h>
+#include <linux/slab.h>
 
 #include <plat/clock.h>
 #include <plat/sram.h>
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index d5153b6bd6cb..9cba5560519b 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -895,7 +895,7 @@ static struct clk dpll4_m4x2_ck = {
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &dpll4_m4_ck,
         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
+        .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
         .flags          = INVERT_ENABLE,
         .clkdm_name     = "dpll4_clkdm",
         .recalc         = &omap3_clkoutx2_recalc,
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 28b107967c86..a5c0c9c8e496 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -2671,10 +2671,10 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.4",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap-mcspi.1",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap-mcspi.2",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap-mcspi.3",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap-mcspi.4",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.1",    "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.2",    "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.3",    "ick",                  &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.4",    "ick",                  &dummy_ck,      CK_443X),
         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index b87ad66f083e..6e568ec995ee 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -240,7 +240,7 @@ static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
                         bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
                 else
                         bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
-        } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) {
+        } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
                 if (enable)
                         bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
                 else
@@ -812,7 +812,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
                 cm_set_mod_reg_bits(OMAP24XX_FORCESTATE,
                             clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
 
-        } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) {
+        } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 
                 u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP <<
                          __ffs(clkdm->clktrctrl_mask));
@@ -856,7 +856,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
                 cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE,
                               clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
 
-        } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) {
+        } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 
                 u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP <<
                          __ffs(clkdm->clktrctrl_mask));
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 4a1c2328bcc3..12154d10e536 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -759,7 +759,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
                         if (!cpu_is_omap44xx())
                                 return;
                         base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
-                        irq = OMAP44XX_IRQ_MMC4;
+                        irq = OMAP44XX_IRQ_MMC5;
                         break;
                 default:
                         continue;
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 64d74f05abbe..e57fb29ff855 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -39,6 +39,9 @@ static int omap2_nand_gpmc_retime(void)
         struct gpmc_timings t;
         int err;
 
+        if (!gpmc_nand_data->gpmc_t)
+                return 0;
+
         memset(&t, 0, sizeof(t));
         t.sync_clk = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->sync_clk);
         t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on);
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index ff25c7e4e606..50fd74916643 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -52,7 +52,7 @@ omap_irq_base:	.word	0
 
                 mrc     p15, 0, \tmp, c0, c0, 0 @ get processor revision
                 and     \tmp, \tmp, #0x000f0000 @ only check architecture
-                cmp     \tmp, #0x00060000       @ is v6?
+                cmp     \tmp, #0x00070000       @ is v6?
                 beq     2400f                   @ found v6 so it's omap24xx
                 mrc     p15, 0, \tmp, c0, c0, 0 @ get processor revision
                 and     \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 6f4b7cc8f4d1..4f63dc6859a4 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -15,6 +15,7 @@
 #include <linux/device.h>
 #include <linux/jiffies.h>
 #include <linux/module.h>
+#include <linux/slab.h>
 #include <linux/stringify.h>
 
 #include <plat/iommu.h>
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index be8fce395a58..2f3cad6f9402 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -16,6 +16,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 
 #include <mach/irqs.h>
 #include <plat/dma.h>
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index b4ca84ee0a95..8b3d26935a39 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -26,6 +26,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/list.h>
 #include <linux/ctype.h>
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index aa3f65c2ac97..ef0e7a00dd6c 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -33,7 +33,7 @@
 ENTRY(omap_secondary_startup)
 hold:   ldr     r12,=0x103
         dsb
-        smc                             @ read from AuxCoreBoot0
+        smc     #0                      @ read from AuxCoreBoot0
         mov     r0, r0, lsr #9
         mrc     p15, 0, r4, c0, c0, 5
         and     r4, r4, #0x0f
@@ -52,7 +52,7 @@ ENTRY(omap_modify_auxcoreboot0)
         stmfd   sp!, {r1-r12, lr}
         ldr     r12, =0x104
         dsb
-        smc
+        smc     #0
         ldmfd   sp!, {r1-r12, pc}
 END(omap_modify_auxcoreboot0)
 
@@ -60,6 +60,6 @@ ENTRY(omap_auxcoreboot_addr)
         stmfd   sp!, {r2-r12, lr}
         ldr     r12, =0x105
         dsb
-        smc
+        smc     #0
         ldmfd   sp!, {r2-r12, pc}
 END(omap_auxcoreboot_addr)
diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S
index 89bb2b141473..f61c7771ca47 100644
--- a/arch/arm/mach-omap2/omap44xx-smc.S
+++ b/arch/arm/mach-omap2/omap44xx-smc.S
@@ -27,6 +27,6 @@ ENTRY(omap_smc1)
         mov     r12, r0
         mov     r0, r1
         dsb
-        smc
+        smc     #0
         ldmfd   sp!, {r2-r12, pc}
 END(omap_smc1)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index aa3e20915d72..2c12e8cd7183 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1510,6 +1510,9 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
                 c = oh->slaves[oh->_mpu_port_index]->_clk;
         }
 
+        if (!c->clkdm)
+                return NULL;
+
         return c->clkdm->pwrdm.ptr;
 
 }
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index c18f7f2f19bc..6cac9817c243 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -25,6 +25,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/slab.h>
 
 #include <plat/clock.h>
 #include <plat/board.h>
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fee2efb172e7..ea0000bc5358 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -27,6 +27,7 @@
 #include <linux/gpio.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/slab.h>
 
 #include <plat/sram.h>
 #include <plat/clockdomain.h>
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 9a0fb385622b..ebfce7d1a5d3 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -222,7 +222,7 @@ void pwrdm_init(struct powerdomain **pwrdm_list)
 {
         struct powerdomain **p = NULL;
 
-        if (cpu_is_omap24xx() | cpu_is_omap34xx()) {
+        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
                 pwrstctrl_reg_offs = OMAP2_PM_PWSTCTRL;
                 pwrstst_reg_offs = OMAP2_PM_PWSTST;
         } else if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 9537f6f2352d..07a60f1204ca 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -123,7 +123,7 @@ struct omap3_prcm_regs prcm_context;
 u32 omap_prcm_get_reset_sources(void)
 {
         /* XXX This presumably needs modification for 34XX */
-        if (cpu_is_omap24xx() | cpu_is_omap34xx())
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
                 return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
         if (cpu_is_omap44xx())
                 return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
@@ -157,7 +157,7 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
         else
                 WARN_ON(1);
 
-        if (cpu_is_omap24xx() | cpu_is_omap34xx())
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
                 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
                                                  OMAP2_RM_RSTCTRL);
         if (cpu_is_omap44xx())
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index da77930480e9..3771254dfa81 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -115,7 +115,6 @@ static struct plat_serial8250_port serial_platform_data2[] = {
         }
 };
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 static struct plat_serial8250_port serial_platform_data3[] = {
         {
                 .irq            = 70,
@@ -128,23 +127,12 @@ static struct plat_serial8250_port serial_platform_data3[] = {
         }
 };
 
-static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals)
-{
-        serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
-}
-#else
-static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals)
-{
-}
-#endif
-
 void __init omap2_set_globals_uart(struct omap_globals *omap2_globals)
 {
         serial_platform_data0[0].mapbase = omap2_globals->uart1_phys;
         serial_platform_data1[0].mapbase = omap2_globals->uart2_phys;
         serial_platform_data2[0].mapbase = omap2_globals->uart3_phys;
-        if (cpu_is_omap3630() || cpu_is_omap44xx())
-                omap2_set_globals_uart4(omap2_globals);
+        serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
 }
 
 static inline unsigned int __serial_read_reg(struct uart_port *up,
@@ -550,7 +538,7 @@ static ssize_t sleep_timeout_store(struct device *dev,
         unsigned int value;
 
         if (sscanf(buf, "%u", &value) != 1) {
-                printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
+                dev_err(dev, "sleep_timeout_store: Invalid value\n");
                 return -EINVAL;
         }
 
@@ -664,27 +652,33 @@ void __init omap_serial_early_init(void)
                 struct device *dev = &pdev->dev;
                 struct plat_serial8250_port *p = dev->platform_data;
 
+                /* Don't map zero-based physical address */
+                if (p->mapbase == 0) {
+                        dev_warn(dev, "no physical address for uart#%d,"
+                                 " so skipping early_init...\n", i);
+                        continue;
+                }
                 /*
                  * Module 4KB + L4 interconnect 4KB
                  * Static mapping, never released
                  */
                 p->membase = ioremap(p->mapbase, SZ_8K);
                 if (!p->membase) {
-                        printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
+                        dev_err(dev, "ioremap failed for uart%i\n", i + 1);
                         continue;
                 }
 
                 sprintf(name, "uart%d_ick", i + 1);
                 uart->ick = clk_get(NULL, name);
                 if (IS_ERR(uart->ick)) {
-                        printk(KERN_ERR "Could not get uart%d_ick\n", i + 1);
+                        dev_err(dev, "Could not get uart%d_ick\n", i + 1);
                         uart->ick = NULL;
                 }
 
                 sprintf(name, "uart%d_fck", i+1);
                 uart->fck = clk_get(NULL, name);
                 if (IS_ERR(uart->fck)) {
-                        printk(KERN_ERR "Could not get uart%d_fck\n", i + 1);
+                        dev_err(dev, "Could not get uart%d_fck\n", i + 1);
                         uart->fck = NULL;
                 }
 
@@ -727,6 +721,13 @@ void __init omap_serial_init_port(int port)
         pdev = &uart->pdev;
         dev = &pdev->dev;
 
+        /* Don't proceed if there's no clocks available */
+        if (unlikely(!uart->ick || !uart->fck)) {
+                WARN(1, "%s: can't init uart%d, no clocks available\n",
+                     kobject_name(&dev->kobj), port);
+                return;
+        }
+
         omap_uart_enable_clocks(uart);
 
         omap_uart_reset(uart);
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 421b82f7c63d..685f34a9634b 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -439,6 +439,7 @@ static void __init dns323_init(void)
          */
         if (dns323_dev_id() == MV88F5181_DEV_ID) {
                 dns323_leds[0].active_low = 1;
+                gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
                 gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
         }
 
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index bdf96eb523bc..e8706f15a670 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -12,6 +12,7 @@
 
 #include <linux/kernel.h>
 #include <linux/pci.h>
+#include <linux/slab.h>
 #include <linux/mbus.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index cb0feca193d4..f9f222ebb7ed 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -77,7 +77,7 @@ static struct gpio_keys_button wrt350n_v2_buttons[] = {
                 .desc           = "Reset Button",
                 .active_low     = 1,
         }, {
-                .code           = KEY_WLAN,
+                .code           = KEY_WPS_BUTTON,
                 .gpio           = 2,
                 .desc           = "WPS Button",
                 .active_low     = 1,
diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c
index 425f7188505e..7fa4bf2e2125 100644
--- a/arch/arm/mach-pnx4008/dma.c
+++ b/arch/arm/mach-pnx4008/dma.c
@@ -22,6 +22,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/gfp.h>
 
 #include <asm/system.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-pnx4008/pm.c b/arch/arm/mach-pnx4008/pm.c
index 1f0585329be4..ee3c29c57ae3 100644
--- a/arch/arm/mach-pnx4008/pm.c
+++ b/arch/arm/mach-pnx4008/pm.c
@@ -19,6 +19,7 @@
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 
 #include <asm/cacheflush.h>
 
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 38fbd0a0e402..3b51741a4810 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -19,7 +19,6 @@ config MACH_MAINSTONE
 config MACH_ZYLONITE
         bool
         select PXA3xx
-        select PXA_SSP
         select HAVE_PWM
         select PXA_HAVE_BOARD_IRQS
 
@@ -39,7 +38,6 @@ config MACH_LITTLETON
         select PXA3xx
         select CPU_PXA300
         select CPU_PXA310
-        select PXA_SSP
 
 config MACH_TAVOREVB
         bool "PXA930 Evaluation Board (aka TavorEVB)"
@@ -98,7 +96,6 @@ config MACH_ARMCORE
         select PXA27x
         select IWMMXT
         select PXA25x
-        select PXA_SSP
 
 config MACH_EM_X270
         bool "CompuLab EM-x270 platform"
@@ -161,7 +158,6 @@ config MACH_XCEP
         select MTD_CFI
         select MTD_CHAR
         select SMC91X
-        select PXA_SSP
         help
           PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash.
           Tuned for usage in Libera instruments for particle accelerators.
@@ -180,7 +176,6 @@ config MACH_TRIZEPS4WL
         depends on TRIZEPS_PXA
         select TRIZEPS_PCMCIA
         select PXA27x
-        select PXA_SSP
 
 choice
         prompt "Select base board for Trizeps module"
@@ -217,7 +212,6 @@ config MACH_PCM027
         bool "Phytec phyCORE-PXA270 CPU module (PCM-027)"
         select PXA27x
         select IWMMXT
-        select PXA_SSP
         select PXA_HAVE_BOARD_IRQS
 
 config MACH_PCM990_BASEBOARD
@@ -255,13 +249,19 @@ config MACH_COLIBRI320
         select PXA3xx
         select CPU_PXA320
 
+config MACH_VPAC270
+        bool "Voipac PXA270"
+        select PXA27x
+        select HAVE_PATA_PLATFORM
+        help
+          PXA270 based Single Board Computer.
+
 comment "End-user Products (sorted by vendor name)"
 
 config MACH_H4700
         bool "HP iPAQ hx4700"
         select PXA27x
         select IWMMXT
-        select PXA_SSP
         select HAVE_PWM
         select PXA_HAVE_BOARD_IRQS
 
@@ -272,13 +272,11 @@ config MACH_H5000
 config MACH_HIMALAYA
         bool "HTC Himalaya Support"
         select CPU_PXA26x
-        select FB_W100
 
 config MACH_MAGICIAN
         bool "Enable HTC Magician Support"
         select PXA27x
         select IWMMXT
-        select PXA_SSP
         select HAVE_PWM
         select PXA_HAVE_BOARD_IRQS
 
@@ -432,13 +430,11 @@ config MACH_RAUMFELD_CONNECTOR
         bool "Raumfeld Connector"
         select PXA3xx
         select CPU_PXA300
-        select PXA_SSP
 
 config MACH_RAUMFELD_SPEAKER
         bool "Raumfeld Speaker"
         select PXA3xx
         select CPU_PXA300
-        select PXA_SSP
 
 config PXA_SHARPSL
         bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models"
@@ -454,22 +450,19 @@ config PXA_SHARPSL
 config SHARPSL_PM
         bool
         select APM_EMULATION
+        select SHARPSL_PM_MAX1111
 
-config CORGI_SSP_DEPRECATED
+config SHARPSL_PM_MAX1111
         bool
-        select PXA_SSP
-        select PXA_SSP_LEGACY
-        help
-          This option will include corgi_ssp.c and corgi_lcd.c
-          that corgi_ts.c and other legacy drivers (corgi_bl.c
-          and sharpsl_pm.c) may depend on.
+        depends on !CORGI_SSP_DEPRECATED
+        select HWMON
+        select SENSORS_MAX1111
 
 config MACH_POODLE
         bool "Enable Sharp SL-5600 (Poodle) Support"
         depends on PXA_SHARPSL
         select PXA25x
         select SHARP_LOCOMO
-        select PXA_SSP
         select PXA_HAVE_BOARD_IRQS
 
 config MACH_CORGI
@@ -547,7 +540,6 @@ config MACH_E740
         bool "Toshiba e740"
         default y
         depends on ARCH_PXA_ESERIES
-        select FB_W100
         help
           Say Y here if you intend to run this kernel on a Toshiba
           e740 family PDA.
@@ -556,7 +548,6 @@ config MACH_E750
         bool "Toshiba e750"
         default y
         depends on ARCH_PXA_ESERIES
-        select FB_W100
         help
           Say Y here if you intend to run this kernel on a Toshiba
           e750 family PDA.
@@ -573,11 +564,16 @@ config MACH_E800
         bool "Toshiba e800"
         default y
         depends on ARCH_PXA_ESERIES
-        select FB_W100
         help
           Say Y here if you intend to run this kernel on a Toshiba
           e800 family PDA.
 
+config MACH_ZIPIT2
+        bool "Zipit Z2 Handheld"
+        select PXA27x
+        select HAVE_PWM
+        select PXA_HAVE_BOARD_IRQS
+
 endmenu
 
 config PXA25x
@@ -642,28 +638,16 @@ config CPU_PXA950
 
 config PXA_SHARP_C7xx
         bool
-        select PXA_SSP
         select SHARPSL_PM
         help
           Enable support for all Sharp C7xx models
 
 config PXA_SHARP_Cxx00
         bool
-        select PXA_SSP
         select SHARPSL_PM
         help
           Enable common support for Sharp Cxx00 models
 
-config PXA_SSP
-        tristate
-        help
-          Enable support for PXA2xx SSP ports
-
-config PXA_SSP_LEGACY
-        bool
-        help
-          Support of legacy SSP API
-
 config TOSA_BT
         tristate "Control the state of built-in bluetooth chip on Sharp SL-6000"
         depends on MACH_TOSA
@@ -672,6 +656,18 @@ config TOSA_BT
           This is a simple driver that is able to control
           the state of built in bluetooth chip on tosa.
 
+config TOSA_USE_EXT_KEYCODES
+        bool "Tosa keyboard: use extended keycodes"
+        depends on MACH_TOSA
+        default n
+        help
+          Say Y here to enable the tosa keyboard driver to generate extended
+          (>= 127) keycodes. Be aware, that they can't be correctly interpreted
+          by either console keyboard driver or by Kdrive keybd driver.
+
+          Say Y only if you know, what you are doing!
+
+
 config PXA_HAVE_BOARD_IRQS
         bool
 
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 86bc87b7f2dd..b8f1f4bc7ca7 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_PXA3xx)		+= cpufreq-pxa3xx.o
 endif
 
 # Generic drivers that other drivers may depend upon
-obj-$(CONFIG_PXA_SSP)           += ssp.o
 
 # SoC-specific code
 obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o pxa2xx.o pxa25x.o
@@ -62,6 +61,7 @@ obj-$(CONFIG_MACH_PCM990_BASEBOARD)	+= pcm990-baseboard.o
 obj-$(CONFIG_MACH_COLIBRI)      += colibri-pxa270.o
 obj-$(CONFIG_MACH_COLIBRI300)   += colibri-pxa3xx.o colibri-pxa300.o
 obj-$(CONFIG_MACH_COLIBRI320)   += colibri-pxa3xx.o colibri-pxa320.o
+obj-$(CONFIG_MACH_VPAC270)      += vpac270.o
 
 # End-user Products
 obj-$(CONFIG_MACH_H4700)        += hx4700.o
@@ -80,7 +80,6 @@ obj-$(CONFIG_MACH_PALMLD)	+= palmld.o
 obj-$(CONFIG_PALM_TREO)         += palmtreo.o
 obj-$(CONFIG_PXA_SHARP_C7xx)    += corgi.o sharpsl_pm.o corgi_pm.o
 obj-$(CONFIG_PXA_SHARP_Cxx00)   += spitz.o sharpsl_pm.o spitz_pm.o
-obj-$(CONFIG_CORGI_SSP_DEPRECATED)      += corgi_ssp.o corgi_lcd.o
 obj-$(CONFIG_MACH_POODLE)       += poodle.o
 obj-$(CONFIG_MACH_TOSA)         += tosa.o
 obj-$(CONFIG_MACH_ICONTROL)     += icontrol.o mxm8x10.o
@@ -94,6 +93,7 @@ obj-$(CONFIG_MACH_E800)		+= e800.o
 obj-$(CONFIG_MACH_RAUMFELD_RC)          += raumfeld.o
 obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR)   += raumfeld.o
 obj-$(CONFIG_MACH_RAUMFELD_SPEAKER)     += raumfeld.o
+obj-$(CONFIG_MACH_ZIPIT2)       += z2.o
 
 # Support for blinky lights
 led-y := leds.o
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index d37cfa132a65..fdda6be6c391 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -30,6 +30,9 @@
 #include <linux/i2c/pca953x.h>
 
 #include <linux/mfd/da903x.h>
+#include <linux/regulator/machine.h>
+#include <linux/power_supply.h>
+#include <linux/apm-emulation.h>
 
 #include <linux/spi/spi.h>
 #include <linux/spi/spi_gpio.h>
@@ -430,7 +433,7 @@ static inline void cm_x300_init_nand(void) {}
 
 #if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
 static struct pxamci_platform_data cm_x300_mci_platform_data = {
-        .detect_delay           = 20,
+        .detect_delay_ms        = 200,
         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
         .gpio_card_detect       = GPIO82_MMC_IRQ,
         .gpio_card_ro           = GPIO85_MMC_WP,
@@ -451,7 +454,7 @@ static void cm_x300_mci2_exit(struct device *dev, void *data)
 }
 
 static struct pxamci_platform_data cm_x300_mci2_platform_data = {
-        .detect_delay           = 20,
+        .detect_delay_ms        = 200,
         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
         .init                   = cm_x300_mci2_init,
         .exit                   = cm_x300_mci2_exit,
@@ -584,12 +587,87 @@ static void __init cm_x300_init_rtc(void)
 static inline void cm_x300_init_rtc(void) {}
 #endif
 
+/* Battery */
+struct power_supply_info cm_x300_psy_info = {
+        .name = "battery",
+        .technology = POWER_SUPPLY_TECHNOLOGY_LIPO,
+        .voltage_max_design = 4200000,
+        .voltage_min_design = 3000000,
+        .use_for_apm = 1,
+};
+
+static void cm_x300_battery_low(void)
+{
+#if defined(CONFIG_APM_EMULATION)
+        apm_queue_event(APM_LOW_BATTERY);
+#endif
+}
+
+static void cm_x300_battery_critical(void)
+{
+#if defined(CONFIG_APM_EMULATION)
+        apm_queue_event(APM_CRITICAL_SUSPEND);
+#endif
+}
+
+struct da9030_battery_info cm_x300_battery_info = {
+        .battery_info = &cm_x300_psy_info,
+
+        .charge_milliamp = 1000,
+        .charge_millivolt = 4200,
+
+        .vbat_low = 3600,
+        .vbat_crit = 3400,
+        .vbat_charge_start = 4100,
+        .vbat_charge_stop = 4200,
+        .vbat_charge_restart = 4000,
+
+        .vcharge_min = 3200,
+        .vcharge_max = 5500,
+
+        .tbat_low = 197,
+        .tbat_high = 78,
+        .tbat_restart = 100,
+
+        .batmon_interval = 0,
+
+        .battery_low = cm_x300_battery_low,
+        .battery_critical = cm_x300_battery_critical,
+};
+
+static struct regulator_consumer_supply buck2_consumers[] = {
+        {
+                .dev = NULL,
+                .supply = "vcc_core",
+        },
+};
+
+static struct regulator_init_data buck2_data = {
+        .constraints = {
+                .min_uV = 1375000,
+                .max_uV = 1375000,
+                .state_mem = {
+                        .enabled = 0,
+                },
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .apply_uV = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(buck2_consumers),
+        .consumer_supplies = buck2_consumers,
+};
+
 /* DA9030 */
 struct da903x_subdev_info cm_x300_da9030_subdevs[] = {
         {
-                .name = "da903x-backlight",
-                .id = DA9030_ID_WLED,
-        }
+                .name = "da903x-battery",
+                .id = DA9030_ID_BAT,
+                .platform_data = &cm_x300_battery_info,
+        },
+        {
+                .name = "da903x-regulator",
+                .id = DA9030_ID_BUCK2,
+                .platform_data = &buck2_data,
+        },
 };
 
 static struct da903x_platform_data cm_x300_da9030_info = {
@@ -599,7 +677,7 @@ static struct da903x_platform_data cm_x300_da9030_info = {
 
 static struct i2c_board_info cm_x300_pmic_info = {
         I2C_BOARD_INFO("da9030", 0x49),
-        .irq = IRQ_GPIO(0),
+        .irq = IRQ_WAKEUP0,
         .platform_data = &cm_x300_da9030_info,
 };
 
@@ -689,13 +767,13 @@ static void __init cm_x300_init(void)
 static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags,
                                  char **cmdline, struct meminfo *mi)
 {
-        mi->nr_banks = 2;
-        mi->bank[0].start = 0xa0000000;
-        mi->bank[0].node = 0;
-        mi->bank[0].size = (64*1024*1024);
-        mi->bank[1].start = 0xc0000000;
-        mi->bank[1].node = 0;
-        mi->bank[1].size = (64*1024*1024);
+        /* Make sure that mi->bank[0].start = PHYS_ADDR */
+        for (; tags->hdr.size; tags = tag_next(tags))
+                if (tags->hdr.tag == ATAG_MEM &&
+                        tags->u.mem.start == 0x80000000) {
+                        tags->u.mem.start = 0xa0000000;
+                        break;
+                }
 }
 
 MACHINE_START(CM_X300, "CM-X300 module")
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
index e6c0a2287eb8..199afa2ae303 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -96,7 +96,7 @@ static void colibri_pxa3xx_mci_exit(struct device *dev, void *data)
 }
 
 static struct pxamci_platform_data colibri_pxa3xx_mci_platform_data = {
-        .detect_delay           = 20,
+        .detect_delay_ms        = 200,
         .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
         .init                   = colibri_pxa3xx_mci_init,
         .exit                   = colibri_pxa3xx_mci_exit,
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index da3156d8690b..3d1dcb9ac08f 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -106,18 +106,18 @@ static unsigned long corgi_pin_config[] __initdata = {
         GPIO8_MMC_CS0,
 
         /* GPIO Matrix Keypad */
-        GPIO66_GPIO,    /* column 0 */
-        GPIO67_GPIO,    /* column 1 */
-        GPIO68_GPIO,    /* column 2 */
-        GPIO69_GPIO,    /* column 3 */
-        GPIO70_GPIO,    /* column 4 */
-        GPIO71_GPIO,    /* column 5 */
-        GPIO72_GPIO,    /* column 6 */
-        GPIO73_GPIO,    /* column 7 */
-        GPIO74_GPIO,    /* column 8 */
-        GPIO75_GPIO,    /* column 9 */
-        GPIO76_GPIO,    /* column 10 */
-        GPIO77_GPIO,    /* column 11 */
+        GPIO66_GPIO | MFP_LPM_DRIVE_HIGH,       /* column 0 */
+        GPIO67_GPIO | MFP_LPM_DRIVE_HIGH,       /* column 1 */
+        GPIO68_GPIO | MFP_LPM_DRIVE_HIGH,       /* column 2 */
+        GPIO69_GPIO | MFP_LPM_DRIVE_HIGH,       /* column 3 */
+        GPIO70_GPIO | MFP_LPM_DRIVE_HIGH,       /* column 4 */
+        GPIO71_GPIO | MFP_LPM_DRIVE_HIGH,       /* column 5 */
+        GPIO72_GPIO | MFP_LPM_DRIVE_HIGH,       /* column 6 */
+        GPIO73_GPIO | MFP_LPM_DRIVE_HIGH,       /* column 7 */
+        GPIO74_GPIO | MFP_LPM_DRIVE_HIGH,       /* column 8 */
+        GPIO75_GPIO | MFP_LPM_DRIVE_HIGH,       /* column 9 */
+        GPIO76_GPIO | MFP_LPM_DRIVE_HIGH,       /* column 10 */
+        GPIO77_GPIO | MFP_LPM_DRIVE_HIGH,       /* column 11 */
         GPIO58_GPIO,    /* row 0 */
         GPIO59_GPIO,    /* row 1 */
         GPIO60_GPIO,    /* row 2 */
@@ -128,13 +128,20 @@ static unsigned long corgi_pin_config[] __initdata = {
         GPIO65_GPIO,    /* row 7 */
 
         /* GPIO */
-        GPIO9_GPIO,     /* CORGI_GPIO_nSD_DETECT */
-        GPIO7_GPIO,     /* CORGI_GPIO_nSD_WP */
-        GPIO33_GPIO,    /* CORGI_GPIO_SD_PWR */
-        GPIO22_GPIO,    /* CORGI_GPIO_IR_ON */
-        GPIO44_GPIO,    /* CORGI_GPIO_HSYNC */
-
-        GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
+        GPIO9_GPIO,                             /* CORGI_GPIO_nSD_DETECT */
+        GPIO7_GPIO,                             /* CORGI_GPIO_nSD_WP */
+        GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH,      /* CORGI_GPIO_MAIN_BAT_{LOW,COVER} */
+        GPIO13_GPIO | MFP_LPM_KEEP_OUTPUT,      /* CORGI_GPIO_LED_ORANGE */
+        GPIO21_GPIO,                            /* CORGI_GPIO_ADC_TEMP */
+        GPIO22_GPIO,                            /* CORGI_GPIO_IR_ON */
+        GPIO33_GPIO,                            /* CORGI_GPIO_SD_PWR */
+        GPIO38_GPIO | MFP_LPM_KEEP_OUTPUT,      /* CORGI_GPIO_CHRG_ON */
+        GPIO43_GPIO | MFP_LPM_KEEP_OUTPUT,      /* CORGI_GPIO_CHRG_UKN */
+        GPIO44_GPIO,                            /* CORGI_GPIO_HSYNC */
+
+        GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH,       /* CORGI_GPIO_KEY_INT */
+        GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,       /* CORGI_GPIO_AC_IN */
+        GPIO3_GPIO | WAKEUP_ON_EDGE_BOTH,       /* CORGI_GPIO_WAKEUP */
 };
 
 /*
@@ -437,6 +444,7 @@ static struct platform_device corgiled_device = {
  * to give the card a chance to fully insert/eject.
  */
 static struct pxamci_platform_data corgi_mci_platform_data = {
+        .detect_delay_ms        = 250,
         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
         .gpio_card_detect       = -1,
         .gpio_card_ro           = CORGI_GPIO_nSD_WP,
@@ -672,6 +680,15 @@ static void __init corgi_init(void)
 
         pxa2xx_mfp_config(ARRAY_AND_SIZE(corgi_pin_config));
 
+        /* allow wakeup from various GPIOs */
+        gpio_set_wake(CORGI_GPIO_KEY_INT, 1);
+        gpio_set_wake(CORGI_GPIO_WAKEUP, 1);
+        gpio_set_wake(CORGI_GPIO_AC_IN, 1);
+        gpio_set_wake(CORGI_GPIO_CHRG_FULL, 1);
+
+        if (!machine_is_corgi())
+                gpio_set_wake(CORGI_GPIO_MAIN_BAT_LOW, 1);
+
         pxa_set_ffuart_info(NULL);
         pxa_set_btuart_info(NULL);
         pxa_set_stuart_info(NULL);
@@ -679,7 +696,6 @@ static void __init corgi_init(void)
         corgi_init_spi();
 
         pxa_set_udc_info(&udc_info);
-        corgi_mci_platform_data.detect_delay = msecs_to_jiffies(250);
         pxa_set_mci_info(&corgi_mci_platform_data);
         pxa_set_ficp_info(&corgi_ficp_platform_data);
         pxa_set_i2c_info(NULL);
diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c
deleted file mode 100644
index d9b96319d498..000000000000
--- a/arch/arm/mach-pxa/corgi_lcd.c
+++ /dev/null
@@ -1,288 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/corgi_lcd.c
- *
- * Corgi/Spitz LCD Specific Code
- *
- * Copyright (C) 2005 Richard Purdie
- *
- * Connectivity:
- *   Corgi - LCD to ATI Imageon w100 (Wallaby)
- *   Spitz - LCD to PXA Framebuffer
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <mach/corgi.h>
-#include <mach/hardware.h>
-#include <mach/sharpsl.h>
-#include <mach/spitz.h>
-#include <asm/hardware/scoop.h>
-#include <asm/mach/sharpsl_param.h>
-#include "generic.h"
-
-/* Register Addresses */
-#define RESCTL_ADRS     0x00
-#define PHACTRL_ADRS    0x01
-#define DUTYCTRL_ADRS   0x02
-#define POWERREG0_ADRS  0x03
-#define POWERREG1_ADRS  0x04
-#define GPOR3_ADRS      0x05
-#define PICTRL_ADRS     0x06
-#define POLCTRL_ADRS    0x07
-
-/* Register Bit Definitions */
-#define RESCTL_QVGA     0x01
-#define RESCTL_VGA      0x00
-
-#define POWER1_VW_ON    0x01  /* VW Supply FET ON */
-#define POWER1_GVSS_ON  0x02  /* GVSS(-8V) Power Supply ON */
-#define POWER1_VDD_ON   0x04  /* VDD(8V),SVSS(-4V) Power Supply ON */
-
-#define POWER1_VW_OFF   0x00  /* VW Supply FET OFF */
-#define POWER1_GVSS_OFF 0x00  /* GVSS(-8V) Power Supply OFF */
-#define POWER1_VDD_OFF  0x00  /* VDD(8V),SVSS(-4V) Power Supply OFF */
-
-#define POWER0_COM_DCLK 0x01  /* COM Voltage DC Bias DAC Serial Data Clock */
-#define POWER0_COM_DOUT 0x02  /* COM Voltage DC Bias DAC Serial Data Out */
-#define POWER0_DAC_ON   0x04  /* DAC Power Supply ON */
-#define POWER0_COM_ON   0x08  /* COM Power Supply ON */
-#define POWER0_VCC5_ON  0x10  /* VCC5 Power Supply ON */
-
-#define POWER0_DAC_OFF  0x00  /* DAC Power Supply OFF */
-#define POWER0_COM_OFF  0x00  /* COM Power Supply OFF */
-#define POWER0_VCC5_OFF 0x00  /* VCC5 Power Supply OFF */
-
-#define PICTRL_INIT_STATE      0x01
-#define PICTRL_INIOFF          0x02
-#define PICTRL_POWER_DOWN      0x04
-#define PICTRL_COM_SIGNAL_OFF  0x08
-#define PICTRL_DAC_SIGNAL_OFF  0x10
-
-#define POLCTRL_SYNC_POL_FALL  0x01
-#define POLCTRL_EN_POL_FALL    0x02
-#define POLCTRL_DATA_POL_FALL  0x04
-#define POLCTRL_SYNC_ACT_H     0x08
-#define POLCTRL_EN_ACT_L       0x10
-
-#define POLCTRL_SYNC_POL_RISE  0x00
-#define POLCTRL_EN_POL_RISE    0x00
-#define POLCTRL_DATA_POL_RISE  0x00
-#define POLCTRL_SYNC_ACT_L     0x00
-#define POLCTRL_EN_ACT_H       0x00
-
-#define PHACTRL_PHASE_MANUAL   0x01
-#define DEFAULT_PHAD_QVGA     (9)
-#define DEFAULT_COMADJ        (125)
-
-/*
- * This is only a psuedo I2C interface. We can't use the standard kernel
- * routines as the interface is write only. We just assume the data is acked...
- */
-static void lcdtg_ssp_i2c_send(u8 data)
-{
-        corgi_ssp_lcdtg_send(POWERREG0_ADRS, data);
-        udelay(10);
-}
-
-static void lcdtg_i2c_send_bit(u8 data)
-{
-        lcdtg_ssp_i2c_send(data);
-        lcdtg_ssp_i2c_send(data | POWER0_COM_DCLK);
-        lcdtg_ssp_i2c_send(data);
-}
-
-static void lcdtg_i2c_send_start(u8 base)
-{
-        lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
-        lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
-        lcdtg_ssp_i2c_send(base);
-}
-
-static void lcdtg_i2c_send_stop(u8 base)
-{
-        lcdtg_ssp_i2c_send(base);
-        lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
-        lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
-}
-
-static void lcdtg_i2c_send_byte(u8 base, u8 data)
-{
-        int i;
-        for (i = 0; i < 8; i++) {
-                if (data & 0x80)
-                        lcdtg_i2c_send_bit(base | POWER0_COM_DOUT);
-                else
-                        lcdtg_i2c_send_bit(base);
-                data <<= 1;
-        }
-}
-
-static void lcdtg_i2c_wait_ack(u8 base)
-{
-        lcdtg_i2c_send_bit(base);
-}
-
-static void lcdtg_set_common_voltage(u8 base_data, u8 data)
-{
-        /* Set Common Voltage to M62332FP via I2C */
-        lcdtg_i2c_send_start(base_data);
-        lcdtg_i2c_send_byte(base_data, 0x9c);
-        lcdtg_i2c_wait_ack(base_data);
-        lcdtg_i2c_send_byte(base_data, 0x00);
-        lcdtg_i2c_wait_ack(base_data);
-        lcdtg_i2c_send_byte(base_data, data);
-        lcdtg_i2c_wait_ack(base_data);
-        lcdtg_i2c_send_stop(base_data);
-}
-
-/* Set Phase Adjust */
-static void lcdtg_set_phadadj(int mode)
-{
-        int adj;
-        switch(mode) {
-                case 480:
-                case 640:
-                        /* Setting for VGA */
-                        adj = sharpsl_param.phadadj;
-                        if (adj < 0) {
-                                adj = PHACTRL_PHASE_MANUAL;
-                        } else {
-                                adj = ((adj & 0x0f) << 1) | PHACTRL_PHASE_MANUAL;
-                        }
-                        break;
-                case 240:
-                case 320:
-                default:
-                        /* Setting for QVGA */
-                        adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL;
-                        break;
-        }
-
-        corgi_ssp_lcdtg_send(PHACTRL_ADRS, adj);
-}
-
-static int lcd_inited;
-
-void corgi_lcdtg_hw_init(int mode)
-{
-        if (!lcd_inited) {
-                int comadj;
-
-                /* Initialize Internal Logic & Port */
-                corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE
-                                | PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF);
-
-                corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF
-                                | POWER0_COM_OFF | POWER0_VCC5_OFF);
-
-                corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
-
-                /* VDD(+8V), SVSS(-4V) ON */
-                corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
-                mdelay(3);
-
-                /* DAC ON */
-                corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
-                                | POWER0_COM_OFF | POWER0_VCC5_OFF);
-
-                /* INIB = H, INI = L  */
-                /* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */
-                corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF);
-
-                /* Set Common Voltage */
-                comadj = sharpsl_param.comadj;
-                if (comadj < 0)
-                        comadj = DEFAULT_COMADJ;
-                lcdtg_set_common_voltage((POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF), comadj);
-
-                /* VCC5 ON, DAC ON */
-                corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON |
-                                POWER0_COM_OFF | POWER0_VCC5_ON);
-
-                /* GVSS(-8V) ON, VDD ON */
-                corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
-                mdelay(2);
-
-                /* COM SIGNAL ON (PICTL[3] = L) */
-                corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE);
-
-                /* COM ON, DAC ON, VCC5_ON */
-                corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
-                                | POWER0_COM_ON | POWER0_VCC5_ON);
-
-                /* VW ON, GVSS ON, VDD ON */
-                corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON);
-
-                /* Signals output enable */
-                corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
-
-                /* Set Phase Adjust */
-                lcdtg_set_phadadj(mode);
-
-                /* Initialize for Input Signals from ATI */
-                corgi_ssp_lcdtg_send(POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE
-                                | POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H);
-                udelay(1000);
-
-                lcd_inited=1;
-        } else {
-                lcdtg_set_phadadj(mode);
-        }
-
-        switch(mode) {
-                case 480:
-                case 640:
-                        /* Set Lcd Resolution (VGA) */
-                        corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_VGA);
-                        break;
-                case 240:
-                case 320:
-                default:
-                        /* Set Lcd Resolution (QVGA) */
-                        corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_QVGA);
-                        break;
-        }
-}
-
-void corgi_lcdtg_suspend(void)
-{
-        /* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */
-        mdelay(34);
-
-        /* (1)VW OFF */
-        corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
-
-        /* (2)COM OFF */
-        corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF);
-        corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON);
-
-        /* (3)Set Common Voltage Bias 0V */
-        lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON, 0);
-
-        /* (4)GVSS OFF */
-        corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
-
-        /* (5)VCC5 OFF */
-        corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF);
-
-        /* (6)Set PDWN, INIOFF, DACOFF */
-        corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF |
-                        PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF);
-
-        /* (7)DAC OFF */
-        corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF);
-
-        /* (8)VDD OFF */
-        corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
-
-        lcd_inited = 0;
-}
-
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index d4a0733e905b..3f1dc74ac048 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/delay.h>
+#include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/apm-emulation.h>
@@ -25,7 +26,8 @@
 #include <mach/sharpsl.h>
 #include <mach/corgi.h>
 #include <mach/pxa2xx-regs.h>
-#include <mach/pxa2xx-gpio.h>
+
+#include "generic.h"
 #include "sharpsl.h"
 
 #define SHARPSL_CHARGE_ON_VOLT         0x99  /* 2.9V */
@@ -35,87 +37,46 @@
 #define SHARPSL_FATAL_ACIN_VOLT        182   /* 3.45V */
 #define SHARPSL_FATAL_NOACIN_VOLT      170   /* 3.40V */
 
+static struct gpio charger_gpios[] = {
+        { CORGI_GPIO_ADC_TEMP_ON, GPIOF_OUT_INIT_LOW, "ADC Temp On" },
+        { CORGI_GPIO_CHRG_ON,     GPIOF_OUT_INIT_LOW, "Charger On" },
+        { CORGI_GPIO_CHRG_UKN,    GPIOF_OUT_INIT_LOW, "Charger Unknown" },
+        { CORGI_GPIO_KEY_INT,     GPIOF_IN, "Key Interrupt" },
+};
+
 static void corgi_charger_init(void)
 {
-        pxa_gpio_mode(CORGI_GPIO_ADC_TEMP_ON | GPIO_OUT);
-        pxa_gpio_mode(CORGI_GPIO_CHRG_ON | GPIO_OUT);
-        pxa_gpio_mode(CORGI_GPIO_CHRG_UKN | GPIO_OUT);
-        pxa_gpio_mode(CORGI_GPIO_KEY_INT | GPIO_IN);
+        gpio_request_array(ARRAY_AND_SIZE(charger_gpios));
 }
 
 static void corgi_measure_temp(int on)
 {
-        if (on)
-                GPSR(CORGI_GPIO_ADC_TEMP_ON) = GPIO_bit(CORGI_GPIO_ADC_TEMP_ON);
-        else
-                GPCR(CORGI_GPIO_ADC_TEMP_ON) = GPIO_bit(CORGI_GPIO_ADC_TEMP_ON);
+        gpio_set_value(CORGI_GPIO_ADC_TEMP_ON, on);
 }
 
 static void corgi_charge(int on)
 {
         if (on) {
                 if (machine_is_corgi() && (sharpsl_pm.flags & SHARPSL_SUSPENDED)) {
-                        GPCR(CORGI_GPIO_CHRG_ON) = GPIO_bit(CORGI_GPIO_CHRG_ON);
-                        GPSR(CORGI_GPIO_CHRG_UKN) = GPIO_bit(CORGI_GPIO_CHRG_UKN);
+                        gpio_set_value(CORGI_GPIO_CHRG_ON, 0);
+                        gpio_set_value(CORGI_GPIO_CHRG_UKN, 1);
                 } else {
-                        GPSR(CORGI_GPIO_CHRG_ON) = GPIO_bit(CORGI_GPIO_CHRG_ON);
-                        GPCR(CORGI_GPIO_CHRG_UKN) = GPIO_bit(CORGI_GPIO_CHRG_UKN);
+                        gpio_set_value(CORGI_GPIO_CHRG_ON, 1);
+                        gpio_set_value(CORGI_GPIO_CHRG_UKN, 0);
                 }
         } else {
-                GPCR(CORGI_GPIO_CHRG_ON) = GPIO_bit(CORGI_GPIO_CHRG_ON);
-                GPCR(CORGI_GPIO_CHRG_UKN) = GPIO_bit(CORGI_GPIO_CHRG_UKN);
+                gpio_set_value(CORGI_GPIO_CHRG_ON, 0);
+                gpio_set_value(CORGI_GPIO_CHRG_UKN, 0);
         }
 }
 
 static void corgi_discharge(int on)
 {
-        if (on)
-                GPSR(CORGI_GPIO_DISCHARGE_ON) = GPIO_bit(CORGI_GPIO_DISCHARGE_ON);
-        else
-                GPCR(CORGI_GPIO_DISCHARGE_ON) = GPIO_bit(CORGI_GPIO_DISCHARGE_ON);
+        gpio_set_value(CORGI_GPIO_DISCHARGE_ON, on);
 }
 
 static void corgi_presuspend(void)
 {
-        int i;
-        unsigned long wakeup_mask;
-
-        /* charging , so CHARGE_ON bit is HIGH during OFF. */
-        if (READ_GPIO_BIT(CORGI_GPIO_CHRG_ON))
-                PGSR1 |= GPIO_bit(CORGI_GPIO_CHRG_ON);
-        else
-                PGSR1 &= ~GPIO_bit(CORGI_GPIO_CHRG_ON);
-
-        if (READ_GPIO_BIT(CORGI_GPIO_LED_ORANGE))
-                PGSR0 |= GPIO_bit(CORGI_GPIO_LED_ORANGE);
-        else
-                PGSR0 &= ~GPIO_bit(CORGI_GPIO_LED_ORANGE);
-
-        if (READ_GPIO_BIT(CORGI_GPIO_CHRG_UKN))
-                PGSR1 |= GPIO_bit(CORGI_GPIO_CHRG_UKN);
-        else
-                PGSR1 &= ~GPIO_bit(CORGI_GPIO_CHRG_UKN);
-
-        /* Resume on keyboard power key */
-        PGSR2 = (PGSR2 & ~CORGI_GPIO_ALL_STROBE_BIT) | CORGI_GPIO_STROBE_BIT(0);
-
-        wakeup_mask = GPIO_bit(CORGI_GPIO_KEY_INT) | GPIO_bit(CORGI_GPIO_WAKEUP) | GPIO_bit(CORGI_GPIO_AC_IN) | GPIO_bit(CORGI_GPIO_CHRG_FULL);
-
-        if (!machine_is_corgi())
-                wakeup_mask |= GPIO_bit(CORGI_GPIO_MAIN_BAT_LOW);
-
-        PWER = wakeup_mask | PWER_RTC;
-        PRER = wakeup_mask;
-        PFER = wakeup_mask;
-
-        for (i = 0; i <=15; i++) {
-                if (PRER & PFER & GPIO_bit(i)) {
-                        if (GPLR0 & GPIO_bit(i) )
-                                PRER &= ~GPIO_bit(i);
-                        else
-                                PFER &= ~GPIO_bit(i);
-                }
-        }
 }
 
 static void corgi_postsuspend(void)
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c
deleted file mode 100644
index 1d9bc118ee32..000000000000
--- a/arch/arm/mach-pxa/corgi_ssp.c
+++ /dev/null
@@ -1,275 +0,0 @@
-/*
- *  SSP control code for Sharp Corgi devices
- *
- *  Copyright (c) 2004-2005 Richard Purdie
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- *
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-
-#include <mach/ssp.h>
-#include <mach/pxa2xx-gpio.h>
-#include <mach/regs-ssp.h>
-#include "sharpsl.h"
-
-static DEFINE_SPINLOCK(corgi_ssp_lock);
-static struct ssp_dev corgi_ssp_dev;
-static struct ssp_state corgi_ssp_state;
-static struct corgissp_machinfo *ssp_machinfo;
-
-/*
- * There are three devices connected to the SSP interface:
- *   1. A touchscreen controller (TI ADS7846 compatible)
- *   2. An LCD controller (with some Backlight functionality)
- *   3. A battery monitoring IC (Maxim MAX1111)
- *
- * Each device uses a different speed/mode of communication.
- *
- * The touchscreen is very sensitive and the most frequently used
- * so the port is left configured for this.
- *
- * Devices are selected using Chip Selects on GPIOs.
- */
-
-/*
- *  ADS7846 Routines
- */
-unsigned long corgi_ssp_ads7846_putget(ulong data)
-{
-        unsigned long flag;
-        u32 ret = 0;
-
-        spin_lock_irqsave(&corgi_ssp_lock, flag);
-        if (ssp_machinfo->cs_ads7846 >= 0)
-                GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
-
-        ssp_write_word(&corgi_ssp_dev,data);
-        ssp_read_word(&corgi_ssp_dev, &ret);
-
-        if (ssp_machinfo->cs_ads7846 >= 0)
-                GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
-        spin_unlock_irqrestore(&corgi_ssp_lock, flag);
-
-        return ret;
-}
-
-/*
- * NOTE: These functions should always be called in interrupt context
- * and use the _lock and _unlock functions. They are very time sensitive.
- */
-void corgi_ssp_ads7846_lock(void)
-{
-        spin_lock(&corgi_ssp_lock);
-        if (ssp_machinfo->cs_ads7846 >= 0)
-                GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
-}
-
-void corgi_ssp_ads7846_unlock(void)
-{
-        if (ssp_machinfo->cs_ads7846 >= 0)
-                GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
-        spin_unlock(&corgi_ssp_lock);
-}
-
-void corgi_ssp_ads7846_put(ulong data)
-{
-        ssp_write_word(&corgi_ssp_dev,data);
-}
-
-unsigned long corgi_ssp_ads7846_get(void)
-{
-        u32 ret = 0;
-        ssp_read_word(&corgi_ssp_dev, &ret);
-        return ret;
-}
-
-EXPORT_SYMBOL(corgi_ssp_ads7846_putget);
-EXPORT_SYMBOL(corgi_ssp_ads7846_lock);
-EXPORT_SYMBOL(corgi_ssp_ads7846_unlock);
-EXPORT_SYMBOL(corgi_ssp_ads7846_put);
-EXPORT_SYMBOL(corgi_ssp_ads7846_get);
-
-
-/*
- *  LCD/Backlight Routines
- */
-unsigned long corgi_ssp_dac_put(ulong data)
-{
-        unsigned long flag, sscr1 = SSCR1_SPH;
-        u32 tmp;
-
-        spin_lock_irqsave(&corgi_ssp_lock, flag);
-
-        if (machine_is_spitz() || machine_is_akita() || machine_is_borzoi())
-                sscr1 = 0;
-
-        ssp_disable(&corgi_ssp_dev);
-        ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), sscr1, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_lcdcon));
-        ssp_enable(&corgi_ssp_dev);
-
-        if (ssp_machinfo->cs_lcdcon >= 0)
-                GPCR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
-        ssp_write_word(&corgi_ssp_dev,data);
-        /* Read null data back from device to prevent SSP overflow */
-        ssp_read_word(&corgi_ssp_dev, &tmp);
-        if (ssp_machinfo->cs_lcdcon >= 0)
-                GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
-
-        ssp_disable(&corgi_ssp_dev);
-        ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
-        ssp_enable(&corgi_ssp_dev);
-
-        spin_unlock_irqrestore(&corgi_ssp_lock, flag);
-
-        return 0;
-}
-
-void corgi_ssp_lcdtg_send(u8 adrs, u8 data)
-{
-        corgi_ssp_dac_put(((adrs & 0x07) << 5) | (data & 0x1f));
-}
-
-void corgi_ssp_blduty_set(int duty)
-{
-        corgi_ssp_lcdtg_send(0x02,duty);
-}
-
-EXPORT_SYMBOL(corgi_ssp_lcdtg_send);
-EXPORT_SYMBOL(corgi_ssp_blduty_set);
-
-/*
- *  Max1111 Routines
- */
-int corgi_ssp_max1111_get(ulong data)
-{
-        unsigned long flag;
-        long voltage = 0, voltage1 = 0, voltage2 = 0;
-
-        spin_lock_irqsave(&corgi_ssp_lock, flag);
-        if (ssp_machinfo->cs_max1111 >= 0)
-                GPCR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
-        ssp_disable(&corgi_ssp_dev);
-        ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_max1111));
-        ssp_enable(&corgi_ssp_dev);
-
-        udelay(1);
-
-        /* TB1/RB1 */
-        ssp_write_word(&corgi_ssp_dev,data);
-        ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1); /* null read */
-
-        /* TB12/RB2 */
-        ssp_write_word(&corgi_ssp_dev,0);
-        ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1);
-
-        /* TB13/RB3*/
-        ssp_write_word(&corgi_ssp_dev,0);
-        ssp_read_word(&corgi_ssp_dev, (u32*)&voltage2);
-
-        ssp_disable(&corgi_ssp_dev);
-        ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
-        ssp_enable(&corgi_ssp_dev);
-        if (ssp_machinfo->cs_max1111 >= 0)
-                GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
-        spin_unlock_irqrestore(&corgi_ssp_lock, flag);
-
-        if (voltage1 & 0xc0 || voltage2 & 0x3f)
-                voltage = -1;
-        else
-                voltage = ((voltage1 << 2) & 0xfc) | ((voltage2 >> 6) & 0x03);
-
-        return voltage;
-}
-
-EXPORT_SYMBOL(corgi_ssp_max1111_get);
-
-/*
- *  Support Routines
- */
-
-void __init corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo)
-{
-        ssp_machinfo = machinfo;
-}
-
-static int __devinit corgi_ssp_probe(struct platform_device *dev)
-{
-        int ret;
-
-        /* Chip Select - Disable All */
-        if (ssp_machinfo->cs_lcdcon >= 0)
-                pxa_gpio_mode(ssp_machinfo->cs_lcdcon  | GPIO_OUT | GPIO_DFLT_HIGH);
-        if (ssp_machinfo->cs_max1111 >= 0)
-                pxa_gpio_mode(ssp_machinfo->cs_max1111 | GPIO_OUT | GPIO_DFLT_HIGH);
-        if (ssp_machinfo->cs_ads7846 >= 0)
-                pxa_gpio_mode(ssp_machinfo->cs_ads7846 | GPIO_OUT | GPIO_DFLT_HIGH);
-
-        ret = ssp_init(&corgi_ssp_dev, ssp_machinfo->port, 0);
-
-        if (ret)
-                printk(KERN_ERR "Unable to register SSP handler!\n");
-        else {
-                ssp_disable(&corgi_ssp_dev);
-                ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
-                ssp_enable(&corgi_ssp_dev);
-        }
-
-        return ret;
-}
-
-static int corgi_ssp_remove(struct platform_device *dev)
-{
-        ssp_exit(&corgi_ssp_dev);
-        return 0;
-}
-
-static int corgi_ssp_suspend(struct platform_device *dev, pm_message_t state)
-{
-        ssp_flush(&corgi_ssp_dev);
-        ssp_save_state(&corgi_ssp_dev,&corgi_ssp_state);
-
-        return 0;
-}
-
-static int corgi_ssp_resume(struct platform_device *dev)
-{
-        if (ssp_machinfo->cs_lcdcon >= 0)
-                GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);  /* High - Disable LCD Control/Timing Gen */
-        if (ssp_machinfo->cs_max1111 >= 0)
-                GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111); /* High - Disable MAX1111*/
-        if (ssp_machinfo->cs_ads7846 >= 0)
-                GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); /* High - Disable ADS7846*/
-        ssp_restore_state(&corgi_ssp_dev,&corgi_ssp_state);
-        ssp_enable(&corgi_ssp_dev);
-
-        return 0;
-}
-
-static struct platform_driver corgissp_driver = {
-        .probe          = corgi_ssp_probe,
-        .remove         = corgi_ssp_remove,
-        .suspend        = corgi_ssp_suspend,
-        .resume         = corgi_ssp_resume,
-        .driver         = {
-                .name   = "corgi-ssp",
-        },
-};
-
-int __init corgi_ssp_init(void)
-{
-        return platform_driver_register(&corgissp_driver);
-}
-
-arch_initcall(corgi_ssp_init);
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
index 149cdd9aee4d..27fa329d9a8b 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
@@ -14,6 +14,7 @@
 #include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/cpufreq.h>
+#include <linux/slab.h>
 
 #include <mach/pxa3xx-regs.h>
 
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index 88575b87bd33..91fd4fea6a54 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -125,18 +125,9 @@ static unsigned long csb726_pin_config[] = {
         GPIO118_I2C_SDA,
 };
 
-static struct pxamci_platform_data csb726_mci_data;
-
-static int csb726_mci_init(struct device *dev,
-                irq_handler_t detect, void *data)
-{
-        csb726_mci_data.detect_delay = msecs_to_jiffies(500);
-        return 0;
-}
-
 static struct pxamci_platform_data csb726_mci = {
+        .detect_delay_ms        = 500,
         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
-        .init                   = csb726_mci_init,
         /* FIXME setpower */
         .gpio_card_detect       = CSB726_GPIO_MMC_DETECT,
         .gpio_card_ro           = CSB726_GPIO_MMC_RO,
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index aab04f33e49b..0517c17978f3 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -626,6 +626,7 @@ static int em_x270_mci_get_ro(struct device *dev)
 }
 
 static struct pxamci_platform_data em_x270_mci_platform_data = {
+        .detect_delay_ms        = 250,
         .ocr_mask               = MMC_VDD_20_21|MMC_VDD_21_22|MMC_VDD_22_23|
                                   MMC_VDD_24_25|MMC_VDD_25_26|MMC_VDD_26_27|
                                   MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
@@ -643,7 +644,6 @@ static void __init em_x270_init_mmc(void)
         if (machine_is_em_x270())
                 em_x270_mci_platform_data.get_ro = em_x270_mci_get_ro;
 
-        em_x270_mci_platform_data.detect_delay  = msecs_to_jiffies(250);
         pxa_set_mci_info(&em_x270_mci_platform_data);
 }
 #else
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 3126a35aa002..baabb3ce088e 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -28,7 +28,6 @@
 
 #include <mach/reset.h>
 #include <mach/gpio.h>
-#include <mach/pxa2xx-gpio.h>
 
 #include "generic.h"
 
@@ -128,33 +127,3 @@ void __init pxa_map_io(void)
         iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
         get_clk_frequency_khz(1);
 }
-
-/*
- * Configure pins for GPIO or other functions
- */
-int pxa_gpio_mode(int gpio_mode)
-{
-        unsigned long flags;
-        int gpio = gpio_mode & GPIO_MD_MASK_NR;
-        int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
-        int gafr;
-
-        if (gpio > pxa_last_gpio)
-                return -EINVAL;
-
-        local_irq_save(flags);
-        if (gpio_mode & GPIO_DFLT_LOW)
-                GPCR(gpio) = GPIO_bit(gpio);
-        else if (gpio_mode & GPIO_DFLT_HIGH)
-                GPSR(gpio) = GPIO_bit(gpio);
-        if (gpio_mode & GPIO_MD_MASK_DIR)
-                GPDR(gpio) |= GPIO_bit(gpio);
-        else
-                GPDR(gpio) &= ~GPIO_bit(gpio);
-        gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
-        GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
-        local_irq_restore(flags);
-
-        return 0;
-}
-EXPORT_SYMBOL(pxa_gpio_mode);
diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c
index b2f878bd460b..5161dca8ccc0 100644
--- a/arch/arm/mach-pxa/imote2.c
+++ b/arch/arm/mach-pxa/imote2.c
@@ -559,10 +559,6 @@ static void __init imote2_init(void)
         pxa_set_btuart_info(NULL);
         pxa_set_stuart_info(NULL);
 
-        /* SPI chip select directions - all other directions should
-         * be handled by drivers.*/
-        gpio_direction_output(37, 0);
-
         platform_add_devices(imote2_devices, ARRAY_SIZE(imote2_devices));
 
         pxa2xx_set_spi_info(1, &pxa_ssp_master_0_info);
diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h
index 811743c56147..5f2ba8d9015c 100644
--- a/arch/arm/mach-pxa/include/mach/colibri.h
+++ b/arch/arm/mach-pxa/include/mach/colibri.h
@@ -2,6 +2,7 @@
 #define _COLIBRI_H_
 
 #include <net/ax88796.h>
+#include <mach/mfp.h>
 
 /*
  * common settings for all modules
diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h
index 7239281788de..585970ef08ce 100644
--- a/arch/arm/mach-pxa/include/mach/corgi.h
+++ b/arch/arm/mach-pxa/include/mach/corgi.h
@@ -113,7 +113,6 @@
  * Shared data structures
  */
 extern struct platform_device corgiscoop_device;
-extern struct platform_device corgissp_device;
 
 #endif /* __ASM_ARCH_CORGI_H  */
 
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 7515757d6911..3d8d8cb09685 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -202,7 +202,7 @@
 #define __cpu_is_pxa950(id)                             \
         ({                                              \
                 unsigned int _id = (id) >> 4 & 0xfff;   \
-                id == 0x697;                            \
+                _id == 0x697;                           \
          })
 #else
 #define __cpu_is_pxa950(id)     (0)
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
index 658b28ed129b..c54cef25895c 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
@@ -25,6 +25,8 @@
 #define MFP_DIR(x)              (((x) >> 23) & 0x1)
 
 #define MFP_LPM_CAN_WAKEUP      (0x1 << 24)
+#define MFP_LPM_KEEP_OUTPUT     (0x1 << 25)
+
 #define WAKEUP_ON_EDGE_RISE     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
 #define WAKEUP_ON_EDGE_FALL     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL)
 #define WAKEUP_ON_EDGE_BOTH     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH)
diff --git a/arch/arm/mach-pxa/include/mach/mmc.h b/arch/arm/mach-pxa/include/mach/mmc.h
index 02a69dc2ee63..9eb515bb799d 100644
--- a/arch/arm/mach-pxa/include/mach/mmc.h
+++ b/arch/arm/mach-pxa/include/mach/mmc.h
@@ -9,7 +9,7 @@ struct mmc_host;
 
 struct pxamci_platform_data {
         unsigned int ocr_mask;                  /* available voltages */
-        unsigned long detect_delay;             /* delay in jiffies before detecting cards after interrupt */
+        unsigned long detect_delay_ms;          /* delay in millisecond before detecting cards after interrupt */
         int (*init)(struct device *, irq_handler_t , void *);
         int (*get_ro)(struct device *);
         void (*setpower)(struct device *, unsigned int);
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
deleted file mode 100644
index 1209c44aa6f1..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
+++ /dev/null
@@ -1,375 +0,0 @@
-#ifndef __ASM_ARCH_PXA2XX_GPIO_H
-#define __ASM_ARCH_PXA2XX_GPIO_H
-
-#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h
-
-#include <mach/gpio.h>
-
-/* GPIO alternate function assignments */
-
-#define GPIO1_RST               1       /* reset */
-#define GPIO6_MMCCLK            6       /* MMC Clock */
-#define GPIO7_48MHz             7       /* 48 MHz clock output */
-#define GPIO8_MMCCS0            8       /* MMC Chip Select 0 */
-#define GPIO9_MMCCS1            9       /* MMC Chip Select 1 */
-#define GPIO10_RTCCLK           10      /* real time clock (1 Hz) */
-#define GPIO11_3_6MHz           11      /* 3.6 MHz oscillator out */
-#define GPIO12_32KHz            12      /* 32 kHz out */
-#define GPIO12_CIF_DD_7         12      /* Camera data pin 7 */
-#define GPIO13_MBGNT            13      /* memory controller grant */
-#define GPIO14_MBREQ            14      /* alternate bus master request */
-#define GPIO15_nCS_1            15      /* chip select 1 */
-#define GPIO16_PWM0             16      /* PWM0 output */
-#define GPIO17_PWM1             17      /* PWM1 output */
-#define GPIO17_CIF_DD_6         17      /* Camera data pin 6 */
-#define GPIO18_RDY              18      /* Ext. Bus Ready */
-#define GPIO19_DREQ1            19      /* External DMA Request */
-#define GPIO20_DREQ0            20      /* External DMA Request */
-#define GPIO23_SCLK             23      /* SSP clock */
-#define GPIO23_CIF_MCLK         23      /* Camera Master Clock */
-#define GPIO24_SFRM             24      /* SSP Frame */
-#define GPIO24_CIF_FV           24      /* Camera frame start signal */
-#define GPIO25_STXD             25      /* SSP transmit */
-#define GPIO25_CIF_LV           25      /* Camera line start signal */
-#define GPIO26_SRXD             26      /* SSP receive */
-#define GPIO26_CIF_PCLK         26      /* Camera Pixel Clock */
-#define GPIO27_SEXTCLK          27      /* SSP ext_clk */
-#define GPIO27_CIF_DD_0         27      /* Camera data pin 0 */
-#define GPIO28_BITCLK           28      /* AC97/I2S bit_clk */
-#define GPIO29_SDATA_IN         29      /* AC97 Sdata_in0 / I2S Sdata_in */
-#define GPIO30_SDATA_OUT        30      /* AC97/I2S Sdata_out */
-#define GPIO31_SYNC             31      /* AC97/I2S sync */
-#define GPIO32_SDATA_IN1        32      /* AC97 Sdata_in1 */
-#define GPIO32_SYSCLK           32      /* I2S System Clock */
-#define GPIO32_MMCCLK           32      /* MMC Clock (PXA270) */
-#define GPIO33_nCS_5            33      /* chip select 5 */
-#define GPIO34_FFRXD            34      /* FFUART receive */
-#define GPIO34_MMCCS0           34      /* MMC Chip Select 0 */
-#define GPIO35_FFCTS            35      /* FFUART Clear to send */
-#define GPIO36_FFDCD            36      /* FFUART Data carrier detect */
-#define GPIO37_FFDSR            37      /* FFUART data set ready */
-#define GPIO38_FFRI             38      /* FFUART Ring Indicator */
-#define GPIO39_MMCCS1           39      /* MMC Chip Select 1 */
-#define GPIO39_FFTXD            39      /* FFUART transmit data */
-#define GPIO40_FFDTR            40      /* FFUART data terminal Ready */
-#define GPIO41_FFRTS            41      /* FFUART request to send */
-#define GPIO42_BTRXD            42      /* BTUART receive data */
-#define GPIO42_HWRXD            42      /* HWUART receive data */
-#define GPIO42_CIF_MCLK         42      /* Camera Master Clock */
-#define GPIO43_BTTXD            43      /* BTUART transmit data */
-#define GPIO43_HWTXD            43      /* HWUART transmit data */
-#define GPIO43_CIF_FV           43      /* Camera frame start signal */
-#define GPIO44_BTCTS            44      /* BTUART clear to send */
-#define GPIO44_HWCTS            44      /* HWUART clear to send */
-#define GPIO44_CIF_LV           44      /* Camera line start signal */
-#define GPIO45_BTRTS            45      /* BTUART request to send */
-#define GPIO45_HWRTS            45      /* HWUART request to send */
-#define GPIO45_AC97_SYSCLK      45      /* AC97 System Clock */
-#define GPIO45_CIF_PCLK         45      /* Camera Pixel Clock */
-#define GPIO46_ICPRXD           46      /* ICP receive data */
-#define GPIO46_STRXD            46      /* STD_UART receive data */
-#define GPIO47_ICPTXD           47      /* ICP transmit data */
-#define GPIO47_STTXD            47      /* STD_UART transmit data */
-#define GPIO47_CIF_DD_0         47      /* Camera data pin 0 */
-#define GPIO48_nPOE             48      /* Output Enable for Card Space */
-#define GPIO48_CIF_DD_5         48      /* Camera data pin 5 */
-#define GPIO49_nPWE             49      /* Write Enable for Card Space */
-#define GPIO50_nPIOR            50      /* I/O Read for Card Space */
-#define GPIO50_CIF_DD_3         50      /* Camera data pin 3 */
-#define GPIO51_nPIOW            51      /* I/O Write for Card Space */
-#define GPIO51_CIF_DD_2         51      /* Camera data pin 2 */
-#define GPIO52_nPCE_1           52      /* Card Enable for Card Space */
-#define GPIO52_CIF_DD_4         52      /* Camera data pin 4 */
-#define GPIO53_nPCE_2           53      /* Card Enable for Card Space */
-#define GPIO53_MMCCLK           53      /* MMC Clock */
-#define GPIO53_CIF_MCLK         53      /* Camera Master Clock */
-#define GPIO54_MMCCLK           54      /* MMC Clock */
-#define GPIO54_pSKTSEL          54      /* Socket Select for Card Space */
-#define GPIO54_nPCE_2           54      /* Card Enable for Card Space (PXA27x) */
-#define GPIO54_CIF_PCLK         54      /* Camera Pixel Clock */
-#define GPIO55_nPREG            55      /* Card Address bit 26 */
-#define GPIO55_CIF_DD_1         55      /* Camera data pin 1 */
-#define GPIO56_nPWAIT           56      /* Wait signal for Card Space */
-#define GPIO57_nIOIS16          57      /* Bus Width select for I/O Card Space */
-#define GPIO58_LDD_0            58      /* LCD data pin 0 */
-#define GPIO59_LDD_1            59      /* LCD data pin 1 */
-#define GPIO60_LDD_2            60      /* LCD data pin 2 */
-#define GPIO61_LDD_3            61      /* LCD data pin 3 */
-#define GPIO62_LDD_4            62      /* LCD data pin 4 */
-#define GPIO63_LDD_5            63      /* LCD data pin 5 */
-#define GPIO64_LDD_6            64      /* LCD data pin 6 */
-#define GPIO65_LDD_7            65      /* LCD data pin 7 */
-#define GPIO66_LDD_8            66      /* LCD data pin 8 */
-#define GPIO66_MBREQ            66      /* alternate bus master req */
-#define GPIO67_LDD_9            67      /* LCD data pin 9 */
-#define GPIO67_MMCCS0           67      /* MMC Chip Select 0 */
-#define GPIO68_LDD_10           68      /* LCD data pin 10 */
-#define GPIO68_MMCCS1           68      /* MMC Chip Select 1 */
-#define GPIO69_LDD_11           69      /* LCD data pin 11 */
-#define GPIO69_MMCCLK           69      /* MMC_CLK */
-#define GPIO70_LDD_12           70      /* LCD data pin 12 */
-#define GPIO70_RTCCLK           70      /* Real Time clock (1 Hz) */
-#define GPIO71_LDD_13           71      /* LCD data pin 13 */
-#define GPIO71_3_6MHz           71      /* 3.6 MHz Oscillator clock */
-#define GPIO72_LDD_14           72      /* LCD data pin 14 */
-#define GPIO72_32kHz            72      /* 32 kHz clock */
-#define GPIO73_LDD_15           73      /* LCD data pin 15 */
-#define GPIO73_MBGNT            73      /* Memory controller grant */
-#define GPIO74_LCD_FCLK         74      /* LCD Frame clock */
-#define GPIO75_LCD_LCLK         75      /* LCD line clock */
-#define GPIO76_LCD_PCLK         76      /* LCD Pixel clock */
-#define GPIO77_LCD_ACBIAS       77      /* LCD AC Bias */
-#define GPIO78_nCS_2            78      /* chip select 2 */
-#define GPIO79_nCS_3            79      /* chip select 3 */
-#define GPIO80_nCS_4            80      /* chip select 4 */
-#define GPIO81_NSCLK            81      /* NSSP clock */
-#define GPIO81_CIF_DD_0         81      /* Camera data pin 0 */
-#define GPIO82_NSFRM            82      /* NSSP Frame */
-#define GPIO82_CIF_DD_5         82      /* Camera data pin 5 */
-#define GPIO83_NSTXD            83      /* NSSP transmit */
-#define GPIO83_CIF_DD_4         83      /* Camera data pin 4 */
-#define GPIO84_NSRXD            84      /* NSSP receive */
-#define GPIO84_CIF_FV           84      /* Camera frame start signal */
-#define GPIO85_nPCE_1           85      /* Card Enable for Card Space (PXA27x) */
-#define GPIO85_CIF_LV           85      /* Camera line start signal */
-#define GPIO90_CIF_DD_4         90      /* Camera data pin 4 */
-#define GPIO91_CIF_DD_5         91      /* Camera data pin 5 */
-#define GPIO92_MMCDAT0          92      /* MMC DAT0 (PXA27x) */
-#define GPIO93_CIF_DD_6         93      /* Camera data pin 6 */
-#define GPIO94_CIF_DD_5         94      /* Camera data pin 5 */
-#define GPIO95_CIF_DD_4         95      /* Camera data pin 4 */
-#define GPIO96_FFRXD            96      /* FFUART recieve */
-#define GPIO98_FFRTS            98      /* FFUART request to send */
-#define GPIO98_CIF_DD_0         98      /* Camera data pin 0 */
-#define GPIO99_FFTXD            99      /* FFUART transmit data */
-#define GPIO100_FFCTS           100     /* FFUART Clear to send */
-#define GPIO102_nPCE_1          102     /* PCMCIA (PXA27x) */
-#define GPIO103_CIF_DD_3        103     /* Camera data pin 3 */
-#define GPIO104_CIF_DD_2        104     /* Camera data pin 2 */
-#define GPIO105_CIF_DD_1        105     /* Camera data pin 1 */
-#define GPIO106_CIF_DD_9        106     /* Camera data pin 9 */
-#define GPIO107_CIF_DD_8        107     /* Camera data pin 8 */
-#define GPIO108_CIF_DD_7        108     /* Camera data pin 7 */
-#define GPIO109_MMCDAT1         109     /* MMC DAT1 (PXA27x) */
-#define GPIO110_MMCDAT2         110     /* MMC DAT2 (PXA27x) */
-#define GPIO110_MMCCS0          110     /* MMC Chip Select 0 (PXA27x) */
-#define GPIO111_MMCDAT3         111     /* MMC DAT3 (PXA27x) */
-#define GPIO111_MMCCS1          111     /* MMC Chip Select 1 (PXA27x) */
-#define GPIO112_MMCCMD          112     /* MMC CMD (PXA27x) */
-#define GPIO113_I2S_SYSCLK      113     /* I2S System Clock (PXA27x) */
-#define GPIO113_AC97_RESET_N    113     /* AC97 NRESET on (PXA27x) */
-#define GPIO114_CIF_DD_1        114     /* Camera data pin 1 */
-#define GPIO115_CIF_DD_3        115     /* Camera data pin 3 */
-#define GPIO116_CIF_DD_2        116     /* Camera data pin 2 */
-
-/* GPIO alternate function mode & direction */
-
-#define GPIO_IN                 0x000
-#define GPIO_OUT                0x080
-#define GPIO_ALT_FN_1_IN        0x100
-#define GPIO_ALT_FN_1_OUT       0x180
-#define GPIO_ALT_FN_2_IN        0x200
-#define GPIO_ALT_FN_2_OUT       0x280
-#define GPIO_ALT_FN_3_IN        0x300
-#define GPIO_ALT_FN_3_OUT       0x380
-#define GPIO_MD_MASK_NR         0x07f
-#define GPIO_MD_MASK_DIR        0x080
-#define GPIO_MD_MASK_FN         0x300
-#define GPIO_DFLT_LOW           0x400
-#define GPIO_DFLT_HIGH          0x800
-
-#define GPIO1_RTS_MD            ( 1 | GPIO_ALT_FN_1_IN)
-#define GPIO6_MMCCLK_MD         ( 6 | GPIO_ALT_FN_1_OUT)
-#define GPIO7_48MHz_MD          ( 7 | GPIO_ALT_FN_1_OUT)
-#define GPIO8_MMCCS0_MD         ( 8 | GPIO_ALT_FN_1_OUT)
-#define GPIO9_MMCCS1_MD         ( 9 | GPIO_ALT_FN_1_OUT)
-#define GPIO10_RTCCLK_MD        (10 | GPIO_ALT_FN_1_OUT)
-#define GPIO11_3_6MHz_MD        (11 | GPIO_ALT_FN_1_OUT)
-#define GPIO12_32KHz_MD         (12 | GPIO_ALT_FN_1_OUT)
-#define GPIO12_CIF_DD_7_MD      (12 | GPIO_ALT_FN_2_IN)
-#define GPIO13_MBGNT_MD         (13 | GPIO_ALT_FN_2_OUT)
-#define GPIO14_MBREQ_MD         (14 | GPIO_ALT_FN_1_IN)
-#define GPIO15_nCS_1_MD         (15 | GPIO_ALT_FN_2_OUT)
-#define GPIO16_PWM0_MD          (16 | GPIO_ALT_FN_2_OUT)
-#define GPIO17_PWM1_MD          (17 | GPIO_ALT_FN_2_OUT)
-#define GPIO17_CIF_DD_6_MD      (17 | GPIO_ALT_FN_2_IN)
-#define GPIO18_RDY_MD           (18 | GPIO_ALT_FN_1_IN)
-#define GPIO19_DREQ1_MD         (19 | GPIO_ALT_FN_1_IN)
-#define GPIO20_DREQ0_MD         (20 | GPIO_ALT_FN_1_IN)
-#define GPIO23_CIF_MCLK_MD      (23 | GPIO_ALT_FN_1_OUT)
-#define GPIO23_SCLK_MD          (23 | GPIO_ALT_FN_2_OUT)
-#define GPIO24_CIF_FV_MD        (24 | GPIO_ALT_FN_1_OUT)
-#define GPIO24_SFRM_MD          (24 | GPIO_ALT_FN_2_OUT)
-#define GPIO25_CIF_LV_MD        (25 | GPIO_ALT_FN_1_OUT)
-#define GPIO25_STXD_MD          (25 | GPIO_ALT_FN_2_OUT)
-#define GPIO26_SRXD_MD          (26 | GPIO_ALT_FN_1_IN)
-#define GPIO26_CIF_PCLK_MD      (26 | GPIO_ALT_FN_2_IN)
-#define GPIO27_SEXTCLK_MD       (27 | GPIO_ALT_FN_1_IN)
-#define GPIO27_CIF_DD_0_MD      (27 | GPIO_ALT_FN_3_IN)
-#define GPIO28_BITCLK_AC97_MD   (28 | GPIO_ALT_FN_1_IN)
-#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
-#define GPIO28_BITCLK_OUT_I2S_MD        (28 | GPIO_ALT_FN_1_OUT)
-#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
-#define GPIO29_SDATA_IN_I2S_MD  (29 | GPIO_ALT_FN_2_IN)
-#define GPIO30_SDATA_OUT_AC97_MD        (30 | GPIO_ALT_FN_2_OUT)
-#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
-#define GPIO31_SYNC_I2S_MD      (31 | GPIO_ALT_FN_1_OUT)
-#define GPIO31_SYNC_AC97_MD     (31 | GPIO_ALT_FN_2_OUT)
-#define GPIO32_SDATA_IN1_AC97_MD        (32 | GPIO_ALT_FN_1_IN)
-#define GPIO32_SYSCLK_I2S_MD    (32 | GPIO_ALT_FN_1_OUT)
-#define GPIO32_MMCCLK_MD        (32 | GPIO_ALT_FN_2_OUT)
-#define GPIO33_nCS_5_MD         (33 | GPIO_ALT_FN_2_OUT)
-#define GPIO34_FFRXD_MD         (34 | GPIO_ALT_FN_1_IN)
-#define GPIO34_MMCCS0_MD        (34 | GPIO_ALT_FN_2_OUT)
-#define GPIO35_FFCTS_MD         (35 | GPIO_ALT_FN_1_IN)
-#define GPIO35_KP_MKOUT6_MD     (35 | GPIO_ALT_FN_2_OUT)
-#define GPIO36_FFDCD_MD         (36 | GPIO_ALT_FN_1_IN)
-#define GPIO37_FFDSR_MD         (37 | GPIO_ALT_FN_1_IN)
-#define GPIO38_FFRI_MD          (38 | GPIO_ALT_FN_1_IN)
-#define GPIO39_MMCCS1_MD        (39 | GPIO_ALT_FN_1_OUT)
-#define GPIO39_FFTXD_MD         (39 | GPIO_ALT_FN_2_OUT)
-#define GPIO40_FFDTR_MD         (40 | GPIO_ALT_FN_2_OUT)
-#define GPIO41_FFRTS_MD         (41 | GPIO_ALT_FN_2_OUT)
-#define GPIO41_KP_MKOUT7_MD     (41 | GPIO_ALT_FN_1_OUT)
-#define GPIO42_BTRXD_MD         (42 | GPIO_ALT_FN_1_IN)
-#define GPIO42_HWRXD_MD         (42 | GPIO_ALT_FN_3_IN)
-#define GPIO42_CIF_MCLK_MD      (42 | GPIO_ALT_FN_3_OUT)
-#define GPIO43_BTTXD_MD         (43 | GPIO_ALT_FN_2_OUT)
-#define GPIO43_HWTXD_MD         (43 | GPIO_ALT_FN_3_OUT)
-#define GPIO43_CIF_FV_MD        (43 | GPIO_ALT_FN_3_OUT)
-#define GPIO44_BTCTS_MD         (44 | GPIO_ALT_FN_1_IN)
-#define GPIO44_HWCTS_MD         (44 | GPIO_ALT_FN_3_IN)
-#define GPIO44_CIF_LV_MD        (44 | GPIO_ALT_FN_3_OUT)
-#define GPIO45_CIF_PCLK_MD      (45 | GPIO_ALT_FN_3_IN)
-#define GPIO45_BTRTS_MD         (45 | GPIO_ALT_FN_2_OUT)
-#define GPIO45_HWRTS_MD         (45 | GPIO_ALT_FN_3_OUT)
-#define GPIO45_SYSCLK_AC97_MD   (45 | GPIO_ALT_FN_1_OUT)
-#define GPIO46_ICPRXD_MD        (46 | GPIO_ALT_FN_1_IN)
-#define GPIO46_STRXD_MD         (46 | GPIO_ALT_FN_2_IN)
-#define GPIO47_CIF_DD_0_MD      (47 | GPIO_ALT_FN_1_IN)
-#define GPIO47_ICPTXD_MD        (47 | GPIO_ALT_FN_2_OUT)
-#define GPIO47_STTXD_MD         (47 | GPIO_ALT_FN_1_OUT)
-#define GPIO48_CIF_DD_5_MD      (48 | GPIO_ALT_FN_1_IN)
-#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
-#define GPIO48_HWTXD_MD         (48 | GPIO_ALT_FN_1_OUT)
-#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
-#define GPIO49_HWRXD_MD         (49 | GPIO_ALT_FN_1_IN)
-#define GPIO49_nPWE_MD          (49 | GPIO_ALT_FN_2_OUT)
-#define GPIO50_CIF_DD_3_MD      (50 | GPIO_ALT_FN_1_IN)
-#define GPIO50_nPIOR_MD         (50 | GPIO_ALT_FN_2_OUT)
-#define GPIO50_HWCTS_MD         (50 | GPIO_ALT_FN_1_IN)
-#define GPIO50_CIF_DD_3_MD      (50 | GPIO_ALT_FN_1_IN)
-#define GPIO51_CIF_DD_2_MD      (51 | GPIO_ALT_FN_1_IN)
-#define GPIO51_nPIOW_MD         (51 | GPIO_ALT_FN_2_OUT)
-#define GPIO51_HWRTS_MD         (51 | GPIO_ALT_FN_1_OUT)
-#define GPIO51_CIF_DD_2_MD      (51 | GPIO_ALT_FN_1_IN)
-#define GPIO52_nPCE_1_MD        (52 | GPIO_ALT_FN_2_OUT)
-#define GPIO52_CIF_DD_4_MD      (52 | GPIO_ALT_FN_1_IN)
-#define GPIO53_nPCE_2_MD        (53 | GPIO_ALT_FN_2_OUT)
-#define GPIO53_MMCCLK_MD        (53 | GPIO_ALT_FN_1_OUT)
-#define GPIO53_CIF_MCLK_MD      (53 | GPIO_ALT_FN_2_OUT)
-#define GPIO54_MMCCLK_MD        (54 | GPIO_ALT_FN_1_OUT)
-#define GPIO54_nPCE_2_MD        (54 | GPIO_ALT_FN_2_OUT)
-#define GPIO54_pSKTSEL_MD       (54 | GPIO_ALT_FN_2_OUT)
-#define GPIO54_CIF_PCLK_MD      (54 | GPIO_ALT_FN_3_IN)
-#define GPIO55_nPREG_MD         (55 | GPIO_ALT_FN_2_OUT)
-#define GPIO55_CIF_DD_1_MD      (55 | GPIO_ALT_FN_1_IN)
-#define GPIO56_nPWAIT_MD        (56 | GPIO_ALT_FN_1_IN)
-#define GPIO57_nIOIS16_MD       (57 | GPIO_ALT_FN_1_IN)
-#define GPIO58_LDD_0_MD         (58 | GPIO_ALT_FN_2_OUT)
-#define GPIO59_LDD_1_MD         (59 | GPIO_ALT_FN_2_OUT)
-#define GPIO60_LDD_2_MD         (60 | GPIO_ALT_FN_2_OUT)
-#define GPIO61_LDD_3_MD         (61 | GPIO_ALT_FN_2_OUT)
-#define GPIO62_LDD_4_MD         (62 | GPIO_ALT_FN_2_OUT)
-#define GPIO63_LDD_5_MD         (63 | GPIO_ALT_FN_2_OUT)
-#define GPIO64_LDD_6_MD         (64 | GPIO_ALT_FN_2_OUT)
-#define GPIO65_LDD_7_MD         (65 | GPIO_ALT_FN_2_OUT)
-#define GPIO66_LDD_8_MD         (66 | GPIO_ALT_FN_2_OUT)
-#define GPIO66_MBREQ_MD         (66 | GPIO_ALT_FN_1_IN)
-#define GPIO67_LDD_9_MD         (67 | GPIO_ALT_FN_2_OUT)
-#define GPIO67_MMCCS0_MD        (67 | GPIO_ALT_FN_1_OUT)
-#define GPIO68_LDD_10_MD        (68 | GPIO_ALT_FN_2_OUT)
-#define GPIO68_MMCCS1_MD        (68 | GPIO_ALT_FN_1_OUT)
-#define GPIO69_LDD_11_MD        (69 | GPIO_ALT_FN_2_OUT)
-#define GPIO69_MMCCLK_MD        (69 | GPIO_ALT_FN_1_OUT)
-#define GPIO70_LDD_12_MD        (70 | GPIO_ALT_FN_2_OUT)
-#define GPIO70_RTCCLK_MD        (70 | GPIO_ALT_FN_1_OUT)
-#define GPIO71_LDD_13_MD        (71 | GPIO_ALT_FN_2_OUT)
-#define GPIO71_3_6MHz_MD        (71 | GPIO_ALT_FN_1_OUT)
-#define GPIO72_LDD_14_MD        (72 | GPIO_ALT_FN_2_OUT)
-#define GPIO72_32kHz_MD         (72 | GPIO_ALT_FN_1_OUT)
-#define GPIO73_LDD_15_MD        (73 | GPIO_ALT_FN_2_OUT)
-#define GPIO73_MBGNT_MD         (73 | GPIO_ALT_FN_1_OUT)
-#define GPIO74_LCD_FCLK_MD      (74 | GPIO_ALT_FN_2_OUT)
-#define GPIO75_LCD_LCLK_MD      (75 | GPIO_ALT_FN_2_OUT)
-#define GPIO76_LCD_PCLK_MD      (76 | GPIO_ALT_FN_2_OUT)
-#define GPIO77_LCD_ACBIAS_MD    (77 | GPIO_ALT_FN_2_OUT)
-#define GPIO78_nCS_2_MD         (78 | GPIO_ALT_FN_2_OUT)
-#define GPIO78_nPCE_2_MD        (78 | GPIO_ALT_FN_1_OUT)
-#define GPIO79_nCS_3_MD         (79 | GPIO_ALT_FN_2_OUT)
-#define GPIO79_pSKTSEL_MD       (79 | GPIO_ALT_FN_1_OUT)
-#define GPIO80_nCS_4_MD         (80 | GPIO_ALT_FN_2_OUT)
-#define GPIO81_NSSP_CLK_OUT     (81 | GPIO_ALT_FN_1_OUT)
-#define GPIO81_NSSP_CLK_IN      (81 | GPIO_ALT_FN_1_IN)
-#define GPIO81_CIF_DD_0_MD      (81 | GPIO_ALT_FN_2_IN)
-#define GPIO82_NSSP_FRM_OUT     (82 | GPIO_ALT_FN_1_OUT)
-#define GPIO82_NSSP_FRM_IN      (82 | GPIO_ALT_FN_1_IN)
-#define GPIO82_CIF_DD_5_MD      (82 | GPIO_ALT_FN_3_IN)
-#define GPIO83_NSSP_TX          (83 | GPIO_ALT_FN_1_OUT)
-#define GPIO83_NSSP_RX          (83 | GPIO_ALT_FN_2_IN)
-#define GPIO83_CIF_DD_4_MD      (83 | GPIO_ALT_FN_3_IN)
-#define GPIO84_NSSP_TX          (84 | GPIO_ALT_FN_1_OUT)
-#define GPIO84_NSSP_RX          (84 | GPIO_ALT_FN_2_IN)
-#define GPIO84_CIF_FV_MD        (84 | GPIO_ALT_FN_3_IN)
-#define GPIO85_nPCE_1_MD        (85 | GPIO_ALT_FN_1_OUT)
-#define GPIO85_CIF_LV_MD        (85 | GPIO_ALT_FN_3_IN)
-#define GPIO86_nPCE_1_MD        (86 | GPIO_ALT_FN_1_OUT)
-#define GPIO88_USBH1_PWR_MD     (88 | GPIO_ALT_FN_1_IN)
-#define GPIO89_USBH1_PEN_MD     (89 | GPIO_ALT_FN_2_OUT)
-#define GPIO90_CIF_DD_4_MD      (90 | GPIO_ALT_FN_3_IN)
-#define GPIO91_CIF_DD_5_MD      (91 | GPIO_ALT_FN_3_IN)
-#define GPIO92_MMCDAT0_MD       (92 | GPIO_ALT_FN_1_OUT)
-#define GPIO93_CIF_DD_6_MD      (93 | GPIO_ALT_FN_2_IN)
-#define GPIO94_CIF_DD_5_MD      (94 | GPIO_ALT_FN_2_IN)
-#define GPIO95_CIF_DD_4_MD      (95 | GPIO_ALT_FN_2_IN)
-#define GPIO95_KP_MKIN6_MD      (95 | GPIO_ALT_FN_3_IN)
-#define GPIO96_KP_DKIN3_MD      (96 | GPIO_ALT_FN_1_IN)
-#define GPIO96_FFRXD_MD         (96 | GPIO_ALT_FN_3_IN)
-#define GPIO97_KP_MKIN3_MD      (97 | GPIO_ALT_FN_3_IN)
-#define GPIO98_CIF_DD_0_MD      (98 | GPIO_ALT_FN_2_IN)
-#define GPIO98_FFRTS_MD         (98 | GPIO_ALT_FN_3_OUT)
-#define GPIO99_FFTXD_MD         (99 | GPIO_ALT_FN_3_OUT)
-#define GPIO100_KP_MKIN0_MD     (100 | GPIO_ALT_FN_1_IN)
-#define GPIO101_KP_MKIN1_MD     (101 | GPIO_ALT_FN_1_IN)
-#define GPIO102_nPCE_1_MD       (102 | GPIO_ALT_FN_1_OUT)
-#define GPIO102_KP_MKIN2_MD     (102 | GPIO_ALT_FN_1_IN)
-#define GPIO103_CIF_DD_3_MD     (103 | GPIO_ALT_FN_1_IN)
-#define GPIO103_KP_MKOUT0_MD    (103 | GPIO_ALT_FN_2_OUT)
-#define GPIO104_CIF_DD_2_MD     (104 | GPIO_ALT_FN_1_IN)
-#define GPIO104_pSKTSEL_MD      (104 | GPIO_ALT_FN_1_OUT)
-#define GPIO104_KP_MKOUT1_MD    (104 | GPIO_ALT_FN_2_OUT)
-#define GPIO105_CIF_DD_1_MD     (105 | GPIO_ALT_FN_1_IN)
-#define GPIO105_KP_MKOUT2_MD    (105 | GPIO_ALT_FN_2_OUT)
-#define GPIO106_CIF_DD_9_MD     (106 | GPIO_ALT_FN_1_IN)
-#define GPIO106_KP_MKOUT3_MD    (106 | GPIO_ALT_FN_2_OUT)
-#define GPIO107_CIF_DD_8_MD     (107 | GPIO_ALT_FN_1_IN)
-#define GPIO107_KP_MKOUT4_MD    (107 | GPIO_ALT_FN_2_OUT)
-#define GPIO108_CIF_DD_7_MD     (108 | GPIO_ALT_FN_1_IN)
-#define GPIO108_KP_MKOUT5_MD    (108 | GPIO_ALT_FN_2_OUT)
-#define GPIO109_MMCDAT1_MD      (109 | GPIO_ALT_FN_1_OUT)
-#define GPIO110_MMCDAT2_MD      (110 | GPIO_ALT_FN_1_OUT)
-#define GPIO110_MMCCS0_MD       (110 | GPIO_ALT_FN_1_OUT)
-#define GPIO111_MMCDAT3_MD      (111 | GPIO_ALT_FN_1_OUT)
-#define GPIO110_MMCCS1_MD       (111 | GPIO_ALT_FN_1_OUT)
-#define GPIO112_MMCCMD_MD       (112 | GPIO_ALT_FN_1_OUT)
-#define GPIO113_I2S_SYSCLK_MD   (113 | GPIO_ALT_FN_1_OUT)
-#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
-#define GPIO117_I2CSCL_MD       (117 | GPIO_ALT_FN_1_IN)
-#define GPIO118_I2CSDA_MD       (118 | GPIO_ALT_FN_1_IN)
-
-/*
- * Handy routine to set GPIO alternate functions
- */
-extern int pxa_gpio_mode( int gpio_mode );
-
-#endif /* __ASM_ARCH_PXA2XX_GPIO_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-u2d.h b/arch/arm/mach-pxa/include/mach/regs-u2d.h
index 44b0b20b69a4..c15c0c57de08 100644
--- a/arch/arm/mach-pxa/include/mach/regs-u2d.h
+++ b/arch/arm/mach-pxa/include/mach/regs-u2d.h
@@ -166,7 +166,8 @@
 #define U2DMACSR_BUSERRTYPE     (7 << 10)       /* PX Bus Error Type */
 #define U2DMACSR_EORINTR        (1 << 9)        /* End Of Receive */
 #define U2DMACSR_REQPEND        (1 << 8)        /* Request Pending */
-#define U2DMACSR_RASINTR        (1 << 4)        /* Request After Channel Stopped (read / write 1 clear) */#define U2DMACSR_STOPINTR     (1 << 3)        /* Stop Interrupt (read only) */
+#define U2DMACSR_RASINTR        (1 << 4)        /* Request After Channel Stopped (read / write 1 clear) */
+#define U2DMACSR_STOPINTR       (1 << 3)        /* Stop Interrupt (read only) */
 #define U2DMACSR_ENDINTR        (1 << 2)        /* End Interrupt (read / write 1 clear) */
 #define U2DMACSR_STARTINTR      (1 << 1)        /* Start Interrupt (read / write 1 clear) */
 #define U2DMACSR_BUSERRINTR     (1 << 0)        /* Bus Error Interrupt (read / write 1 clear) */
diff --git a/arch/arm/mach-pxa/include/mach/ssp.h b/arch/arm/mach-pxa/include/mach/ssp.h
deleted file mode 100644
index be1be5b6db51..000000000000
--- a/arch/arm/mach-pxa/include/mach/ssp.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- *  ssp.h
- *
- *  Copyright (C) 2003 Russell King, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This driver supports the following PXA CPU/SSP ports:-
- *
- *       PXA250     SSP
- *       PXA255     SSP, NSSP
- *       PXA26x     SSP, NSSP, ASSP
- *       PXA27x     SSP1, SSP2, SSP3
- *       PXA3xx     SSP1, SSP2, SSP3, SSP4
- */
-
-#ifndef __ASM_ARCH_SSP_H
-#define __ASM_ARCH_SSP_H
-
-#include <linux/list.h>
-#include <linux/io.h>
-
-enum pxa_ssp_type {
-        SSP_UNDEFINED = 0,
-        PXA25x_SSP,  /* pxa 210, 250, 255, 26x */
-        PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
-        PXA27x_SSP,
-};
-
-struct ssp_device {
-        struct platform_device *pdev;
-        struct list_head        node;
-
-        struct clk      *clk;
-        void __iomem    *mmio_base;
-        unsigned long   phys_base;
-
-        const char      *label;
-        int             port_id;
-        int             type;
-        int             use_count;
-        int             irq;
-        int             drcmr_rx;
-        int             drcmr_tx;
-};
-
-#ifdef CONFIG_PXA_SSP_LEGACY
-/*
- * SSP initialisation flags
- */
-#define SSP_NO_IRQ      0x1             /* don't register an irq handler in SSP driver */
-
-struct ssp_state {
-        u32     cr0;
-        u32 cr1;
-        u32 to;
-        u32 psp;
-};
-
-struct ssp_dev {
-        struct ssp_device *ssp;
-        u32 port;
-        u32 mode;
-        u32 flags;
-        u32 psp_flags;
-        u32 speed;
-        int irq;
-};
-
-int ssp_write_word(struct ssp_dev *dev, u32 data);
-int ssp_read_word(struct ssp_dev *dev, u32 *data);
-int ssp_flush(struct ssp_dev *dev);
-void ssp_enable(struct ssp_dev *dev);
-void ssp_disable(struct ssp_dev *dev);
-void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp);
-void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp);
-int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
-int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
-void ssp_exit(struct ssp_dev *dev);
-#endif /* CONFIG_PXA_SSP_LEGACY */
-
-/**
- * ssp_write_reg - Write to a SSP register
- *
- * @dev: SSP device to access
- * @reg: Register to write to
- * @val: Value to be written.
- */
-static inline void ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
-{
-        __raw_writel(val, dev->mmio_base + reg);
-}
-
-/**
- * ssp_read_reg - Read from a SSP register
- *
- * @dev: SSP device to access
- * @reg: Register to read from
- */
-static inline u32 ssp_read_reg(struct ssp_device *dev, u32 reg)
-{
-        return __raw_readl(dev->mmio_base + reg);
-}
-
-struct ssp_device *ssp_request(int port, const char *label);
-void ssp_free(struct ssp_device *);
-#endif /* __ASM_ARCH_SSP_H */
diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h
index 4df2d38507dc..1bbd1f2e4beb 100644
--- a/arch/arm/mach-pxa/include/mach/tosa.h
+++ b/arch/arm/mach-pxa/include/mach/tosa.h
@@ -167,7 +167,7 @@
 
 #define TOSA_KEY_SYNC           KEY_102ND /* ??? */
 
-#ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES
+#ifndef CONFIG_TOSA_USE_EXT_KEYCODES
 #define TOSA_KEY_RECORD         KEY_YEN
 #define TOSA_KEY_ADDRESSBOOK    KEY_KATAKANA
 #define TOSA_KEY_CANCEL         KEY_ESC
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index 5ef91d9d17e4..759b851ec985 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -16,9 +16,9 @@
 #define BTUART_BASE     (0x40200000)
 #define STUART_BASE     (0x40700000)
 
-static unsigned long uart_base = FFUART_BASE;
-static unsigned int uart_shift = 2;
-static unsigned int uart_is_pxa = 1;
+static unsigned long uart_base;
+static unsigned int uart_shift;
+static unsigned int uart_is_pxa;
 
 static inline unsigned char uart_read(int offset)
 {
@@ -56,6 +56,11 @@ static inline void flush(void)
 
 static inline void arch_decomp_setup(void)
 {
+        /* initialize to default */
+        uart_base = FFUART_BASE;
+        uart_shift = 2;
+        uart_is_pxa = 1;
+
         if (machine_is_littleton() || machine_is_intelmote2()
             || machine_is_csb726() || machine_is_stargate2()
             || machine_is_cm_x300() || machine_is_balloon3())
diff --git a/arch/arm/mach-pxa/include/mach/vpac270.h b/arch/arm/mach-pxa/include/mach/vpac270.h
new file mode 100644
index 000000000000..7bfa3dd0fd5e
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/vpac270.h
@@ -0,0 +1,42 @@
+/*
+ * GPIOs and interrupts for Voipac PXA270
+ *
+ * Copyright (C) 2010
+ * Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _INCLUDE_VPAC270_H_
+#define _INCLUDE_VPAC270_H_
+
+#define GPIO1_VPAC270_USER_BTN          1
+
+#define GPIO15_VPAC270_LED_ORANGE       15
+
+#define GPIO81_VPAC270_BKL_ON           81
+#define GPIO83_VPAC270_NL_ON            83
+
+#define GPIO52_VPAC270_SD_READONLY      52
+#define GPIO53_VPAC270_SD_DETECT_N      53
+
+#define GPIO84_VPAC270_PCMCIA_CD        84
+#define GPIO35_VPAC270_PCMCIA_RDY       35
+#define GPIO107_VPAC270_PCMCIA_PPEN     107
+#define GPIO11_VPAC270_PCMCIA_RESET     11
+#define GPIO17_VPAC270_CF_CD            17
+#define GPIO12_VPAC270_CF_RDY           12
+#define GPIO16_VPAC270_CF_RESET         16
+
+#define GPIO41_VPAC270_UDC_DETECT       41
+
+#define GPIO114_VPAC270_ETH_IRQ         114
+
+#define GPIO36_VPAC270_IDE_IRQ          36
+
+#define GPIO113_VPAC270_TS_IRQ          113
+
+#endif
diff --git a/arch/arm/mach-pxa/include/mach/z2.h b/arch/arm/mach-pxa/include/mach/z2.h
new file mode 100644
index 000000000000..8835c16bc82f
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/z2.h
@@ -0,0 +1,41 @@
+/*
+ *  arch/arm/mach-pxa/include/mach/z2.h
+ *
+ *  Author: Ken McGuire
+ *  Created: Feb 6, 2009
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef ASM_ARCH_ZIPIT2_H
+#define ASM_ARCH_ZIPIT2_H
+
+/* LEDs */
+#define GPIO10_ZIPITZ2_LED_WIFI         10
+#define GPIO85_ZIPITZ2_LED_CHARGED      85
+#define GPIO83_ZIPITZ2_LED_CHARGING     83
+
+/* SD/MMC */
+#define GPIO96_ZIPITZ2_SD_DETECT        96
+
+/* GPIO Buttons */
+#define GPIO1_ZIPITZ2_POWER_BUTTON      1
+#define GPIO98_ZIPITZ2_LID_BUTTON       98
+
+/* Libertas GSPI8686 WiFi */
+#define GPIO14_ZIPITZ2_WIFI_RESET       14
+#define GPIO15_ZIPITZ2_WIFI_POWER       15
+#define GPIO24_ZIPITZ2_WIFI_CS          24
+#define GPIO36_ZIPITZ2_WIFI_IRQ         36
+
+/* LCD */
+#define GPIO19_ZIPITZ2_LCD_RESET        19
+#define GPIO88_ZIPITZ2_LCD_CS           88
+
+/* MISC GPIOs */
+#define GPIO0_ZIPITZ2_AC_DETECT         0
+#define GPIO37_ZIPITZ2_HEADSET_DETECT   37
+
+#endif
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index fa527b258d61..9b9046185b00 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -41,7 +41,6 @@
 
 #include <mach/pxa300.h>
 #include <mach/pxafb.h>
-#include <mach/ssp.h>
 #include <mach/mmc.h>
 #include <mach/pxa2xx_spi.h>
 #include <mach/pxa27x_keypad.h>
@@ -272,7 +271,7 @@ static inline void littleton_init_keypad(void) {}
 
 #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
 static struct pxamci_platform_data littleton_mci_platform_data = {
-        .detect_delay           = 20,
+        .detect_delay_ms        = 200,
         .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
         .gpio_card_detect       = GPIO_MMC1_CARD_DETECT,
         .gpio_card_ro           = -1,
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 63d65a2a0387..330c3282856e 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -478,7 +478,7 @@ static void lubbock_mci_exit(struct device *dev, void *data)
 
 static struct pxamci_platform_data lubbock_mci_platform_data = {
         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
-        .detect_delay           = 1,
+        .detect_delay_ms        = 10,
         .init                   = lubbock_mci_init,
         .get_ro                 = lubbock_mci_get_ro,
         .exit                   = lubbock_mci_exit,
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index cf6b720c055f..1d1419b73457 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -81,6 +81,7 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
                 PGSR(bank) &= ~mask;
                 is_out = 1;
                 break;
+        case MFP_LPM_INPUT:
         case MFP_LPM_DEFAULT:
                 break;
         default:
@@ -178,8 +179,17 @@ int gpio_set_wake(unsigned int gpio, unsigned int on)
         if (!d->valid)
                 return -EINVAL;
 
-        if (d->keypad_gpio)
-                return -EINVAL;
+        /* Allow keypad GPIOs to wakeup system when
+         * configured as generic GPIOs.
+         */
+        if (d->keypad_gpio && (MFP_AF(d->config) == 0) &&
+            (d->config & MFP_LPM_CAN_WAKEUP)) {
+                if (on)
+                        PKWR |= d->mask;
+                else
+                        PKWR &= ~d->mask;
+                return 0;
+        }
 
         mux_taken = (PWER & d->mux_mask) & (~d->mask);
         if (on && mux_taken)
@@ -239,21 +249,25 @@ static int pxa27x_pkwr_gpio[] = {
 int keypad_set_wake(unsigned int on)
 {
         unsigned int i, gpio, mask = 0;
-
-        if (!on) {
-                PKWR = 0;
-                return 0;
-        }
+        struct gpio_desc *d;
 
         for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
 
                 gpio = pxa27x_pkwr_gpio[i];
+                d = &gpio_desc[gpio];
 
-                if (gpio_desc[gpio].config & MFP_LPM_CAN_WAKEUP)
+                /* skip if configured as generic GPIO */
+                if (MFP_AF(d->config) == 0)
+                        continue;
+
+                if (d->config & MFP_LPM_CAN_WAKEUP)
                         mask |= gpio_desc[gpio].mask;
         }
 
-        PKWR = mask;
+        if (on)
+                PKWR |= mask;
+        else
+                PKWR &= ~mask;
         return 0;
 }
 
@@ -328,6 +342,17 @@ static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state)
 {
         int i;
 
+        /* set corresponding PGSR bit of those marked MFP_LPM_KEEP_OUTPUT */
+        for (i = 0; i < pxa_last_gpio; i++) {
+                if ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
+                    (GPDR(i) & GPIO_bit(i))) {
+                        if (GPLR(i) & GPIO_bit(i))
+                                PGSR(i) |= GPIO_bit(i);
+                        else
+                                PGSR(i) &= ~GPIO_bit(i);
+                }
+        }
+
         for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
 
                 saved_gafr[0][i] = GAFR_L(i);
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 843fcca76e26..d60db87dde08 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -38,6 +38,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/usb/gpio_vbus.h>
 #include <linux/regulator/max1586.h>
+#include <linux/slab.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -425,6 +426,7 @@ struct gpio_vbus_mach_info gpio_vbus_data = {
  * to give the card a chance to fully insert/eject.
  */
 static struct pxamci_platform_data mioa701_mci_info = {
+        .detect_delay_ms        = 250,
         .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
         .gpio_card_detect       = GPIO15_SDIO_INSERT,
         .gpio_card_ro           = GPIO78_SDIO_RO,
@@ -790,7 +792,6 @@ static void __init mioa701_machine_init(void)
         mio_gpio_request(ARRAY_AND_SIZE(global_gpios));
         bootstrap_init();
         set_pxa_fb_info(&mioa701_pxafb_info);
-        mioa701_mci_info.detect_delay = msecs_to_jiffies(250);
         pxa_set_mci_info(&mioa701_mci_info);
         pxa_set_keypad_info(&mioa701_keypad_info);
         wm97xx_bat_set_pdata(&mioa701_battery_data);
diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c
index 8c9c6f0d56bb..462167ac05f9 100644
--- a/arch/arm/mach-pxa/mxm8x10.c
+++ b/arch/arm/mach-pxa/mxm8x10.c
@@ -325,7 +325,7 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
 #if defined(CONFIG_MMC)
 static struct pxamci_platform_data mxm_8x10_mci_platform_data = {
         .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
-        .detect_delay = 1,
+        .detect_delay_ms = 10,
         .gpio_card_detect = MXM_8X10_SD_nCD,
         .gpio_card_ro = MXM_8X10_SD_WP,
         .gpio_power = -1
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index f70c75b38769..1963819dba98 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -168,7 +168,7 @@ static struct pxamci_platform_data palmld_mci_platform_data = {
         .gpio_card_detect       = GPIO_NR_PALMLD_SD_DETECT_N,
         .gpio_card_ro           = GPIO_NR_PALMLD_SD_READONLY,
         .gpio_power             = GPIO_NR_PALMLD_SD_POWER,
-        .detect_delay           = 20,
+        .detect_delay_ms        = 200,
 };
 
 /******************************************************************************
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index d902a813aae3..5305a3993e69 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -110,7 +110,7 @@ static struct pxamci_platform_data palmt5_mci_platform_data = {
         .gpio_card_detect       = GPIO_NR_PALMT5_SD_DETECT_N,
         .gpio_card_ro           = GPIO_NR_PALMT5_SD_READONLY,
         .gpio_power             = GPIO_NR_PALMT5_SD_POWER,
-        .detect_delay           = 20,
+        .detect_delay_ms        = 200,
 };
 
 /******************************************************************************
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index 717d7a638675..033b567e50bb 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -121,7 +121,7 @@ static struct pxamci_platform_data palmtc_mci_platform_data = {
         .gpio_power             = GPIO_NR_PALMTC_SD_POWER,
         .gpio_card_ro           = GPIO_NR_PALMTC_SD_READONLY,
         .gpio_card_detect       = GPIO_NR_PALMTC_SD_DETECT_N,
-        .detect_delay           = 20,
+        .detect_delay_ms        = 200,
 };
 
 /******************************************************************************
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 007b58c11f8d..ecc1a401598e 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -170,7 +170,7 @@ static struct pxamci_platform_data palmtx_mci_platform_data = {
         .gpio_card_detect       = GPIO_NR_PALMTX_SD_DETECT_N,
         .gpio_card_ro           = GPIO_NR_PALMTX_SD_READONLY,
         .gpio_power             = GPIO_NR_PALMTX_SD_POWER,
-        .detect_delay           = 20,
+        .detect_delay_ms        = 200,
 };
 
 /******************************************************************************
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 9d0ecea1760c..f56ae1008759 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -326,7 +326,7 @@ static void pcm990_mci_exit(struct device *dev, void *data)
 #define MSECS_PER_JIFFY (1000/HZ)
 
 static struct pxamci_platform_data pcm990_mci_platform_data = {
-        .detect_delay           = 250 / MSECS_PER_JIFFY,
+        .detect_delay_ms        = 250,
         .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
         .init                   = pcm990_mci_init,
         .setpower               = pcm990_mci_setpower,
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index 7693355ee637..166c15f62916 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -14,6 +14,7 @@
 #include <linux/module.h>
 #include <linux/suspend.h>
 #include <linux/errno.h>
+#include <linux/slab.h>
 
 #include <mach/pm.h>
 
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index d58a52415d75..f4abdaafdac4 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -40,13 +40,12 @@
 #include <mach/pxa25x.h>
 #include <mach/mmc.h>
 #include <mach/udc.h>
-#include <plat/i2c.h>
 #include <mach/irda.h>
 #include <mach/poodle.h>
 #include <mach/pxafb.h>
 #include <mach/sharpsl.h>
-#include <mach/ssp.h>
 #include <mach/pxa2xx_spi.h>
+#include <plat/i2c.h>
 
 #include <asm/hardware/scoop.h>
 #include <asm/hardware/locomo.h>
@@ -277,6 +276,7 @@ static void poodle_mci_exit(struct device *dev, void *data)
 }
 
 static struct pxamci_platform_data poodle_mci_platform_data = {
+        .detect_delay_ms        = 250,
         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
         .init                   = poodle_mci_init,
         .setpower               = poodle_mci_setpower,
@@ -450,7 +450,6 @@ static void __init poodle_init(void)
         set_pxa_fb_parent(&poodle_locomo_device.dev);
         set_pxa_fb_info(&poodle_fb_info);
         pxa_set_udc_info(&udc_info);
-        poodle_mci_platform_data.detect_delay = msecs_to_jiffies(250);
         pxa_set_mci_info(&poodle_mci_platform_data);
         pxa_set_ficp_info(&poodle_ficp_platform_data);
         pxa_set_i2c_info(NULL);
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 4d7c03e72504..f544e58e1536 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -29,7 +29,6 @@
 #include <mach/ohci.h>
 #include <mach/pm.h>
 #include <mach/dma.h>
-#include <mach/ssp.h>
 #include <mach/regs-intc.h>
 #include <plat/i2c.h>
 
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 3184bdc14526..d4b61b3f08f3 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -37,8 +37,6 @@
 #include <linux/lis3lv02d.h>
 #include <linux/pda_power.h>
 #include <linux/power_supply.h>
-#include <linux/pda_power.h>
-#include <linux/power_supply.h>
 #include <linux/regulator/max8660.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
@@ -444,7 +442,7 @@ static struct gpio_keys_button gpio_keys_button[] = {
                 .active_low             = 0,
                 .wakeup                 = 0,
                 .debounce_interval      = 5, /* ms */
-                .desc                   = "on/off button",
+                .desc                   = "on_off button",
         },
 };
 
@@ -716,7 +714,7 @@ static void raumfeld_mci_exit(struct device *dev, void *data)
 static struct pxamci_platform_data raumfeld_mci_platform_data = {
         .init                   = raumfeld_mci_init,
         .exit                   = raumfeld_mci_exit,
-        .detect_delay           = 20,
+        .detect_delay_ms        = 200,
         .gpio_card_detect       = -1,
         .gpio_card_ro           = -1,
         .gpio_power             = -1,
@@ -985,7 +983,7 @@ static void __init raumfeld_common_init(void)
                 int i;
 
                 for (i = 0; i < ARRAY_SIZE(gpio_keys_button); i++)
-                        if (!strcmp(gpio_keys_button[i].desc, "on/off button"))
+                        if (!strcmp(gpio_keys_button[i].desc, "on_off button"))
                                 gpio_keys_button[i].active_low = 1;
         }
 
@@ -1011,8 +1009,7 @@ static void __init raumfeld_common_init(void)
                 gpio_direction_output(GPIO_W2W_PDN, 0);
 
         /* this can be used to switch off the device */
-        ret = gpio_request(GPIO_SHUTDOWN_SUPPLY,
-                                "supply shutdown");
+        ret = gpio_request(GPIO_SHUTDOWN_SUPPLY, "supply shutdown");
         if (ret < 0)
                 pr_warning("Unable to request GPIO_SHUTDOWN_SUPPLY\n");
         else
diff --git a/arch/arm/mach-pxa/sharpsl.h b/arch/arm/mach-pxa/sharpsl.h
index 1439785d3979..0cc1203c5bef 100644
--- a/arch/arm/mach-pxa/sharpsl.h
+++ b/arch/arm/mach-pxa/sharpsl.h
@@ -10,29 +10,6 @@
 #include <mach/sharpsl_pm.h>
 
 /*
- * SharpSL SSP Driver
- */
-struct corgissp_machinfo {
-        int port;
-        int cs_lcdcon;
-        int cs_ads7846;
-        int cs_max1111;
-        int clk_lcdcon;
-        int clk_ads7846;
-        int clk_max1111;
-};
-
-void corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo);
-
-
-/*
- * SharpSL/Corgi LCD Driver
- */
-void corgi_lcdtg_suspend(void);
-void corgi_lcdtg_hw_init(int mode);
-
-
-/*
  * SharpSL Battery/PM Driver
  */
 #define READ_GPIO_BIT(x)    (GPLR(x) & GPIO_bit(x))
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 463d874bb867..cb4767251f3c 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -28,7 +28,6 @@
 #include <asm/mach-types.h>
 #include <mach/pm.h>
 #include <mach/pxa2xx-regs.h>
-#include <mach/pxa2xx-gpio.h>
 #include <mach/regs-rtc.h>
 #include <mach/sharpsl.h>
 #include <mach/sharpsl_pm.h>
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 19b5109d9808..4d2413ed0ffa 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -86,6 +86,7 @@ static unsigned long spitz_pin_config[] __initdata = {
 
         /* GPIOs */
         GPIO9_GPIO,     /* SPITZ_GPIO_nSD_DETECT */
+        GPIO16_GPIO,    /* SPITZ_GPIO_SYNC */
         GPIO81_GPIO,    /* SPITZ_GPIO_nSD_WP */
         GPIO41_GPIO,    /* SPITZ_GPIO_USB_CONNECT */
         GPIO37_GPIO,    /* SPITZ_GPIO_USB_HOST */
@@ -119,7 +120,8 @@ static unsigned long spitz_pin_config[] __initdata = {
         GPIO117_I2C_SCL,
         GPIO118_I2C_SDA,
 
-        GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
+        GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,       /* SPITZ_GPIO_KEY_INT */
+        GPIO1_GPIO | WAKEUP_ON_EDGE_FALL,       /* SPITZ_GPIO_RESET */
 };
 
 /*
@@ -363,7 +365,7 @@ static struct gpio_keys_button spitz_gpio_keys[] = {
                 .type   = EV_PWR,
                 .code   = KEY_SUSPEND,
                 .gpio   = SPITZ_GPIO_ON_KEY,
-                .desc   = "On/Off",
+                .desc   = "On Off",
                 .wakeup = 1,
         },
         /* Two buttons detecting the lid state */
@@ -537,6 +539,7 @@ static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
 }
 
 static struct pxamci_platform_data spitz_mci_platform_data = {
+        .detect_delay_ms        = 250,
         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
         .setpower               = spitz_mci_setpower,
         .gpio_card_detect       = SPITZ_GPIO_nSD_DETECT,
@@ -757,7 +760,6 @@ static void __init common_init(void)
         spitz_init_spi();
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
-        spitz_mci_platform_data.detect_delay = msecs_to_jiffies(250);
         pxa_set_mci_info(&spitz_mci_platform_data);
         pxa_set_ohci_info(&spitz_ohci_platform_data);
         pxa_set_ficp_info(&spitz_ficp_platform_data);
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index fc5a70c40358..4209ddf6da61 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -24,9 +24,10 @@
 
 #include <mach/sharpsl.h>
 #include <mach/spitz.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/pxa2xx-gpio.h>
+#include <mach/pxa27x.h>
+
 #include "sharpsl.h"
+#include "generic.h"
 
 #define SHARPSL_CHARGE_ON_VOLT         0x99  /* 2.9V */
 #define SHARPSL_CHARGE_ON_TEMP         0xe0  /* 2.9V */
@@ -37,10 +38,17 @@
 
 static int spitz_last_ac_status;
 
+static struct gpio spitz_charger_gpios[] = {
+        { SPITZ_GPIO_KEY_INT,   GPIOF_IN, "Keyboard Interrupt" },
+        { SPITZ_GPIO_SYNC,      GPIOF_IN, "Sync" },
+        { SPITZ_GPIO_ADC_TEMP_ON, GPIOF_OUT_INIT_LOW, "ADC Temp On" },
+        { SPITZ_GPIO_JK_B,        GPIOF_OUT_INIT_LOW, "JK B" },
+        { SPITZ_GPIO_CHRG_ON,     GPIOF_OUT_INIT_LOW, "Charger On" },
+};
+
 static void spitz_charger_init(void)
 {
-        pxa_gpio_mode(SPITZ_GPIO_KEY_INT | GPIO_IN);
-        pxa_gpio_mode(SPITZ_GPIO_SYNC | GPIO_IN);
+        gpio_request_array(ARRAY_AND_SIZE(spitz_charger_gpios));
 }
 
 static void spitz_measure_temp(int on)
@@ -76,6 +84,11 @@ static void spitz_discharge1(int on)
         gpio_set_value(SPITZ_GPIO_LED_GREEN, on);
 }
 
+static unsigned long gpio18_config[] = {
+        GPIO18_RDY,
+        GPIO18_GPIO,
+};
+
 static void spitz_presuspend(void)
 {
         spitz_last_ac_status = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
@@ -97,7 +110,9 @@ static void spitz_presuspend(void)
         PGSR3 &= ~SPITZ_GPIO_G3_STROBE_BIT;
         PGSR2 |= GPIO_bit(SPITZ_GPIO_KEY_STROBE0);
 
-        pxa_gpio_mode(GPIO18_RDY|GPIO_OUT | GPIO_DFLT_HIGH);
+        pxa2xx_mfp_config(&gpio18_config[0], 1);
+        gpio_request_one(18, GPIOF_OUT_INIT_HIGH, "Unknown");
+        gpio_free(18);
 
         PRER = GPIO_bit(SPITZ_GPIO_KEY_INT);
         PFER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET);
@@ -114,8 +129,7 @@ static void spitz_presuspend(void)
 
 static void spitz_postsuspend(void)
 {
-        pxa_gpio_mode(GPIO18_RDY_MD);
-        pxa_gpio_mode(10 | GPIO_IN);
+        pxa2xx_mfp_config(&gpio18_config[1], 1);
 }
 
 static int spitz_should_wakeup(unsigned int resume_on_alarm)
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c
deleted file mode 100644
index a81d6dbf662d..000000000000
--- a/arch/arm/mach-pxa/ssp.c
+++ /dev/null
@@ -1,510 +0,0 @@
-/*
- *  linux/arch/arm/mach-pxa/ssp.c
- *
- *  based on linux/arch/arm/mach-sa1100/ssp.c by Russell King
- *
- *  Copyright (C) 2003 Russell King.
- *  Copyright (C) 2003 Wolfson Microelectronics PLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  PXA2xx SSP driver.  This provides the generic core for simple
- *  IO-based SSP applications and allows easy port setup for DMA access.
- *
- *  Author: Liam Girdwood <liam.girdwood@wolfsonmicro.com>
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <linux/mutex.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/ssp.h>
-#include <mach/regs-ssp.h>
-
-#ifdef CONFIG_PXA_SSP_LEGACY
-
-#define TIMEOUT 100000
-
-static irqreturn_t ssp_interrupt(int irq, void *dev_id)
-{
-        struct ssp_dev *dev = dev_id;
-        struct ssp_device *ssp = dev->ssp;
-        unsigned int status;
-
-        status = __raw_readl(ssp->mmio_base + SSSR);
-        __raw_writel(status, ssp->mmio_base + SSSR);
-
-        if (status & SSSR_ROR)
-                printk(KERN_WARNING "SSP(%d): receiver overrun\n", dev->port);
-
-        if (status & SSSR_TUR)
-                printk(KERN_WARNING "SSP(%d): transmitter underrun\n", dev->port);
-
-        if (status & SSSR_BCE)
-                printk(KERN_WARNING "SSP(%d): bit count error\n", dev->port);
-
-        return IRQ_HANDLED;
-}
-
-/**
- * ssp_write_word - write a word to the SSP port
- * @data: 32-bit, MSB justified data to write.
- *
- * Wait for a free entry in the SSP transmit FIFO, and write a data
- * word to the SSP port.
- *
- * The caller is expected to perform the necessary locking.
- *
- * Returns:
- *   %-ETIMEDOUT        timeout occurred
- *   0                  success
- */
-int ssp_write_word(struct ssp_dev *dev, u32 data)
-{
-        struct ssp_device *ssp = dev->ssp;
-        int timeout = TIMEOUT;
-
-        while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_TNF)) {
-                if (!--timeout)
-                        return -ETIMEDOUT;
-                cpu_relax();
-        }
-
-        __raw_writel(data, ssp->mmio_base + SSDR);
-
-        return 0;
-}
-
-/**
- * ssp_read_word - read a word from the SSP port
- *
- * Wait for a data word in the SSP receive FIFO, and return the
- * received data.  Data is LSB justified.
- *
- * Note: Currently, if data is not expected to be received, this
- * function will wait for ever.
- *
- * The caller is expected to perform the necessary locking.
- *
- * Returns:
- *   %-ETIMEDOUT        timeout occurred
- *   32-bit data        success
- */
-int ssp_read_word(struct ssp_dev *dev, u32 *data)
-{
-        struct ssp_device *ssp = dev->ssp;
-        int timeout = TIMEOUT;
-
-        while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE)) {
-                if (!--timeout)
-                        return -ETIMEDOUT;
-                cpu_relax();
-        }
-
-        *data = __raw_readl(ssp->mmio_base + SSDR);
-        return 0;
-}
-
-/**
- * ssp_flush - flush the transmit and receive FIFOs
- *
- * Wait for the SSP to idle, and ensure that the receive FIFO
- * is empty.
- *
- * The caller is expected to perform the necessary locking.
- */
-int ssp_flush(struct ssp_dev *dev)
-{
-        struct ssp_device *ssp = dev->ssp;
-        int timeout = TIMEOUT * 2;
-
-        /* ensure TX FIFO is empty instead of not full */
-        if (cpu_is_pxa3xx()) {
-                while (__raw_readl(ssp->mmio_base + SSSR) & 0xf00) {
-                        if (!--timeout)
-                                return -ETIMEDOUT;
-                        cpu_relax();
-                }
-                timeout = TIMEOUT * 2;
-        }
-
-        do {
-                while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE) {
-                        if (!--timeout)
-                                return -ETIMEDOUT;
-                        (void)__raw_readl(ssp->mmio_base + SSDR);
-                }
-                if (!--timeout)
-                        return -ETIMEDOUT;
-        } while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_BSY);
-
-        return 0;
-}
-
-/**
- * ssp_enable - enable the SSP port
- *
- * Turn on the SSP port.
- */
-void ssp_enable(struct ssp_dev *dev)
-{
-        struct ssp_device *ssp = dev->ssp;
-        uint32_t sscr0;
-
-        sscr0 = __raw_readl(ssp->mmio_base + SSCR0);
-        sscr0 |= SSCR0_SSE;
-        __raw_writel(sscr0, ssp->mmio_base + SSCR0);
-}
-
-/**
- * ssp_disable - shut down the SSP port
- *
- * Turn off the SSP port, optionally powering it down.
- */
-void ssp_disable(struct ssp_dev *dev)
-{
-        struct ssp_device *ssp = dev->ssp;
-        uint32_t sscr0;
-
-        sscr0 = __raw_readl(ssp->mmio_base + SSCR0);
-        sscr0 &= ~SSCR0_SSE;
-        __raw_writel(sscr0, ssp->mmio_base + SSCR0);
-}
-
-/**
- * ssp_save_state - save the SSP configuration
- * @ssp: pointer to structure to save SSP configuration
- *
- * Save the configured SSP state for suspend.
- */
-void ssp_save_state(struct ssp_dev *dev, struct ssp_state *state)
-{
-        struct ssp_device *ssp = dev->ssp;
-
-        state->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
-        state->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
-        state->to  = __raw_readl(ssp->mmio_base + SSTO);
-        state->psp = __raw_readl(ssp->mmio_base + SSPSP);
-
-        ssp_disable(dev);
-}
-
-/**
- * ssp_restore_state - restore a previously saved SSP configuration
- * @ssp: pointer to configuration saved by ssp_save_state
- *
- * Restore the SSP configuration saved previously by ssp_save_state.
- */
-void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *state)
-{
-        struct ssp_device *ssp = dev->ssp;
-        uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
-
-        __raw_writel(sssr, ssp->mmio_base + SSSR);
-
-        __raw_writel(state->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
-        __raw_writel(state->cr1, ssp->mmio_base + SSCR1);
-        __raw_writel(state->to,  ssp->mmio_base + SSTO);
-        __raw_writel(state->psp, ssp->mmio_base + SSPSP);
-        __raw_writel(state->cr0, ssp->mmio_base + SSCR0);
-}
-
-/**
- * ssp_config - configure SSP port settings
- * @mode: port operating mode
- * @flags: port config flags
- * @psp_flags: port PSP config flags
- * @speed: port speed
- *
- * Port MUST be disabled by ssp_disable before making any config changes.
- */
-int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed)
-{
-        struct ssp_device *ssp = dev->ssp;
-
-        dev->mode = mode;
-        dev->flags = flags;
-        dev->psp_flags = psp_flags;
-        dev->speed = speed;
-
-        /* set up port type, speed, port settings */
-        __raw_writel((dev->speed | dev->mode), ssp->mmio_base + SSCR0);
-        __raw_writel(dev->flags, ssp->mmio_base + SSCR1);
-        __raw_writel(dev->psp_flags, ssp->mmio_base + SSPSP);
-
-        return 0;
-}
-
-/**
- * ssp_init - setup the SSP port
- *
- * initialise and claim resources for the SSP port.
- *
- * Returns:
- *   %-ENODEV   if the SSP port is unavailable
- *   %-EBUSY    if the resources are already in use
- *   %0         on success
- */
-int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags)
-{
-        struct ssp_device *ssp;
-        int ret;
-
-        ssp = ssp_request(port, "SSP");
-        if (ssp == NULL)
-                return -ENODEV;
-
-        dev->ssp = ssp;
-        dev->port = port;
-
-        /* do we need to get irq */
-        if (!(init_flags & SSP_NO_IRQ)) {
-                ret = request_irq(ssp->irq, ssp_interrupt,
-                                0, "SSP", dev);
-                if (ret)
-                        goto out_region;
-                dev->irq = ssp->irq;
-        } else
-                dev->irq = NO_IRQ;
-
-        /* turn on SSP port clock */
-        clk_enable(ssp->clk);
-        return 0;
-
-out_region:
-        ssp_free(ssp);
-        return ret;
-}
-
-/**
- * ssp_exit - undo the effects of ssp_init
- *
- * release and free resources for the SSP port.
- */
-void ssp_exit(struct ssp_dev *dev)
-{
-        struct ssp_device *ssp = dev->ssp;
-
-        ssp_disable(dev);
-        if (dev->irq != NO_IRQ)
-                free_irq(dev->irq, dev);
-        clk_disable(ssp->clk);
-        ssp_free(ssp);
-}
-#endif /* CONFIG_PXA_SSP_LEGACY */
-
-static DEFINE_MUTEX(ssp_lock);
-static LIST_HEAD(ssp_list);
-
-struct ssp_device *ssp_request(int port, const char *label)
-{
-        struct ssp_device *ssp = NULL;
-
-        mutex_lock(&ssp_lock);
-
-        list_for_each_entry(ssp, &ssp_list, node) {
-                if (ssp->port_id == port && ssp->use_count == 0) {
-                        ssp->use_count++;
-                        ssp->label = label;
-                        break;
-                }
-        }
-
-        mutex_unlock(&ssp_lock);
-
-        if (&ssp->node == &ssp_list)
-                return NULL;
-
-        return ssp;
-}
-EXPORT_SYMBOL(ssp_request);
-
-void ssp_free(struct ssp_device *ssp)
-{
-        mutex_lock(&ssp_lock);
-        if (ssp->use_count) {
-                ssp->use_count--;
-                ssp->label = NULL;
-        } else
-                dev_err(&ssp->pdev->dev, "device already free\n");
-        mutex_unlock(&ssp_lock);
-}
-EXPORT_SYMBOL(ssp_free);
-
-static int __devinit ssp_probe(struct platform_device *pdev)
-{
-        const struct platform_device_id *id = platform_get_device_id(pdev);
-        struct resource *res;
-        struct ssp_device *ssp;
-        int ret = 0;
-
-        ssp = kzalloc(sizeof(struct ssp_device), GFP_KERNEL);
-        if (ssp == NULL) {
-                dev_err(&pdev->dev, "failed to allocate memory");
-                return -ENOMEM;
-        }
-        ssp->pdev = pdev;
-
-        ssp->clk = clk_get(&pdev->dev, NULL);
-        if (IS_ERR(ssp->clk)) {
-                ret = PTR_ERR(ssp->clk);
-                goto err_free;
-        }
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (res == NULL) {
-                dev_err(&pdev->dev, "no memory resource defined\n");
-                ret = -ENODEV;
-                goto err_free_clk;
-        }
-
-        res = request_mem_region(res->start, res->end - res->start + 1,
-                        pdev->name);
-        if (res == NULL) {
-                dev_err(&pdev->dev, "failed to request memory resource\n");
-                ret = -EBUSY;
-                goto err_free_clk;
-        }
-
-        ssp->phys_base = res->start;
-
-        ssp->mmio_base = ioremap(res->start, res->end - res->start + 1);
-        if (ssp->mmio_base == NULL) {
-                dev_err(&pdev->dev, "failed to ioremap() registers\n");
-                ret = -ENODEV;
-                goto err_free_mem;
-        }
-
-        ssp->irq = platform_get_irq(pdev, 0);
-        if (ssp->irq < 0) {
-                dev_err(&pdev->dev, "no IRQ resource defined\n");
-                ret = -ENODEV;
-                goto err_free_io;
-        }
-
-        res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
-        if (res == NULL) {
-                dev_err(&pdev->dev, "no SSP RX DRCMR defined\n");
-                ret = -ENODEV;
-                goto err_free_io;
-        }
-        ssp->drcmr_rx = res->start;
-
-        res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
-        if (res == NULL) {
-                dev_err(&pdev->dev, "no SSP TX DRCMR defined\n");
-                ret = -ENODEV;
-                goto err_free_io;
-        }
-        ssp->drcmr_tx = res->start;
-
-        /* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id
-         * starts from 0, do a translation here
-         */
-        ssp->port_id = pdev->id + 1;
-        ssp->use_count = 0;
-        ssp->type = (int)id->driver_data;
-
-        mutex_lock(&ssp_lock);
-        list_add(&ssp->node, &ssp_list);
-        mutex_unlock(&ssp_lock);
-
-        platform_set_drvdata(pdev, ssp);
-        return 0;
-
-err_free_io:
-        iounmap(ssp->mmio_base);
-err_free_mem:
-        release_mem_region(res->start, res->end - res->start + 1);
-err_free_clk:
-        clk_put(ssp->clk);
-err_free:
-        kfree(ssp);
-        return ret;
-}
-
-static int __devexit ssp_remove(struct platform_device *pdev)
-{
-        struct resource *res;
-        struct ssp_device *ssp;
-
-        ssp = platform_get_drvdata(pdev);
-        if (ssp == NULL)
-                return -ENODEV;
-
-        iounmap(ssp->mmio_base);
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        release_mem_region(res->start, res->end - res->start + 1);
-
-        clk_put(ssp->clk);
-
-        mutex_lock(&ssp_lock);
-        list_del(&ssp->node);
-        mutex_unlock(&ssp_lock);
-
-        kfree(ssp);
-        return 0;
-}
-
-static const struct platform_device_id ssp_id_table[] = {
-        { "pxa25x-ssp",         PXA25x_SSP },
-        { "pxa25x-nssp",        PXA25x_NSSP },
-        { "pxa27x-ssp",         PXA27x_SSP },
-        { },
-};
-
-static struct platform_driver ssp_driver = {
-        .probe          = ssp_probe,
-        .remove         = __devexit_p(ssp_remove),
-        .driver         = {
-                .owner  = THIS_MODULE,
-                .name   = "pxa2xx-ssp",
-        },
-        .id_table       = ssp_id_table,
-};
-
-static int __init pxa_ssp_init(void)
-{
-        return platform_driver_register(&ssp_driver);
-}
-
-static void __exit pxa_ssp_exit(void)
-{
-        platform_driver_unregister(&ssp_driver);
-}
-
-arch_initcall(pxa_ssp_init);
-module_exit(pxa_ssp_exit);
-
-#ifdef CONFIG_PXA_SSP_LEGACY
-EXPORT_SYMBOL(ssp_write_word);
-EXPORT_SYMBOL(ssp_read_word);
-EXPORT_SYMBOL(ssp_flush);
-EXPORT_SYMBOL(ssp_enable);
-EXPORT_SYMBOL(ssp_disable);
-EXPORT_SYMBOL(ssp_save_state);
-EXPORT_SYMBOL(ssp_restore_state);
-EXPORT_SYMBOL(ssp_init);
-EXPORT_SYMBOL(ssp_exit);
-EXPORT_SYMBOL(ssp_config);
-#endif
-
-MODULE_DESCRIPTION("PXA SSP driver");
-MODULE_AUTHOR("Liam Girdwood");
-MODULE_LICENSE("GPL");
-
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index a98a434f0111..af40d2a12d37 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -464,8 +464,6 @@ static struct platform_device smc91x_device = {
 
 
 
-static struct pxamci_platform_data stargate2_mci_platform_data;
-
 /*
  * The card detect interrupt isn't debounced so we delay it by 250ms
  * to give the card a chance to fully insert / eject.
@@ -489,8 +487,6 @@ static int stargate2_mci_init(struct device *dev,
                 goto free_power_en;
         }
         gpio_direction_input(SG2_GPIO_nSD_DETECT);
-        /* Delay to allow for full insertion */
-        stargate2_mci_platform_data.detect_delay = msecs_to_jiffies(250);
 
         err = request_irq(IRQ_GPIO(SG2_GPIO_nSD_DETECT),
                           stargate2_detect_int,
@@ -529,6 +525,7 @@ static void stargate2_mci_exit(struct device *dev, void *data)
 }
 
 static struct pxamci_platform_data stargate2_mci_platform_data = {
+        .detect_delay_ms = 250,
         .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
         .init = stargate2_mci_init,
         .setpower = stargate2_mci_setpower,
@@ -764,11 +761,6 @@ static void __init stargate2_init(void)
         pxa_set_btuart_info(NULL);
         pxa_set_stuart_info(NULL);
 
-        /* spi chip selects */
-        gpio_direction_output(37, 0);
-        gpio_direction_output(24, 0);
-        gpio_direction_output(39, 0);
-
         platform_add_devices(ARRAY_AND_SIZE(stargate2_devices));
 
         pxa2xx_set_spi_info(1, &pxa_ssp_master_0_info);
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index ad552791c4ce..7512b822c6ca 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -275,6 +275,7 @@ static void tosa_mci_exit(struct device *dev, void *data)
 }
 
 static struct pxamci_platform_data tosa_mci_platform_data = {
+        .detect_delay_ms        = 250,
         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
         .init                   = tosa_mci_init,
         .exit                   = tosa_mci_exit,
@@ -926,7 +927,6 @@ static void __init tosa_init(void)
         dummy = gpiochip_reserve(TOSA_SCOOP_JC_GPIO_BASE, 12);
         dummy = gpiochip_reserve(TOSA_TC6393XB_GPIO_BASE, 16);
 
-        tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250);
         pxa_set_mci_info(&tosa_mci_platform_data);
         pxa_set_udc_info(&udc_info);
         pxa_set_ficp_info(&tosa_ficp_platform_data);
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 797f2544d0ce..69689112eae7 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -349,7 +349,7 @@ static void trizeps4_mci_exit(struct device *dev, void *data)
 
 static struct pxamci_platform_data trizeps4_mci_platform_data = {
         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
-        .detect_delay   = 1,
+        .detect_delay_ms= 10,
         .init           = trizeps4_mci_init,
         .exit           = trizeps4_mci_exit,
         .get_ro         = NULL, /* write-protection not supported */
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 1dd13346f977..e90114a7e246 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -27,12 +27,14 @@
 #include <linux/delay.h>
 #include <linux/fs.h>
 #include <linux/init.h>
+#include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/major.h>
 #include <linux/module.h>
 #include <linux/pm.h>
 #include <linux/sched.h>
 #include <linux/gpio.h>
+#include <linux/jiffies.h>
 #include <linux/i2c-gpio.h>
 #include <linux/serial_8250.h>
 #include <linux/smc91x.h>
@@ -453,7 +455,7 @@ static struct i2c_gpio_platform_data i2c_bus_data = {
         .sda_pin = VIPER_RTC_I2C_SDA_GPIO,
         .scl_pin = VIPER_RTC_I2C_SCL_GPIO,
         .udelay  = 10,
-        .timeout = 100,
+        .timeout = HZ,
 };
 
 static struct platform_device i2c_bus_device = {
@@ -778,7 +780,7 @@ static void __init viper_tpm_init(void)
                 .sda_pin = VIPER_TPM_I2C_SDA_GPIO,
                 .scl_pin = VIPER_TPM_I2C_SCL_GPIO,
                 .udelay  = 10,
-                .timeout = 100,
+                .timeout = HZ,
         };
         char *errstr;
 
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
new file mode 100644
index 000000000000..9884fa978f16
--- /dev/null
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -0,0 +1,615 @@
+/*
+ * Hardware definitions for Voipac PXA270
+ *
+ * Copyright (C) 2010
+ * Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/gpio.h>
+#include <linux/sysdev.h>
+#include <linux/usb/gpio_vbus.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/onenand.h>
+#include <linux/dm9000.h>
+#include <linux/ucb1400.h>
+#include <linux/ata_platform.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/pxa27x.h>
+#include <mach/audio.h>
+#include <mach/vpac270.h>
+#include <mach/mmc.h>
+#include <mach/pxafb.h>
+#include <mach/ohci.h>
+#include <mach/pxa27x-udc.h>
+#include <mach/udc.h>
+
+#include <plat/i2c.h>
+
+#include "generic.h"
+#include "devices.h"
+
+/******************************************************************************
+ * Pin configuration
+ ******************************************************************************/
+static unsigned long vpac270_pin_config[] __initdata = {
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+        GPIO53_GPIO,    /* SD detect */
+        GPIO52_GPIO,    /* SD r/o switch */
+
+        /* GPIO KEYS */
+        GPIO1_GPIO,     /* USER BTN */
+
+        /* LEDs */
+        GPIO15_GPIO,    /* orange led */
+
+        /* FFUART */
+        GPIO34_FFUART_RXD,
+        GPIO39_FFUART_TXD,
+        GPIO27_FFUART_RTS,
+        GPIO100_FFUART_CTS,
+        GPIO33_FFUART_DSR,
+        GPIO40_FFUART_DTR,
+        GPIO10_FFUART_DCD,
+        GPIO38_FFUART_RI,
+
+        /* LCD */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO86_LCD_LDD_16,
+        GPIO87_LCD_LDD_17,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+        GPIO77_LCD_BIAS,
+
+        /* PCMCIA */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO85_nPCE_1,
+        GPIO54_nPCE_2,
+        GPIO55_nPREG,
+        GPIO57_nIOIS16,
+        GPIO56_nPWAIT,
+        GPIO104_PSKTSEL,
+        GPIO84_GPIO,    /* PCMCIA CD */
+        GPIO35_GPIO,    /* PCMCIA RDY */
+        GPIO107_GPIO,   /* PCMCIA PPEN */
+        GPIO11_GPIO,    /* PCMCIA RESET */
+        GPIO17_GPIO,    /* CF CD */
+        GPIO12_GPIO,    /* CF RDY */
+        GPIO16_GPIO,    /* CF RESET */
+
+        /* UHC */
+        GPIO88_USBH1_PWR,
+        GPIO89_USBH1_PEN,
+        GPIO119_USBH2_PWR,
+        GPIO120_USBH2_PEN,
+
+        /* UDC */
+        GPIO41_GPIO,
+
+        /* Ethernet */
+        GPIO114_GPIO,   /* IRQ */
+
+        /* AC97 */
+        GPIO28_AC97_BITCLK,
+        GPIO29_AC97_SDATA_IN_0,
+        GPIO30_AC97_SDATA_OUT,
+        GPIO31_AC97_SYNC,
+        GPIO95_AC97_nRESET,
+        GPIO98_AC97_SYSCLK,
+        GPIO113_GPIO,   /* TS IRQ */
+
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+
+        /* IDE */
+        GPIO36_GPIO,    /* IDE IRQ */
+        GPIO80_DREQ_1,
+};
+
+/******************************************************************************
+ * NOR Flash
+ ******************************************************************************/
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static struct mtd_partition vpac270_nor_partitions[] = {
+        {
+                .name           = "Flash",
+                .offset         = 0x00000000,
+                .size           = MTDPART_SIZ_FULL,
+        }
+};
+
+static struct physmap_flash_data vpac270_flash_data[] = {
+        {
+                .width          = 2,    /* bankwidth in bytes */
+                .parts          = vpac270_nor_partitions,
+                .nr_parts       = ARRAY_SIZE(vpac270_nor_partitions)
+        }
+};
+
+static struct resource vpac270_flash_resource = {
+        .start  = PXA_CS0_PHYS,
+        .end    = PXA_CS0_PHYS + SZ_64M - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device vpac270_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .resource       = &vpac270_flash_resource,
+        .num_resources  = 1,
+        .dev            = {
+                .platform_data = vpac270_flash_data,
+        },
+};
+static void __init vpac270_nor_init(void)
+{
+        platform_device_register(&vpac270_flash);
+}
+#else
+static inline void vpac270_nor_init(void) {}
+#endif
+
+/******************************************************************************
+ * OneNAND Flash
+ ******************************************************************************/
+#if defined(CONFIG_MTD_ONENAND) || defined(CONFIG_MTD_ONENAND_MODULE)
+static struct mtd_partition vpac270_onenand_partitions[] = {
+        {
+                .name           = "Flash",
+                .offset         = 0x00000000,
+                .size           = MTDPART_SIZ_FULL,
+        }
+};
+
+static struct onenand_platform_data vpac270_onenand_info = {
+        .parts          = vpac270_onenand_partitions,
+        .nr_parts       = ARRAY_SIZE(vpac270_onenand_partitions),
+};
+
+static struct resource vpac270_onenand_resources[] = {
+        [0] = {
+                .start  = PXA_CS0_PHYS,
+                .end    = PXA_CS0_PHYS + SZ_1M,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device vpac270_onenand = {
+        .name           = "onenand-flash",
+        .id             = -1,
+        .resource       = vpac270_onenand_resources,
+        .num_resources  = ARRAY_SIZE(vpac270_onenand_resources),
+        .dev            = {
+                .platform_data  = &vpac270_onenand_info,
+        },
+};
+
+static void __init vpac270_onenand_init(void)
+{
+        platform_device_register(&vpac270_onenand);
+}
+#else
+static void __init vpac270_onenand_init(void) {}
+#endif
+
+/******************************************************************************
+ * SD/MMC card controller
+ ******************************************************************************/
+#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
+static struct pxamci_platform_data vpac270_mci_platform_data = {
+        .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
+        .gpio_card_detect       = GPIO53_VPAC270_SD_DETECT_N,
+        .gpio_card_ro           = GPIO52_VPAC270_SD_READONLY,
+        .detect_delay_ms        = 200,
+};
+
+static void __init vpac270_mmc_init(void)
+{
+        pxa_set_mci_info(&vpac270_mci_platform_data);
+}
+#else
+static inline void vpac270_mmc_init(void) {}
+#endif
+
+/******************************************************************************
+ * GPIO keys
+ ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button vpac270_pxa_buttons[] = {
+        {KEY_POWER, GPIO1_VPAC270_USER_BTN, 0, "USER BTN"},
+};
+
+static struct gpio_keys_platform_data vpac270_pxa_keys_data = {
+        .buttons        = vpac270_pxa_buttons,
+        .nbuttons       = ARRAY_SIZE(vpac270_pxa_buttons),
+};
+
+static struct platform_device vpac270_pxa_keys = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &vpac270_pxa_keys_data,
+        },
+};
+
+static void __init vpac270_keys_init(void)
+{
+        platform_device_register(&vpac270_pxa_keys);
+}
+#else
+static inline void vpac270_keys_init(void) {}
+#endif
+
+/******************************************************************************
+ * LED
+ ******************************************************************************/
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+struct gpio_led vpac270_gpio_leds[] = {
+{
+        .name                   = "vpac270:orange:user",
+        .default_trigger        = "none",
+        .gpio                   = GPIO15_VPAC270_LED_ORANGE,
+        .active_low             = 1,
+}
+};
+
+static struct gpio_led_platform_data vpac270_gpio_led_info = {
+        .leds           = vpac270_gpio_leds,
+        .num_leds       = ARRAY_SIZE(vpac270_gpio_leds),
+};
+
+static struct platform_device vpac270_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &vpac270_gpio_led_info,
+        }
+};
+
+static void __init vpac270_leds_init(void)
+{
+        platform_device_register(&vpac270_leds);
+}
+#else
+static inline void vpac270_leds_init(void) {}
+#endif
+
+/******************************************************************************
+ * USB Host
+ ******************************************************************************/
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static int vpac270_ohci_init(struct device *dev)
+{
+        UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
+        return 0;
+}
+
+static struct pxaohci_platform_data vpac270_ohci_info = {
+        .port_mode      = PMM_PERPORT_MODE,
+        .flags          = ENABLE_PORT1 | ENABLE_PORT2 |
+                        POWER_CONTROL_LOW | POWER_SENSE_LOW,
+        .init           = vpac270_ohci_init,
+};
+
+static void __init vpac270_uhc_init(void)
+{
+        pxa_set_ohci_info(&vpac270_ohci_info);
+}
+#else
+static inline void vpac270_uhc_init(void) {}
+#endif
+
+/******************************************************************************
+ * USB Gadget
+ ******************************************************************************/
+#if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE)
+static struct gpio_vbus_mach_info vpac270_gpio_vbus_info = {
+        .gpio_vbus              = GPIO41_VPAC270_UDC_DETECT,
+        .gpio_pullup            = -1,
+};
+
+static struct platform_device vpac270_gpio_vbus = {
+        .name   = "gpio-vbus",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &vpac270_gpio_vbus_info,
+        },
+};
+
+static void vpac270_udc_command(int cmd)
+{
+        if (cmd == PXA2XX_UDC_CMD_CONNECT)
+                UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
+        else if (cmd == PXA2XX_UDC_CMD_DISCONNECT)
+                UP2OCR = UP2OCR_HXOE;
+}
+
+static struct pxa2xx_udc_mach_info vpac270_udc_info __initdata = {
+        .udc_command            = vpac270_udc_command,
+        .gpio_pullup            = -1,
+};
+
+static void __init vpac270_udc_init(void)
+{
+        pxa_set_udc_info(&vpac270_udc_info);
+        platform_device_register(&vpac270_gpio_vbus);
+}
+#else
+static inline void vpac270_udc_init(void) {}
+#endif
+
+/******************************************************************************
+ * Ethernet
+ ******************************************************************************/
+#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+static struct resource vpac270_dm9000_resources[] = {
+        [0] = {
+                .start  = PXA_CS2_PHYS + 0x300,
+                .end    = PXA_CS2_PHYS + 0x303,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = PXA_CS2_PHYS + 0x304,
+                .end    = PXA_CS2_PHYS + 0x343,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = IRQ_GPIO(GPIO114_VPAC270_ETH_IRQ),
+                .end    = IRQ_GPIO(GPIO114_VPAC270_ETH_IRQ),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        },
+};
+
+static struct dm9000_plat_data vpac270_dm9000_platdata = {
+        .flags          = DM9000_PLATF_32BITONLY,
+};
+
+static struct platform_device vpac270_dm9000_device = {
+        .name           = "dm9000",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(vpac270_dm9000_resources),
+        .resource       = vpac270_dm9000_resources,
+        .dev            = {
+                .platform_data = &vpac270_dm9000_platdata,
+        }
+};
+
+static void __init vpac270_eth_init(void)
+{
+        platform_device_register(&vpac270_dm9000_device);
+}
+#else
+static inline void vpac270_eth_init(void) {}
+#endif
+
+/******************************************************************************
+ * Audio and Touchscreen
+ ******************************************************************************/
+#if     defined(CONFIG_TOUCHSCREEN_UCB1400) || \
+        defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
+static pxa2xx_audio_ops_t vpac270_ac97_pdata = {
+        .reset_gpio     = 95,
+};
+
+static struct ucb1400_pdata vpac270_ucb1400_pdata = {
+        .irq            = IRQ_GPIO(GPIO113_VPAC270_TS_IRQ),
+};
+
+static struct platform_device vpac270_ucb1400_device = {
+        .name           = "ucb1400_core",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &vpac270_ucb1400_pdata,
+        },
+};
+
+static void __init vpac270_ts_init(void)
+{
+        pxa_set_ac97_info(&vpac270_ac97_pdata);
+        platform_device_register(&vpac270_ucb1400_device);
+}
+#else
+static inline void vpac270_ts_init(void) {}
+#endif
+
+/******************************************************************************
+ * RTC
+ ******************************************************************************/
+#if defined(CONFIG_RTC_DRV_DS1307) || defined(CONFIG_RTC_DRV_DS1307_MODULE)
+static struct i2c_board_info __initdata vpac270_i2c_devs[] = {
+        {
+                I2C_BOARD_INFO("ds1339", 0x68),
+        },
+};
+
+static void __init vpac270_rtc_init(void)
+{
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(vpac270_i2c_devs));
+}
+#else
+static inline void vpac270_rtc_init(void) {}
+#endif
+
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static struct pxafb_mode_info vpac270_lcd_modes[] = {
+{
+        .pixclock       = 57692,
+        .xres           = 640,
+        .yres           = 480,
+        .bpp            = 32,
+        .depth          = 18,
+
+        .left_margin    = 144,
+        .right_margin   = 32,
+        .upper_margin   = 13,
+        .lower_margin   = 30,
+
+        .hsync_len      = 32,
+        .vsync_len      = 2,
+
+        .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+},
+};
+
+static struct pxafb_mach_info vpac270_lcd_screen = {
+        .modes          = vpac270_lcd_modes,
+        .num_modes      = ARRAY_SIZE(vpac270_lcd_modes),
+        .lcd_conn       = LCD_COLOR_TFT_18BPP,
+};
+
+static void vpac270_lcd_power(int on, struct fb_var_screeninfo *info)
+{
+        gpio_set_value(GPIO81_VPAC270_BKL_ON, on);
+}
+
+static void __init vpac270_lcd_init(void)
+{
+        int ret;
+
+        ret = gpio_request(GPIO81_VPAC270_BKL_ON, "BKL-ON");
+        if (ret) {
+                pr_err("Requesting BKL-ON GPIO failed!\n");
+                goto err;
+        }
+
+        ret = gpio_direction_output(GPIO81_VPAC270_BKL_ON, 1);
+        if (ret) {
+                pr_err("Setting BKL-ON GPIO direction failed!\n");
+                goto err2;
+        }
+
+        vpac270_lcd_screen.pxafb_lcd_power = vpac270_lcd_power;
+        set_pxa_fb_info(&vpac270_lcd_screen);
+        return;
+
+err2:
+        gpio_free(GPIO81_VPAC270_BKL_ON);
+err:
+        return;
+}
+#else
+static inline void vpac270_lcd_init(void) {}
+#endif
+
+/******************************************************************************
+ * PATA IDE
+ ******************************************************************************/
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+static struct pata_platform_info vpac270_pata_pdata = {
+        .ioport_shift   = 1,
+        .irq_flags      = IRQF_TRIGGER_RISING,
+};
+
+static struct resource vpac270_ide_resources[] = {
+        [0] = { /* I/O Base address */
+               .start   = PXA_CS3_PHYS + 0x120,
+               .end     = PXA_CS3_PHYS + 0x13f,
+               .flags   = IORESOURCE_MEM
+        },
+        [1] = { /* CTL Base address */
+               .start   = PXA_CS3_PHYS + 0x15c,
+               .end     = PXA_CS3_PHYS + 0x15f,
+               .flags   = IORESOURCE_MEM
+        },
+        [2] = { /* IDE IRQ pin */
+               .start   = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ),
+               .end     = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ),
+               .flags   = IORESOURCE_IRQ
+        }
+};
+
+static struct platform_device vpac270_ide_device = {
+        .name           = "pata_platform",
+        .num_resources  = ARRAY_SIZE(vpac270_ide_resources),
+        .resource       = vpac270_ide_resources,
+        .dev            = {
+                .platform_data  = &vpac270_pata_pdata,
+        }
+};
+
+static void __init vpac270_ide_init(void)
+{
+        platform_device_register(&vpac270_ide_device);
+}
+#else
+static inline void vpac270_ide_init(void) {}
+#endif
+
+/******************************************************************************
+ * Machine init
+ ******************************************************************************/
+static void __init vpac270_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(vpac270_pin_config));
+
+        pxa_set_ffuart_info(NULL);
+        pxa_set_btuart_info(NULL);
+        pxa_set_stuart_info(NULL);
+
+        vpac270_lcd_init();
+        vpac270_mmc_init();
+        vpac270_nor_init();
+        vpac270_onenand_init();
+        vpac270_leds_init();
+        vpac270_keys_init();
+        vpac270_uhc_init();
+        vpac270_udc_init();
+        vpac270_eth_init();
+        vpac270_ts_init();
+        vpac270_rtc_init();
+        vpac270_ide_init();
+}
+
+MACHINE_START(VPAC270, "Voipac PXA270")
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa27x_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = vpac270_init
+MACHINE_END
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
new file mode 100644
index 000000000000..f5d1ae3db3a4
--- /dev/null
+++ b/arch/arm/mach-pxa/z2.c
@@ -0,0 +1,609 @@
+/*
+ *  linux/arch/arm/mach-pxa/z2.c
+ *
+ *  Support for the Zipit Z2 Handheld device.
+ *
+ *  Author:     Ken McGuire
+ *  Created:    Jan 25, 2009
+ *  Based on mainstone.c as modified for the Zipit Z2.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/pwm_backlight.h>
+#include <linux/dma-mapping.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/libertas_spi.h>
+#include <linux/spi/lms283gf05.h>
+#include <linux/power_supply.h>
+#include <linux/mtd/physmap.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/delay.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/pxa27x.h>
+#include <mach/mfp-pxa27x.h>
+#include <mach/z2.h>
+#include <mach/pxafb.h>
+#include <mach/mmc.h>
+#include <mach/pxa27x_keypad.h>
+#include <mach/pxa2xx_spi.h>
+
+#include <plat/i2c.h>
+
+#include "generic.h"
+#include "devices.h"
+
+/******************************************************************************
+ * Pin configuration
+ ******************************************************************************/
+static unsigned long z2_pin_config[] = {
+
+        /* LCD - 16bpp Active TFT */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+        GPIO77_LCD_BIAS,
+        GPIO19_GPIO,            /* LCD reset */
+        GPIO88_GPIO,            /* LCD chipselect */
+
+        /* PWM */
+        GPIO115_PWM1_OUT,       /* Keypad Backlight */
+        GPIO11_PWM2_OUT,        /* LCD Backlight */
+
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO112_MMC_CMD,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO96_GPIO,            /* SD detect */
+
+        /* STUART */
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
+
+        /* Keypad */
+        GPIO100_KP_MKIN_0       | WAKEUP_ON_LEVEL_HIGH,
+        GPIO101_KP_MKIN_1       | WAKEUP_ON_LEVEL_HIGH,
+        GPIO102_KP_MKIN_2       | WAKEUP_ON_LEVEL_HIGH,
+        GPIO34_KP_MKIN_3        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO38_KP_MKIN_4        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO16_KP_MKIN_5        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO17_KP_MKIN_6        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO103_KP_MKOUT_0,
+        GPIO104_KP_MKOUT_1,
+        GPIO105_KP_MKOUT_2,
+        GPIO106_KP_MKOUT_3,
+        GPIO107_KP_MKOUT_4,
+        GPIO108_KP_MKOUT_5,
+        GPIO35_KP_MKOUT_6,
+        GPIO41_KP_MKOUT_7,
+
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+
+        /* SSP1 */
+        GPIO23_SSP1_SCLK,       /* SSP1_SCK */
+        GPIO25_SSP1_TXD,        /* SSP1_TXD */
+        GPIO26_SSP1_RXD,        /* SSP1_RXD */
+
+        /* SSP2 */
+        GPIO22_SSP2_SCLK,       /* SSP2_SCK */
+        GPIO13_SSP2_TXD,        /* SSP2_TXD */
+        GPIO40_SSP2_RXD,        /* SSP2_RXD */
+
+        /* LEDs */
+        GPIO10_GPIO,            /* WiFi LED */
+        GPIO83_GPIO,            /* Charging LED */
+        GPIO85_GPIO,            /* Charged LED */
+
+        /* I2S */
+        GPIO28_I2S_BITCLK_OUT,
+        GPIO29_I2S_SDATA_IN,
+        GPIO30_I2S_SDATA_OUT,
+        GPIO31_I2S_SYNC,
+        GPIO113_I2S_SYSCLK,
+
+        /* MISC */
+        GPIO0_GPIO,             /* AC power detect */
+        GPIO1_GPIO,             /* Power button */
+        GPIO37_GPIO,            /* Headphone detect */
+        GPIO98_GPIO,            /* Lid switch */
+        GPIO14_GPIO,            /* WiFi Reset */
+        GPIO15_GPIO,            /* WiFi Power */
+        GPIO24_GPIO,            /* WiFi CS */
+        GPIO36_GPIO,            /* WiFi IRQ */
+        GPIO88_GPIO,            /* LCD CS */
+};
+
+/******************************************************************************
+ * NOR Flash
+ ******************************************************************************/
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static struct resource z2_flash_resource = {
+        .start  = PXA_CS0_PHYS,
+        .end    = PXA_CS0_PHYS + SZ_8M - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct mtd_partition z2_flash_parts[] = {
+        {
+                .name   = "U-Boot Bootloader",
+                .offset = 0x0,
+                .size   = 0x20000,
+        },
+        {
+                .name   = "Linux Kernel",
+                .offset = 0x20000,
+                .size   = 0x220000,
+        },
+        {
+                .name   = "Filesystem",
+                .offset = 0x240000,
+                .size   = 0x5b0000,
+        },
+        {
+                .name   = "U-Boot Environment",
+                .offset = 0x7f0000,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data z2_flash_data = {
+        .width          = 2,
+        .parts          = z2_flash_parts,
+        .nr_parts       = ARRAY_SIZE(z2_flash_parts),
+};
+
+static struct platform_device z2_flash = {
+        .name           = "physmap-flash",
+        .id             = -1,
+        .resource       = &z2_flash_resource,
+        .num_resources  = 1,
+        .dev = {
+                .platform_data  = &z2_flash_data,
+        },
+};
+
+static void __init z2_nor_init(void)
+{
+        platform_device_register(&z2_flash);
+}
+#else
+static inline void z2_nor_init(void) {}
+#endif
+
+/******************************************************************************
+ * Backlight
+ ******************************************************************************/
+#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
+static struct platform_pwm_backlight_data z2_backlight_data[] = {
+        [0] = {
+                /* Keypad Backlight */
+                .pwm_id         = 1,
+                .max_brightness = 1023,
+                .dft_brightness = 512,
+                .pwm_period_ns  = 1260320,
+        },
+        [1] = {
+                /* LCD Backlight */
+                .pwm_id         = 2,
+                .max_brightness = 1023,
+                .dft_brightness = 512,
+                .pwm_period_ns  = 1260320,
+        },
+};
+
+static struct platform_device z2_backlight_devices[2] = {
+        {
+                .name   = "pwm-backlight",
+                .id     = 0,
+                .dev    = {
+                        .platform_data  = &z2_backlight_data[1],
+                },
+        },
+        {
+                .name   = "pwm-backlight",
+                .id     = 1,
+                .dev    = {
+                        .platform_data  = &z2_backlight_data[0],
+                },
+        },
+};
+static void __init z2_pwm_init(void)
+{
+        platform_device_register(&z2_backlight_devices[0]);
+        platform_device_register(&z2_backlight_devices[1]);
+}
+#else
+static inline void z2_pwm_init(void) {}
+#endif
+
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static struct pxafb_mode_info z2_lcd_modes[] = {
+{
+        .pixclock       = 192000,
+        .xres           = 240,
+        .yres           = 320,
+        .bpp            = 16,
+
+        .left_margin    = 4,
+        .right_margin   = 8,
+        .upper_margin   = 4,
+        .lower_margin   = 8,
+
+        .hsync_len      = 4,
+        .vsync_len      = 4,
+},
+};
+
+static struct pxafb_mach_info z2_lcd_screen = {
+        .modes          = z2_lcd_modes,
+        .num_modes      = ARRAY_SIZE(z2_lcd_modes),
+        .lcd_conn       = LCD_COLOR_TFT_16BPP | LCD_BIAS_ACTIVE_LOW |
+                          LCD_ALTERNATE_MAPPING,
+};
+
+static void __init z2_lcd_init(void)
+{
+        set_pxa_fb_info(&z2_lcd_screen);
+}
+#else
+static inline void z2_lcd_init(void) {}
+#endif
+
+/******************************************************************************
+ * SD/MMC card controller
+ ******************************************************************************/
+#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
+static struct pxamci_platform_data z2_mci_platform_data = {
+        .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
+        .gpio_card_detect       = GPIO96_ZIPITZ2_SD_DETECT,
+        .gpio_power             = -1,
+        .gpio_card_ro           = -1,
+        .detect_delay_ms        = 200,
+};
+
+static void __init z2_mmc_init(void)
+{
+        pxa_set_mci_info(&z2_mci_platform_data);
+}
+#else
+static inline void z2_mmc_init(void) {}
+#endif
+
+/******************************************************************************
+ * LEDs
+ ******************************************************************************/
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+struct gpio_led z2_gpio_leds[] = {
+{
+        .name                   = "z2:green:wifi",
+        .default_trigger        = "none",
+        .gpio                   = GPIO10_ZIPITZ2_LED_WIFI,
+        .active_low             = 1,
+}, {
+        .name                   = "z2:green:charged",
+        .default_trigger        = "none",
+        .gpio                   = GPIO85_ZIPITZ2_LED_CHARGED,
+        .active_low             = 1,
+}, {
+        .name                   = "z2:amber:charging",
+        .default_trigger        = "none",
+        .gpio                   = GPIO83_ZIPITZ2_LED_CHARGING,
+        .active_low             = 1,
+},
+};
+
+static struct gpio_led_platform_data z2_gpio_led_info = {
+        .leds           = z2_gpio_leds,
+        .num_leds       = ARRAY_SIZE(z2_gpio_leds),
+};
+
+static struct platform_device z2_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &z2_gpio_led_info,
+        }
+};
+
+static void __init z2_leds_init(void)
+{
+        platform_device_register(&z2_leds);
+}
+#else
+static inline void z2_leds_init(void) {}
+#endif
+
+/******************************************************************************
+ * GPIO keyboard
+ ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
+static unsigned int z2_matrix_keys[] = {
+        KEY(0, 0, KEY_OPTION),
+        KEY(1, 0, KEY_UP),
+        KEY(2, 0, KEY_DOWN),
+        KEY(3, 0, KEY_LEFT),
+        KEY(4, 0, KEY_RIGHT),
+        KEY(5, 0, KEY_END),
+        KEY(6, 0, KEY_KPPLUS),
+
+        KEY(0, 1, KEY_HOME),
+        KEY(1, 1, KEY_Q),
+        KEY(2, 1, KEY_I),
+        KEY(3, 1, KEY_G),
+        KEY(4, 1, KEY_X),
+        KEY(5, 1, KEY_ENTER),
+        KEY(6, 1, KEY_KPMINUS),
+
+        KEY(0, 2, KEY_PAGEUP),
+        KEY(1, 2, KEY_W),
+        KEY(2, 2, KEY_O),
+        KEY(3, 2, KEY_H),
+        KEY(4, 2, KEY_C),
+        KEY(5, 2, KEY_LEFTALT),
+
+        KEY(0, 3, KEY_PAGEDOWN),
+        KEY(1, 3, KEY_E),
+        KEY(2, 3, KEY_P),
+        KEY(3, 3, KEY_J),
+        KEY(4, 3, KEY_V),
+        KEY(5, 3, KEY_LEFTSHIFT),
+
+        KEY(0, 4, KEY_ESC),
+        KEY(1, 4, KEY_R),
+        KEY(2, 4, KEY_A),
+        KEY(3, 4, KEY_K),
+        KEY(4, 4, KEY_B),
+        KEY(5, 4, KEY_LEFTCTRL),
+
+        KEY(0, 5, KEY_TAB),
+        KEY(1, 5, KEY_T),
+        KEY(2, 5, KEY_S),
+        KEY(3, 5, KEY_L),
+        KEY(4, 5, KEY_N),
+        KEY(5, 5, KEY_SPACE),
+
+        KEY(0, 6, KEY_STOPCD),
+        KEY(1, 6, KEY_Y),
+        KEY(2, 6, KEY_D),
+        KEY(3, 6, KEY_BACKSPACE),
+        KEY(4, 6, KEY_M),
+        KEY(5, 6, KEY_COMMA),
+
+        KEY(0, 7, KEY_PLAYCD),
+        KEY(1, 7, KEY_U),
+        KEY(2, 7, KEY_F),
+        KEY(3, 7, KEY_Z),
+        KEY(4, 7, KEY_SEMICOLON),
+        KEY(5, 7, KEY_DOT),
+};
+
+static struct pxa27x_keypad_platform_data z2_keypad_platform_data = {
+        .matrix_key_rows        = 7,
+        .matrix_key_cols        = 8,
+        .matrix_key_map         = z2_matrix_keys,
+        .matrix_key_map_size    = ARRAY_SIZE(z2_matrix_keys),
+
+        .debounce_interval      = 30,
+};
+
+static void __init z2_mkp_init(void)
+{
+        pxa_set_keypad_info(&z2_keypad_platform_data);
+}
+#else
+static inline void z2_mkp_init(void) {}
+#endif
+
+/******************************************************************************
+ * GPIO keys
+ ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button z2_pxa_buttons[] = {
+        {KEY_POWER, GPIO1_ZIPITZ2_POWER_BUTTON, 0, "Power Button" },
+        {KEY_CLOSE, GPIO98_ZIPITZ2_LID_BUTTON, 0, "Lid Button" },
+};
+
+static struct gpio_keys_platform_data z2_pxa_keys_data = {
+        .buttons        = z2_pxa_buttons,
+        .nbuttons       = ARRAY_SIZE(z2_pxa_buttons),
+};
+
+static struct platform_device z2_pxa_keys = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &z2_pxa_keys_data,
+        },
+};
+
+static void __init z2_keys_init(void)
+{
+        platform_device_register(&z2_pxa_keys);
+}
+#else
+static inline void z2_keys_init(void) {}
+#endif
+
+/******************************************************************************
+ * SSP Devices - WiFi and LCD control
+ ******************************************************************************/
+#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
+/* WiFi */
+static int z2_lbs_spi_setup(struct spi_device *spi)
+{
+        int ret = 0;
+
+        ret = gpio_request(GPIO15_ZIPITZ2_WIFI_POWER, "WiFi Power");
+        if (ret)
+                goto err;
+
+        ret = gpio_direction_output(GPIO15_ZIPITZ2_WIFI_POWER, 1);
+        if (ret)
+                goto err2;
+
+        ret = gpio_request(GPIO14_ZIPITZ2_WIFI_RESET, "WiFi Reset");
+        if (ret)
+                goto err2;
+
+        ret = gpio_direction_output(GPIO14_ZIPITZ2_WIFI_RESET, 0);
+        if (ret)
+                goto err3;
+
+        /* Reset the card */
+        mdelay(180);
+        gpio_set_value(GPIO14_ZIPITZ2_WIFI_RESET, 1);
+        mdelay(20);
+
+        spi->bits_per_word = 16;
+        spi->mode = SPI_MODE_2,
+
+        spi_setup(spi);
+
+        return 0;
+
+err3:
+        gpio_free(GPIO14_ZIPITZ2_WIFI_RESET);
+err2:
+        gpio_free(GPIO15_ZIPITZ2_WIFI_POWER);
+err:
+        return ret;
+};
+
+static int z2_lbs_spi_teardown(struct spi_device *spi)
+{
+        gpio_set_value(GPIO14_ZIPITZ2_WIFI_RESET, 0);
+        gpio_set_value(GPIO15_ZIPITZ2_WIFI_POWER, 0);
+        gpio_free(GPIO14_ZIPITZ2_WIFI_RESET);
+        gpio_free(GPIO15_ZIPITZ2_WIFI_POWER);
+        return 0;
+
+};
+
+static struct pxa2xx_spi_chip z2_lbs_chip_info = {
+        .rx_threshold   = 8,
+        .tx_threshold   = 8,
+        .timeout        = 1000,
+        .gpio_cs        = GPIO24_ZIPITZ2_WIFI_CS,
+};
+
+static struct libertas_spi_platform_data z2_lbs_pdata = {
+        .use_dummy_writes       = 1,
+        .setup                  = z2_lbs_spi_setup,
+        .teardown               = z2_lbs_spi_teardown,
+};
+
+/* LCD */
+static struct pxa2xx_spi_chip lms283_chip_info = {
+        .rx_threshold   = 1,
+        .tx_threshold   = 1,
+        .timeout        = 64,
+        .gpio_cs        = GPIO88_ZIPITZ2_LCD_CS,
+};
+
+static const struct lms283gf05_pdata lms283_pdata = {
+        .reset_gpio     = GPIO19_ZIPITZ2_LCD_RESET,
+};
+
+static struct spi_board_info spi_board_info[] __initdata = {
+{
+        .modalias               = "libertas_spi",
+        .platform_data          = &z2_lbs_pdata,
+        .controller_data        = &z2_lbs_chip_info,
+        .irq                    = gpio_to_irq(GPIO36_ZIPITZ2_WIFI_IRQ),
+        .max_speed_hz           = 13000000,
+        .bus_num                = 1,
+        .chip_select            = 0,
+},
+{
+        .modalias               = "lms283gf05",
+        .controller_data        = &lms283_chip_info,
+        .platform_data          = &lms283_pdata,
+        .max_speed_hz           = 400000,
+        .bus_num                = 2,
+        .chip_select            = 0,
+},
+};
+
+static struct pxa2xx_spi_master pxa_ssp1_master_info = {
+        .clock_enable   = CKEN_SSP,
+        .num_chipselect = 1,
+        .enable_dma     = 1,
+};
+
+static struct pxa2xx_spi_master pxa_ssp2_master_info = {
+        .clock_enable   = CKEN_SSP2,
+        .num_chipselect = 1,
+};
+
+static void __init z2_spi_init(void)
+{
+        pxa2xx_set_spi_info(1, &pxa_ssp1_master_info);
+        pxa2xx_set_spi_info(2, &pxa_ssp2_master_info);
+        spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+}
+#else
+static inline void z2_spi_init(void) {}
+#endif
+
+/******************************************************************************
+ * Machine init
+ ******************************************************************************/
+static void __init z2_init(void)
+{
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(z2_pin_config));
+
+        z2_lcd_init();
+        z2_mmc_init();
+        z2_mkp_init();
+
+        pxa_set_i2c_info(NULL);
+
+        z2_spi_init();
+        z2_nor_init();
+        z2_pwm_init();
+        z2_leds_init();
+        z2_keys_init();
+}
+
+MACHINE_START(ZIPIT2, "Zipit Z2")
+        .phys_io        = 0x40000000,
+        .boot_params    = 0xa0000100,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa27x_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = z2_init,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 39896d883584..3680f6a90623 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -644,7 +644,7 @@ static struct pxafb_mach_info zeus_fb_info = {
 
 static struct pxamci_platform_data zeus_mci_platform_data = {
         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
-        .detect_delay           = HZ/4,
+        .detect_delay_ms        = 250,
         .gpio_card_detect       = ZEUS_MMC_CD_GPIO,
         .gpio_card_ro           = ZEUS_MMC_WP_GPIO,
         .gpio_card_ro_invert    = 1,
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 2b4043c04d0c..c479cbecf784 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -218,7 +218,7 @@ static inline void zylonite_init_lcd(void) {}
 
 #if defined(CONFIG_MMC)
 static struct pxamci_platform_data zylonite_mci_platform_data = {
-        .detect_delay   = 20,
+        .detect_delay_ms= 200,
         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
         .gpio_card_detect = EXT_GPIO(0),
         .gpio_card_ro   = EXT_GPIO(2),
@@ -226,7 +226,7 @@ static struct pxamci_platform_data zylonite_mci_platform_data = {
 };
 
 static struct pxamci_platform_data zylonite_mci2_platform_data = {
-        .detect_delay   = 20,
+        .detect_delay_ms= 200,
         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
         .gpio_card_detect = EXT_GPIO(1),
         .gpio_card_ro   = EXT_GPIO(3),
@@ -234,7 +234,7 @@ static struct pxamci_platform_data zylonite_mci2_platform_data = {
 };
 
 static struct pxamci_platform_data zylonite_mci3_platform_data = {
-        .detect_delay   = 20,
+        .detect_delay_ms= 200,
         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
         .gpio_card_detect = EXT_GPIO(30),
         .gpio_card_ro   = EXT_GPIO(31),
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 1b468bd490af..595be19f8ad5 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -29,6 +29,7 @@
 #include <linux/smsc911x.h>
 #include <linux/ata_platform.h>
 #include <linux/amba/mmci.h>
+#include <linux/gfp.h>
 
 #include <asm/clkdev.h>
 #include <asm/system.h>
@@ -236,7 +237,7 @@ static unsigned int realview_mmc_status(struct device *dev)
         else
                 mask = 2;
 
-        return readl(REALVIEW_SYSMCI) & mask;
+        return !(readl(REALVIEW_SYSMCI) & mask);
 }
 
 struct mmci_platform_data realview_mmc0_plat_data = {
diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c
index c47d974d52bd..85883b2e0e49 100644
--- a/arch/arm/mach-rpc/dma.c
+++ b/arch/arm/mach-rpc/dma.c
@@ -9,7 +9,6 @@
  *
  *  DMA functions specific to RiscPC architecture
  */
-#include <linux/slab.h>
 #include <linux/mman.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 554731868b07..9e5e96f12d86 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -6,6 +6,7 @@ config CPU_S3C2410
         bool
         depends on ARCH_S3C2410
         select CPU_ARM920T
+        select S3C_GPIO_PULL_UP
         select S3C2410_CLOCK
         select S3C2410_GPIO
         select CPU_LLSERIAL_S3C2410
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c
index a3f3c7b1ca38..8cdeb14af592 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c
@@ -33,14 +33,15 @@ static void h1940bt_enable(int on)
                 h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
                 /* Reset the chip */
                 mdelay(10);
-                s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
+
+                gpio_set_value(S3C2410_GPH(1), 1);
                 mdelay(10);
-                s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
+                gpio_set_value(S3C2410_GPH(1), 0);
         }
         else {
-                s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
+                gpio_set_value(S3C2410_GPH(1), 1);
                 mdelay(10);
-                s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
+                gpio_set_value(S3C2410_GPH(1), 0);
                 mdelay(10);
                 h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
         }
@@ -61,15 +62,21 @@ static int __devinit h1940bt_probe(struct platform_device *pdev)
         struct rfkill *rfk;
         int ret = 0;
 
+        ret = gpio_request(S3C2410_GPH(1), dev_name(&pdev->dev));
+        if (ret) {
+                dev_err(&pdev->dev, "could not get GPH1\n");\
+                return ret;
+        }
+
         /* Configures BT serial port GPIOs */
-        s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
-        s3c2410_gpio_pullup(S3C2410_GPH(0), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_pullup(S3C2410_GPH(1), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
-        s3c2410_gpio_pullup(S3C2410_GPH(2), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
-        s3c2410_gpio_pullup(S3C2410_GPH(3), 1);
+        s3c_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
+        s3c_gpio_cfgpull(S3C2410_GPH(0), S3C_GPIO_PULL_NONE);
+        s3c_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpull(S3C2410_GPH(1), S3C_GPIO_PULL_NONE);
+        s3c_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
+        s3c_gpio_cfgpull(S3C2410_GPH(2), S3C_GPIO_PULL_NONE);
+        s3c_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
+        s3c_gpio_cfgpull(S3C2410_GPH(3), S3C_GPIO_PULL_NONE);
 
 
         rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH,
@@ -100,6 +107,7 @@ static int h1940bt_remove(struct platform_device *pdev)
         struct rfkill *rfk = platform_get_drvdata(pdev);
 
         platform_set_drvdata(pdev, NULL);
+        gpio_free(S3C2410_GPH(1));
 
         if (rfk) {
                 rfkill_unregister(rfk);
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index 08ac5f96c012..cf68136cc668 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -54,7 +54,7 @@ enum dma_ch {
 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
 
 /* we have 4 dma channels */
-#ifndef CONFIG_CPU_S3C2443
+#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
 #define S3C_DMA_CHANNELS                (4)
 #else
 #define S3C_DMA_CHANNELS                (6)
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
index 035a493952db..f453c4f2cb8e 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
@@ -10,14 +10,28 @@
  * published by the Free Software Foundation.
 */
 
+#ifndef __MACH_GPIO_FNS_H
+#define __MACH_GPIO_FNS_H __FILE__
+
 /* These functions are in the to-be-removed category and it is strongly
  * encouraged not to use these in new code. They will be marked deprecated
  * very soon.
  *
  * Most of the functionality can be either replaced by the gpiocfg calls
  * for the s3c platform or by the generic GPIOlib API.
+ *
+ * As of 2.6.35-rc, these will be removed, with the few drivers using them
+ * either replaced or given a wrapper until the calls can be removed.
 */
 
+#include <plat/gpio-cfg.h>
+
+static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
+{
+        /* 1:1 mapping between cfgpin and setcfg calls at the moment */
+        s3c_gpio_cfgpin(pin, cfg);
+}
+
 /* external functions for GPIO support
  *
  * These allow various different clients to access the same GPIO
@@ -25,17 +39,6 @@
  * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
 */
 
-/* s3c2410_gpio_cfgpin
- *
- * set the configuration of the given pin to the value passed.
- *
- * eg:
- *    s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
- *    s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
-*/
-
-extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
-
 extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
 
 /* s3c2410_gpio_getirq
@@ -73,6 +76,14 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
 
 /* s3c2410_gpio_pullup
  *
+ * This call should be replaced with s3c_gpio_setpull().
+ *
+ * As a note, there is currently no distinction between pull-up and pull-down
+ * in the s3c24xx series devices with only an on/off configuration.
+ */
+
+/* s3c2410_gpio_pullup
+ *
  * configure the pull-up control on the given pin
  *
  * to = 1 => disable the pull-up
@@ -86,18 +97,8 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
 
 extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
 
-/* s3c2410_gpio_getpull
- *
- * Read the state of the pull-up on a given pin
- *
- * return:
- *      < 0 => error code
- *        0 => enabled
- *        1 => disabled
-*/
-
-extern int s3c2410_gpio_getpull(unsigned int pin);
-
 extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
 
 extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
+
+#endif /* __MACH_GPIO_FNS_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
index 2edbb9c88ab3..f3182ff847cb 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
@@ -34,6 +34,10 @@
 #define S3C2410_GPIO_F_NR       (32)
 #define S3C2410_GPIO_G_NR       (32)
 #define S3C2410_GPIO_H_NR       (32)
+#define S3C2410_GPIO_J_NR       (32)    /* technically 16. */
+#define S3C2410_GPIO_K_NR       (32)    /* technically 16. */
+#define S3C2410_GPIO_L_NR       (32)    /* technically 15. */
+#define S3C2410_GPIO_M_NR       (32)    /* technically 2. */
 
 #if CONFIG_S3C_GPIO_SPACE != 0
 #error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment
@@ -53,6 +57,10 @@ enum s3c_gpio_number {
         S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
         S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
         S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
+        S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
+        S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
+        S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
+        S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
 };
 
 #endif /* __ASSEMBLY__ */
@@ -67,6 +75,10 @@ enum s3c_gpio_number {
 #define S3C2410_GPF(_nr)        (S3C2410_GPIO_F_START + (_nr))
 #define S3C2410_GPG(_nr)        (S3C2410_GPIO_G_START + (_nr))
 #define S3C2410_GPH(_nr)        (S3C2410_GPIO_H_START + (_nr))
+#define S3C2410_GPJ(_nr)        (S3C2410_GPIO_J_START + (_nr))
+#define S3C2410_GPK(_nr)        (S3C2410_GPIO_K_START + (_nr))
+#define S3C2410_GPL(_nr)        (S3C2410_GPIO_L_START + (_nr))
+#define S3C2410_GPM(_nr)        (S3C2410_GPIO_M_START + (_nr))
 
 /* compatibility until drivers can be modified */
 
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
index 6c12c6312ad8..877c15e1b154 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -115,6 +115,26 @@
 #define IRQ_S3C2412_SDI         S3C2410_IRQSUB(13)
 #define IRQ_S3C2412_CF          S3C2410_IRQSUB(14)
 
+
+#define IRQ_S3C2416_EINT8t15    S3C2410_IRQ(5)
+#define IRQ_S3C2416_DMA         S3C2410_IRQ(17)
+#define IRQ_S3C2416_UART3       S3C2410_IRQ(18)
+#define IRQ_S3C2416_SDI1        S3C2410_IRQ(20)
+#define IRQ_S3C2416_SDI0        S3C2410_IRQ(21)
+
+#define IRQ_S3C2416_LCD2        S3C2410_IRQSUB(15)
+#define IRQ_S3C2416_LCD3        S3C2410_IRQSUB(16)
+#define IRQ_S3C2416_LCD4        S3C2410_IRQSUB(17)
+#define IRQ_S3C2416_DMA0        S3C2410_IRQSUB(18)
+#define IRQ_S3C2416_DMA1        S3C2410_IRQSUB(19)
+#define IRQ_S3C2416_DMA2        S3C2410_IRQSUB(20)
+#define IRQ_S3C2416_DMA3        S3C2410_IRQSUB(21)
+#define IRQ_S3C2416_DMA4        S3C2410_IRQSUB(22)
+#define IRQ_S3C2416_DMA5        S3C2410_IRQSUB(23)
+#define IRQ_S32416_WDT          S3C2410_IRQSUB(27)
+#define IRQ_S32416_AC97         S3C2410_IRQSUB(28)
+
+
 /* extra irqs for s3c2440 */
 
 #define IRQ_S3C2440_CAM_C       S3C2410_IRQSUB(11)      /* S3C2443 too */
@@ -130,7 +150,10 @@
 #define IRQ_S3C2443_HSMMC       S3C2410_IRQ(20)         /* IRQ_SDI */
 #define IRQ_S3C2443_NAND        S3C2410_IRQ(24)         /* reserved */
 
+#define IRQ_S3C2416_HSMMC0      S3C2410_IRQ(21)         /* S3C2416/S3C2450 */
+
 #define IRQ_HSMMC0              IRQ_S3C2443_HSMMC
+#define IRQ_HSMMC1              IRQ_S3C2416_HSMMC0
 
 #define IRQ_S3C2443_LCD1        S3C2410_IRQSUB(14)
 #define IRQ_S3C2443_LCD2        S3C2410_IRQSUB(15)
@@ -152,7 +175,7 @@
 #define IRQ_S3C2443_WDT         S3C2410_IRQSUB(27)
 #define IRQ_S3C2443_AC97        S3C2410_IRQSUB(28)
 
-#ifdef CONFIG_CPU_S3C2443
+#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
 #define NR_IRQS (IRQ_S3C2443_AC97+1)
 #else
 #define NR_IRQS (IRQ_S3C2440_AC97+1)
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index b049e61460b6..f07d68066d7e 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -63,9 +63,9 @@
 #define S3C2440_PA_AC97    (0x5B000000)
 #define S3C2440_SZ_AC97    SZ_1M
 
-/* S3C2443 High-speed SD/MMC */
+/* S3C2443/S3C2416 High-speed SD/MMC */
 #define S3C2443_PA_HSMMC   (0x4A800000)
-#define S3C2443_SZ_HSMMC   (256)
+#define S3C2416_PA_HSMMC0  (0x4AC00000)
 
 /* S3C2412 memory and IO controls */
 #define S3C2412_PA_SSMC (0x4F000000)
@@ -110,6 +110,7 @@
 #define S3C_PA_UART         S3C24XX_PA_UART
 #define S3C_PA_USBHOST  S3C2410_PA_USBHOST
 #define S3C_PA_HSMMC0       S3C2443_PA_HSMMC
+#define S3C_PA_HSMMC1       S3C2416_PA_HSMMC0
 #define S3C_PA_NAND         S3C24XX_PA_NAND
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
index 9a0d169be137..3415b60082d7 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
@@ -161,4 +161,6 @@
 
 #endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
 
+#define S3C2416_CLKDIV2         S3C2410_CLKREG(0x28)
+
 #endif /* __ASM_ARM_REGS_CLOCK */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
index 3c3853cd3cf7..98fd4a05587c 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
@@ -19,6 +19,42 @@
 #define S3C2412_DSC1       S3C2410_GPIOREG(0xe0)
 #endif
 
+#if defined(CONFIG_CPU_S3C2416)
+#define S3C2416_DSC0       S3C2410_GPIOREG(0xc0)
+#define S3C2416_DSC1       S3C2410_GPIOREG(0xc4)
+#define S3C2416_DSC2       S3C2410_GPIOREG(0xc8)
+#define S3C2416_DSC3       S3C2410_GPIOREG(0x110)
+
+#define S3C2416_SELECT_DSC0     (0 << 30)
+#define S3C2416_SELECT_DSC1     (1 << 30)
+#define S3C2416_SELECT_DSC2     (2 << 30)
+#define S3C2416_SELECT_DSC3     (3 << 30)
+
+#define S3C2416_DSC_GETSHIFT(x) (x & 30)
+
+#define S3C2416_DSC0_CF         (S3C2416_SELECT_DSC0 | 28)
+#define S3C2416_DSC0_CF_5mA     (0 << 28)
+#define S3C2416_DSC0_CF_10mA    (1 << 28)
+#define S3C2416_DSC0_CF_15mA    (2 << 28)
+#define S3C2416_DSC0_CF_21mA    (3 << 28)
+#define S3C2416_DSC0_CF_MASK    (3 << 28)
+
+#define S3C2416_DSC0_nRBE       (S3C2416_SELECT_DSC0 | 26)
+#define S3C2416_DSC0_nRBE_5mA   (0 << 26)
+#define S3C2416_DSC0_nRBE_10mA  (1 << 26)
+#define S3C2416_DSC0_nRBE_15mA  (2 << 26)
+#define S3C2416_DSC0_nRBE_21mA  (3 << 26)
+#define S3C2416_DSC0_nRBE_MASK  (3 << 26)
+
+#define S3C2416_DSC0_nROE       (S3C2416_SELECT_DSC0 | 24)
+#define S3C2416_DSC0_nROE_5mA   (0 << 24)
+#define S3C2416_DSC0_nROE_10mA  (1 << 24)
+#define S3C2416_DSC0_nROE_15mA  (2 << 24)
+#define S3C2416_DSC0_nROE_21mA  (3 << 24)
+#define S3C2416_DSC0_nROE_MASK  (3 << 24)
+
+#endif
+
 #if defined(CONFIG_CPU_S3C244X)
 
 #define S3C2440_DSC0       S3C2410_GPIOREG(0xc4)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index fd672f330bf2..a6384239eddf 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -610,35 +610,73 @@
 #define S3C2410_GPHUP      S3C2410_GPIOREG(0x78)
 
 #define S3C2410_GPH0_nCTS0  (0x02 << 0)
+#define S3C2416_GPH0_TXD0  (0x02 << 0)
 
 #define S3C2410_GPH1_nRTS0  (0x02 << 2)
+#define S3C2416_GPH1_RXD0  (0x02 << 2)
 
 #define S3C2410_GPH2_TXD0   (0x02 << 4)
+#define S3C2416_GPH2_TXD1   (0x02 << 4)
 
 #define S3C2410_GPH3_RXD0   (0x02 << 6)
+#define S3C2416_GPH3_RXD1   (0x02 << 6)
 
 #define S3C2410_GPH4_TXD1   (0x02 << 8)
+#define S3C2416_GPH4_TXD2   (0x02 << 8)
 
 #define S3C2410_GPH5_RXD1   (0x02 << 10)
+#define S3C2416_GPH5_RXD2   (0x02 << 10)
 
 #define S3C2410_GPH6_TXD2   (0x02 << 12)
+#define S3C2416_GPH6_TXD3   (0x02 << 12)
 #define S3C2410_GPH6_nRTS1  (0x03 << 12)
+#define S3C2416_GPH6_nRTS2  (0x03 << 12)
 
 #define S3C2410_GPH7_RXD2   (0x02 << 14)
+#define S3C2416_GPH7_RXD3   (0x02 << 14)
 #define S3C2410_GPH7_nCTS1  (0x03 << 14)
+#define S3C2416_GPH7_nCTS2  (0x03 << 14)
 
 #define S3C2410_GPH8_UCLK   (0x02 << 16)
+#define S3C2416_GPH8_nCTS0  (0x02 << 16)
 
 #define S3C2410_GPH9_CLKOUT0  (0x02 << 18)
 #define S3C2442_GPH9_nSPICS0  (0x03 << 18)
+#define S3C2416_GPH9_nRTS0    (0x02 << 18)
 
 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
+#define S3C2416_GPH10_nCTS1   (0x02 << 20)
+
+#define S3C2416_GPH11_nRTS1   (0x02 << 22)
+
+#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24)
+
+#define S3C2416_GPH13_CLKOUT0 (0x02 << 26)
+
+#define S3C2416_GPH14_CLKOUT1 (0x02 << 28)
 
 /* The S3C2412 and S3C2413 move the GPJ register set to after
  * GPH, which means all registers after 0x80 are now offset by 0x10
  * for the 2412/2413 from the 2410/2440/2442
 */
 
+/* S3C2443 and above */
+#define S3C2440_GPJCON     S3C2410_GPIOREG(0xD0)
+#define S3C2440_GPJDAT     S3C2410_GPIOREG(0xD4)
+#define S3C2440_GPJUP      S3C2410_GPIOREG(0xD8)
+
+#define S3C2443_GPKCON     S3C2410_GPIOREG(0xE0)
+#define S3C2443_GPKDAT     S3C2410_GPIOREG(0xE4)
+#define S3C2443_GPKUP      S3C2410_GPIOREG(0xE8)
+
+#define S3C2443_GPLCON     S3C2410_GPIOREG(0xF0)
+#define S3C2443_GPLDAT     S3C2410_GPIOREG(0xF4)
+#define S3C2443_GPLUP      S3C2410_GPIOREG(0xF8)
+
+#define S3C2443_GPMCON     S3C2410_GPIOREG(0x100)
+#define S3C2443_GPMDAT     S3C2410_GPIOREG(0x104)
+#define S3C2443_GPMUP      S3C2410_GPIOREG(0x108)
+
 /* miscellaneous control */
 #define S3C2400_MISCCR     S3C2410_GPIOREG(0x54)
 #define S3C2410_MISCCR     S3C2410_GPIOREG(0x80)
@@ -686,6 +724,7 @@
 #define S3C2412_MISCCR_CLK1_CLKsrc  (0<<8)
 
 #define S3C2410_MISCCR_USBSUSPND0   (1<<12)
+#define S3C2416_MISCCR_SEL_SUSPND   (1<<12)
 #define S3C2410_MISCCR_USBSUSPND1   (1<<13)
 
 #define S3C2410_MISCCR_nRSTCON      (1<<16)
@@ -695,6 +734,9 @@
 #define S3C2410_MISCCR_nEN_SCLKE    (1<<19)     /* not 2412 */
 #define S3C2410_MISCCR_SDSLEEP      (7<<17)
 
+#define S3C2416_MISCCR_FLT_I2C      (1<<24)
+#define S3C2416_MISCCR_HSSPI_EN2    (1<<31)
+
 /* external interrupt control... */
 /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
  * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
@@ -762,8 +804,11 @@
 #define S3C2410_GSTATUS1_IDMASK    (0xffff0000)
 #define S3C2410_GSTATUS1_2410      (0x32410000)
 #define S3C2410_GSTATUS1_2412      (0x32412001)
+#define S3C2410_GSTATUS1_2416      (0x32416003)
 #define S3C2410_GSTATUS1_2440      (0x32440000)
 #define S3C2410_GSTATUS1_2442      (0x32440aaa)
+/* some 2416 CPUs report this value also */
+#define S3C2410_GSTATUS1_2450      (0x32450003)
 
 #define S3C2410_GSTATUS2_WTRESET   (1<<2)
 #define S3C2410_GSTATUS2_OFFRESET  (1<<1)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
index 1202ca5e99f6..19575e061114 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
@@ -22,85 +22,49 @@
  * pull up works like all other ports.
 */
 
-#define S3C2440_GPIO_BANKJ  (416)
-
-#define S3C2440_GPJCON      S3C2410_GPIOREG(0xd0)
-#define S3C2440_GPJDAT      S3C2410_GPIOREG(0xd4)
-#define S3C2440_GPJUP       S3C2410_GPIOREG(0xd8)
-
 #define S3C2413_GPJCON          S3C2410_GPIOREG(0x80)
 #define S3C2413_GPJDAT          S3C2410_GPIOREG(0x84)
 #define S3C2413_GPJUP           S3C2410_GPIOREG(0x88)
 #define S3C2413_GPJSLPCON       S3C2410_GPIOREG(0x8C)
 
-#define S3C2440_GPJ0            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
-#define S3C2440_GPJ0_INP        (0x00 << 0)
 #define S3C2440_GPJ0_OUTP       (0x01 << 0)
 #define S3C2440_GPJ0_CAMDATA0   (0x02 << 0)
 
-#define S3C2440_GPJ1            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 1)
-#define S3C2440_GPJ1_INP        (0x00 << 2)
 #define S3C2440_GPJ1_OUTP       (0x01 << 2)
 #define S3C2440_GPJ1_CAMDATA1   (0x02 << 2)
 
-#define S3C2440_GPJ2            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 2)
-#define S3C2440_GPJ2_INP        (0x00 << 4)
 #define S3C2440_GPJ2_OUTP       (0x01 << 4)
 #define S3C2440_GPJ2_CAMDATA2   (0x02 << 4)
 
-#define S3C2440_GPJ3            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 3)
-#define S3C2440_GPJ3_INP        (0x00 << 6)
 #define S3C2440_GPJ3_OUTP       (0x01 << 6)
 #define S3C2440_GPJ3_CAMDATA3   (0x02 << 6)
 
-#define S3C2440_GPJ4            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 4)
-#define S3C2440_GPJ4_INP        (0x00 << 8)
 #define S3C2440_GPJ4_OUTP       (0x01 << 8)
 #define S3C2440_GPJ4_CAMDATA4   (0x02 << 8)
 
-#define S3C2440_GPJ5            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 5)
-#define S3C2440_GPJ5_INP        (0x00 << 10)
 #define S3C2440_GPJ5_OUTP       (0x01 << 10)
 #define S3C2440_GPJ5_CAMDATA5   (0x02 << 10)
 
-#define S3C2440_GPJ6            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 6)
-#define S3C2440_GPJ6_INP        (0x00 << 12)
 #define S3C2440_GPJ6_OUTP       (0x01 << 12)
 #define S3C2440_GPJ6_CAMDATA6   (0x02 << 12)
 
-#define S3C2440_GPJ7            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 7)
-#define S3C2440_GPJ7_INP        (0x00 << 14)
 #define S3C2440_GPJ7_OUTP       (0x01 << 14)
 #define S3C2440_GPJ7_CAMDATA7   (0x02 << 14)
 
-#define S3C2440_GPJ8            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 8)
-#define S3C2440_GPJ8_INP        (0x00 << 16)
 #define S3C2440_GPJ8_OUTP       (0x01 << 16)
 #define S3C2440_GPJ8_CAMPCLK    (0x02 << 16)
 
-#define S3C2440_GPJ9            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 9)
-#define S3C2440_GPJ9_INP        (0x00 << 18)
 #define S3C2440_GPJ9_OUTP       (0x01 << 18)
 #define S3C2440_GPJ9_CAMVSYNC   (0x02 << 18)
 
-#define S3C2440_GPJ10           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 10)
-#define S3C2440_GPJ10_INP       (0x00 << 20)
 #define S3C2440_GPJ10_OUTP      (0x01 << 20)
 #define S3C2440_GPJ10_CAMHREF   (0x02 << 20)
 
-#define S3C2440_GPJ11           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 11)
-#define S3C2440_GPJ11_INP       (0x00 << 22)
 #define S3C2440_GPJ11_OUTP      (0x01 << 22)
 #define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22)
 
-#define S3C2440_GPJ12           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 12)
-#define S3C2440_GPJ12_INP       (0x00 << 24)
 #define S3C2440_GPJ12_OUTP      (0x01 << 24)
 #define S3C2440_GPJ12_CAMRESET  (0x02 << 24)
 
-#define S3C2443_GPJ13           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 13)
-#define S3C2443_GPJ14           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 14)
-#define S3C2443_GPJ15           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 15)
-
 #endif  /* __ASM_ARCH_REGS_GPIOJ_H */
 
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-irq.h b/arch/arm/mach-s3c2410/include/mach/regs-irq.h
index de86ee8812bd..0f07ba30b1fb 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-irq.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-irq.h
@@ -27,6 +27,16 @@
 #define S3C2410_SUBSRCPND      S3C2410_IRQREG(0x018)
 #define S3C2410_INTSUBMSK      S3C2410_IRQREG(0x01C)
 
+#define S3C2416_PRIORITY_MODE1          S3C2410_IRQREG(0x030)
+#define S3C2416_PRIORITY_UPDATE1        S3C2410_IRQREG(0x034)
+#define S3C2416_SRCPND2                 S3C2410_IRQREG(0x040)
+#define S3C2416_INTMOD2                 S3C2410_IRQREG(0x044)
+#define S3C2416_INTMSK2                 S3C2410_IRQREG(0x048)
+#define S3C2416_INTPND2                 S3C2410_IRQREG(0x050)
+#define S3C2416_INTOFFSET2              S3C2410_IRQREG(0x054)
+#define S3C2416_PRIORITY_MODE2          S3C2410_IRQREG(0x070)
+#define S3C2416_PRIORITY_UPDATE2        S3C2410_IRQREG(0x074)
+
 /* mask: 0=enable, 1=disable
  * 1 bit EINT, 4=EINT4, 23=EINT23
  * EINT0,1,2,3 are not handled here.
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
new file mode 100644
index 000000000000..2f31b74974af
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
@@ -0,0 +1,30 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
+ *      as part of OpenInkpot project
+ * Copyright (c) 2009 Promwad Innovation Company
+ *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2416 memory register definitions
+*/
+
+#ifndef __ASM_ARM_REGS_S3C2416_MEM
+#define __ASM_ARM_REGS_S3C2416_MEM
+
+#ifndef S3C2416_MEMREG
+#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
+#endif
+
+#define S3C2416_BANKCFG                 S3C2416_MEMREG(0x00)
+#define S3C2416_BANKCON1                S3C2416_MEMREG(0x04)
+#define S3C2416_BANKCON2                S3C2416_MEMREG(0x08)
+#define S3C2416_BANKCON3                S3C2416_MEMREG(0x0C)
+
+#define S3C2416_REFRESH                 S3C2416_MEMREG(0x10)
+#define S3C2416_TIMEOUT                 S3C2416_MEMREG(0x14)
+
+#endif /*  __ASM_ARM_REGS_S3C2416_MEM */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
new file mode 100644
index 000000000000..e443167efb87
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
@@ -0,0 +1,24 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
+ *      as part of OpenInkpot project
+ * Copyright (c) 2009 Promwad Innovation Company
+ *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2416 specific register definitions
+*/
+
+#ifndef __ASM_ARCH_REGS_S3C2416_H
+#define __ASM_ARCH_REGS_S3C2416_H "s3c2416"
+
+#define S3C2416_SWRST           (S3C24XX_VA_CLKPWR + 0x44)
+#define S3C2416_SWRST_RESET     (0x533C2416)
+
+/* see regs-power.h for the other registers in the power block. */
+
+#endif  /* __ASM_ARCH_REGS_S3C2416_H */
+
diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h
index 72f756c5e504..8b283f847daa 100644
--- a/arch/arm/mach-s3c2410/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h
@@ -40,7 +40,9 @@ static void arch_detect_cpu(void)
         cpuid &= S3C2410_GSTATUS1_IDMASK;
 
         if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
-            cpuid == S3C2410_GSTATUS1_2442) {
+            cpuid == S3C2410_GSTATUS1_2442 ||
+            cpuid == S3C2410_GSTATUS1_2416 ||
+            cpuid == S3C2410_GSTATUS1_2450) {
                 fifo_mask = S3C2440_UFSTAT_TXMASK;
                 fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
         } else {
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 7047317ed7f4..34fc05a4244b 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -56,6 +56,7 @@
 #include <plat/iic.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/gpio-cfg.h>
 
 #ifdef CONFIG_MTD_PARTITIONS
 
@@ -225,8 +226,8 @@ static void amlm5900_init_pm(void)
         } else {
                 enable_irq_wake(IRQ_EINT9);
                 /* configure the suspend/resume status pin */
-                s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
-                s3c2410_gpio_pullup(S3C2410_GPF(2), 0);
+                s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
+                s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_UP);
         }
 }
 static void __init amlm5900_init(void)
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 02b1b6220cba..b061ddcf3067 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -61,6 +61,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/cpu-freq.h>
+#include <plat/gpio-cfg.h>
 #include <plat/audio-simtec.h>
 
 #include "usb-simtec.h"
@@ -216,15 +217,13 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
 {
         /* ensure that an nRESET is not generated on resume. */
-        s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
-
+        gpio_direction_output(S3C2410_GPA(21), 1);
         return 0;
 }
 
 static int bast_pm_resume(struct sys_device *sd)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
+        s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
         return 0;
 }
 
@@ -658,6 +657,8 @@ static void __init bast_init(void)
         nor_simtec_init();
         simtec_audio_add(NULL, true, &bast_audio);
 
+        WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
+        
         s3c_cpufreq_setboard(&bast_cpufreq);
 }
 
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index fbedd0760941..9531b4c41deb 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -50,6 +50,7 @@
 #include <plat/udc.h>
 #include <plat/iic.h>
 
+#include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -207,16 +208,16 @@ static int h1940_backlight_init(struct device *dev)
 {
         gpio_request(S3C2410_GPB(0), "Backlight");
 
-        s3c2410_gpio_setpin(S3C2410_GPB(0), 0);
-        s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
+        gpio_direction_output(S3C2410_GPB(0), 0);
+        s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
+        s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
 
         return 0;
 }
 
 static void h1940_backlight_exit(struct device *dev)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPB(0), 1/*S3C2410_GPB0_OUTP*/);
+        gpio_direction_output(S3C2410_GPB(0), 1);
 }
 
 static struct platform_pwm_backlight_data backlight_data = {
@@ -245,18 +246,18 @@ static void h1940_lcd_power_set(struct plat_lcd_data *pd,
 
         if (!power) {
                 /* set to 3ec */
-                s3c2410_gpio_setpin(S3C2410_GPC(0), 0);
+                gpio_direction_output(S3C2410_GPC(0), 0);
                 /* wait for 3ac */
                 do {
-                        value = s3c2410_gpio_getpin(S3C2410_GPC(6));
+                        value = gpio_get_value(S3C2410_GPC(6));
                 } while (value);
                 /* set to 38c */
-                s3c2410_gpio_setpin(S3C2410_GPC(5), 0);
+                gpio_direction_output(S3C2410_GPC(5), 0);
         } else {
                 /* Set to 3ac */
-                s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
+                gpio_direction_output(S3C2410_GPC(5), 1);
                 /* Set to 3ad */
-                s3c2410_gpio_setpin(S3C2410_GPC(0), 1);
+                gpio_direction_output(S3C2410_GPC(0), 1);
         }
 }
 
@@ -332,6 +333,7 @@ static void __init h1940_init(void)
         gpio_request(S3C2410_GPC(5), "LCD power");
         gpio_request(S3C2410_GPC(6), "LCD power");
 
+        gpio_direction_input(S3C2410_GPC(6));
 
         platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
 }
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 684710f88142..75a9fd37a467 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -86,10 +86,10 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
 {
         switch (cmd) {
         case S3C2410_UDC_P_ENABLE :
-                s3c2410_gpio_setpin(S3C2410_GPB(3), 1);
+                gpio_set_value(S3C2410_GPB(3), 1);
                 break;
         case S3C2410_UDC_P_DISABLE :
-                s3c2410_gpio_setpin(S3C2410_GPB(3), 0);
+                gpio_set_value(S3C2410_GPB(3), 0);
                 break;
         case S3C2410_UDC_P_RESET :
                 break;
@@ -536,6 +536,9 @@ static void __init n30_init(void)
 
                 platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices));
         }
+
+        WARN_ON(gpio_request(S3C2410_GPB(3), "udc pup"));
+        gpio_direction_output(S3C2410_GPB(3), 0);
 }
 
 MACHINE_START(N30, "Acer-N30")
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 92a4ec375d82..d0e87b6e2e0f 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -58,6 +58,7 @@
 #include <plat/iic.h>
 
 #include <plat/common-smdk.h>
+#include <plat/gpio-cfg.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
@@ -219,10 +220,10 @@ static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
 {
         switch (cs) {
         case BITBANG_CS_ACTIVE:
-                s3c2410_gpio_setpin(S3C2410_GPB(5), 0);
+                gpio_set_value(S3C2410_GPB(5), 0);
                 break;
         case BITBANG_CS_INACTIVE:
-                s3c2410_gpio_setpin(S3C2410_GPB(5), 1);
+                gpio_set_value(S3C2410_GPB(5), 1);
                 break;
         }
 }
@@ -347,13 +348,14 @@ static void __init qt2410_machine_init(void)
         }
         s3c24xx_fb_set_platdata(&qt2410_fb_info);
 
-        s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
         s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
 
         s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
         s3c_i2c0_set_platdata(NULL);
 
-        s3c2410_gpio_cfgpin(S3C2410_GPB(5), S3C2410_GPIO_OUTPUT);
+        WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs"));
+        gpio_direction_output(S3C2410_GPB(5), 1);
 
         platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
         s3c_pm_init();
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 9051f0d31123..d540d79dd264 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -357,8 +357,7 @@ static struct clk *vr1000_clocks[] __initdata = {
 
 static void vr1000_power_off(void)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPB(9), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPB(9), 1);
+        gpio_direction_output(S3C2410_GPB(9), 1);
 }
 
 static void __init vr1000_map_io(void)
@@ -395,6 +394,8 @@ static void __init vr1000_init(void)
 
         nor_simtec_init();
         simtec_audio_add(NULL, true, NULL);
+
+        WARN_ON(gpio_request(S3C2410_GPB(9), "power off"));
 }
 
 MACHINE_START(VR1000, "Thorcom-VR1000")
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 91ba42f688ac..adc90a3c5890 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -16,6 +16,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/clk.h>
 #include <linux/sysdev.h>
 #include <linux/serial_core.h>
@@ -40,6 +41,10 @@
 #include <plat/clock.h>
 #include <plat/pll.h>
 
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
 /* Initial IO mappings */
 
 static struct map_desc s3c2410_iodesc[] __initdata = {
@@ -65,6 +70,9 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 
 void __init s3c2410_map_io(void)
 {
+        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
+        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
+
         iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
 }
 
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index 9a8c0657ae50..cef6a65637bd 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -16,7 +16,8 @@ config CPU_S3C2412
 config CPU_S3C2412_ONLY
         bool
         depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \
-                   !CPU_S3C2440 && !CPU_S3C2442 && !CPU_S3C2443 && CPU_S3C2412
+                   !CPU_2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
+                   !CPU_S3C2443 && CPU_S3C2412
         default y if CPU_S3C2412
 
 config S3C2412_DMA
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 14f4798291aa..43160183571a 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -48,6 +48,7 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 
+#include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -357,8 +358,7 @@ static void jive_lcm_reset(unsigned int set)
 {
         printk(KERN_DEBUG "%s(%d)\n", __func__, set);
 
-        s3c2410_gpio_setpin(S3C2410_GPG(13), set);
-        s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
+        gpio_set_value(S3C2410_GPG(13), set);
 }
 
 #undef LCD_UPPER_MARGIN
@@ -391,7 +391,7 @@ static struct ili9320_platdata jive_lcm_config = {
 
 static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
 {
-        s3c2410_gpio_setpin(S3C2410_GPB(7), cs ? 0 : 1);
+        gpio_set_value(S3C2410_GPB(7), cs ? 0 : 1);
 }
 
 static struct s3c2410_spigpio_info jive_lcd_spi = {
@@ -413,7 +413,7 @@ static struct platform_device jive_device_lcdspi = {
 
 static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
 {
-        s3c2410_gpio_setpin(S3C2410_GPH(10), cs ? 0 : 1);
+        gpio_set_value(S3C2410_GPH(10), cs ? 0 : 1);
 }
 
 static struct s3c2410_spigpio_info jive_wm8750_spi = {
@@ -531,7 +531,7 @@ static void jive_power_off(void)
         printk(KERN_INFO "powering system down...\n");
 
         s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
 }
 
 static void __init jive_machine_init(void)
@@ -636,22 +636,22 @@ static void __init jive_machine_init(void)
 
         /* initialise the spi */
 
-        s3c2410_gpio_setpin(S3C2410_GPG(13), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
+        gpio_request(S3C2410_GPG(13), "lcm reset");
+        gpio_direction_output(S3C2410_GPG(13), 0);
 
-        s3c2410_gpio_setpin(S3C2410_GPB(7), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPB(7), S3C2410_GPIO_OUTPUT);
+        gpio_request(S3C2410_GPB(7), "jive spi");
+        gpio_direction_output(S3C2410_GPB(7), 1);
 
         s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
 
         s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
 
         /* initialise the WM8750 spi */
 
-        s3c2410_gpio_setpin(S3C2410_GPH(10), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPH(10), S3C2410_GPIO_OUTPUT);
+        gpio_request(S3C2410_GPH(10), "jive wm8750 spi");
+        gpio_direction_output(S3C2410_GPH(10), 1);
 
         /* Turn off suspend on both USB ports, and switch the
          * selectable USB port to USB device mode. */
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index 0392065af1af..faddb36ed23b 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -85,10 +85,10 @@ static void smdk2413_udc_pullup(enum s3c2410_udc_cmd_e cmd)
         switch (cmd)
         {
                 case S3C2410_UDC_P_ENABLE :
-                        s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
+                        gpio_set_value(S3C2410_GPF(2), 1);
                         break;
                 case S3C2410_UDC_P_DISABLE :
-                        s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
+                        gpio_set_value(S3C2410_GPF(2), 0);
                         break;
                 case S3C2410_UDC_P_RESET :
                         break;
@@ -134,8 +134,8 @@ static void __init smdk2413_machine_init(void)
 {       /* Turn off suspend on both USB ports, and switch the
          * selectable USB port to USB device mode. */
 
-        s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
+        WARN_ON(gpio_request(S3C2410_GPF(2), "udc pull"));
+        gpio_direction_output(S3C2410_GPF(2), 0);
 
         s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
                               S3C2410_MISCCR_USBSUSPND0 |
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
new file mode 100644
index 000000000000..29103a6047de
--- /dev/null
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -0,0 +1,38 @@
+# arch/arm/mach-s3c2416/Kconfig
+#
+# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com>
+#
+# Licensed under GPLv2
+
+# note, this also supports the S3C2450 which is so similar it has the same
+# ID code as the S3C2416.
+
+config CPU_S3C2416
+        bool
+        depends on ARCH_S3C2410
+        select CPU_ARM926T
+        select S3C2416_DMA if S3C2410_DMA
+        select CPU_LLSERIAL_S3C2440
+        select S3C_GPIO_PULL_UPDOWN
+        select SAMSUNG_CLKSRC
+        select S3C2443_CLOCK
+        help
+          Support for the S3C2416 SoC from the S3C24XX line
+
+config S3C2416_DMA
+        bool
+        depends on CPU_S3C2416
+        help
+          Internal config node for S3C2416 DMA support
+
+menu "S3C2416 Machines"
+
+config MACH_SMDK2416
+        bool "SMDK2416"
+        select CPU_S3C2416
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        help
+          Say Y here if you are using an SMDK2416
+
+endmenu
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
new file mode 100644
index 000000000000..6c12c7bf40ad
--- /dev/null
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -0,0 +1,19 @@
+# arch/arm/mach-s3c2416/Makefile
+#
+# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com>
+#
+# Licensed under GPLv2
+
+obj-y                           :=
+obj-m                           :=
+obj-n                           :=
+obj-                            :=
+
+obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o clock.o
+obj-$(CONFIG_CPU_S3C2416)       += irq.o
+
+#obj-$(CONFIG_S3C2416_DMA)      += dma.o
+
+# Machine support
+
+obj-$(CONFIG_MACH_SMDK2416)     += mach-smdk2416.o
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
new file mode 100644
index 000000000000..7ccf5a2a2bfc
--- /dev/null
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -0,0 +1,135 @@
+/* linux/arch/arm/mach-s3c2416/clock.c
+ *
+ * Copyright (c) 2010 Simtec Electronics
+ * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
+ *
+ * S3C2416 Clock control support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+
+#include <plat/s3c2416.h>
+#include <plat/s3c2443.h>
+#include <plat/clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/cpu.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/pll6553x.h>
+#include <plat/pll.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-s3c2443-clock.h>
+
+static unsigned int armdiv[8] = {
+        [0] = 1,
+        [1] = 2,
+        [2] = 3,
+        [3] = 4,
+        [5] = 6,
+        [7] = 8,
+};
+
+/* ID to hardware numbering, 0 is HSMMC1, 1 is HSMMC0 */
+static struct clksrc_clk hsmmc_div[] = {
+        [0] = {
+                .clk = {
+                        .name   = "hsmmc-div",
+                        .id     = 1,
+                        .parent = &clk_esysclk.clk,
+                },
+                .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
+        },
+        [1] = {
+                .clk = {
+                        .name   = "hsmmc-div",
+                        .id     = 0,
+                        .parent = &clk_esysclk.clk,
+                },
+                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
+        },
+};
+
+static struct clksrc_clk hsmmc_mux[] = {
+        [0] = {
+                .clk    = {
+                        .id     = 1,
+                        .name   = "hsmmc-if",
+                        .ctrlbit = (1 << 6),
+                        .enable = s3c2443_clkcon_enable_s,
+                },
+                .sources = &(struct clksrc_sources) {
+                        .nr_sources = 2,
+                        .sources = (struct clk *[]) {
+                                [0] = &hsmmc_div[0].clk,
+                                [1] = NULL, /* to fix */
+                        },
+                },
+                .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
+        },
+        [1] = {
+                .clk    = {
+                        .id     = 0,
+                        .name   = "hsmmc-if",
+                        .ctrlbit = (1 << 12),
+                        .enable = s3c2443_clkcon_enable_s,
+                },
+                .sources = &(struct clksrc_sources) {
+                        .nr_sources = 2,
+                        .sources = (struct clk *[]) {
+                                [0] = &hsmmc_div[1].clk,
+                                [1] = NULL, /* to fix */
+                        },
+                },
+                .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
+        },
+};
+
+
+static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
+{
+        clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
+
+        return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
+}
+
+void __init_or_cpufreq s3c2416_setup_clocks(void)
+{
+        s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
+}
+
+
+static struct clksrc_clk *clksrcs[] __initdata = {
+        &hsmmc_div[0],
+        &hsmmc_div[1],
+        &hsmmc_mux[0],
+        &hsmmc_mux[1],
+};
+
+void __init s3c2416_init_clocks(int xtal)
+{
+        u32 epllcon = __raw_readl(S3C2443_EPLLCON);
+        u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
+        int ptr;
+
+        /* s3c2416 EPLL compatible with s3c64xx */
+        clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
+
+        clk_epll.parent = &clk_epllref.clk;
+
+        s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+                s3c_register_clksrc(clksrcs[ptr], 1);
+
+        s3c_pwmclk_init();
+
+}
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
new file mode 100644
index 000000000000..89f521d59d06
--- /dev/null
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -0,0 +1,254 @@
+/* linux/arch/arm/mach-s3c2416/irq.c
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
+ *      as part of OpenInkpot project
+ * Copyright (c) 2009 Promwad Innovation Company
+ *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/mach/irq.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/irq.h>
+
+#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
+
+static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len)
+{
+        unsigned int subsrc, submsk;
+        unsigned int end;
+
+        /* read the current pending interrupts, and the mask
+         * for what it is available */
+
+        subsrc = __raw_readl(S3C2410_SUBSRCPND);
+        submsk = __raw_readl(S3C2410_INTSUBMSK);
+
+        subsrc  &= ~submsk;
+        subsrc >>= (irq - S3C2410_IRQSUB(0));
+        subsrc  &= (1 << len)-1;
+
+        end = len + irq;
+
+        for (; irq < end && subsrc; irq++) {
+                if (subsrc & 1)
+                        generic_handle_irq(irq);
+
+                subsrc >>= 1;
+        }
+}
+
+/* WDT/AC97 sub interrupts */
+
+static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
+{
+        s3c2416_irq_demux(IRQ_S3C2443_WDT, 4);
+}
+
+#define INTMSK_WDTAC97  (1UL << (IRQ_WDT - IRQ_EINT0))
+#define SUBMSK_WDTAC97  INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
+
+static void s3c2416_irq_wdtac97_mask(unsigned int irqno)
+{
+        s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
+}
+
+static void s3c2416_irq_wdtac97_unmask(unsigned int irqno)
+{
+        s3c_irqsub_unmask(irqno, INTMSK_WDTAC97);
+}
+
+static void s3c2416_irq_wdtac97_ack(unsigned int irqno)
+{
+        s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
+}
+
+static struct irq_chip s3c2416_irq_wdtac97 = {
+        .mask       = s3c2416_irq_wdtac97_mask,
+        .unmask     = s3c2416_irq_wdtac97_unmask,
+        .ack        = s3c2416_irq_wdtac97_ack,
+};
+
+
+/* LCD sub interrupts */
+
+static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
+{
+        s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4);
+}
+
+#define INTMSK_LCD      (1UL << (IRQ_LCD - IRQ_EINT0))
+#define SUBMSK_LCD      INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
+
+static void s3c2416_irq_lcd_mask(unsigned int irqno)
+{
+        s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD);
+}
+
+static void s3c2416_irq_lcd_unmask(unsigned int irqno)
+{
+        s3c_irqsub_unmask(irqno, INTMSK_LCD);
+}
+
+static void s3c2416_irq_lcd_ack(unsigned int irqno)
+{
+        s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD);
+}
+
+static struct irq_chip s3c2416_irq_lcd = {
+        .mask       = s3c2416_irq_lcd_mask,
+        .unmask     = s3c2416_irq_lcd_unmask,
+        .ack        = s3c2416_irq_lcd_ack,
+};
+
+
+/* DMA sub interrupts */
+
+static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
+{
+        s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6);
+}
+
+#define INTMSK_DMA      (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
+#define SUBMSK_DMA      INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
+
+
+static void s3c2416_irq_dma_mask(unsigned int irqno)
+{
+        s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA);
+}
+
+static void s3c2416_irq_dma_unmask(unsigned int irqno)
+{
+        s3c_irqsub_unmask(irqno, INTMSK_DMA);
+}
+
+static void s3c2416_irq_dma_ack(unsigned int irqno)
+{
+        s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA);
+}
+
+static struct irq_chip s3c2416_irq_dma = {
+        .mask       = s3c2416_irq_dma_mask,
+        .unmask     = s3c2416_irq_dma_unmask,
+        .ack        = s3c2416_irq_dma_ack,
+};
+
+
+/* UART3 sub interrupts */
+
+static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
+{
+        s3c2416_irq_demux(IRQ_S3C2443_UART3, 3);
+}
+
+#define INTMSK_UART3    (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
+#define SUBMSK_UART3    (0xf << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
+
+
+static void s3c2416_irq_uart3_mask(unsigned int irqno)
+{
+        s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3);
+}
+
+static void s3c2416_irq_uart3_unmask(unsigned int irqno)
+{
+        s3c_irqsub_unmask(irqno, INTMSK_UART3);
+}
+
+static void s3c2416_irq_uart3_ack(unsigned int irqno)
+{
+        s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3);
+}
+
+static struct irq_chip s3c2416_irq_uart3 = {
+        .mask       = s3c2416_irq_uart3_mask,
+        .unmask     = s3c2416_irq_uart3_unmask,
+        .ack        = s3c2416_irq_uart3_ack,
+};
+
+
+/* IRQ initialisation code */
+
+static int __init s3c2416_add_sub(unsigned int base,
+                                   void (*demux)(unsigned int,
+                                                 struct irq_desc *),
+                                   struct irq_chip *chip,
+                                   unsigned int start, unsigned int end)
+{
+        unsigned int irqno;
+
+        set_irq_chip(base, &s3c_irq_level_chip);
+        set_irq_handler(base, handle_level_irq);
+        set_irq_chained_handler(base, demux);
+
+        for (irqno = start; irqno <= end; irqno++) {
+                set_irq_chip(irqno, chip);
+                set_irq_handler(irqno, handle_level_irq);
+                set_irq_flags(irqno, IRQF_VALID);
+        }
+
+        return 0;
+}
+
+static int __init s3c2416_irq_add(struct sys_device *sysdev)
+{
+        printk(KERN_INFO "S3C2416: IRQ Support\n");
+
+        s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd,
+                        IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4);
+
+        s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma,
+                        &s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
+
+        s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3,
+                        &s3c2416_irq_uart3,
+                        IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
+
+        s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97,
+                        &s3c2416_irq_wdtac97,
+                        IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
+
+        return 0;
+}
+
+static struct sysdev_driver s3c2416_irq_driver = {
+        .add            = s3c2416_irq_add,
+};
+
+static int __init s3c2416_irq_init(void)
+{
+        return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_irq_driver);
+}
+
+arch_initcall(s3c2416_irq_init);
+
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
new file mode 100644
index 000000000000..99d24c44f30f
--- /dev/null
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -0,0 +1,150 @@
+/* linux/arch/arm/mach-s3c2416/mach-hanlin_v3c.c
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
+ *      as part of OpenInkpot project
+ * Copyright (c) 2009 Promwad Innovation Company
+ *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/mtd/partitions.h>
+#include <linux/gpio.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-lcd.h>
+
+#include <mach/idle.h>
+#include <mach/fb.h>
+#include <mach/leds-gpio.h>
+#include <plat/iic.h>
+
+#include <plat/s3c2416.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/nand.h>
+
+#include <plat/common-smdk.h>
+
+static struct map_desc smdk2416_iodesc[] __initdata = {
+        /* ISA IO Space map (memory space selected by A24) */
+
+        {
+                .virtual        = (u32)S3C24XX_VA_ISA_WORD,
+                .pfn            = __phys_to_pfn(S3C2410_CS2),
+                .length         = 0x10000,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
+                .pfn            = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
+                .length         = SZ_4M,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (u32)S3C24XX_VA_ISA_BYTE,
+                .pfn            = __phys_to_pfn(S3C2410_CS2),
+                .length         = 0x10000,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
+                .pfn            = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
+                .length         = SZ_4M,
+                .type           = MT_DEVICE,
+        }
+};
+
+#define UCON (S3C2410_UCON_DEFAULT      | \
+                S3C2440_UCON_PCLK       | \
+                S3C2443_UCON_RXERR_IRQEN)
+
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
+
+#define UFCON (S3C2410_UFCON_RXTRIG8    | \
+                S3C2410_UFCON_FIFOMODE  | \
+                S3C2440_UFCON_TXTRIG16)
+
+static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        /* IR port */
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON | 0x50,
+                .ufcon       = UFCON,
+        }
+};
+
+static struct platform_device *smdk2416_devices[] __initdata = {
+        &s3c_device_wdt,
+        &s3c_device_ohci,
+        &s3c_device_i2c0,
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
+};
+
+static void __init smdk2416_map_io(void)
+{
+
+        s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
+
+}
+
+static void __init smdk2416_machine_init(void)
+{
+        s3c_i2c0_set_platdata(NULL);
+
+        gpio_request(S3C2410_GPB(4), "USBHost Power");
+        gpio_direction_output(S3C2410_GPB(4), 1);
+
+        platform_add_devices(smdk2416_devices, ARRAY_SIZE(smdk2416_devices));
+        smdk_machine_init();
+}
+
+MACHINE_START(SMDK2416, "SMDK2416")
+        /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */
+        .phys_io        = S3C2410_PA_UART,
+        .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C2410_SDRAM_PA + 0x100,
+
+        .init_irq       = s3c24xx_init_irq,
+        .map_io         = smdk2416_map_io,
+        .init_machine   = smdk2416_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
new file mode 100644
index 000000000000..3bff05745d0b
--- /dev/null
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -0,0 +1,128 @@
+/* linux/arch/arm/mach-s3c2416/s3c2416.c
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
+ *      as part of OpenInkpot project
+ * Copyright (c) 2009 Promwad Innovation Company
+ *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
+ *
+ * Samsung S3C2416 Mobile CPU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/sysdev.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <asm/proc-fns.h>
+#include <asm/irq.h>
+
+#include <mach/reset.h>
+#include <mach/idle.h>
+#include <mach/regs-s3c2443-clock.h>
+
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+#include <plat/s3c2416.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+#include <plat/iic-core.h>
+
+static struct map_desc s3c2416_iodesc[] __initdata = {
+        IODESC_ENT(WATCHDOG),
+        IODESC_ENT(CLKPWR),
+        IODESC_ENT(TIMER),
+};
+
+struct sysdev_class s3c2416_sysclass = {
+        .name = "s3c2416-core",
+};
+
+static struct sys_device s3c2416_sysdev = {
+        .cls            = &s3c2416_sysclass,
+};
+
+static void s3c2416_hard_reset(void)
+{
+        __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
+}
+
+int __init s3c2416_init(void)
+{
+        printk(KERN_INFO "S3C2416: Initializing architecture\n");
+
+        s3c24xx_reset_hook = s3c2416_hard_reset;
+        /* s3c24xx_idle = s3c2416_idle; */
+
+        /* change WDT IRQ number */
+        s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
+        s3c_device_wdt.resource[1].end   = IRQ_S3C2443_WDT;
+
+        /* the i2c devices are directly compatible with s3c2440 */
+        s3c_i2c0_setname("s3c2440-i2c");
+        s3c_i2c1_setname("s3c2440-i2c");
+
+        return sysdev_register(&s3c2416_sysdev);
+}
+
+void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
+
+        s3c_device_nand.name = "s3c2416-nand";
+}
+
+/* s3c2416_map_io
+ *
+ * register the standard cpu IO areas, and any passed in from the
+ * machine specific initialisation.
+ */
+
+void __init s3c2416_map_io(void)
+{
+        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
+        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
+
+        iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
+}
+
+/* need to register class before we actually register the device, and
+ * we also need to ensure that it has been initialised before any of the
+ * drivers even try to use it (even if not on an s3c2416 based system)
+ * as a driver which may support both 2443 and 2440 may try and use it.
+*/
+
+static int __init s3c2416_core_init(void)
+{
+        return sysdev_class_register(&s3c2416_sysclass);
+}
+
+core_initcall(s3c2416_core_init);
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 7f465265cf04..9d102b912091 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -6,6 +6,7 @@ config CPU_S3C2440
         bool
         depends on ARCH_S3C2410
         select CPU_ARM920T
+        select S3C_GPIO_PULL_UP
         select S3C2410_CLOCK
         select S3C2410_PM if PM
         select S3C2410_GPIO
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index 571b17683d96..a76bcda210ad 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -53,6 +53,7 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 
+#include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -102,10 +103,10 @@ static void mini2440_udc_pullup(enum s3c2410_udc_cmd_e cmd)
 
         switch (cmd) {
                 case S3C2410_UDC_P_ENABLE :
-                        s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
+                        gpio_set_value(S3C2410_GPC(5), 1);
                         break;
                 case S3C2410_UDC_P_DISABLE :
-                        s3c2410_gpio_setpin(S3C2410_GPC(5), 0);
+                        gpio_set_value(S3C2410_GPC(5), 0);
                         break;
                 case S3C2410_UDC_P_RESET :
                         break;
@@ -632,25 +633,25 @@ static void __init mini2440_init(void)
         mini2440_parse_features(&features, mini2440_features_str);
 
         /* turn LCD on */
-        s3c2410_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND);
+        s3c_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND);
 
         /* Turn the backlight early on */
-        s3c2410_gpio_setpin(S3C2410_GPG(4), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPG(4), S3C2410_GPIO_OUTPUT);
+        WARN_ON(gpio_request(S3C2410_GPG(4), "backlight"));
+        gpio_direction_output(S3C2410_GPG(4), 1);
 
         /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */
-        s3c2410_gpio_pullup(S3C2410_GPB(1), 0);
+        s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP);
         s3c2410_gpio_setpin(S3C2410_GPB(1), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT);
+        s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT);
 
         /* Make sure the D+ pullup pin is output */
-        s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
+        WARN_ON(gpio_request(S3C2410_GPC(5), "udc pup"));
+        gpio_direction_output(S3C2410_GPC(5), 0);
 
         /* mark the key as input, without pullups (there is one on the board) */
         for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) {
-                s3c2410_gpio_pullup(mini2440_buttons[i].gpio, 0);
-                s3c2410_gpio_cfgpin(mini2440_buttons[i].gpio,
-                                        S3C2410_GPIO_INPUT);
+                s3c_gpio_setpull(mini2440_buttons[i].gpio, S3C_GPIO_PULL_UP);
+                s3c_gpio_cfgpin(mini2440_buttons[i].gpio, S3C2410_GPIO_INPUT);
         }
         if (features.lcd_index != -1) {
                 int li;
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 342041593f22..3ff62de45fde 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -40,6 +40,7 @@
 #include <plat/regs-serial.h>
 #include <plat/iic.h>
 
+#include <plat/gpio-cfg.h>
 #include <plat/s3c2410.h>
 #include <plat/s3c244x.h>
 #include <plat/clock.h>
@@ -122,15 +123,15 @@ static void __init nexcoder_sensorboard_init(void)
 {
         // Initialize SCCB bus
         s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
-        s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
         s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
-        s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
 
         // Power up the sensor board
         s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
+        s3c_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
         s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
-        s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
+        s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
 }
 
 static void __init nexcoder_map_io(void)
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index f35371db33f5..319458da71a0 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -49,6 +49,7 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 
+#include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -298,7 +299,7 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
 
         /* ensure that an nRESET is not generated on resume. */
         s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
-        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
 
         return 0;
 }
@@ -310,7 +311,7 @@ static int osiris_pm_resume(struct sys_device *sd)
 
         __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
 
-        s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
+        s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 
         return 0;
 }
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c
index 2b68f7ea45ae..d50f3ae6173d 100644
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -19,6 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
 #include <linux/sysdev.h>
+#include <linux/gpio.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 
@@ -33,6 +34,10 @@
 #include <plat/cpu.h>
 #include <plat/s3c244x.h>
 
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
 static struct sys_device s3c2440_sysdev = {
         .cls            = &s3c2440_sysclass,
 };
@@ -41,6 +46,9 @@ int __init s3c2440_init(void)
 {
         printk("S3C2440: Initialising architecture\n");
 
+        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
+        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
+
         /* change irq for watchdog */
 
         s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT;
diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig
index 698140af247c..4fef723126fa 100644
--- a/arch/arm/mach-s3c2443/Kconfig
+++ b/arch/arm/mach-s3c2443/Kconfig
@@ -8,6 +8,7 @@ config CPU_S3C2443
         select S3C2443_DMA if S3C2410_DMA
         select CPU_LLSERIAL_S3C2440
         select SAMSUNG_CLKSRC
+        select S3C2443_CLOCK
         help
           Support for the S3C2443 SoC from the S3C24XX line
 
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 62cd4eaee01b..83b1aa63d778 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -21,6 +21,7 @@
 */
 
 #include <linux/init.h>
+
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/list.h>
@@ -54,111 +55,13 @@
  * set the correct muxing at initialisation
 */
 
-static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
-{
-        u32 ctrlbit = clk->ctrlbit;
-        u32 con = __raw_readl(reg);
-
-        if (enable)
-                con |= ctrlbit;
-        else
-                con &= ~ctrlbit;
-
-        __raw_writel(con, reg);
-        return 0;
-}
-
-static int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
-{
-        return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
-}
-
-static int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
-{
-        return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
-}
-
-static int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
-{
-        return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
-}
-
 /* clock selections */
 
-/* mpllref is a direct descendant of clk_xtal by default, but it is not
- * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
- * such directly equating the two source clocks is impossible.
- */
-static struct clk clk_mpllref = {
-        .name           = "mpllref",
-        .parent         = &clk_xtal,
-        .id             = -1,
-};
-
 static struct clk clk_i2s_ext = {
         .name           = "i2s-ext",
         .id             = -1,
 };
 
-static struct clk *clk_epllref_sources[] = {
-        [0] = &clk_mpllref,
-        [1] = &clk_mpllref,
-        [2] = &clk_xtal,
-        [3] = &clk_ext,
-};
-
-static struct clksrc_clk clk_epllref = {
-        .clk    = {
-                .name           = "epllref",
-                .id             = -1,
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_epllref_sources,
-                .nr_sources = ARRAY_SIZE(clk_epllref_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
-};
-
-static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long div = __raw_readl(S3C2443_CLKDIV0);
-
-        div  &= S3C2443_CLKDIV0_EXTDIV_MASK;
-        div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1);       /* x2 */
-
-        return parent_rate / (div + 1);
-}
-
-static struct clk clk_mdivclk = {
-        .name           = "mdivclk",
-        .parent         = &clk_mpllref,
-        .id             = -1,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2443_getrate_mdivclk,
-        },
-};
-
-static struct clk *clk_msysclk_sources[] = {
-        [0] = &clk_mpllref,
-        [1] = &clk_mpll,
-        [2] = &clk_mdivclk,
-        [3] = &clk_mpllref,
-};
-
-static struct clksrc_clk clk_msysclk = {
-        .clk    = {
-                .name           = "msysclk",
-                .parent         = &clk_xtal,
-                .id             = -1,
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_msysclk_sources,
-                .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
-};
-
 /* armdiv
  *
  * this clock is sourced from msysclk and can have a number of
@@ -266,44 +169,6 @@ static struct clksrc_clk clk_arm = {
         .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
 };
 
-/* esysclk
- *
- * this is sourced from either the EPLL or the EPLLref clock
-*/
-
-static struct clk *clk_sysclk_sources[] = {
-        [0] = &clk_epllref.clk,
-        [1] = &clk_epll,
-};
-
-static struct clksrc_clk clk_esysclk = {
-        .clk    = {
-                .name           = "esysclk",
-                .parent         = &clk_epll,
-                .id             = -1,
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_sysclk_sources,
-                .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
-};
-
-/* uartclk
- *
- * UART baud-rate clock sourced from esysclk via a divisor
-*/
-
-static struct clksrc_clk clk_uart = {
-        .clk    = {
-                .name           = "uartclk",
-                .id             = -1,
-                .parent         = &clk_esysclk.clk,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
-};
-
-
 /* hsspi
  *
  * high-speed spi clock, sourced from esysclk
@@ -320,21 +185,6 @@ static struct clksrc_clk clk_hsspi = {
         .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
 };
 
-/* usbhost
- *
- * usb host bus-clock, usually 48MHz to provide USB bus clock timing
-*/
-
-static struct clksrc_clk clk_usb_bus_host = {
-        .clk    = {
-                .name           = "usb-bus-host-parent",
-                .id             = -1,
-                .parent         = &clk_esysclk.clk,
-                .ctrlbit        = S3C2443_SCLKCON_USBHOST,
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
-};
 
 /* clk_hsmcc_div
  *
@@ -433,89 +283,16 @@ static struct clksrc_clk clk_i2s = {
         .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
 };
 
-/* cam-if
- *
- * camera interface bus-clock, divided down from esysclk
-*/
-
-static struct clksrc_clk clk_cam = {
-        .clk    = {
-                .name           = "camif-upll", /* same as 2440 name */
-                .id             = -1,
-                .parent         = &clk_esysclk.clk,
-                .ctrlbit        = S3C2443_SCLKCON_CAMCLK,
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
-};
-
-/* display-if
- *
- * display interface clock, divided from esysclk
-*/
-
-static struct clksrc_clk clk_display = {
-        .clk    = {
-                .name           = "display-if",
-                .id             = -1,
-                .parent         = &clk_esysclk.clk,
-                .ctrlbit        = S3C2443_SCLKCON_DISPCLK,
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
-};
-
-/* prediv
- *
- * this divides the msysclk down to pass to h/p/etc.
- */
-
-static unsigned long s3c2443_prediv_getrate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
-
-        clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
-        clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
-
-        return rate / (clkdiv0 + 1);
-}
-
-static struct clk clk_prediv = {
-        .name           = "prediv",
-        .id             = -1,
-        .parent         = &clk_msysclk.clk,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2443_prediv_getrate,
-        },
-};
-
 /* standard clock definitions */
 
-static struct clk init_clocks_disable[] = {
+static struct clk init_clocks_off[] = {
         {
-                .name           = "nand",
-                .id             = -1,
-                .parent         = &clk_h,
-        }, {
                 .name           = "sdi",
                 .id             = -1,
                 .parent         = &clk_p,
                 .enable         = s3c2443_clkcon_enable_p,
                 .ctrlbit        = S3C2443_PCLKCON_SDI,
         }, {
-                .name           = "adc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_ADC,
-        }, {
-                .name           = "i2c",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_IIC,
-        }, {
                 .name           = "iis",
                 .id             = -1,
                 .parent         = &clk_p,
@@ -537,179 +314,12 @@ static struct clk init_clocks_disable[] = {
 };
 
 static struct clk init_clocks[] = {
-        {
-                .name           = "dma",
-                .id             = 0,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA0,
-        }, {
-                .name           = "dma",
-                .id             = 1,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA1,
-        }, {
-                .name           = "dma",
-                .id             = 2,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA2,
-        }, {
-                .name           = "dma",
-                .id             = 3,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA3,
-        }, {
-                .name           = "dma",
-                .id             = 4,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA4,
-        }, {
-                .name           = "dma",
-                .id             = 5,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA5,
-        }, {
-                .name           = "lcd",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_LCDC,
-        }, {
-                .name           = "gpio",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_GPIO,
-        }, {
-                .name           = "usb-host",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_USBH,
-        }, {
-                .name           = "usb-device",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_USBD,
-        }, {
-                .name           = "hsmmc",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_HSMMC,
-        }, {
-                .name           = "cfc",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_CFC,
-        }, {
-                .name           = "ssmc",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_SSMC,
-        }, {
-                .name           = "timers",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_PWMT,
-        }, {
-                .name           = "uart",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART0,
-        }, {
-                .name           = "uart",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART1,
-        }, {
-                .name           = "uart",
-                .id             = 2,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART2,
-        }, {
-                .name           = "uart",
-                .id             = 3,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART3,
-        }, {
-                .name           = "rtc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_RTC,
-        }, {
-                .name           = "watchdog",
-                .id             = -1,
-                .parent         = &clk_p,
-                .ctrlbit        = S3C2443_PCLKCON_WDT,
-        }, {
-                .name           = "usb-bus-host",
-                .id             = -1,
-                .parent         = &clk_usb_bus_host.clk,
-        }, {
-                .name           = "ac97",
-                .id             = -1,
-                .parent         = &clk_p,
-                .ctrlbit        = S3C2443_PCLKCON_AC97,
-        }
-};
-
-/* clocks to add where we need to check their parentage */
-
-static struct clksrc_clk __initdata *init_list[] = {
-        &clk_epllref, /* should be first */
-        &clk_esysclk,
-        &clk_msysclk,
-        &clk_arm,
-        &clk_i2s_eplldiv,
-        &clk_i2s,
-        &clk_cam,
-        &clk_uart,
-        &clk_display,
-        &clk_hsmmc_div,
-        &clk_usb_bus_host,
 };
 
-static void __init s3c2443_clk_initparents(void)
-{
-        int ptr;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(init_list); ptr++)
-                s3c_set_clksrc(init_list[ptr], true);
-}
-
-static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
-{
-        clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
-
-        return clkcon0 + 1;
-}
-
 /* clocks to add straight away */
 
 static struct clksrc_clk *clksrcs[] __initdata = {
-        &clk_usb_bus_host,
-        &clk_epllref,
-        &clk_esysclk,
-        &clk_msysclk,
         &clk_arm,
-        &clk_uart,
-        &clk_display,
-        &clk_cam,
         &clk_i2s_eplldiv,
         &clk_i2s,
         &clk_hsspi,
@@ -717,92 +327,32 @@ static struct clksrc_clk *clksrcs[] __initdata = {
 };
 
 static struct clk *clks[] __initdata = {
-        &clk_ext,
-        &clk_epll,
-        &clk_usb_bus,
-        &clk_mpllref,
         &clk_hsmmc,
         &clk_armdiv,
-        &clk_prediv,
 };
 
 void __init_or_cpufreq s3c2443_setup_clocks(void)
 {
-        unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
-        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
-        struct clk *xtal_clk;
-        unsigned long xtal;
-        unsigned long pll;
-        unsigned long fclk;
-        unsigned long hclk;
-        unsigned long pclk;
-
-        xtal_clk = clk_get(NULL, "xtal");
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-
-        pll = s3c2443_get_mpll(mpllcon, xtal);
-        clk_msysclk.clk.rate = pll;
-
-        fclk = pll / s3c2443_fclk_div(clkdiv0);
-        hclk = s3c2443_prediv_getrate(&clk_prediv);
-        hclk /= s3c2443_get_hdiv(clkdiv0);
-        pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
-
-        s3c24xx_setup_clocks(fclk, hclk, pclk);
-
-        printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
-               (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
-               print_mhz(pll), print_mhz(fclk),
-               print_mhz(hclk), print_mhz(pclk));
-
-        s3c24xx_setup_clocks(fclk, hclk, pclk);
+        s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div);
 }
 
 void __init s3c2443_init_clocks(int xtal)
 {
-        struct clk *clkp;
         unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
-        int ret;
         int ptr;
 
-        /* s3c2443 parents h and p clocks from prediv */
-        clk_h.parent = &clk_prediv;
-        clk_p.parent = &clk_prediv;
+        clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
+        clk_epll.parent = &clk_epllref.clk;
+
+        s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div);
 
-        s3c24xx_register_baseclocks(xtal);
         s3c2443_setup_clocks();
-        s3c2443_clk_initparents();
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
-                clkp = clks[ptr];
 
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-        }
+        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 
         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
                 s3c_register_clksrc(clksrcs[ptr], 1);
 
-        clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
-        clk_epll.parent = &clk_epllref.clk;
-        clk_usb_bus.parent = &clk_usb_bus_host.clk;
-
-        /* ensure usb bus clock is within correct rate of 48MHz */
-
-        if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
-                printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
-                clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
-        }
-
-        printk("S3C2443: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
-               (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
-               print_mhz(clk_get_rate(&clk_epll)),
-               print_mhz(clk_get_rate(&clk_usb_bus)));
-
         /* register clocks from clock array */
 
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
@@ -819,17 +369,8 @@ void __init s3c2443_init_clocks(int xtal)
 
         /* install (and disable) the clocks we do not need immediately */
 
-        clkp = init_clocks_disable;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-
-                (clkp->enable)(clkp, 0);
-        }
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index b62bdf18dca4..33ccf7bf766a 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -18,6 +18,7 @@
 #include <linux/dmapool.h>
 #include <linux/sysdev.h>
 #include <linux/errno.h>
+#include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/err.h>
diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c
index 66e6794481d2..60c929a3cab6 100644
--- a/arch/arm/mach-s3c64xx/gpiolib.c
+++ b/arch/arm/mach-s3c64xx/gpiolib.c
@@ -51,6 +51,7 @@
 
 static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .get_config     = s3c_gpio_getcfg_s3c64xx_4bit,
         .set_pull       = s3c_gpio_setpull_updown,
         .get_pull       = s3c_gpio_getpull_updown,
 };
@@ -58,12 +59,14 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
 static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
         .cfg_eint       = 7,
         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .get_config     = s3c_gpio_getcfg_s3c64xx_4bit,
         .set_pull       = s3c_gpio_setpull_updown,
         .get_pull       = s3c_gpio_getpull_updown,
 };
 
 static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
         .cfg_eint       = 3,
+        .get_config     = s3c_gpio_getcfg_s3c64xx_4bit,
         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
         .set_pull       = s3c_gpio_setpull_updown,
         .get_pull       = s3c_gpio_getpull_updown,
@@ -171,6 +174,7 @@ static struct s3c_gpio_chip gpio_4bit2[] = {
 
 static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
         .set_config     = s3c_gpio_setcfg_s3c24xx,
+        .get_config     = s3c_gpio_getcfg_s3c24xx,
         .set_pull       = s3c_gpio_setpull_updown,
         .get_pull       = s3c_gpio_getpull_updown,
 };
@@ -178,6 +182,7 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
 static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
         .cfg_eint       = 2,
         .set_config     = s3c_gpio_setcfg_s3c24xx,
+        .get_config     = s3c_gpio_getcfg_s3c24xx,
         .set_pull       = s3c_gpio_setpull_updown,
         .get_pull       = s3c_gpio_getpull_updown,
 };
@@ -185,6 +190,7 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
 static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
         .cfg_eint       = 3,
         .set_config     = s3c_gpio_setcfg_s3c24xx,
+        .get_config     = s3c_gpio_getcfg_s3c24xx,
         .set_pull       = s3c_gpio_setpull_updown,
         .get_pull       = s3c_gpio_getpull_updown,
 };
diff --git a/arch/arm/mach-s3c64xx/include/mach/pll.h b/arch/arm/mach-s3c64xx/include/mach/pll.h
index 90bbd72fdc4e..5ef0bb698ee0 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pll.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pll.h
@@ -20,6 +20,7 @@
 #define S3C6400_PLL_SDIV_SHIFT  (0)
 
 #include <asm/div64.h>
+#include <plat/pll6553x.h>
 
 static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
                                             u32 pllcon)
@@ -37,38 +38,8 @@ static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
         return (unsigned long)fvco;
 }
 
-#define S3C6400_EPLL_MDIV_MASK  ((1 << (23-16)) - 1)
-#define S3C6400_EPLL_PDIV_MASK  ((1 << (13-8)) - 1)
-#define S3C6400_EPLL_SDIV_MASK  ((1 << (2-0)) - 1)
-#define S3C6400_EPLL_MDIV_SHIFT (16)
-#define S3C6400_EPLL_PDIV_SHIFT (8)
-#define S3C6400_EPLL_SDIV_SHIFT (0)
-#define S3C6400_EPLL_KDIV_MASK  (0xffff)
-
 static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
 {
-        unsigned long result;
-        u32 epll0 = __raw_readl(S3C_EPLL_CON0);
-        u32 epll1 = __raw_readl(S3C_EPLL_CON1);
-        u32 mdiv, pdiv, sdiv, kdiv;
-        u64 tmp;
-
-        mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK;
-        pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK;
-        sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK;
-        kdiv = epll1 & S3C6400_EPLL_KDIV_MASK;
-
-        /* We need to multiple baseclk by mdiv (the integer part) and kdiv
-         * which is in 2^16ths, so shift mdiv up (does not overflow) and
-         * add kdiv before multiplying. The use of tmp is to avoid any
-         * overflows before shifting bac down into result when multipling
-         * by the mdiv and kdiv pair.
-         */
-
-        tmp = baseclk;
-        tmp *= (mdiv << 16) + kdiv;
-        do_div(tmp, (pdiv << sdiv));
-        result = tmp >> 16;
-
-        return result;
+        return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0),
+                                __raw_readl(S3C_EPLL_CON1));
 }
diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p6440/gpio.c
index b0ea741177ad..262dc75d5bea 100644
--- a/arch/arm/mach-s5p6440/gpio.c
+++ b/arch/arm/mach-s5p6440/gpio.c
@@ -161,12 +161,15 @@ static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
         }, {
                 .cfg_eint       = 0,
                 .set_config     = s3c_gpio_setcfg_s3c24xx,
+                .get_config     = s3c_gpio_getcfg_s3c24xx,
         }, {
                 .cfg_eint       = 2,
                 .set_config     = s3c_gpio_setcfg_s3c24xx,
+                .get_config     = s3c_gpio_getcfg_s3c24xx,
         }, {
                 .cfg_eint       = 3,
                 .set_config     = s3c_gpio_setcfg_s3c24xx,
+                .get_config     = s3c_gpio_getcfg_s3c24xx,
         },
 };
 
@@ -279,6 +282,8 @@ void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
         for (; nr_chips > 0; nr_chips--, chipcfg++) {
                 if (!chipcfg->set_config)
                         chipcfg->set_config     = s3c_gpio_setcfg_s3c64xx_4bit;
+                if (!chipcfg->get_config)
+                        chipcfg->get_config     = s3c_gpio_getcfg_s3c64xx_4bit;
                 if (!chipcfg->set_pull)
                         chipcfg->set_pull       = s3c_gpio_setpull_updown;
                 if (!chipcfg->get_pull)
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index b17d52f7cc48..fd4c52b7ccb6 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -57,7 +57,7 @@ config SA1100_COLLIE
 config SA1100_H3100
         bool "Compaq iPAQ H3100"
         select HTC_EGPIO
-        select CPU_FREQ_SA1100
+        select CPU_FREQ_SA1110
         help
           Say Y here if you intend to run this kernel on the Compaq iPAQ
           H3100 handheld computer.  Information about this machine and the
@@ -68,7 +68,7 @@ config SA1100_H3100
 config SA1100_H3600
         bool "Compaq iPAQ H3600/H3700"
         select HTC_EGPIO
-        select CPU_FREQ_SA1100
+        select CPU_FREQ_SA1110
         help
           Say Y here if you intend to run this kernel on the Compaq iPAQ
           H3600 handheld computer.  Information about this machine and the
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
index 63b32b68b296..7252874d328b 100644
--- a/arch/arm/mach-sa1100/cpu-sa1110.c
+++ b/arch/arm/mach-sa1100/cpu-sa1110.c
@@ -363,6 +363,9 @@ static int __init sa1110_clk_init(void)
         struct sdram_params *sdram;
         const char *name = sdram_name;
 
+        if (!cpu_is_sa1110())
+                return -ENODEV;
+
         if (!name[0]) {
                 if (machine_is_assabet())
                         name = "TC59SM716-CL3";
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index 9b6dee5d16db..9d490c66891c 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -18,7 +18,6 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
-#include <linux/slab.h>
 
 #include <mach/hardware.h>
 #include <mach/jornada720.h>
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index 0b505d9f22d6..c601a75a333d 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -8,7 +8,6 @@
 #include <linux/ioport.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
-#include <linux/slab.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c
index 962f9de454de..5f55012b7c9e 100644
--- a/arch/arm/mach-u300/dummyspichip.c
+++ b/arch/arm/mach-u300/dummyspichip.c
@@ -15,6 +15,7 @@
 #include <linux/mutex.h>
 #include <linux/spi/spi.h>
 #include <linux/dma-mapping.h>
+#include <linux/slab.h>
 /*
  * WARNING! Do not include this pl022-specific controller header
  * for any generic driver. It is only done in this dummy chip
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
index 783f1236fe1b..88506d030596 100644
--- a/arch/arm/mach-u300/mmc.c
+++ b/arch/arm/mach-u300/mmc.c
@@ -20,6 +20,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/gpio.h>
 #include <linux/amba/mmci.h>
+#include <linux/slab.h>
 
 #include "mmc.h"
 #include "padmux.h"
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 60baba65635e..3dff8641b03f 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -29,6 +29,7 @@
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
+#include <linux/gfp.h>
 
 #include <asm/clkdev.h>
 #include <asm/system.h>
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 7161ba23b58a..334f0df4e948 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -16,7 +16,6 @@
  */
 #include <linux/kernel.h>
 #include <linux/pci.h>
-#include <linux/slab.h>
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
 #include <linux/spinlock.h>
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index 48876122df91..e2958eb567f9 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -18,6 +18,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/mtd.h>
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 33027301639e..346ae14824a5 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -572,6 +572,8 @@ config CPU_TLB_V6
 config CPU_TLB_V7
         bool
 
+config VERIFY_PERMISSION_FAULT
+        bool
 endif
 
 config CPU_HAS_ASID
@@ -736,6 +738,12 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
 config OUTER_CACHE
         bool
 
+config OUTER_CACHE_SYNC
+        bool
+        help
+          The outer cache has a outer_cache_fns.sync function pointer
+          that can be used to drain the write buffer of the outer cache.
+
 config CACHE_FEROCEON_L2
         bool "Enable the Feroceon L2 cache controller"
         depends on ARCH_KIRKWOOD || ARCH_MV78XX0
@@ -758,12 +766,13 @@ config CACHE_L2X0
                    ARCH_NOMADIK || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
         default y
         select OUTER_CACHE
+        select OUTER_CACHE_SYNC
         help
           This option enables the L2x0 PrimeCell.
 
 config CACHE_TAUROS2
         bool "Enable the Tauros2 L2 cache controller"
-        depends on ARCH_DOVE
+        depends on (ARCH_DOVE || ARCH_MMP)
         default y
         select OUTER_CACHE
         help
@@ -801,3 +810,9 @@ config ARM_DMA_MEM_BUFFERABLE
           behaviour.  Therefore, we offer this as an option.
 
           You are recommended say 'Y' here and debug any affected drivers.
+
+config ARCH_HAS_BARRIERS
+        bool
+        help
+          This option allows the use of custom mandatory barriers
+          included via the mach/barriers.h file.
diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S
index 2e6dc040c654..ec88b157d3bb 100644
--- a/arch/arm/mm/abort-ev7.S
+++ b/arch/arm/mm/abort-ev7.S
@@ -29,5 +29,26 @@ ENTRY(v7_early_abort)
          * V6 code adjusts the returned DFSR.
          * New designs should not need to patch up faults.
          */
+
+#if defined(CONFIG_VERIFY_PERMISSION_FAULT)
+        /*
+         * Detect erroneous permission failures and fix
+         */
+        ldr     r3, =0x40d                      @ On permission fault
+        and     r3, r1, r3
+        cmp     r3, #0x0d
+        movne   pc, lr
+
+        mcr     p15, 0, r0, c7, c8, 0           @ Retranslate FAR
+        isb
+        mrc     p15, 0, r2, c7, c4, 0           @ Read the PAR
+        and     r3, r2, #0x7b                   @ On translation fault
+        cmp     r3, #0x0b
+        movne   pc, lr
+        bic     r1, r1, #0xf                    @ Fix up FSR FS[5:0]
+        and     r2, r2, #0x7e
+        orr     r1, r1, r2, LSR #1
+#endif
+
         mov     pc, lr
 ENDPROC(v7_early_abort)
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 28b7c2776198..6f98c358989a 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -167,15 +167,15 @@ union offset_union {
  THUMB( "1:     "ins"   %1, [%2]\n"     )               \
  THUMB( "       add     %2, %2, #1\n"   )               \
         "2:\n"                                          \
-        "       .section .fixup,\"ax\"\n"               \
+        "       .pushsection .fixup,\"ax\"\n"           \
         "       .align  2\n"                            \
         "3:     mov     %0, #1\n"                       \
         "       b       2b\n"                           \
-        "       .previous\n"                            \
-        "       .section __ex_table,\"a\"\n"            \
+        "       .popsection\n"                          \
+        "       .pushsection __ex_table,\"a\"\n"        \
         "       .align  3\n"                            \
         "       .long   1b, 3b\n"                       \
-        "       .previous\n"                            \
+        "       .popsection\n"                          \
         : "=r" (err), "=&r" (val), "=r" (addr)          \
         : "0" (err), "2" (addr))
 
@@ -227,16 +227,16 @@ union offset_union {
                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
                 "2:     "ins"   %1, [%2]\n"                     \
                 "3:\n"                                          \
-                "       .section .fixup,\"ax\"\n"               \
+                "       .pushsection .fixup,\"ax\"\n"           \
                 "       .align  2\n"                            \
                 "4:     mov     %0, #1\n"                       \
                 "       b       3b\n"                           \
-                "       .previous\n"                            \
-                "       .section __ex_table,\"a\"\n"            \
+                "       .popsection\n"                          \
+                "       .pushsection __ex_table,\"a\"\n"        \
                 "       .align  3\n"                            \
                 "       .long   1b, 4b\n"                       \
                 "       .long   2b, 4b\n"                       \
-                "       .previous\n"                            \
+                "       .popsection\n"                          \
                 : "=r" (err), "=&r" (v), "=&r" (a)              \
                 : "0" (err), "1" (v), "2" (a));                 \
                 if (err)                                        \
@@ -267,18 +267,18 @@ union offset_union {
                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
                 "4:     "ins"   %1, [%2]\n"                     \
                 "5:\n"                                          \
-                "       .section .fixup,\"ax\"\n"               \
+                "       .pushsection .fixup,\"ax\"\n"           \
                 "       .align  2\n"                            \
                 "6:     mov     %0, #1\n"                       \
                 "       b       5b\n"                           \
-                "       .previous\n"                            \
-                "       .section __ex_table,\"a\"\n"            \
+                "       .popsection\n"                          \
+                "       .pushsection __ex_table,\"a\"\n"        \
                 "       .align  3\n"                            \
                 "       .long   1b, 6b\n"                       \
                 "       .long   2b, 6b\n"                       \
                 "       .long   3b, 6b\n"                       \
                 "       .long   4b, 6b\n"                       \
-                "       .previous\n"                            \
+                "       .popsection\n"                          \
                 : "=r" (err), "=&r" (v), "=&r" (a)              \
                 : "0" (err), "1" (v), "2" (a));                 \
                 if (err)                                        \
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 78f0fc8595e2..9819869d2bc9 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -94,6 +94,15 @@ static inline void l2x0_flush_line(unsigned long addr)
 }
 #endif
 
+static void l2x0_cache_sync(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&l2x0_lock, flags);
+        cache_sync();
+        spin_unlock_irqrestore(&l2x0_lock, flags);
+}
+
 static inline void l2x0_inv_all(void)
 {
         unsigned long flags;
@@ -252,6 +261,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
         outer_cache.inv_range = l2x0_inv_range;
         outer_cache.clean_range = l2x0_clean_range;
         outer_cache.flush_range = l2x0_flush_range;
+        outer_cache.sync = l2x0_cache_sync;
 
         printk(KERN_INFO "%s cache controller enabled\n", type);
         printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
diff --git a/arch/arm/mm/copypage-fa.c b/arch/arm/mm/copypage-fa.c
index b2a6008b0111..d2852e1635b1 100644
--- a/arch/arm/mm/copypage-fa.c
+++ b/arch/arm/mm/copypage-fa.c
@@ -40,7 +40,7 @@ fa_copy_user_page(void *kto, const void *kfrom)
 }
 
 void fa_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto, *kfrom;
 
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 8bca4dea6dfa..f55fa1044f72 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -41,14 +41,7 @@ static void v6_copy_user_highpage_nonaliasing(struct page *to,
         kfrom = kmap_atomic(from, KM_USER0);
         kto = kmap_atomic(to, KM_USER1);
         copy_page(kto, kfrom);
-#ifdef CONFIG_HIGHMEM
-        /*
-         * kmap_atomic() doesn't set the page virtual address, and
-         * kunmap_atomic() takes care of cache flushing already.
-         */
-        if (page_address(to) != NULL)
-#endif
-                __cpuc_flush_dcache_area(kto, PAGE_SIZE);
+        __cpuc_flush_dcache_area(kto, PAGE_SIZE);
         kunmap_atomic(kto, KM_USER1);
         kunmap_atomic(kfrom, KM_USER0);
 }
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 0da7eccf7749..13fa536d82e6 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -11,7 +11,7 @@
  */
 #include <linux/module.h>
 #include <linux/mm.h>
-#include <linux/slab.h>
+#include <linux/gfp.h>
 #include <linux/errno.h>
 #include <linux/list.h>
 #include <linux/init.h>
@@ -464,6 +464,11 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
                                 vaddr += offset;
                                 op(vaddr, len, dir);
                                 kunmap_high(page);
+                        } else if (cache_is_vipt()) {
+                                pte_t saved_pte;
+                                vaddr = kmap_high_l1_vipt(page, &saved_pte);
+                                op(vaddr + offset, len, dir);
+                                kunmap_high_l1_vipt(page, saved_pte);
                         }
                 } else {
                         vaddr = page_address(page) + offset;
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 82df01a72f4a..9b906dec1ca1 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -16,6 +16,7 @@
 #include <linux/vmalloc.h>
 #include <linux/init.h>
 #include <linux/pagemap.h>
+#include <linux/gfp.h>
 
 #include <asm/bugs.h>
 #include <asm/cacheflush.h>
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index e34f095e2090..c6844cb9b508 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -13,6 +13,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
+#include <asm/highmem.h>
 #include <asm/smp_plat.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
@@ -152,21 +153,25 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 
 void __flush_dcache_page(struct address_space *mapping, struct page *page)
 {
-        void *addr = page_address(page);
-
         /*
          * Writeback any data associated with the kernel mapping of this
          * page.  This ensures that data in the physical page is mutually
          * coherent with the kernels mapping.
          */
-#ifdef CONFIG_HIGHMEM
-        /*
-         * kmap_atomic() doesn't set the page virtual address, and
-         * kunmap_atomic() takes care of cache flushing already.
-         */
-        if (addr)
-#endif
-                __cpuc_flush_dcache_area(addr, PAGE_SIZE);
+        if (!PageHighMem(page)) {
+                __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
+        } else {
+                void *addr = kmap_high_get(page);
+                if (addr) {
+                        __cpuc_flush_dcache_area(addr, PAGE_SIZE);
+                        kunmap_high(page);
+                } else if (cache_is_vipt()) {
+                        pte_t saved_pte;
+                        addr = kmap_high_l1_vipt(page, &saved_pte);
+                        __cpuc_flush_dcache_area(addr, PAGE_SIZE);
+                        kunmap_high_l1_vipt(page, saved_pte);
+                }
+        }
 
         /*
          * If this is a page cache page, and we have an aliasing VIPT cache,
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index 2be1ec7c1b41..77b030f5ec09 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -79,7 +79,8 @@ void kunmap_atomic(void *kvaddr, enum km_type type)
         unsigned int idx = type + KM_TYPE_NR * smp_processor_id();
 
         if (kvaddr >= (void *)FIXADDR_START) {
-                __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE);
+                if (cache_is_vivt())
+                        __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE);
 #ifdef CONFIG_DEBUG_HIGHMEM
                 BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
                 set_pte_ext(TOP_PTE(vaddr), __pte(0), 0);
@@ -124,3 +125,87 @@ struct page *kmap_atomic_to_page(const void *ptr)
         pte = TOP_PTE(vaddr);
         return pte_page(*pte);
 }
+
+#ifdef CONFIG_CPU_CACHE_VIPT
+
+#include <linux/percpu.h>
+
+/*
+ * The VIVT cache of a highmem page is always flushed before the page
+ * is unmapped. Hence unmapped highmem pages need no cache maintenance
+ * in that case.
+ *
+ * However unmapped pages may still be cached with a VIPT cache, and
+ * it is not possible to perform cache maintenance on them using physical
+ * addresses unfortunately.  So we have no choice but to set up a temporary
+ * virtual mapping for that purpose.
+ *
+ * Yet this VIPT cache maintenance may be triggered from DMA support
+ * functions which are possibly called from interrupt context. As we don't
+ * want to keep interrupt disabled all the time when such maintenance is
+ * taking place, we therefore allow for some reentrancy by preserving and
+ * restoring the previous fixmap entry before the interrupted context is
+ * resumed.  If the reentrancy depth is 0 then there is no need to restore
+ * the previous fixmap, and leaving the current one in place allow it to
+ * be reused the next time without a TLB flush (common with DMA).
+ */
+
+static DEFINE_PER_CPU(int, kmap_high_l1_vipt_depth);
+
+void *kmap_high_l1_vipt(struct page *page, pte_t *saved_pte)
+{
+        unsigned int idx, cpu = smp_processor_id();
+        int *depth = &per_cpu(kmap_high_l1_vipt_depth, cpu);
+        unsigned long vaddr, flags;
+        pte_t pte, *ptep;
+
+        idx = KM_L1_CACHE + KM_TYPE_NR * cpu;
+        vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+        ptep = TOP_PTE(vaddr);
+        pte = mk_pte(page, kmap_prot);
+
+        if (!in_interrupt())
+                preempt_disable();
+
+        raw_local_irq_save(flags);
+        (*depth)++;
+        if (pte_val(*ptep) == pte_val(pte)) {
+                *saved_pte = pte;
+        } else {
+                *saved_pte = *ptep;
+                set_pte_ext(ptep, pte, 0);
+                local_flush_tlb_kernel_page(vaddr);
+        }
+        raw_local_irq_restore(flags);
+
+        return (void *)vaddr;
+}
+
+void kunmap_high_l1_vipt(struct page *page, pte_t saved_pte)
+{
+        unsigned int idx, cpu = smp_processor_id();
+        int *depth = &per_cpu(kmap_high_l1_vipt_depth, cpu);
+        unsigned long vaddr, flags;
+        pte_t pte, *ptep;
+
+        idx = KM_L1_CACHE + KM_TYPE_NR * cpu;
+        vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+        ptep = TOP_PTE(vaddr);
+        pte = mk_pte(page, kmap_prot);
+
+        BUG_ON(pte_val(*ptep) != pte_val(pte));
+        BUG_ON(*depth <= 0);
+
+        raw_local_irq_save(flags);
+        (*depth)--;
+        if (*depth != 0 && pte_val(pte) != pte_val(saved_pte)) {
+                set_pte_ext(ptep, saved_pte, 0);
+                local_flush_tlb_kernel_page(vaddr);
+        }
+        raw_local_irq_restore(flags);
+
+        if (!in_interrupt())
+                preempt_enable();
+}
+
+#endif  /* CONFIG_CPU_CACHE_VIPT */
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 105d1d4f420b..1ba6cf5a2c02 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -16,6 +16,7 @@
 #include <linux/nodemask.h>
 #include <linux/initrd.h>
 #include <linux/highmem.h>
+#include <linux/gfp.h>
 
 #include <asm/mach-types.h>
 #include <asm/sections.h>
@@ -84,9 +85,6 @@ void show_mem(void)
         printk("Mem-info:\n");
         show_free_areas();
         for_each_online_node(node) {
-                pg_data_t *n = NODE_DATA(node);
-                struct page *map = pgdat_page_nr(n, 0) - n->node_start_pfn;
-
                 for_each_nodebank (i,mi,node) {
                         struct membank *bank = &mi->bank[i];
                         unsigned int pfn1, pfn2;
@@ -95,8 +93,8 @@ void show_mem(void)
                         pfn1 = bank_pfn_start(bank);
                         pfn2 = bank_pfn_end(bank);
 
-                        page = map + pfn1;
-                        end  = map + pfn2;
+                        page = pfn_to_page(pfn1);
+                        end  = pfn_to_page(pfn2 - 1) + 1;
 
                         do {
                                 total++;
@@ -568,9 +566,6 @@ void __init mem_init(void)
         reserved_pages = free_pages = 0;
 
         for_each_online_node(node) {
-                pg_data_t *n = NODE_DATA(node);
-                struct page *map = pgdat_page_nr(n, 0) - n->node_start_pfn;
-
                 for_each_nodebank(i, &meminfo, node) {
                         struct membank *bank = &meminfo.bank[i];
                         unsigned int pfn1, pfn2;
@@ -579,8 +574,8 @@ void __init mem_init(void)
                         pfn1 = bank_pfn_start(bank);
                         pfn2 = bank_pfn_end(bank);
 
-                        page = map + pfn1;
-                        end  = map + pfn2;
+                        page = pfn_to_page(pfn1);
+                        end  = pfn_to_page(pfn2 - 1) + 1;
 
                         do {
                                 if (PageReserved(page))
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 69852003675f..e7113d0b8168 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -421,6 +421,10 @@ static void __init build_mem_type_table(void)
                 user_pgprot |= L_PTE_SHARED;
                 kern_pgprot |= L_PTE_SHARED;
                 vecs_pgprot |= L_PTE_SHARED;
+                mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+                mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+                mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+                mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 #endif
@@ -1087,10 +1091,12 @@ void setup_mm_for_reboot(char mode)
         pgd_t *pgd;
         int i;
 
-        if (current->mm && current->mm->pgd)
-                pgd = current->mm->pgd;
-        else
-                pgd = init_mm.pgd;
+        /*
+         * We need to access to user-mode page tables here. For kernel threads
+         * we don't have any user-mode mappings so we use the context that we
+         * "borrowed".
+         */
+        pgd = current->active_mm->pgd;
 
         base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
         if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c
index 2690146161ba..be5f58e153bf 100644
--- a/arch/arm/mm/pgd.c
+++ b/arch/arm/mm/pgd.c
@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/mm.h>
+#include <linux/gfp.h>
 #include <linux/highmem.h>
 
 #include <asm/pgalloc.h>
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index ee7700242c19..5c47760c2064 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -45,7 +45,7 @@ ENTRY(cpu_sa1100_proc_init)
         mcr     p15, 0, r0, c9, c0, 5           @ Allow read-buffer operations from userland
         mov     pc, lr
 
-        .previous
+        .section .text
 
 /*
  * cpu_sa1100_proc_fin()
diff --git a/arch/arm/nwfpe/entry.S b/arch/arm/nwfpe/entry.S
index 48bca0db4607..cafa18354339 100644
--- a/arch/arm/nwfpe/entry.S
+++ b/arch/arm/nwfpe/entry.S
@@ -111,12 +111,12 @@ next:
         @ to fault.  Emit the appropriate exception gunk to fix things up.
         @ ??? For some reason, faults can happen at .Lx2 even with a
         @ plain LDR instruction.  Weird, but it seems harmless.
-        .section .fixup,"ax"
+        .pushsection .fixup,"ax"
         .align  2
 .Lfix:  mov     pc, r9                  @ let the user eat segfaults
-        .previous
+        .popsection
 
-        .section __ex_table,"a"
+        .pushsection __ex_table,"a"
         .align  3
         .long   .Lx1, .Lfix
-        .previous
+        .popsection
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index d983cd6c788c..0c2cc5cd4d83 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/debugfs.h>
+#include <linux/slab.h>
 #include <mach/audmux.h>
 #include <mach/hardware.h>
 
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
index 2bbd6ed17f50..da92933a233b 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
@@ -8,8 +8,8 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__
-#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__
+#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
+#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
 
 /* Definitions for components on the Debug board */
 
@@ -56,4 +56,4 @@
 
 #define MXC_MAX_EXP_IO_LINES    16
 
-#endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */
+#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
index 07be8ad7ec37..7c4870bd5a21 100644
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
@@ -31,7 +31,13 @@
 #define DMA_MODE_WRITE          1
 #define DMA_MODE_MASK           1
 
-#define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR)
+#define MX1_DMA_REG(offset)     MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
+
+/* DMA Interrupt Mask Register */
+#define MX1_DMA_DIMR            MX1_DMA_REG(0x08)
+
+/* Channel Control Register */
+#define MX1_DMA_CCR(x)          MX1_DMA_REG(0x8c + ((x) << 6))
 
 #define IMX_DMA_MEMSIZE_32      (0 << 4)
 #define IMX_DMA_MEMSIZE_8       (1 << 4)
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 771532b6b4a6..5aad344d5651 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -14,7 +14,7 @@
  * FB100000     70000000        1M      SPBA 0
  * FB000000     73F00000        1M      AIPS 1
  * FB200000     83F00000        1M      AIPS 2
- * FA100000     8FFFC000        16K     TZIC (interrupt controller)
+ *              8FFFC000        16K     TZIC (interrupt controller)
  *              90000000        256M    CSD0 SDRAM/DDR
  *              A0000000        256M    CSD1 SDRAM/DDR
  *              B0000000        128M    CS0 Flash
@@ -23,11 +23,17 @@
  *              C8000000        64M     CS3 Flash
  *              CC000000        32M     CS4 SRAM
  *              CE000000        32M     CS5 SRAM
- * F9000000     CFFF0000        64K     NFC (NAND Flash AXI)
+ *              CFFF0000        64K     NFC (NAND Flash AXI)
  *
  */
 
 /*
+ * IROM
+ */
+#define MX51_IROM_BASE_ADDR             0x0
+#define MX51_IROM_SIZE                  SZ_64K
+
+/*
  * IRAM
  */
 #define MX51_IRAM_BASE_ADDR             0x1FFE0000      /* internal ram */
@@ -40,7 +46,6 @@
  * NFC
  */
 #define MX51_NFC_AXI_BASE_ADDR          0xCFFF0000      /* NAND flash AXI */
-#define MX51_NFC_AXI_BASE_ADDR_VIRT     0xF9000000
 #define MX51_NFC_AXI_SIZE               SZ_64K
 
 /*
@@ -49,9 +54,8 @@
 #define MX51_GPU_BASE_ADDR              0x20000000
 #define MX51_GPU2D_BASE_ADDR            0xD0000000
 
-#define MX51_TZIC_BASE_ADDR             0x8FFFC000
-#define MX51_TZIC_BASE_ADDR_VIRT        0xFA100000
-#define MX51_TZIC_SIZE                  SZ_16K
+#define MX51_TZIC_BASE_ADDR_TO1         0x8FFFC000
+#define MX51_TZIC_BASE_ADDR             0xE0000000
 
 #define MX51_DEBUG_BASE_ADDR            0x60000000
 #define MX51_DEBUG_BASE_ADDR_VIRT       0xFA200000
@@ -232,12 +236,10 @@
 #define MX51_IO_ADDRESS(x)                                      \
         (void __iomem *)                                        \
         (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) :    \
-        MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) :     \
         MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) :   \
         MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) :   \
         MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) :   \
-        MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) :   \
-        MX51_IS_MODULE(x, NFC_AXI) ? MX51_NFC_AXI_IO_ADDRESS(x) : \
+        MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
         0xDEADBEEF)
 
 /*
@@ -246,9 +248,6 @@
 #define MX51_IRAM_IO_ADDRESS(x)  \
         (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
 
-#define MX51_TZIC_IO_ADDRESS(x)  \
-        (((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT)
-
 #define MX51_DEBUG_IO_ADDRESS(x)  \
         (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
 
@@ -261,9 +260,6 @@
 #define MX51_AIPS2_IO_ADDRESS(x)  \
         (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
 
-#define MX51_NFC_AXI_IO_ADDRESS(x) \
-        (((x) - MX51_NFC_AXI_BASE_ADDR) + MX51_NFC_AXI_BASE_ADDR_VIRT)
-
 #define MX51_IS_MEM_DEVICE_NONSHARED(x)         0
 
 /*
@@ -443,12 +439,7 @@
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 
-extern unsigned int system_rev;
-
-static inline unsigned int mx51_revision(void)
-{
-        return system_rev;
-}
+extern int mx51_revision(void);
 #endif
 
 #endif  /*  __ASM_ARCH_MXC_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 52e476a150ca..b6d3d0fddc48 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -66,6 +66,7 @@ static inline void flush(void)
 #define MX2X_UART1_BASE_ADDR    0x1000a000
 #define MX3X_UART1_BASE_ADDR    0x43F90000
 #define MX3X_UART2_BASE_ADDR    0x43F94000
+#define MX51_UART1_BASE_ADDR    0x73fbc000
 
 static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 {
@@ -101,6 +102,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
         case MACH_TYPE_MAGX_ZN5:
                 uart_base = MX3X_UART2_BASE_ADDR;
                 break;
+        case MACH_TYPE_MX51_BABBAGE:
+                uart_base = MX51_UART1_BASE_ADDR;
+                break;
         default:
                 break;
         }
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index 4ff6dfe04283..c36f2630ed93 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -11,6 +11,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index d28900cfa541..5a6ef252c38b 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -21,6 +21,7 @@
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/slab.h>
 
 #include <mach/hardware.h>
 #include <mach/gpio.h>
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 088c1a03b946..f12f0e39ddf2 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -44,9 +44,6 @@
 
 #define NO_LENGTH_CHECK 0xffffffff
 
-unsigned char omap_bootloader_tag[512];
-int omap_bootloader_tag_len;
-
 struct omap_board_config_kernel *omap_board_config;
 int omap_board_config_size;
 
@@ -100,10 +97,17 @@ EXPORT_SYMBOL(omap_get_var_config);
 
 #include <linux/clocksource.h>
 
+/*
+ * offset_32k holds the init time counter value. It is then subtracted
+ * from every counter read to achieve a counter that counts time from the
+ * kernel boot (needed for sched_clock()).
+ */
+static u32 offset_32k __read_mostly;
+
 #ifdef CONFIG_ARCH_OMAP16XX
 static cycle_t omap16xx_32k_read(struct clocksource *cs)
 {
-        return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED);
+        return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
 }
 #else
 #define omap16xx_32k_read       NULL
@@ -112,7 +116,7 @@ static cycle_t omap16xx_32k_read(struct clocksource *cs)
 #ifdef CONFIG_ARCH_OMAP2420
 static cycle_t omap2420_32k_read(struct clocksource *cs)
 {
-        return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10);
+        return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
 }
 #else
 #define omap2420_32k_read       NULL
@@ -121,7 +125,7 @@ static cycle_t omap2420_32k_read(struct clocksource *cs)
 #ifdef CONFIG_ARCH_OMAP2430
 static cycle_t omap2430_32k_read(struct clocksource *cs)
 {
-        return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10);
+        return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
 }
 #else
 #define omap2430_32k_read       NULL
@@ -130,7 +134,7 @@ static cycle_t omap2430_32k_read(struct clocksource *cs)
 #ifdef CONFIG_ARCH_OMAP3
 static cycle_t omap34xx_32k_read(struct clocksource *cs)
 {
-        return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10);
+        return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
 }
 #else
 #define omap34xx_32k_read       NULL
@@ -139,7 +143,7 @@ static cycle_t omap34xx_32k_read(struct clocksource *cs)
 #ifdef CONFIG_ARCH_OMAP4
 static cycle_t omap44xx_32k_read(struct clocksource *cs)
 {
-        return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10);
+        return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
 }
 #else
 #define omap44xx_32k_read       NULL
@@ -227,6 +231,8 @@ static int __init omap_init_clocksource_32k(void)
                 clocksource_32k.mult = clocksource_hz2mult(32768,
                                             clocksource_32k.shift);
 
+                offset_32k = clocksource_32k.read(&clocksource_32k);
+
                 if (clocksource_register(&clocksource_32k))
                         printk(err, clocksource_32k.name);
         }
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 4a4cd8774aaa..95677d17cd1c 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 2ab224c8e16c..1d959965ff52 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -29,6 +29,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 
 #include <asm/system.h>
 #include <mach/hardware.h>
@@ -936,6 +937,15 @@ void omap_start_dma(int lch)
 {
         u32 l;
 
+        /*
+         * The CPC/CDAC register needs to be initialized to zero
+         * before starting dma transfer.
+         */
+        if (cpu_is_omap15xx())
+                dma_write(0, CPC(lch));
+        else
+                dma_write(0, CDAC(lch));
+
         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                 int next_lch, cur_lch;
                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 76a347b3ce07..45a225d09125 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -798,7 +798,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
         case METHOD_MPUIO:
                 reg += OMAP_MPUIO_GPIO_INT_EDGE;
                 l = __raw_readl(reg);
-                if (trigger & IRQ_TYPE_EDGE_BOTH)
+                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
                         bank->toggle_mask |= 1 << gpio;
                 if (trigger & IRQ_TYPE_EDGE_RISING)
                         l |= 1 << gpio;
@@ -812,7 +812,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
         case METHOD_GPIO_1510:
                 reg += OMAP1510_GPIO_INT_CONTROL;
                 l = __raw_readl(reg);
-                if (trigger & IRQ_TYPE_EDGE_BOTH)
+                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
                         bank->toggle_mask |= 1 << gpio;
                 if (trigger & IRQ_TYPE_EDGE_RISING)
                         l |= 1 << gpio;
@@ -846,7 +846,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
         case METHOD_GPIO_7XX:
                 reg += OMAP7XX_GPIO_INT_CONTROL;
                 l = __raw_readl(reg);
-                if (trigger & IRQ_TYPE_EDGE_BOTH)
+                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
                         bank->toggle_mask |= 1 << gpio;
                 if (trigger & IRQ_TYPE_EDGE_RISING)
                         l |= 1 << gpio;
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index b65088a869e9..401701977dbb 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -345,8 +345,6 @@
 #define INT_34XX_MMC3_IRQ       94
 #define INT_34XX_GPT12_IRQ      95
 
-#define INT_34XX_BENCH_MPU_EMUL 3
-
 #define INT_35XX_HECC0_IRQ              24
 #define INT_35XX_HECC1_IRQ              28
 #define INT_35XX_EMAC_C0_RXTHRESH_IRQ   67
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 39748354ce45..7de903d7c1ce 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -59,7 +59,7 @@
 #define OMAP44XX_MCBSP1_BASE    0x49022000
 #define OMAP44XX_MCBSP2_BASE    0x49024000
 #define OMAP44XX_MCBSP3_BASE    0x49026000
-#define OMAP44XX_MCBSP4_BASE    0x48074000
+#define OMAP44XX_MCBSP4_BASE    0x48096000
 
 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 6ba88d2630d9..f8efd5466b1d 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -29,4 +29,11 @@ struct omap_nand_platform_data {
 /* size (4 KiB) for IO mapping */
 #define NAND_IO_SIZE    SZ_4K
 
+#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 extern int gpmc_nand_init(struct omap_nand_platform_data *d);
+#else
+static inline int gpmc_nand_init(struct omap_nand_platform_data *d)
+{
+        return 0;
+}
+#endif
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index 2302474a3748..b3ef1a7f53cc 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -32,7 +32,7 @@
 #define OMAP4430_PRM_BASE               0x4a306000
 #define OMAP44XX_GPMC_BASE              0x50000000
 #define OMAP443X_SCM_BASE               0x4a002000
-#define OMAP443X_CTRL_BASE              OMAP443X_SCM_BASE
+#define OMAP443X_CTRL_BASE              0x4a100000
 #define OMAP44XX_IC_BASE                0x48200000
 #define OMAP44XX_IVA_INTC_BASE          0x40000000
 #define IRQ_SIR_IRQ                     0x0040
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 440b4164f2f6..36d6ea56ab51 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -294,8 +294,8 @@ struct omap_hwmod_class_sysconfig {
         u16 rev_offs;
         u16 sysc_offs;
         u16 syss_offs;
+        u16 sysc_flags;
         u8 idlemodes;
-        u8 sysc_flags;
         u8 clockact;
         struct omap_hwmod_sysc_fields *sysc_fields;
 };
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 568578db93b6..876ca8d5e927 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -46,7 +46,7 @@ struct ehci_hcd_omap_platform_data {
 struct omap_musb_board_data {
         u8      interface_type;
         u8      mode;
-        u8      power;
+        u16     power;
 };
 
 enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
diff --git a/arch/arm/plat-omap/iommu-debug.c b/arch/arm/plat-omap/iommu-debug.c
index afd1c27cff7c..e6c0d536899c 100644
--- a/arch/arm/plat-omap/iommu-debug.c
+++ b/arch/arm/plat-omap/iommu-debug.c
@@ -13,6 +13,7 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 #include <linux/uaccess.h>
 #include <linux/platform_device.h>
 #include <linux/debugfs.h>
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 905ed832df56..0e137663349c 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -13,6 +13,7 @@
 
 #include <linux/err.h>
 #include <linux/module.h>
+#include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/clk.h>
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
index 936aef1971cd..65c6d1ff7237 100644
--- a/arch/arm/plat-omap/iovmm.c
+++ b/arch/arm/plat-omap/iovmm.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/err.h>
+#include <linux/slab.h>
 #include <linux/vmalloc.h>
 #include <linux/device.h>
 #include <linux/scatterlist.h>
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 4229cec53140..08a2df766289 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -25,6 +25,7 @@
 #include <linux/interrupt.h>
 #include <linux/device.h>
 #include <linux/delay.h>
+#include <linux/slab.h>
 
 #include <plat/mailbox.h>
 
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 52dfcc81511e..e1d0440fd4a8 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -23,6 +23,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 
 #include <plat/dma.h>
 #include <plat/mcbsp.h>
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 590435894848..0f5197479513 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -79,6 +79,7 @@
 
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/io.h>
 
diff --git a/arch/arm/plat-pxa/Kconfig b/arch/arm/plat-pxa/Kconfig
index b158e98038ed..da53395a17c6 100644
--- a/arch/arm/plat-pxa/Kconfig
+++ b/arch/arm/plat-pxa/Kconfig
@@ -1,3 +1,8 @@
 if PLAT_PXA
 
+config PXA_SSP
+        tristate
+        help
+          Enable support for PXA2xx SSP ports
+
 endif
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
index f68da35f4fb3..6187edfbcb77 100644
--- a/arch/arm/plat-pxa/Makefile
+++ b/arch/arm/plat-pxa/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PXA3xx)		+= mfp.o
 obj-$(CONFIG_ARCH_MMP)          += mfp.o
 
 obj-$(CONFIG_HAVE_PWM)          += pwm.o
+obj-$(CONFIG_PXA_SSP)           += ssp.o
diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c
index 2975798d411f..2d3c19d7c7b1 100644
--- a/arch/arm/plat-pxa/dma.c
+++ b/arch/arm/plat-pxa/dma.c
@@ -14,6 +14,7 @@
 
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/slab.h>
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
 #include <linux/errno.h>
@@ -244,7 +245,7 @@ static void pxa_dma_init_debugfs(void)
 
         dbgfs_chan = kmalloc(sizeof(*dbgfs_state) * num_dma_channels,
                              GFP_KERNEL);
-        if (!dbgfs_state)
+        if (!dbgfs_chan)
                 goto err_alloc;
 
         chandir = debugfs_create_dir("channels", dbgfs_root);
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h
index 857a6839071c..9e604c80618f 100644
--- a/arch/arm/plat-pxa/include/plat/mfp.h
+++ b/arch/arm/plat-pxa/include/plat/mfp.h
@@ -316,6 +316,13 @@ enum {
         MFP_PIN_PMIC_INT,
         MFP_PIN_RDY,
 
+        /* additional pins on MMP2 */
+        MFP_PIN_TWSI1_SCL,
+        MFP_PIN_TWSI1_SDA,
+        MFP_PIN_TWSI4_SCL,
+        MFP_PIN_TWSI4_SDA,
+        MFP_PIN_CLK_REQ,
+
         MFP_PIN_MAX,
 };
 
diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/plat-pxa/include/plat/ssp.h
index 6a2ed35acd59..fe43150690ed 100644
--- a/arch/arm/mach-pxa/include/mach/regs-ssp.h
+++ b/arch/arm/plat-pxa/include/plat/ssp.h
@@ -1,5 +1,26 @@
-#ifndef __ASM_ARCH_REGS_SSP_H
-#define __ASM_ARCH_REGS_SSP_H
+/*
+ *  ssp.h
+ *
+ *  Copyright (C) 2003 Russell King, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This driver supports the following PXA CPU/SSP ports:-
+ *
+ *       PXA250     SSP
+ *       PXA255     SSP, NSSP
+ *       PXA26x     SSP, NSSP, ASSP
+ *       PXA27x     SSP1, SSP2, SSP3
+ *       PXA3xx     SSP1, SSP2, SSP3, SSP4
+ */
+
+#ifndef __ASM_ARCH_SSP_H
+#define __ASM_ARCH_SSP_H
+
+#include <linux/list.h>
+#include <linux/io.h>
 
 /*
  * SSP Serial Port Registers
@@ -19,10 +40,7 @@
 #define SSRSA           (0x34)  /* SSP Rx Timeslot Active */
 #define SSTSS           (0x38)  /* SSP Timeslot Status */
 #define SSACD           (0x3C)  /* SSP Audio Clock Divider */
-
-#if defined(CONFIG_PXA3xx)
 #define SSACDD          (0x40)  /* SSP Audio Clock Dither Divider */
-#endif
 
 /* Common PXA2xx bits first */
 #define SSCR0_DSS       (0x0000000f)    /* Data Size Select (mask) */
@@ -33,29 +51,19 @@
 #define SSCR0_National  (0x2 << 4)      /* National Microwire */
 #define SSCR0_ECS       (1 << 6)        /* External clock select */
 #define SSCR0_SSE       (1 << 7)        /* Synchronous Serial Port Enable */
+#define SSCR0_SCR(x)    ((x) << 8)      /* Serial Clock Rate (mask) */
 
-#if defined(CONFIG_PXA25x)
-#define SSCR0_SCR       (0x0000ff00)    /* Serial Clock Rate (mask) */
-#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
-#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-#define SSCR0_SCR       (0x000fff00)    /* Serial Clock Rate (mask) */
-#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
-#endif
-
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
+/* PXA27x, PXA3xx */
 #define SSCR0_EDSS      (1 << 20)       /* Extended data size select */
 #define SSCR0_NCS       (1 << 21)       /* Network clock select */
 #define SSCR0_RIM       (1 << 22)       /* Receive FIFO overrrun interrupt mask */
 #define SSCR0_TUM       (1 << 23)       /* Transmit FIFO underrun interrupt mask */
 #define SSCR0_FRDC      (0x07000000)    /* Frame rate divider control (mask) */
 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)  /* Time slots per frame [1..8] */
+#define SSCR0_FPCKE     (1 << 29)       /* FIFO packing enable */
 #define SSCR0_ACS       (1 << 30)       /* Audio clock select */
 #define SSCR0_MOD       (1 << 31)       /* Mode (normal or network) */
-#endif
 
-#if defined(CONFIG_PXA3xx)
-#define SSCR0_FPCKE     (1 << 29)       /* FIFO packing enable */
-#endif
 
 #define SSCR1_RIE       (1 << 0)        /* Receive FIFO Interrupt Enable */
 #define SSCR1_TIE       (1 << 1)        /* Transmit FIFO Interrupt Enable */
@@ -75,10 +83,6 @@
 #define SSSR_RFS        (1 << 6)        /* Receive FIFO Service Request */
 #define SSSR_ROR        (1 << 7)        /* Receive FIFO Overrun */
 
-#define SSCR0_TIM               (1 << 23)       /* Transmit FIFO Under Run Interrupt Mask */
-#define SSCR0_RIM               (1 << 22)       /* Receive FIFO Over Run interrupt Mask */
-#define SSCR0_NCS               (1 << 21)       /* Network Clock Select */
-#define SSCR0_EDSS              (1 << 20)       /* Extended Data Size Select */
 
 /* extra bits in PXA255, PXA26x and PXA27x SSP ports */
 #define SSCR0_TISSP             (1 << 4)        /* TI Sync Serial Protocol */
@@ -108,27 +112,75 @@
 #define SSSR_TINT               (1 << 19)       /* Receiver Time-out Interrupt */
 #define SSSR_PINT               (1 << 18)       /* Peripheral Trailing Byte Interrupt */
 
-#if defined(CONFIG_PXA3xx)
-#define SSPSP_EDMYSTOP(x)       ((x) << 28)     /* Extended Dummy Stop */
-#define SSPSP_EDMYSTRT(x)       ((x) << 26)     /* Extended Dummy Start */
-#endif
 
-#define SSPSP_FSRT              (1 << 25)       /* Frame Sync Relative Timing */
-#define SSPSP_DMYSTOP(x)        ((x) << 23)     /* Dummy Stop */
-#define SSPSP_SFRMWDTH(x)       ((x) << 16)     /* Serial Frame Width */
-#define SSPSP_SFRMDLY(x)        ((x) << 9)      /* Serial Frame Delay */
-#define SSPSP_DMYSTRT(x)        ((x) << 7)      /* Dummy Start */
-#define SSPSP_STRTDLY(x)        ((x) << 4)      /* Start Delay */
-#define SSPSP_ETDS              (1 << 3)        /* End of Transfer data State */
-#define SSPSP_SFRMP             (1 << 2)        /* Serial Frame Polarity */
 #define SSPSP_SCMODE(x)         ((x) << 0)      /* Serial Bit Rate Clock Mode */
+#define SSPSP_SFRMP             (1 << 2)        /* Serial Frame Polarity */
+#define SSPSP_ETDS              (1 << 3)        /* End of Transfer data State */
+#define SSPSP_STRTDLY(x)        ((x) << 4)      /* Start Delay */
+#define SSPSP_DMYSTRT(x)        ((x) << 7)      /* Dummy Start */
+#define SSPSP_SFRMDLY(x)        ((x) << 9)      /* Serial Frame Delay */
+#define SSPSP_SFRMWDTH(x)       ((x) << 16)     /* Serial Frame Width */
+#define SSPSP_DMYSTOP(x)        ((x) << 23)     /* Dummy Stop */
+#define SSPSP_FSRT              (1 << 25)       /* Frame Sync Relative Timing */
+
+/* PXA3xx */
+#define SSPSP_EDMYSTRT(x)       ((x) << 26)     /* Extended Dummy Start */
+#define SSPSP_EDMYSTOP(x)       ((x) << 28)     /* Extended Dummy Stop */
+#define SSPSP_TIMING_MASK       (0x7f8001f0)
 
 #define SSACD_SCDB              (1 << 3)        /* SSPSYSCLK Divider Bypass */
 #define SSACD_ACPS(x)           ((x) << 4)      /* Audio clock PLL select */
 #define SSACD_ACDS(x)           ((x) << 0)      /* Audio clock divider select */
-#if defined(CONFIG_PXA3xx)
 #define SSACD_SCDX8             (1 << 7)        /* SYSCLK division ratio select */
-#endif
-
 
-#endif /* __ASM_ARCH_REGS_SSP_H */
+enum pxa_ssp_type {
+        SSP_UNDEFINED = 0,
+        PXA25x_SSP,  /* pxa 210, 250, 255, 26x */
+        PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
+        PXA27x_SSP,
+        PXA168_SSP,
+};
+
+struct ssp_device {
+        struct platform_device *pdev;
+        struct list_head        node;
+
+        struct clk      *clk;
+        void __iomem    *mmio_base;
+        unsigned long   phys_base;
+
+        const char      *label;
+        int             port_id;
+        int             type;
+        int             use_count;
+        int             irq;
+        int             drcmr_rx;
+        int             drcmr_tx;
+};
+
+/**
+ * pxa_ssp_write_reg - Write to a SSP register
+ *
+ * @dev: SSP device to access
+ * @reg: Register to write to
+ * @val: Value to be written.
+ */
+static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
+{
+        __raw_writel(val, dev->mmio_base + reg);
+}
+
+/**
+ * pxa_ssp_read_reg - Read from a SSP register
+ *
+ * @dev: SSP device to access
+ * @reg: Register to read from
+ */
+static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
+{
+        return __raw_readl(dev->mmio_base + reg);
+}
+
+struct ssp_device *pxa_ssp_request(int port, const char *label);
+void pxa_ssp_free(struct ssp_device *);
+#endif /* __ASM_ARCH_SSP_H */
diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c
index be58f9fe65b0..b77e018d36c1 100644
--- a/arch/arm/plat-pxa/mfp.c
+++ b/arch/arm/plat-pxa/mfp.c
@@ -110,6 +110,7 @@ static const unsigned long mfpr_lpm[] = {
         MFPR_LPM_PULL_LOW,
         MFPR_LPM_PULL_HIGH,
         MFPR_LPM_FLOAT,
+        MFPR_LPM_INPUT,
 };
 
 /* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */
diff --git a/arch/arm/plat-pxa/pwm.c b/arch/arm/plat-pxa/pwm.c
index 51dc5c8106c0..0732c6c8d511 100644
--- a/arch/arm/plat-pxa/pwm.c
+++ b/arch/arm/plat-pxa/pwm.c
@@ -14,6 +14,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
diff --git a/arch/arm/plat-pxa/ssp.c b/arch/arm/plat-pxa/ssp.c
new file mode 100644
index 000000000000..c6357e554aba
--- /dev/null
+++ b/arch/arm/plat-pxa/ssp.c
@@ -0,0 +1,224 @@
+/*
+ *  linux/arch/arm/mach-pxa/ssp.c
+ *
+ *  based on linux/arch/arm/mach-sa1100/ssp.c by Russell King
+ *
+ *  Copyright (C) 2003 Russell King.
+ *  Copyright (C) 2003 Wolfson Microelectronics PLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  PXA2xx SSP driver.  This provides the generic core for simple
+ *  IO-based SSP applications and allows easy port setup for DMA access.
+ *
+ *  Author: Liam Girdwood <liam.girdwood@wolfsonmicro.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/mutex.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <plat/ssp.h>
+
+static DEFINE_MUTEX(ssp_lock);
+static LIST_HEAD(ssp_list);
+
+struct ssp_device *pxa_ssp_request(int port, const char *label)
+{
+        struct ssp_device *ssp = NULL;
+
+        mutex_lock(&ssp_lock);
+
+        list_for_each_entry(ssp, &ssp_list, node) {
+                if (ssp->port_id == port && ssp->use_count == 0) {
+                        ssp->use_count++;
+                        ssp->label = label;
+                        break;
+                }
+        }
+
+        mutex_unlock(&ssp_lock);
+
+        if (&ssp->node == &ssp_list)
+                return NULL;
+
+        return ssp;
+}
+EXPORT_SYMBOL(pxa_ssp_request);
+
+void pxa_ssp_free(struct ssp_device *ssp)
+{
+        mutex_lock(&ssp_lock);
+        if (ssp->use_count) {
+                ssp->use_count--;
+                ssp->label = NULL;
+        } else
+                dev_err(&ssp->pdev->dev, "device already free\n");
+        mutex_unlock(&ssp_lock);
+}
+EXPORT_SYMBOL(pxa_ssp_free);
+
+static int __devinit pxa_ssp_probe(struct platform_device *pdev)
+{
+        const struct platform_device_id *id = platform_get_device_id(pdev);
+        struct resource *res;
+        struct ssp_device *ssp;
+        int ret = 0;
+
+        ssp = kzalloc(sizeof(struct ssp_device), GFP_KERNEL);
+        if (ssp == NULL) {
+                dev_err(&pdev->dev, "failed to allocate memory");
+                return -ENOMEM;
+        }
+        ssp->pdev = pdev;
+
+        ssp->clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(ssp->clk)) {
+                ret = PTR_ERR(ssp->clk);
+                goto err_free;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "no SSP RX DRCMR defined\n");
+                ret = -ENODEV;
+                goto err_free_clk;
+        }
+        ssp->drcmr_rx = res->start;
+
+        res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "no SSP TX DRCMR defined\n");
+                ret = -ENODEV;
+                goto err_free_clk;
+        }
+        ssp->drcmr_tx = res->start;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "no memory resource defined\n");
+                ret = -ENODEV;
+                goto err_free_clk;
+        }
+
+        res = request_mem_region(res->start, resource_size(res),
+                        pdev->name);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "failed to request memory resource\n");
+                ret = -EBUSY;
+                goto err_free_clk;
+        }
+
+        ssp->phys_base = res->start;
+
+        ssp->mmio_base = ioremap(res->start, resource_size(res));
+        if (ssp->mmio_base == NULL) {
+                dev_err(&pdev->dev, "failed to ioremap() registers\n");
+                ret = -ENODEV;
+                goto err_free_mem;
+        }
+
+        ssp->irq = platform_get_irq(pdev, 0);
+        if (ssp->irq < 0) {
+                dev_err(&pdev->dev, "no IRQ resource defined\n");
+                ret = -ENODEV;
+                goto err_free_io;
+        }
+
+        /* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id
+         * starts from 0, do a translation here
+         */
+        ssp->port_id = pdev->id + 1;
+        ssp->use_count = 0;
+        ssp->type = (int)id->driver_data;
+
+        mutex_lock(&ssp_lock);
+        list_add(&ssp->node, &ssp_list);
+        mutex_unlock(&ssp_lock);
+
+        platform_set_drvdata(pdev, ssp);
+        return 0;
+
+err_free_io:
+        iounmap(ssp->mmio_base);
+err_free_mem:
+        release_mem_region(res->start, resource_size(res));
+err_free_clk:
+        clk_put(ssp->clk);
+err_free:
+        kfree(ssp);
+        return ret;
+}
+
+static int __devexit pxa_ssp_remove(struct platform_device *pdev)
+{
+        struct resource *res;
+        struct ssp_device *ssp;
+
+        ssp = platform_get_drvdata(pdev);
+        if (ssp == NULL)
+                return -ENODEV;
+
+        iounmap(ssp->mmio_base);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(res->start, resource_size(res));
+
+        clk_put(ssp->clk);
+
+        mutex_lock(&ssp_lock);
+        list_del(&ssp->node);
+        mutex_unlock(&ssp_lock);
+
+        kfree(ssp);
+        return 0;
+}
+
+static const struct platform_device_id ssp_id_table[] = {
+        { "pxa25x-ssp",         PXA25x_SSP },
+        { "pxa25x-nssp",        PXA25x_NSSP },
+        { "pxa27x-ssp",         PXA27x_SSP },
+        { "pxa168-ssp",         PXA168_SSP },
+        { },
+};
+
+static struct platform_driver pxa_ssp_driver = {
+        .probe          = pxa_ssp_probe,
+        .remove         = __devexit_p(pxa_ssp_remove),
+        .driver         = {
+                .owner  = THIS_MODULE,
+                .name   = "pxa2xx-ssp",
+        },
+        .id_table       = ssp_id_table,
+};
+
+static int __init pxa_ssp_init(void)
+{
+        return platform_driver_register(&pxa_ssp_driver);
+}
+
+static void __exit pxa_ssp_exit(void)
+{
+        platform_driver_unregister(&pxa_ssp_driver);
+}
+
+arch_initcall(pxa_ssp_init);
+module_exit(pxa_ssp_exit);
+
+MODULE_DESCRIPTION("PXA SSP driver");
+MODULE_AUTHOR("Liam Girdwood");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 6e93ef8f3d43..3ce8f010b3c6 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -9,6 +9,7 @@ config PLAT_S3C24XX
         select NO_IOPORT
         select ARCH_REQUIRE_GPIOLIB
         select S3C_DEVICE_NAND
+        select S3C_GPIO_CFG_S3C24XX
         help
           Base platform code for any Samsung S3C24XX device
 
@@ -44,6 +45,12 @@ config S3C2410_CLOCK
           Clock code for the S3C2410, and similar processors which
           is currently includes the S3C2410, S3C2440, S3C2442.
 
+config S3C2443_CLOCK
+        bool
+        help
+          Clock code for the S3C2443 and similar processors, which includes
+          the S3C2416 and S3C2450.
+
 config S3C24XX_DCLK
         bool
         help
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index c2237c41141f..44aea8868f89 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_PM)		+= pm.o
 obj-$(CONFIG_PM)                += irq-pm.o
 obj-$(CONFIG_PM)                += sleep.o
 obj-$(CONFIG_S3C2410_CLOCK)     += s3c2410-clock.o
+obj-$(CONFIG_S3C2443_CLOCK)     += s3c2443-clock.o
 obj-$(CONFIG_S3C2410_DMA)       += dma.o
 obj-$(CONFIG_S3C2410_IOTIMING)  += s3c2410-iotiming.o
 obj-$(CONFIG_S3C2412_IOTIMING)  += s3c2412-iotiming.o
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 9e0e20ad2e46..7b44d0c592b5 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -42,6 +42,7 @@
 #include <plat/nand.h>
 
 #include <plat/common-smdk.h>
+#include <plat/gpio-cfg.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
 
@@ -185,10 +186,10 @@ void __init smdk_machine_init(void)
 {
         /* Configure the LEDs (even if we have no LED support)*/
 
-        s3c2410_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
+        s3c_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
 
         s3c2410_gpio_setpin(S3C2410_GPF(4), 1);
         s3c2410_gpio_setpin(S3C2410_GPF(5), 1);
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c
index 2d42efb9f4e9..1ecc15bfe9d4 100644
--- a/arch/arm/plat-s3c24xx/cpu-freq.c
+++ b/arch/arm/plat-s3c24xx/cpu-freq.c
@@ -23,6 +23,7 @@
 #include <linux/sysdev.h>
 #include <linux/kobject.h>
 #include <linux/sysfs.h>
+#include <linux/slab.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 9ca64df35bf6..76d0858c3cbb 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -49,6 +49,7 @@
 #include <plat/s3c2400.h>
 #include <plat/s3c2410.h>
 #include <plat/s3c2412.h>
+#include <plat/s3c2416.h>
 #include <plat/s3c244x.h>
 #include <plat/s3c2443.h>
 
@@ -57,6 +58,7 @@
 static const char name_s3c2400[]  = "S3C2400";
 static const char name_s3c2410[]  = "S3C2410";
 static const char name_s3c2412[]  = "S3C2412";
+static const char name_s3c2416[]  = "S3C2416/S3C2450";
 static const char name_s3c2440[]  = "S3C2440";
 static const char name_s3c2442[]  = "S3C2442";
 static const char name_s3c2442b[]  = "S3C2442B";
@@ -137,6 +139,15 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .init           = s3c2412_init,
                 .name           = name_s3c2412,
         },
+        {                       /* a strange version of the s3c2416 */
+                .idcode         = 0x32450003,
+                .idmask         = 0xffffffff,
+                .map_io         = s3c2416_map_io,
+                .init_clocks    = s3c2416_init_clocks,
+                .init_uarts     = s3c2416_init_uarts,
+                .init           = s3c2416_init,
+                .name           = name_s3c2416,
+        },
         {
                 .idcode         = 0x32443001,
                 .idmask         = 0xffffffff,
@@ -170,6 +181,16 @@ static struct map_desc s3c_iodesc[] __initdata = {
 
 static unsigned long s3c24xx_read_idcode_v5(void)
 {
+#if defined(CONFIG_CPU_S3C2416)
+        /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
+
+        u32 gs = __raw_readl(S3C24XX_GSTATUS1);
+
+        /* test for s3c2416 or similar device */
+        if ((gs >> 16) == 0x3245)
+                return gs;
+#endif
+
 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
         return __raw_readl(S3C2412_GSTATUS1);
 #else
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 8c6de1c9968f..9265f09bfa58 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -20,6 +20,7 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
index 5467470badfd..45126d3aafc6 100644
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/gpio.c
  *
- * Copyright (c) 2004-2005 Simtec Electronics
+ * Copyright (c) 2004-2010 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
  * S3C24XX GPIO support
@@ -20,12 +20,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
 
-
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
+#include <linux/gpio.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -34,123 +34,34 @@
 
 #include <mach/regs-gpio.h>
 
-void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
-{
-        void __iomem *base = S3C24XX_GPIO_BASE(pin);
-        unsigned long mask;
-        unsigned long con;
-        unsigned long flags;
-
-        if (pin < S3C2410_GPIO_BANKB) {
-                mask = 1 << S3C2410_GPIO_OFFSET(pin);
-        } else {
-                mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
-        }
-
-        switch (function) {
-        case S3C2410_GPIO_LEAVE:
-                mask = 0;
-                function = 0;
-                break;
-
-        case S3C2410_GPIO_INPUT:
-        case S3C2410_GPIO_OUTPUT:
-        case S3C2410_GPIO_SFN2:
-        case S3C2410_GPIO_SFN3:
-                if (pin < S3C2410_GPIO_BANKB) {
-                        function -= 1;
-                        function &= 1;
-                        function <<= S3C2410_GPIO_OFFSET(pin);
-                } else {
-                        function &= 3;
-                        function <<= S3C2410_GPIO_OFFSET(pin)*2;
-                }
-        }
-
-        /* modify the specified register wwith IRQs off */
-
-        local_irq_save(flags);
-
-        con  = __raw_readl(base + 0x00);
-        con &= ~mask;
-        con |= function;
-
-        __raw_writel(con, base + 0x00);
-
-        local_irq_restore(flags);
-}
-
-EXPORT_SYMBOL(s3c2410_gpio_cfgpin);
-
-unsigned int s3c2410_gpio_getcfg(unsigned int pin)
-{
-        void __iomem *base = S3C24XX_GPIO_BASE(pin);
-        unsigned long val = __raw_readl(base);
-
-        if (pin < S3C2410_GPIO_BANKB) {
-                val >>= S3C2410_GPIO_OFFSET(pin);
-                val &= 1;
-                val += 1;
-        } else {
-                val >>= S3C2410_GPIO_OFFSET(pin)*2;
-                val &= 3;
-        }
-
-        return val | S3C2410_GPIO_INPUT;
-}
-
-EXPORT_SYMBOL(s3c2410_gpio_getcfg);
+/* gpiolib wrappers until these are totally eliminated */
 
 void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
 {
-        void __iomem *base = S3C24XX_GPIO_BASE(pin);
-        unsigned long offs = S3C2410_GPIO_OFFSET(pin);
-        unsigned long flags;
-        unsigned long up;
+        int ret;
 
-        if (pin < S3C2410_GPIO_BANKB)
-                return;
+        WARN_ON(to);    /* should be none of these left */
 
-        local_irq_save(flags);
-
-        up = __raw_readl(base + 0x08);
-        up &= ~(1L << offs);
-        up |= to << offs;
-        __raw_writel(up, base + 0x08);
+        if (!to) {
+                /* if pull is enabled, try first with up, and if that
+                 * fails, try using down */
 
-        local_irq_restore(flags);
+                ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP);
+                if (ret)
+                        s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN);
+        } else {
+                s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE);
+        }
 }
-
 EXPORT_SYMBOL(s3c2410_gpio_pullup);
 
-int s3c2410_gpio_getpull(unsigned int pin)
-{
-        void __iomem *base = S3C24XX_GPIO_BASE(pin);
-        unsigned long offs = S3C2410_GPIO_OFFSET(pin);
-
-        if (pin < S3C2410_GPIO_BANKB)
-                return -EINVAL;
-
-        return (__raw_readl(base + 0x08) & (1L << offs)) ? 1 : 0;
-}
-
-EXPORT_SYMBOL(s3c2410_gpio_getpull);
-
 void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
 {
-        void __iomem *base = S3C24XX_GPIO_BASE(pin);
-        unsigned long offs = S3C2410_GPIO_OFFSET(pin);
-        unsigned long flags;
-        unsigned long dat;
-
-        local_irq_save(flags);
+        /* do this via gpiolib until all users removed */
 
-        dat = __raw_readl(base + 0x04);
-        dat &= ~(1 << offs);
-        dat |= to << offs;
-        __raw_writel(dat, base + 0x04);
-
-        local_irq_restore(flags);
+        gpio_request(pin, "temporary");
+        gpio_set_value(pin, to);
+        gpio_free(pin);
 }
 
 EXPORT_SYMBOL(s3c2410_gpio_setpin);
@@ -181,22 +92,3 @@ unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
 }
 
 EXPORT_SYMBOL(s3c2410_modify_misccr);
-
-int s3c2410_gpio_getirq(unsigned int pin)
-{
-        if (pin < S3C2410_GPF(0) || pin > S3C2410_GPG(15))
-                return -EINVAL; /* not valid interrupts */
-
-        if (pin < S3C2410_GPG(0) && pin > S3C2410_GPF(7))
-                return -EINVAL; /* not valid pin */
-
-        if (pin < S3C2410_GPF(4))
-                return (pin - S3C2410_GPF(0)) + IRQ_EINT0;
-
-        if (pin < S3C2410_GPG(0))
-                return (pin - S3C2410_GPF(4)) + IRQ_EINT4;
-
-        return (pin - S3C2410_GPG(0)) + IRQ_EINT8;
-}
-
-EXPORT_SYMBOL(s3c2410_gpio_getirq);
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 4f0f11a6a677..4c0896f2572d 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/gpiolib.c
  *
- * Copyright (c) 2008 Simtec Electronics
+ * Copyright (c) 2008-2010 Simtec Electronics
  *      http://armlinux.simtec.co.uk/
  *      Ben Dooks <ben@simtec.co.uk>
  *
@@ -21,6 +21,8 @@
 #include <linux/gpio.h>
 
 #include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <plat/pm.h>
@@ -77,10 +79,21 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
         return IRQ_EINT8 + offset;
 }
 
+static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
+        .set_config     = s3c_gpio_setcfg_s3c24xx_a,
+        .get_config     = s3c_gpio_getcfg_s3c24xx_a,
+};
+
+struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
+        .set_config     = s3c_gpio_setcfg_s3c24xx,
+        .get_config     = s3c_gpio_getcfg_s3c24xx,
+};
+
 struct s3c_gpio_chip s3c24xx_gpios[] = {
         [0] = {
                 .base   = S3C2410_GPACON,
                 .pm     = __gpio_pm(&s3c_gpio_pm_1bit),
+                .config = &s3c24xx_gpiocfg_banka,
                 .chip   = {
                         .base                   = S3C2410_GPA(0),
                         .owner                  = THIS_MODULE,
@@ -161,15 +174,58 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
                         .ngpio                  = 11,
                 },
         },
+                /* GPIOS for the S3C2443 and later devices. */
+        {
+                .base   = S3C2440_GPJCON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
+                .chip   = {
+                        .base                   = S3C2410_GPJ(0),
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOJ",
+                        .ngpio                  = 16,
+                },
+        }, {
+                .base   = S3C2443_GPKCON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
+                .chip   = {
+                        .base                   = S3C2410_GPK(0),
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOK",
+                        .ngpio                  = 16,
+                },
+        }, {
+                .base   = S3C2443_GPLCON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
+                .chip   = {
+                        .base                   = S3C2410_GPL(0),
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOL",
+                        .ngpio                  = 15,
+                },
+        }, {
+                .base   = S3C2443_GPMCON,
+                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
+                .chip   = {
+                        .base                   = S3C2410_GPM(0),
+                        .owner                  = THIS_MODULE,
+                        .label                  = "GPIOM",
+                        .ngpio                  = 2,
+                },
+        },
 };
 
+
 static __init int s3c24xx_gpiolib_init(void)
 {
         struct s3c_gpio_chip *chip = s3c24xx_gpios;
         int gpn;
 
-        for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++)
+        for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
+                if (!chip->config)
+                        chip->config = &s3c24xx_gpiocfg_default;
+
                 s3c_gpiolib_add(chip);
+        }
 
         return 0;
 }
diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h
index 7ea8bffa7a9c..005729a1077a 100644
--- a/arch/arm/plat-s3c24xx/include/plat/pll.h
+++ b/arch/arm/plat-s3c24xx/include/plat/pll.h
@@ -35,3 +35,28 @@ s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
 
         return (unsigned int)fvco;
 }
+
+#define S3C2416_PLL_M_SHIFT     (14)
+#define S3C2416_PLL_P_SHIFT     (5)
+#define S3C2416_PLL_S_MASK      (7)
+#define S3C2416_PLL_M_MASK      ((1 << 10) - 1)
+#define S3C2416_PLL_P_MASK      (63)
+
+static inline unsigned int
+s3c2416_get_pll(unsigned int pllval, unsigned int baseclk)
+{
+        unsigned int m, p, s;
+        uint64_t fvco;
+
+        m = pllval >> S3C2416_PLL_M_SHIFT;
+        p = pllval >> S3C2416_PLL_P_SHIFT;
+
+        s = pllval & S3C2416_PLL_S_MASK;
+        m &= S3C2416_PLL_M_MASK;
+        p &= S3C2416_PLL_P_MASK;
+
+        fvco = (uint64_t)baseclk * m;
+        do_div(fvco, (p << s));
+
+        return (unsigned int)fvco;
+}
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2416.h b/arch/arm/plat-s3c24xx/include/plat/s3c2416.h
new file mode 100644
index 000000000000..dc3c0907d221
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2416.h
@@ -0,0 +1,31 @@
+/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>
+ *
+ * Header file for s3c2416 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifdef CONFIG_CPU_S3C2416
+
+struct s3c2410_uartcfg;
+
+extern  int s3c2416_init(void);
+
+extern void s3c2416_map_io(void);
+
+extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+
+extern void s3c2416_init_clocks(int xtal);
+
+extern  int s3c2416_baseclk_add(void);
+
+#else
+#define s3c2416_init_clocks NULL
+#define s3c2416_init_uarts NULL
+#define s3c2416_map_io NULL
+#define s3c2416_init NULL
+#endif
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
index 815b107ed890..a19715feb798 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
@@ -30,3 +30,22 @@ extern  int s3c2443_baseclk_add(void);
 #define s3c2443_map_io NULL
 #define s3c2443_init NULL
 #endif
+
+/* common code used by s3c2443 and others.
+ * note, not to be used outside of arch/arm/mach-s3c* */
+
+struct clk;     /* some files don't need clk.h otherwise */
+
+typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
+typedef unsigned int (*fdiv_fn)(unsigned long clkcon0);
+
+extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv);
+extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv);
+
+extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
+extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
+extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
+
+extern struct clksrc_clk clk_epllref;
+extern struct clksrc_clk clk_esysclk;
+extern struct clksrc_clk clk_msysclk;
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 3620dd299095..60627e63a254 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -43,6 +43,7 @@
 
 #include <asm/mach/time.h>
 
+#include <plat/gpio-cfg.h>
 #include <plat/pm.h>
 
 #define PFX "s3c24xx-pm: "
@@ -90,22 +91,22 @@ static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
 {
         unsigned long irqstate;
         unsigned long pinstate;
-        int irq = s3c2410_gpio_getirq(pin);
+        int irq = gpio_to_irq(pin);
 
         if (irqoffs < 4)
                 irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
         else
                 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
 
-        pinstate = s3c2410_gpio_getcfg(pin);
+        pinstate = s3c_gpio_getcfg(pin);
 
         if (!irqstate) {
                 if (pinstate == S3C2410_GPIO_IRQ)
-                        S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
+                        S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin);
         } else {
                 if (pinstate == S3C2410_GPIO_IRQ) {
                         S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
-                        s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
+                        s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
                 }
         }
 }
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c
index b61bdb793734..9ecc5d913679 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c
@@ -87,7 +87,7 @@ static int s3c2410_upll_enable(struct clk *clk, int enable)
 
 /* standard clock definitions */
 
-static struct clk init_clocks_disable[] = {
+static struct clk init_clocks_off[] = {
         {
                 .name           = "nand",
                 .id             = -1,
@@ -249,17 +249,8 @@ int __init s3c2410_baseclk_add(void)
 
         /* install (and disable) the clocks we do not need immediately */
 
-        clkp = init_clocks_disable;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-
-                s3c2410_clkcon_enable(clkp, 0);
-        }
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
         /* show the clock-slow value */
 
diff --git a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
index 963fb0b4379e..b1908e56da1b 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
+++ b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
@@ -17,6 +17,7 @@
 #include <linux/cpufreq.h>
 #include <linux/seq_file.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 
 #include <mach/map.h>
 #include <mach/regs-mem.h>
diff --git a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
index 24993dce10b5..0b46d3895d62 100644
--- a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
+++ b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
@@ -21,6 +21,7 @@
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/slab.h>
 
 #include <linux/amba/pl093.h>
 
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
new file mode 100644
index 000000000000..461f070eb62d
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -0,0 +1,472 @@
+/* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
+ *
+ * Copyright (c) 2007, 2010 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2443 Clock control suport - common code
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/regs-s3c2443-clock.h>
+
+#include <plat/s3c2443.h>
+#include <plat/clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/cpu.h>
+
+#include <plat/cpu-freq.h>
+
+
+static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
+{
+        u32 ctrlbit = clk->ctrlbit;
+        u32 con = __raw_readl(reg);
+
+        if (enable)
+                con |= ctrlbit;
+        else
+                con &= ~ctrlbit;
+
+        __raw_writel(con, reg);
+        return 0;
+}
+
+int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
+{
+        return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
+}
+
+int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
+{
+        return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
+}
+
+int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
+{
+        return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
+}
+
+/* mpllref is a direct descendant of clk_xtal by default, but it is not
+ * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
+ * such directly equating the two source clocks is impossible.
+ */
+struct clk clk_mpllref = {
+        .name           = "mpllref",
+        .parent         = &clk_xtal,
+        .id             = -1,
+};
+
+static struct clk *clk_epllref_sources[] = {
+        [0] = &clk_mpllref,
+        [1] = &clk_mpllref,
+        [2] = &clk_xtal,
+        [3] = &clk_ext,
+};
+
+struct clksrc_clk clk_epllref = {
+        .clk    = {
+                .name           = "epllref",
+                .id             = -1,
+        },
+        .sources = &(struct clksrc_sources) {
+                .sources = clk_epllref_sources,
+                .nr_sources = ARRAY_SIZE(clk_epllref_sources),
+        },
+        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
+};
+
+/* esysclk
+ *
+ * this is sourced from either the EPLL or the EPLLref clock
+*/
+
+static struct clk *clk_sysclk_sources[] = {
+        [0] = &clk_epllref.clk,
+        [1] = &clk_epll,
+};
+
+struct clksrc_clk clk_esysclk = {
+        .clk    = {
+                .name           = "esysclk",
+                .parent         = &clk_epll,
+                .id             = -1,
+        },
+        .sources = &(struct clksrc_sources) {
+                .sources = clk_sysclk_sources,
+                .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
+        },
+        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
+};
+
+static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long div = __raw_readl(S3C2443_CLKDIV0);
+
+        div  &= S3C2443_CLKDIV0_EXTDIV_MASK;
+        div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1);       /* x2 */
+
+        return parent_rate / (div + 1);
+}
+
+static struct clk clk_mdivclk = {
+        .name           = "mdivclk",
+        .parent         = &clk_mpllref,
+        .id             = -1,
+        .ops            = &(struct clk_ops) {
+                .get_rate       = s3c2443_getrate_mdivclk,
+        },
+};
+
+static struct clk *clk_msysclk_sources[] = {
+        [0] = &clk_mpllref,
+        [1] = &clk_mpll,
+        [2] = &clk_mdivclk,
+        [3] = &clk_mpllref,
+};
+
+struct clksrc_clk clk_msysclk = {
+        .clk    = {
+                .name           = "msysclk",
+                .parent         = &clk_xtal,
+                .id             = -1,
+        },
+        .sources = &(struct clksrc_sources) {
+                .sources = clk_msysclk_sources,
+                .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
+        },
+        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
+};
+
+/* prediv
+ *
+ * this divides the msysclk down to pass to h/p/etc.
+ */
+
+static unsigned long s3c2443_prediv_getrate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+
+        clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
+        clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
+
+        return rate / (clkdiv0 + 1);
+}
+
+static struct clk clk_prediv = {
+        .name           = "prediv",
+        .id             = -1,
+        .parent         = &clk_msysclk.clk,
+        .ops            = &(struct clk_ops) {
+                .get_rate       = s3c2443_prediv_getrate,
+        },
+};
+
+/* usbhost
+ *
+ * usb host bus-clock, usually 48MHz to provide USB bus clock timing
+*/
+
+static struct clksrc_clk clk_usb_bus_host = {
+        .clk    = {
+                .name           = "usb-bus-host-parent",
+                .id             = -1,
+                .parent         = &clk_esysclk.clk,
+                .ctrlbit        = S3C2443_SCLKCON_USBHOST,
+                .enable         = s3c2443_clkcon_enable_s,
+        },
+        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
+};
+
+/* common clksrc clocks */
+
+static struct clksrc_clk clksrc_clks[] = {
+        {
+                /* ART baud-rate clock sourced from esysclk via a divisor */
+                .clk    = {
+                        .name           = "uartclk",
+                        .id             = -1,
+                        .parent         = &clk_esysclk.clk,
+                },
+                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
+        }, {
+                /* camera interface bus-clock, divided down from esysclk */
+                .clk    = {
+                        .name           = "camif-upll", /* same as 2440 name */
+                        .id             = -1,
+                        .parent         = &clk_esysclk.clk,
+                        .ctrlbit        = S3C2443_SCLKCON_CAMCLK,
+                        .enable         = s3c2443_clkcon_enable_s,
+                },
+                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
+        }, {
+                .clk    = {
+                        .name           = "display-if",
+                        .id             = -1,
+                        .parent         = &clk_esysclk.clk,
+                        .ctrlbit        = S3C2443_SCLKCON_DISPCLK,
+                        .enable         = s3c2443_clkcon_enable_s,
+                },
+                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
+        },
+};
+
+
+static struct clk init_clocks_off[] = {
+        {
+                .name           = "adc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_ADC,
+        }, {
+                .name           = "i2c",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_IIC,
+        }
+};
+
+static struct clk init_clocks[] = {
+        {
+                .name           = "dma",
+                .id             = 0,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_DMA0,
+        }, {
+                .name           = "dma",
+                .id             = 1,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_DMA1,
+        }, {
+                .name           = "dma",
+                .id             = 2,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_DMA2,
+        }, {
+                .name           = "dma",
+                .id             = 3,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_DMA3,
+        }, {
+                .name           = "dma",
+                .id             = 4,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_DMA4,
+        }, {
+                .name           = "dma",
+                .id             = 5,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_DMA5,
+        }, {
+                .name           = "hsmmc",
+                .id             = 0,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_HSMMC,
+        }, {
+                .name           = "gpio",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_GPIO,
+        }, {
+                .name           = "usb-host",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_USBH,
+        }, {
+                .name           = "usb-device",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_USBD,
+        }, {
+                .name           = "lcd",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_LCDC,
+
+        }, {
+                .name           = "timers",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_PWMT,
+        }, {
+                .name           = "cfc",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_CFC,
+        }, {
+                .name           = "ssmc",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s3c2443_clkcon_enable_h,
+                .ctrlbit        = S3C2443_HCLKCON_SSMC,
+        }, {
+                .name           = "uart",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_UART0,
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_UART1,
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_UART2,
+        }, {
+                .name           = "uart",
+                .id             = 3,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_UART3,
+        }, {
+                .name           = "rtc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_RTC,
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .parent         = &clk_p,
+                .ctrlbit        = S3C2443_PCLKCON_WDT,
+        }, {
+                .name           = "ac97",
+                .id             = -1,
+                .parent         = &clk_p,
+                .ctrlbit        = S3C2443_PCLKCON_AC97,
+        }, {
+                .name           = "nand",
+                .id             = -1,
+                .parent         = &clk_h,
+        }, {
+                .name           = "usb-bus-host",
+                .id             = -1,
+                .parent         = &clk_usb_bus_host.clk,
+        }
+};
+
+static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
+{
+        clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
+
+        return clkcon0 + 1;
+}
+
+/* EPLLCON compatible enough to get on/off information */
+
+void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
+                                                   fdiv_fn get_fdiv)
+{
+        unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
+        unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
+        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+        struct clk *xtal_clk;
+        unsigned long xtal;
+        unsigned long pll;
+        unsigned long fclk;
+        unsigned long hclk;
+        unsigned long pclk;
+        int ptr;
+
+        xtal_clk = clk_get(NULL, "xtal");
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        pll = get_mpll(mpllcon, xtal);
+        clk_msysclk.clk.rate = pll;
+
+        fclk = pll / get_fdiv(clkdiv0);
+        hclk = s3c2443_prediv_getrate(&clk_prediv);
+        hclk /= s3c2443_get_hdiv(clkdiv0);
+        pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
+
+        s3c24xx_setup_clocks(fclk, hclk, pclk);
+
+        printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
+               (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
+               print_mhz(pll), print_mhz(fclk),
+               print_mhz(hclk), print_mhz(pclk));
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
+                s3c_set_clksrc(&clksrc_clks[ptr], true);
+
+        /* ensure usb bus clock is within correct rate of 48MHz */
+
+        if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
+                printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
+                clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
+        }
+
+        printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
+               (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
+               print_mhz(clk_get_rate(&clk_epll)),
+               print_mhz(clk_get_rate(&clk_usb_bus)));
+}
+
+static struct clk *clks[] __initdata = {
+        &clk_prediv,
+        &clk_mpllref,
+        &clk_mdivclk,
+        &clk_ext,
+        &clk_epll,
+        &clk_usb_bus,
+};
+
+static struct clksrc_clk *clksrcs[] __initdata = {
+        &clk_usb_bus_host,
+        &clk_epllref,
+        &clk_esysclk,
+        &clk_msysclk,
+};
+
+void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
+                                       fdiv_fn get_fdiv)
+{
+        int ptr;
+
+        /* s3c2443 parents h and p clocks from prediv */
+        clk_h.parent = &clk_prediv;
+        clk_p.parent = &clk_prediv;
+
+        clk_usb_bus.parent = &clk_usb_bus_host.clk;
+        clk_epll.parent = &clk_epllref.clk;
+
+        s3c24xx_register_baseclocks(xtal);
+        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+                s3c_register_clksrc(clksrcs[ptr], 1);
+
+        s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
+        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+
+        /* See s3c2443/etc notes on disabling clocks at init time */
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+
+        s3c2443_common_setup_clocks(get_mpll, get_fdiv);
+}
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/plat-s3c24xx/setup-i2c.c
index 71a6accf114e..9e90a7cbd1d6 100644
--- a/arch/arm/plat-s3c24xx/setup-i2c.c
+++ b/arch/arm/plat-s3c24xx/setup-i2c.c
@@ -15,12 +15,13 @@
 
 struct platform_device;
 
+#include <plat/gpio-cfg.h>
 #include <plat/iic.h>
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA);
-        s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL);
+        s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA);
+        s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL);
 }
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
index da7a61728c18..9793544a6ace 100644
--- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
@@ -21,16 +21,16 @@ void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
                                           int enable)
 {
         if (enable) {
-                s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
-                s3c2410_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
-                s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
+                s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
+                s3c_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
+                s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
                 s3c2410_gpio_pullup(S3C2410_GPE(11), 0);
                 s3c2410_gpio_pullup(S3C2410_GPE(13), 0);
         } else {
-                s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_pullup(S3C2410_GPE(11), 1);
-                s3c2410_gpio_pullup(S3C2410_GPE(12), 1);
-                s3c2410_gpio_pullup(S3C2410_GPE(13), 1);
+                s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
+                s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
+                s3c_gpio_cfgpull(S3C2410_GPE(11), S3C_GPIO_PULL_NONE);
+                s3c_gpio_cfgpull(S3C2410_GPE(12), S3C_GPIO_PULL_NONE);
+                s3c_gpio_cfgpull(S3C2410_GPE(13), S3C_GPIO_PULL_NONE);
         }
 }
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
index 89fcf5308cf6..db9e9e477ec1 100644
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
@@ -23,16 +23,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
 
         printk(KERN_INFO "%s(%d)\n", __func__, enable);
         if (enable) {
-                s3c2410_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1);
-                s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1);
-                s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1);
+                s3c_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1);
+                s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1);
+                s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1);
                 s3c2410_gpio_pullup(S3C2410_GPD(10), 0);
                 s3c2410_gpio_pullup(S3C2410_GPD(9), 0);
         } else {
-                s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_pullup(S3C2410_GPD(10), 1);
-                s3c2410_gpio_pullup(S3C2410_GPD(9), 1);
-                s3c2410_gpio_pullup(S3C2410_GPD(8), 1);
+                s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT);
+                s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT);
+                s3c_gpio_cfgpull(S3C2410_GPD(10), S3C_GPIO_PULL_NONE);
+                s3c_gpio_cfgpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE);
+                s3c_gpio_cfgpull(S3C2410_GPD(8), S3C_GPIO_PULL_NONE);
         }
 }
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
index 86b9edc67413..8ea663a438bb 100644
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
@@ -21,16 +21,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
                                        int enable)
 {
         if (enable) {
-                s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
-                s3c2410_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
-                s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
+                s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
+                s3c_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
+                s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
                 s3c2410_gpio_pullup(S3C2410_GPG(5), 0);
                 s3c2410_gpio_pullup(S3C2410_GPG(6), 0);
         } else {
-                s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
-                s3c2410_gpio_pullup(S3C2410_GPG(5), 1);
-                s3c2410_gpio_pullup(S3C2410_GPG(6), 1);
-                s3c2410_gpio_pullup(S3C2410_GPG(7), 1);
+                s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
+                s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
+                s3c_gpio_cfgpull(S3C2410_GPG(5), S3C_GPIO_PULL_NONE);
+                s3c_gpio_cfgpull(S3C2410_GPG(6), S3C_GPIO_PULL_NONE);
+                s3c_gpio_cfgpull(S3C2410_GPG(7), S3C_GPIO_PULL_NONE);
         }
 }
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 0b5833b9ac5b..210030d5cfe1 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/sched.h>
 #include <linux/list.h>
+#include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/interrupt.h>
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 1b25c9d8c403..8bf79f3efdfb 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -376,6 +376,21 @@ void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
         }
 }
 
+/**
+ * s3c_disable_clocks() - disable an array of clocks
+ * @clkp: Pointer to the first clock in the array.
+ * @nr_clks: Number of clocks to register.
+ *
+ * for internal use only at initialisation time. disable the clocks in the
+ * @clkp array.
+ */
+
+void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
+{
+        for (; nr_clks > 0; nr_clks--, clkp++)
+                (clkp->enable)(clkp, 0);
+}
+
 /* initalise all the clocks */
 
 int __init s3c24xx_register_baseclocks(unsigned long xtal)
diff --git a/arch/arm/plat-samsung/dev-fb.c b/arch/arm/plat-samsung/dev-fb.c
index a90198fc4b0f..002a15f313f3 100644
--- a/arch/arm/plat-samsung/dev-fb.c
+++ b/arch/arm/plat-samsung/dev-fb.c
@@ -15,6 +15,7 @@
 #include <linux/string.h>
 #include <linux/platform_device.h>
 #include <linux/fb.h>
+#include <linux/gfp.h>
 
 #include <mach/irqs.h>
 #include <mach/map.h>
diff --git a/arch/arm/plat-samsung/dev-i2c0.c b/arch/arm/plat-samsung/dev-i2c0.c
index 4c761529b949..3a601c16f03c 100644
--- a/arch/arm/plat-samsung/dev-i2c0.c
+++ b/arch/arm/plat-samsung/dev-i2c0.c
@@ -11,6 +11,7 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/gfp.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/platform_device.h>
diff --git a/arch/arm/plat-samsung/dev-i2c1.c b/arch/arm/plat-samsung/dev-i2c1.c
index d44f79110506..858ee2a0414c 100644
--- a/arch/arm/plat-samsung/dev-i2c1.c
+++ b/arch/arm/plat-samsung/dev-i2c1.c
@@ -11,6 +11,7 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/gfp.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/platform_device.h>
diff --git a/arch/arm/plat-samsung/dev-nand.c b/arch/arm/plat-samsung/dev-nand.c
index a52fb6cf618f..3a7b8891ba4f 100644
--- a/arch/arm/plat-samsung/dev-nand.c
+++ b/arch/arm/plat-samsung/dev-nand.c
@@ -6,6 +6,7 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/gfp.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 
diff --git a/arch/arm/plat-samsung/dev-usb.c b/arch/arm/plat-samsung/dev-usb.c
index 88165657fa53..0e0a3bf5c982 100644
--- a/arch/arm/plat-samsung/dev-usb.c
+++ b/arch/arm/plat-samsung/dev-usb.c
@@ -11,6 +11,7 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/gfp.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/platform_device.h>
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c
index 44a84e896546..3282db360fa8 100644
--- a/arch/arm/plat-samsung/gpio-config.c
+++ b/arch/arm/plat-samsung/gpio-config.c
@@ -1,7 +1,7 @@
 /* linux/arch/arm/plat-s3c/gpio-config.c
  *
  * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
+ * Copyright 2008-2010 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *      http://armlinux.simtec.co.uk/
  *
@@ -41,6 +41,26 @@ int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
 }
 EXPORT_SYMBOL(s3c_gpio_cfgpin);
 
+unsigned s3c_gpio_getcfg(unsigned int pin)
+{
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        unsigned long flags;
+        unsigned ret = 0;
+        int offset;
+
+        if (chip) {
+                offset = pin - chip->chip.base;
+
+                local_irq_save(flags);
+                ret = s3c_gpio_do_getcfg(chip, offset);
+                local_irq_restore(flags);
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(s3c_gpio_getcfg);
+
+
 int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
 {
         struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
@@ -61,8 +81,8 @@ int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
 EXPORT_SYMBOL(s3c_gpio_setpull);
 
 #ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
-int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
-                                  unsigned int off, unsigned int cfg)
+int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
+                              unsigned int off, unsigned int cfg)
 {
         void __iomem *reg = chip->base;
         unsigned int shift = off;
@@ -87,6 +107,19 @@ int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
         return 0;
 }
 
+unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
+                                   unsigned int off)
+{
+        u32 con;
+
+        con = __raw_readl(chip->base);
+        con >>= off;
+        con &= 1;
+        con++;
+
+        return S3C_GPIO_SFN(con);
+}
+
 int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
                             unsigned int off, unsigned int cfg)
 {
@@ -109,6 +142,19 @@ int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
 
         return 0;
 }
+
+unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
+                                     unsigned int off)
+{
+        u32 con;
+
+        con = __raw_readl(chip->base);
+        con >>= off * 2;
+        con &= 3;
+
+        /* this conversion works for IN and OUT as well as special mode */
+        return S3C_GPIO_SPECIAL(con);
+}
 #endif
 
 #ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
@@ -134,6 +180,25 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
 
         return 0;
 }
+
+unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
+                                      unsigned int off)
+{
+        void __iomem *reg = chip->base;
+        unsigned int shift = (off & 7) * 4;
+        u32 con;
+
+        if (off < 8 && chip->chip.ngpio > 8)
+                reg -= 4;
+
+        con = __raw_readl(reg);
+        con >>= shift;
+        con &= 0xf;
+
+        /* this conversion works for IN and OUT as well as special mode */
+        return S3C_GPIO_SPECIAL(con);
+}
+
 #endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
 
 #ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
@@ -164,3 +229,35 @@ s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
         return (__force s3c_gpio_pull_t)pup;
 }
 #endif
+
+#ifdef CONFIG_S3C_GPIO_PULL_UP
+int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
+                         unsigned int off, s3c_gpio_pull_t pull)
+{
+        void __iomem *reg = chip->base + 0x08;
+        u32 pup = __raw_readl(reg);
+
+        pup = __raw_readl(reg);
+
+        if (pup == S3C_GPIO_PULL_UP)
+                pup &= ~(1 << off);
+        else if (pup == S3C_GPIO_PULL_NONE)
+                pup |= (1 << off);
+        else
+                return -EINVAL;
+
+        __raw_writel(pup, reg);
+        return 0;
+}
+
+s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
+                                     unsigned int off)
+{
+        void __iomem *reg = chip->base + 0x08;
+        u32 pup = __raw_readl(reg);
+
+        pup &= (1 << off);
+        return pup ? S3C_GPIO_PULL_NONE : S3C_GPIO_PULL_UP;
+}
+#endif /* CONFIG_S3C_GPIO_PULL_UP */
+
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 60b62692ac7a..12caf48a6bdc 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -91,6 +91,7 @@ extern int s3c24xx_register_clock(struct clk *clk);
 extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
 
 extern void s3c_register_clocks(struct clk *clk, int nr_clks);
+extern void s3c_disable_clocks(struct clk *clkp, int nr_clks);
 
 extern int s3c24xx_register_baseclocks(unsigned long xtal);
 
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index d316b4a579f4..5dbeb7991e60 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -73,6 +73,7 @@ extern struct sys_timer s3c24xx_timer;
 extern struct sysdev_class s3c2410_sysclass;
 extern struct sysdev_class s3c2410a_sysclass;
 extern struct sysdev_class s3c2412_sysclass;
+extern struct sysdev_class s3c2416_sysclass;
 extern struct sysdev_class s3c2440_sysclass;
 extern struct sysdev_class s3c2442_sysclass;
 extern struct sysdev_class s3c2443_sysclass;
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
index dda19da037ad..3e21c75feefa 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -30,6 +30,12 @@ static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip,
         return (chip->config->set_config)(chip, off, config);
 }
 
+static inline unsigned s3c_gpio_do_getcfg(struct s3c_gpio_chip *chip,
+                                          unsigned int off)
+{
+        return (chip->config->get_config)(chip, off);
+}
+
 static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
                                       unsigned int off, s3c_gpio_pull_t pull)
 {
@@ -53,6 +59,18 @@ extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
                                    unsigned int off, unsigned int cfg);
 
 /**
+ * s3c_gpio_getcfg_s3c24xx - S3C24XX style GPIO configuration read.
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ *
+ * The reverse of s3c_gpio_setcfg_s3c24xx(). Will return a value whicg
+ * could be directly passed back to s3c_gpio_setcfg_s3c24xx(), from the
+ * S3C_GPIO_SPECIAL() macro.
+ */
+unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
+                                     unsigned int off);
+
+/**
  * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
  * @chip: The gpio chip that is being configured.
  * @off: The offset for the GPIO being configured.
@@ -65,6 +83,21 @@ extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
 extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
                                      unsigned int off, unsigned int cfg);
 
+
+/**
+ * s3c_gpio_getcfg_s3c24xx_a - S3C24XX style GPIO configuration read (Bank A)
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ *
+ * The reverse of s3c_gpio_setcfg_s3c24xx_a() turning an GPIO into a usable
+ * GPIO configuration value.
+ *
+ * @sa s3c_gpio_getcfg_s3c24xx
+ * @sa s3c_gpio_getcfg_s3c64xx_4bit
+ */
+extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
+                                          unsigned int off);
+
 /**
  * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
  * @chip: The gpio chip that is being configured.
@@ -85,6 +118,20 @@ extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
                                         unsigned int off, unsigned int cfg);
 
 
+/**
+ * s3c_gpio_getcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config read.
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ *
+ * The reverse of s3c_gpio_setcfg_s3c64xx_4bit(), turning a gpio configuration
+ * register setting into a value the software can use, such as could be passed
+ * to s3c_gpio_setcfg_s3c64xx_4bit().
+ *
+ * @sa s3c_gpio_getcfg_s3c24xx
+ */
+extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
+                                             unsigned int off);
+
 /* Pull-{up,down} resistor controls.
  *
  * S3C2410,S3C2440,S3C24A0 = Pull-UP,
@@ -146,6 +193,17 @@ extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
                                                unsigned int off);
 
 /**
+ * s3c_gpio_getpull_1up() - Get configuration for choice of up or none
+ * @chip: The gpio chip that the GPIO pin belongs to
+ * @off: The offset to the pin to get the configuration of.
+ *
+ * This helper function reads the state of the pull-up resistor for the
+ * given GPIO in the same case as s3c_gpio_setpull_1up.
+*/
+extern s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
+                                            unsigned int off);
+
+/**
  * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
  * @chip: The gpio chip that is being configured.
  * @off: The offset for the GPIO being configured.
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index 29cd6a86cade..8d01e853df39 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -77,6 +77,17 @@ struct s3c_gpio_cfg {
  */
 extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
 
+/**
+ * s3c_gpio_getcfg - Read the current function for a GPIO pin
+ * @pin: The pin to read the configuration value for.
+ *
+ * Read the configuration state of the given @pin, returning a value that
+ * could be passed back to s3c_gpio_cfgpin().
+ *
+ * @sa s3c_gpio_cfgpin
+ */
+extern unsigned s3c_gpio_getcfg(unsigned int pin);
+
 /* Define values for the pull-{up,down} available for each gpio pin.
  *
  * These values control the state of the weak pull-{up,down} resistors
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index 49ff406a7066..f0584f26d493 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -108,6 +108,9 @@ extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
 extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
 extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
 
+/* exported for core SoC support to change */
+extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
+
 #ifdef CONFIG_S3C_GPIO_TRACK
 extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
 
diff --git a/arch/arm/plat-samsung/include/plat/pll6553x.h b/arch/arm/plat-samsung/include/plat/pll6553x.h
new file mode 100644
index 000000000000..b8b7e1d884f8
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pll6553x.h
@@ -0,0 +1,51 @@
+/* arch/arm/plat-samsung/include/plat/pll6553x.h
+ *      partially from arch/arm/mach-s3c64xx/include/mach/pll.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Samsung PLL6553x PLL code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* S3C6400 and compatible (S3C2416, etc.) EPLL code */
+
+#define PLL6553X_MDIV_MASK      ((1 << (23-16)) - 1)
+#define PLL6553X_PDIV_MASK      ((1 << (13-8)) - 1)
+#define PLL6553X_SDIV_MASK      ((1 << (2-0)) - 1)
+#define PLL6553X_MDIV_SHIFT     (16)
+#define PLL6553X_PDIV_SHIFT     (8)
+#define PLL6553X_SDIV_SHIFT     (0)
+#define PLL6553X_KDIV_MASK      (0xffff)
+
+static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
+                                             u32 pll0, u32 pll1)
+{
+        unsigned long result;
+        u32 mdiv, pdiv, sdiv, kdiv;
+        u64 tmp;
+
+        mdiv = (pll0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
+        pdiv = (pll0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
+        sdiv = (pll0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
+        kdiv = pll1 & PLL6553X_KDIV_MASK;
+
+        /* We need to multiple baseclk by mdiv (the integer part) and kdiv
+         * which is in 2^16ths, so shift mdiv up (does not overflow) and
+         * add kdiv before multiplying. The use of tmp is to avoid any
+         * overflows before shifting bac down into result when multipling
+         * by the mdiv and kdiv pair.
+         */
+
+        tmp = baseclk;
+        tmp *= (mdiv << 16) + kdiv;
+        do_div(tmp, (pdiv << sdiv));
+        result = tmp >> 16;
+
+        return result;
+}
diff --git a/arch/arm/plat-samsung/pm-check.c b/arch/arm/plat-samsung/pm-check.c
index 0b5bb774192a..e4baf76f374a 100644
--- a/arch/arm/plat-samsung/pm-check.c
+++ b/arch/arm/plat-samsung/pm-check.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/crc32.h>
 #include <linux/ioport.h>
+#include <linux/slab.h>
 
 #include <plat/pm.h>
 
diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c
index f2d11390d01c..2eeb49fa056d 100644
--- a/arch/arm/plat-samsung/pwm.c
+++ b/arch/arm/plat-samsung/pwm.c
@@ -14,6 +14,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
diff --git a/arch/arm/plat-stmp3xxx/dma.c b/arch/arm/plat-stmp3xxx/dma.c
index ef88f25fb870..b4dcf8c0477d 100644
--- a/arch/arm/plat-stmp3xxx/dma.c
+++ b/arch/arm/plat-stmp3xxx/dma.c
@@ -15,6 +15,7 @@
  * http://www.opensource.org/licenses/gpl-license.html
  * http://www.gnu.org/copyleft/gpl.html
  */
+#include <linux/gfp.h>
 #include <linux/kernel.h>
 #include <linux/device.h>
 #include <linux/dmapool.h>
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 31c2f4c30a95..8f10d24ae625 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Sat Feb 20 14:16:15 2010
+# Last update: Sat May 1 10:36:42 2010
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -2663,7 +2663,7 @@ reb01			MACH_REB01		REB01			2675
 aquila                  MACH_AQUILA             AQUILA                  2676
 spark_sls_hw2           MACH_SPARK_SLS_HW2      SPARK_SLS_HW2           2677
 sheeva_esata            MACH_ESATA_SHEEVAPLUG   ESATA_SHEEVAPLUG        2678
-surf7x30                MACH_SURF7X30           SURF7X30                2679
+msm7x30_surf            MACH_MSM7X30_SURF       MSM7X30_SURF            2679
 micro2440               MACH_MICRO2440          MICRO2440               2680
 am2440                  MACH_AM2440             AM2440                  2681
 tq2440                  MACH_TQ2440             TQ2440                  2682
@@ -2678,3 +2678,129 @@ vc088x			MACH_VC088X		VC088X			2690
 mioa702                 MACH_MIOA702            MIOA702                 2691
 hpmin                   MACH_HPMIN              HPMIN                   2692
 ak880xak                MACH_AK880XAK           AK880XAK                2693
+arm926tomap850          MACH_ARM926TOMAP850     ARM926TOMAP850          2694
+lkevm                   MACH_LKEVM              LKEVM                   2695
+mw6410                  MACH_MW6410             MW6410                  2696
+terastation_wxl         MACH_TERASTATION_WXL    TERASTATION_WXL         2697
+cpu8000e                MACH_CPU8000E           CPU8000E                2698
+catania                 MACH_CATANIA            CATANIA                 2699
+tokyo                   MACH_TOKYO              TOKYO                   2700
+msm7201a_surf           MACH_MSM7201A_SURF      MSM7201A_SURF           2701
+msm7201a_ffa            MACH_MSM7201A_FFA       MSM7201A_FFA            2702
+msm7x25_surf            MACH_MSM7X25_SURF       MSM7X25_SURF            2703
+msm7x25_ffa             MACH_MSM7X25_FFA        MSM7X25_FFA             2704
+msm7x27_surf            MACH_MSM7X27_SURF       MSM7X27_SURF            2705
+msm7x27_ffa             MACH_MSM7X27_FFA        MSM7X27_FFA             2706
+msm7x30_ffa             MACH_MSM7X30_FFA        MSM7X30_FFA             2707
+qsd8x50_surf            MACH_QSD8X50_SURF       QSD8X50_SURF            2708
+qsd8x50_comet           MACH_QSD8X50_COMET      QSD8X50_COMET           2709
+qsd8x50_ffa             MACH_QSD8X50_FFA        QSD8X50_FFA             2710
+qsd8x50a_surf           MACH_QSD8X50A_SURF      QSD8X50A_SURF           2711
+qsd8x50a_ffa            MACH_QSD8X50A_FFA       QSD8X50A_FFA            2712
+adx_xgcp10              MACH_ADX_XGCP10         ADX_XGCP10              2713
+mcgwumts2a              MACH_MCGWUMTS2A         MCGWUMTS2A              2714
+mobikt                  MACH_MOBIKT             MOBIKT                  2715
+mx53_evk                MACH_MX53_EVK           MX53_EVK                2716
+igep0030                MACH_IGEP0030           IGEP0030                2717
+axell_h40_h50_ctrl      MACH_AXELL_H40_H50_CTRL AXELL_H40_H50_CTRL      2718
+dtcommod                MACH_DTCOMMOD           DTCOMMOD                2719
+gould                   MACH_GOULD              GOULD                   2720
+siberia                 MACH_SIBERIA            SIBERIA                 2721
+sbc3530                 MACH_SBC3530            SBC3530                 2722
+qarm                    MACH_QARM               QARM                    2723
+mips                    MACH_MIPS               MIPS                    2724
+mx27grb                 MACH_MX27GRB            MX27GRB                 2725
+sbc8100                 MACH_SBC8100            SBC8100                 2726
+saarb                   MACH_SAARB              SAARB                   2727
+omap3mini               MACH_OMAP3MINI          OMAP3MINI               2728
+cnmbook7se              MACH_CNMBOOK7SE         CNMBOOK7SE              2729
+catan                   MACH_CATAN              CATAN                   2730
+harmony                 MACH_HARMONY            HARMONY                 2731
+tonga                   MACH_TONGA              TONGA                   2732
+cybook_orizon           MACH_CYBOOK_ORIZON      CYBOOK_ORIZON           2733
+htcrhodiumcdma          MACH_HTCRHODIUMCDMA     HTCRHODIUMCDMA          2734
+epc_g45                 MACH_EPC_G45            EPC_G45                 2735
+epc_lpc3250             MACH_EPC_LPC3250        EPC_LPC3250             2736
+mxc91341evb             MACH_MXC91341EVB        MXC91341EVB             2737
+rtw1000                 MACH_RTW1000            RTW1000                 2738
+bobcat                  MACH_BOBCAT             BOBCAT                  2739
+trizeps6                MACH_TRIZEPS6           TRIZEPS6                2740
+msm7x30_fluid           MACH_MSM7X30_FLUID      MSM7X30_FLUID           2741
+nedap9263               MACH_NEDAP9263          NEDAP9263               2742
+netgear_ms2110          MACH_NETGEAR_MS2110     NETGEAR_MS2110          2743
+bmx                     MACH_BMX                BMX                     2744
+netstream               MACH_NETSTREAM          NETSTREAM               2745
+vpnext_rcu              MACH_VPNEXT_RCU         VPNEXT_RCU              2746
+vpnext_mpu              MACH_VPNEXT_MPU         VPNEXT_MPU              2747
+bcmring_tablet_v1       MACH_BCMRING_TABLET_V1  BCMRING_TABLET_V1       2748
+sgarm10                 MACH_SGARM10            SGARM10                 2749
+cm_t3517                MACH_CM_T3517           CM_T3517                2750
+omap3_cps               MACH_OMAP3_CPS          OMAP3_CPS               2751
+axar1500_receiver       MACH_AXAR1500_RECEIVER  AXAR1500_RECEIVER       2752
+wbd222                  MACH_WBD222             WBD222                  2753
+mt65xx                  MACH_MT65XX             MT65XX                  2754
+msm8x60_surf            MACH_MSM8X60_SURF       MSM8X60_SURF            2755
+msm8x60_sim             MACH_MSM8X60_SIM        MSM8X60_SIM             2756
+vmc300                  MACH_VMC300             VMC300                  2757
+tcc8000_sdk             MACH_TCC8000_SDK        TCC8000_SDK             2758
+nanos                   MACH_NANOS              NANOS                   2759
+stamp9g10               MACH_STAMP9G10          STAMP9G10               2760
+stamp9g45               MACH_STAMP9G45          STAMP9G45               2761
+h6053                   MACH_H6053              H6053                   2762
+smint01                 MACH_SMINT01            SMINT01                 2763
+prtlvt2                 MACH_PRTLVT2            PRTLVT2                 2764
+ap420                   MACH_AP420              AP420                   2765
+htcshift                MACH_HTCSHIFT           HTCSHIFT                2766
+davinci_dm365_fc        MACH_DAVINCI_DM365_FC   DAVINCI_DM365_FC        2767
+msm8x55_surf            MACH_MSM8X55_SURF       MSM8X55_SURF            2768
+msm8x55_ffa             MACH_MSM8X55_FFA        MSM8X55_FFA             2769
+esl_vamana              MACH_ESL_VAMANA         ESL_VAMANA              2770
+sbc35                   MACH_SBC35              SBC35                   2771
+mpx6446                 MACH_MPX6446            MPX6446                 2772
+oreo_controller         MACH_OREO_CONTROLLER    OREO_CONTROLLER         2773
+kopin_models            MACH_KOPIN_MODELS       KOPIN_MODELS            2774
+ttc_vision2             MACH_TTC_VISION2        TTC_VISION2             2775
+cns3420vb               MACH_CNS3420VB          CNS3420VB               2776
+lpc2                    MACH_LPC2               LPC2                    2777
+olympus                 MACH_OLYMPUS            OLYMPUS                 2778
+vortex                  MACH_VORTEX             VORTEX                  2779
+s5pc200                 MACH_S5PC200            S5PC200                 2780
+ecucore_9263            MACH_ECUCORE_9263       ECUCORE_9263            2781
+smdkc200                MACH_SMDKC200           SMDKC200                2782
+emsiso_sx27             MACH_EMSISO_SX27        EMSISO_SX27             2783
+apx_som9g45_ek          MACH_APX_SOM9G45_EK     APX_SOM9G45_EK          2784
+songshan                MACH_SONGSHAN           SONGSHAN                2785
+tianshan                MACH_TIANSHAN           TIANSHAN                2786
+vpx500                  MACH_VPX500             VPX500                  2787
+am3517sam               MACH_AM3517SAM          AM3517SAM               2788
+skat91_sim508           MACH_SKAT91_SIM508      SKAT91_SIM508           2789
+skat91_s3e              MACH_SKAT91_S3E         SKAT91_S3E              2790
+omap4_panda             MACH_OMAP4_PANDA        OMAP4_PANDA             2791
+df7220                  MACH_DF7220             DF7220                  2792
+nemini                  MACH_NEMINI             NEMINI                  2793
+t8200                   MACH_T8200              T8200                   2794
+apf51                   MACH_APF51              APF51                   2795
+dr_rc_unit              MACH_DR_RC_UNIT         DR_RC_UNIT              2796
+bordeaux                MACH_BORDEAUX           BORDEAUX                2797
+catania_b               MACH_CATANIA_B          CATANIA_B               2798
+mx51_ocean              MACH_MX51_OCEAN         MX51_OCEAN              2799
+ti8168evm               MACH_TI8168EVM          TI8168EVM               2800
+neocoreomap             MACH_NEOCOREOMAP        NEOCOREOMAP             2801
+withings_wbp            MACH_WITHINGS_WBP       WITHINGS_WBP            2802
+dbps                    MACH_DBPS               DBPS                    2803
+sbc9261                 MACH_SBC9261            SBC9261                 2804
+pcbfp0001               MACH_PCBFP0001          PCBFP0001               2805
+speedy                  MACH_SPEEDY             SPEEDY                  2806
+chrysaor                MACH_CHRYSAOR           CHRYSAOR                2807
+tango                   MACH_TANGO              TANGO                   2808
+synology_dsx11          MACH_SYNOLOGY_DSX11     SYNOLOGY_DSX11          2809
+hanlin_v3ext            MACH_HANLIN_V3EXT       HANLIN_V3EXT            2810
+hanlin_v5               MACH_HANLIN_V5          HANLIN_V5               2811
+hanlin_v3plus           MACH_HANLIN_V3PLUS      HANLIN_V3PLUS           2812
+iriver_story            MACH_IRIVER_STORY       IRIVER_STORY            2813
+irex_iliad              MACH_IREX_ILIAD         IREX_ILIAD              2814
+irex_dr1000             MACH_IREX_DR1000        IREX_DR1000             2815
+teton_bga               MACH_TETON_BGA          TETON_BGA               2816
+snapper9g45             MACH_SNAPPER9G45        SNAPPER9G45             2817
+tam3517                 MACH_TAM3517            TAM3517                 2818
+pdc100                  MACH_PDC100             PDC100                  2819
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 7f3f59fcaa21..315a540c7ce5 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -428,26 +428,6 @@ static void vfp_pm_init(void)
 static inline void vfp_pm_init(void) { }
 #endif /* CONFIG_PM */
 
-/*
- * Synchronise the hardware VFP state of a thread other than current with the
- * saved one. This function is used by the ptrace mechanism.
- */
-#ifdef CONFIG_SMP
-void vfp_sync_hwstate(struct thread_info *thread)
-{
-}
-
-void vfp_flush_hwstate(struct thread_info *thread)
-{
-        /*
-         * On SMP systems, the VFP state is automatically saved at every
-         * context switch. We mark the thread VFP state as belonging to a
-         * non-existent CPU so that the saved one will be reloaded when
-         * needed.
-         */
-        thread->vfpstate.hard.cpu = NR_CPUS;
-}
-#else
 void vfp_sync_hwstate(struct thread_info *thread)
 {
         unsigned int cpu = get_cpu();
@@ -490,9 +470,18 @@ void vfp_flush_hwstate(struct thread_info *thread)
                 last_VFP_context[cpu] = NULL;
         }
 
+#ifdef CONFIG_SMP
+        /*
+         * For SMP we still have to take care of the case where the thread
+         * migrates to another CPU and then back to the original CPU on which
+         * the last VFP user is still the same thread. Mark the thread VFP
+         * state as belonging to a non-existent CPU so that the saved one will
+         * be reloaded in the above case.
+         */
+        thread->vfpstate.hard.cpu = NR_CPUS;
+#endif
         put_cpu();
 }
-#endif
 
 #include <linux/smp.h>
 
@@ -545,7 +534,7 @@ static int __init vfp_init(void)
                  */
                 elf_hwcap |= HWCAP_VFP;
 #ifdef CONFIG_VFPv3
-                if (VFP_arch >= 3) {
+                if (VFP_arch >= 2) {
                         elf_hwcap |= HWCAP_VFPv3;
 
                         /*