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authorOlof Johansson <olof@lixom.net>2015-04-03 13:44:28 -0400
committerOlof Johansson <olof@lixom.net>2015-04-03 13:44:28 -0400
commitaabab880c5441cd39aef75fc1ecaa3125efb7a89 (patch)
treefa16a997164b3445bb3db233e229c56f9919ac49 /arch/arm
parent4580cb8a9812c3acc7a1663064d2a2800b3541bd (diff)
parent8590ca655a19f9e124b52bfbf28f14eb16a05bec (diff)
Merge tag 'at91-cleanup3' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/drivers
Merge "at91: cleanup for 4.1 #3" from Nicolas Ferre: Third batch of cleanup for 4.1: - System Timer (ST) for at91rm9200 re-work (syscon/regmap): - watchdog - restart handler - timer as a proper clocksource => remove mach dependency + cleanup * tag 'at91-cleanup3' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: (54 commits) ARM: at91: remove useless include clocksource: atmel-st: remove mach/hardware dependency clocksource: atmel-st: use syscon/regmap ARM: at91: time: move the system timer driver to drivers/clocksource ARM: at91: properly initialize timer ARM: at91: at91rm9200: remove deprecated arm_pm_restart watchdog: at91rm9200: implement restart handler watchdog: at91rm9200: use the system timer syscon mfd: syscon: Add atmel system timer registers definition ARM: at91/dt: declare atmel,at91rm9200-st as a syscon ARM: at91: remove old setup ARM: at91: sama5d4: remove useless map_io ARM: at91: sama5 use SoC detection infrastructure ARM: at91: at91sam9: use SoC detection infrastructure ARM: at91: at91rm9200 use SoC detection infrastructure ARM: at91: add soc detection infrastructure ARM: at91/dt: introduce atmel,<chip>-dbgu ARM: at91: remove unused _matrix.h headers ARM: at91: remove unused at91_ioremap_matrix and header ARM: at91: remove NEED_MACH_IO_H ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/dts/at91rm9200.dtsi8
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi9
-rw-r--r--arch/arm/boot/dts/at91sam9261.dtsi11
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi7
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi5
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi3
-rw-r--r--arch/arm/boot/dts/at91sam9rl.dtsi2
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi7
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi5
-rw-r--r--arch/arm/boot/dts/sama5d4.dtsi11
-rw-r--r--arch/arm/configs/at91_dt_defconfig1
-rw-r--r--arch/arm/configs/sama5_defconfig2
-rw-r--r--arch/arm/include/debug/at91.S5
-rw-r--r--arch/arm/mach-at91/Kconfig20
-rw-r--r--arch/arm/mach-at91/Makefile6
-rw-r--r--arch/arm/mach-at91/at91rm9200.c46
-rw-r--r--arch/arm/mach-at91/at91rm9200_time.c251
-rw-r--r--arch/arm/mach-at91/at91sam9.c76
-rw-r--r--arch/arm/mach-at91/generic.h7
-rw-r--r--arch/arm/mach-at91/include/mach/at91_matrix.h23
-rw-r--r--arch/arm/mach-at91/include/mach/at91_st.h61
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260_matrix.h80
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261_matrix.h64
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263_matrix.h129
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h153
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h53
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h96
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h53
-rw-r--r--arch/arm/mach-at91/include/mach/io.h27
-rw-r--r--arch/arm/mach-at91/pm.c159
-rw-r--r--arch/arm/mach-at91/pm.h16
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S323
-rw-r--r--arch/arm/mach-at91/pm_suspend.S338
-rw-r--r--arch/arm/mach-at91/sama5.c97
-rw-r--r--arch/arm/mach-at91/setup.c330
-rw-r--r--arch/arm/mach-at91/soc.c97
-rw-r--r--arch/arm/mach-at91/soc.h78
38 files changed, 747 insertions, 1914 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7ffd1518d2aa..4d66f33cb200 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -361,9 +361,9 @@ config ARCH_AT91
361 select ARCH_REQUIRE_GPIOLIB 361 select ARCH_REQUIRE_GPIOLIB
362 select CLKDEV_LOOKUP 362 select CLKDEV_LOOKUP
363 select IRQ_DOMAIN 363 select IRQ_DOMAIN
364 select NEED_MACH_IO_H if PCCARD
365 select PINCTRL 364 select PINCTRL
366 select PINCTRL_AT91 365 select PINCTRL_AT91
366 select SOC_BUS
367 select USE_OF 367 select USE_OF
368 help 368 help
369 This enables support for systems based on Atmel 369 This enables support for systems based on Atmel
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 21c2b504f977..4fb333bd1f85 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -356,9 +356,13 @@
356 }; 356 };
357 357
358 st: timer@fffffd00 { 358 st: timer@fffffd00 {
359 compatible = "atmel,at91rm9200-st"; 359 compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
360 reg = <0xfffffd00 0x100>; 360 reg = <0xfffffd00 0x100>;
361 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 361 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
362
363 watchdog {
364 compatible = "atmel,at91rm9200-wdt";
365 };
362 }; 366 };
363 367
364 rtc: rtc@fffffe00 { 368 rtc: rtc@fffffe00 {
@@ -830,7 +834,7 @@
830 }; 834 };
831 835
832 dbgu: serial@fffff200 { 836 dbgu: serial@fffff200 {
833 compatible = "atmel,at91rm9200-usart"; 837 compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart";
834 reg = <0xfffff200 0x200>; 838 reg = <0xfffff200 0x200>;
835 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 839 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
836 pinctrl-names = "default"; 840 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index fff0ee69aab4..7d989a8a9cf7 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -494,12 +494,12 @@
494 494
495 pinctrl_usart3_rts: usart3_rts-0 { 495 pinctrl_usart3_rts: usart3_rts-0 {
496 atmel,pins = 496 atmel,pins =
497 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */ 497 <AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
498 }; 498 };
499 499
500 pinctrl_usart3_cts: usart3_cts-0 { 500 pinctrl_usart3_cts: usart3_cts-0 {
501 atmel,pins = 501 atmel,pins =
502 <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */ 502 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
503 }; 503 };
504 }; 504 };
505 505
@@ -753,7 +753,7 @@
753 }; 753 };
754 754
755 dbgu: serial@fffff200 { 755 dbgu: serial@fffff200 {
756 compatible = "atmel,at91sam9260-usart"; 756 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
757 reg = <0xfffff200 0x200>; 757 reg = <0xfffff200 0x200>;
758 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 758 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
759 pinctrl-names = "default"; 759 pinctrl-names = "default";
@@ -853,7 +853,7 @@
853 }; 853 };
854 854
855 usb1: gadget@fffa4000 { 855 usb1: gadget@fffa4000 {
856 compatible = "atmel,at91rm9200-udc"; 856 compatible = "atmel,at91sam9260-udc";
857 reg = <0xfffa4000 0x4000>; 857 reg = <0xfffa4000 0x4000>;
858 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; 858 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
859 clocks = <&udc_clk>, <&udpck>; 859 clocks = <&udc_clk>, <&udpck>;
@@ -976,7 +976,6 @@
976 atmel,watchdog-type = "hardware"; 976 atmel,watchdog-type = "hardware";
977 atmel,reset-type = "all"; 977 atmel,reset-type = "all";
978 atmel,dbg-halt; 978 atmel,dbg-halt;
979 atmel,idle-halt;
980 status = "disabled"; 979 status = "disabled";
981 }; 980 };
982 981
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index e247b0b5fdab..bf8d1856a55a 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -124,11 +124,12 @@
124 }; 124 };
125 125
126 usb1: gadget@fffa4000 { 126 usb1: gadget@fffa4000 {
127 compatible = "atmel,at91rm9200-udc"; 127 compatible = "atmel,at91sam9261-udc";
128 reg = <0xfffa4000 0x4000>; 128 reg = <0xfffa4000 0x4000>;
129 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; 129 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
130 clocks = <&usb>, <&udc_clk>, <&udpck>; 130 clocks = <&udc_clk>, <&udpck>;
131 clock-names = "usb_clk", "udc_clk", "udpck"; 131 clock-names = "pclk", "hclk";
132 atmel,matrix = <&matrix>;
132 status = "disabled"; 133 status = "disabled";
133 }; 134 };
134 135
@@ -262,7 +263,7 @@
262 }; 263 };
263 264
264 matrix: matrix@ffffee00 { 265 matrix: matrix@ffffee00 {
265 compatible = "atmel,at91sam9260-bus-matrix"; 266 compatible = "atmel,at91sam9260-bus-matrix", "syscon";
266 reg = <0xffffee00 0x200>; 267 reg = <0xffffee00 0x200>;
267 }; 268 };
268 269
@@ -275,7 +276,7 @@
275 }; 276 };
276 277
277 dbgu: serial@fffff200 { 278 dbgu: serial@fffff200 {
278 compatible = "atmel,at91sam9260-usart"; 279 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
279 reg = <0xfffff200 0x200>; 280 reg = <0xfffff200 0x200>;
280 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 281 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
281 pinctrl-names = "default"; 282 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 1f67bb4c144e..e07dae75be77 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -69,7 +69,7 @@
69 69
70 sram1: sram@00500000 { 70 sram1: sram@00500000 {
71 compatible = "mmio-sram"; 71 compatible = "mmio-sram";
72 reg = <0x00300000 0x4000>; 72 reg = <0x00500000 0x4000>;
73 }; 73 };
74 74
75 ahb { 75 ahb {
@@ -762,7 +762,7 @@
762 }; 762 };
763 763
764 dbgu: serial@ffffee00 { 764 dbgu: serial@ffffee00 {
765 compatible = "atmel,at91sam9260-usart"; 765 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
766 reg = <0xffffee00 0x200>; 766 reg = <0xffffee00 0x200>;
767 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 767 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
768 pinctrl-names = "default"; 768 pinctrl-names = "default";
@@ -856,7 +856,7 @@
856 }; 856 };
857 857
858 usb1: gadget@fff78000 { 858 usb1: gadget@fff78000 {
859 compatible = "atmel,at91rm9200-udc"; 859 compatible = "atmel,at91sam9263-udc";
860 reg = <0xfff78000 0x4000>; 860 reg = <0xfff78000 0x4000>;
861 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; 861 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
862 clocks = <&udc_clk>, <&udpck>; 862 clocks = <&udc_clk>, <&udpck>;
@@ -905,7 +905,6 @@
905 atmel,watchdog-type = "hardware"; 905 atmel,watchdog-type = "hardware";
906 atmel,reset-type = "all"; 906 atmel,reset-type = "all";
907 atmel,dbg-halt; 907 atmel,dbg-halt;
908 atmel,idle-halt;
909 status = "disabled"; 908 status = "disabled";
910 }; 909 };
911 910
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index ee80aa9c0759..56b66a795df7 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -893,7 +893,7 @@
893 }; 893 };
894 894
895 dbgu: serial@ffffee00 { 895 dbgu: serial@ffffee00 {
896 compatible = "atmel,at91sam9260-usart"; 896 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
897 reg = <0xffffee00 0x200>; 897 reg = <0xffffee00 0x200>;
898 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 898 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
899 pinctrl-names = "default"; 899 pinctrl-names = "default";
@@ -1116,7 +1116,6 @@
1116 atmel,watchdog-type = "hardware"; 1116 atmel,watchdog-type = "hardware";
1117 atmel,reset-type = "all"; 1117 atmel,reset-type = "all";
1118 atmel,dbg-halt; 1118 atmel,dbg-halt;
1119 atmel,idle-halt;
1120 status = "disabled"; 1119 status = "disabled";
1121 }; 1120 };
1122 1121
@@ -1301,7 +1300,7 @@
1301 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1300 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1302 reg = <0x00800000 0x100000>; 1301 reg = <0x00800000 0x100000>;
1303 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1302 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1304 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; 1303 clocks = <&utmi>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1305 clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck"; 1304 clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck";
1306 status = "disabled"; 1305 status = "disabled";
1307 }; 1306 };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index c2666a7cb5b1..ea0af0f6ec7d 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -757,7 +757,7 @@
757 }; 757 };
758 758
759 dbgu: serial@fffff200 { 759 dbgu: serial@fffff200 {
760 compatible = "atmel,at91sam9260-usart"; 760 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
761 reg = <0xfffff200 0x200>; 761 reg = <0xfffff200 0x200>;
762 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 762 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
763 pinctrl-names = "default"; 763 pinctrl-names = "default";
@@ -894,7 +894,6 @@
894 atmel,watchdog-type = "hardware"; 894 atmel,watchdog-type = "hardware";
895 atmel,reset-type = "all"; 895 atmel,reset-type = "all";
896 atmel,dbg-halt; 896 atmel,dbg-halt;
897 atmel,idle-halt;
898 status = "disabled"; 897 status = "disabled";
899 }; 898 };
900 899
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 40f645b8fe25..ebfd5ce9cb38 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -377,7 +377,7 @@
377 }; 377 };
378 378
379 dbgu: serial@fffff200 { 379 dbgu: serial@fffff200 {
380 compatible = "atmel,at91sam9260-usart"; 380 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
381 reg = <0xfffff200 0x200>; 381 reg = <0xfffff200 0x200>;
382 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 382 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
383 pinctrl-names = "default"; 383 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 818dabdd8c0e..3aa56ae3410a 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -860,7 +860,7 @@
860 }; 860 };
861 861
862 dbgu: serial@fffff200 { 862 dbgu: serial@fffff200 {
863 compatible = "atmel,at91sam9260-usart"; 863 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
864 reg = <0xfffff200 0x200>; 864 reg = <0xfffff200 0x200>;
865 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 865 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
866 pinctrl-names = "default"; 866 pinctrl-names = "default";
@@ -1066,7 +1066,7 @@
1066 reg = <0x00500000 0x80000 1066 reg = <0x00500000 0x80000
1067 0xf803c000 0x400>; 1067 0xf803c000 0x400>;
1068 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; 1068 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
1069 clocks = <&usb>, <&udphs_clk>; 1069 clocks = <&utmi>, <&udphs_clk>;
1070 clock-names = "hclk", "pclk"; 1070 clock-names = "hclk", "pclk";
1071 status = "disabled"; 1071 status = "disabled";
1072 1072
@@ -1130,7 +1130,6 @@
1130 atmel,watchdog-type = "hardware"; 1130 atmel,watchdog-type = "hardware";
1131 atmel,reset-type = "all"; 1131 atmel,reset-type = "all";
1132 atmel,dbg-halt; 1132 atmel,dbg-halt;
1133 atmel,idle-halt;
1134 status = "disabled"; 1133 status = "disabled";
1135 }; 1134 };
1136 1135
@@ -1186,7 +1185,7 @@
1186 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1185 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1187 reg = <0x00700000 0x100000>; 1186 reg = <0x00700000 0x100000>;
1188 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1187 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1189 clocks = <&usb>, <&uhphs_clk>, <&uhpck>; 1188 clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
1190 clock-names = "usb_clk", "ehci_clk", "uhpck"; 1189 clock-names = "usb_clk", "ehci_clk", "uhpck";
1191 status = "disabled"; 1190 status = "disabled";
1192 }; 1191 };
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 261311bdf65b..c0a8dfcf8380 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -439,7 +439,7 @@
439 }; 439 };
440 440
441 dbgu: serial@ffffee00 { 441 dbgu: serial@ffffee00 {
442 compatible = "atmel,at91sam9260-usart"; 442 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
443 reg = <0xffffee00 0x200>; 443 reg = <0xffffee00 0x200>;
444 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; 444 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
445 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, 445 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
@@ -1248,7 +1248,6 @@
1248 atmel,watchdog-type = "hardware"; 1248 atmel,watchdog-type = "hardware";
1249 atmel,reset-type = "all"; 1249 atmel,reset-type = "all";
1250 atmel,dbg-halt; 1250 atmel,dbg-halt;
1251 atmel,idle-halt;
1252 status = "disabled"; 1251 status = "disabled";
1253 }; 1252 };
1254 1253
@@ -1416,7 +1415,7 @@
1416 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1415 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1417 reg = <0x00700000 0x100000>; 1416 reg = <0x00700000 0x100000>;
1418 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1417 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1419 clocks = <&usb>, <&uhphs_clk>, <&uhpck>; 1418 clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
1420 clock-names = "usb_clk", "ehci_clk", "uhpck"; 1419 clock-names = "usb_clk", "ehci_clk", "uhpck";
1421 status = "disabled"; 1420 status = "disabled";
1422 }; 1421 };
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index d986b41b9654..782587df5f3f 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -66,6 +66,7 @@
66 gpio4 = &pioE; 66 gpio4 = &pioE;
67 tcb0 = &tcb0; 67 tcb0 = &tcb0;
68 tcb1 = &tcb1; 68 tcb1 = &tcb1;
69 i2c0 = &i2c0;
69 i2c2 = &i2c2; 70 i2c2 = &i2c2;
70 }; 71 };
71 cpus { 72 cpus {
@@ -259,7 +260,7 @@
259 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 260 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
260 reg = <0x00600000 0x100000>; 261 reg = <0x00600000 0x100000>;
261 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; 262 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
262 clocks = <&usb>, <&uhphs_clk>, <&uhpck>; 263 clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
263 clock-names = "usb_clk", "ehci_clk", "uhpck"; 264 clock-names = "usb_clk", "ehci_clk", "uhpck";
264 status = "disabled"; 265 status = "disabled";
265 }; 266 };
@@ -461,8 +462,8 @@
461 462
462 lcdck: lcdck { 463 lcdck: lcdck {
463 #clock-cells = <0>; 464 #clock-cells = <0>;
464 reg = <4>; 465 reg = <3>;
465 clocks = <&smd>; 466 clocks = <&mck>;
466 }; 467 };
467 468
468 smdck: smdck { 469 smdck: smdck {
@@ -770,7 +771,7 @@
770 reg = <50>; 771 reg = <50>;
771 }; 772 };
772 773
773 lcd_clk: lcd_clk { 774 lcdc_clk: lcdc_clk {
774 #clock-cells = <0>; 775 #clock-cells = <0>;
775 reg = <51>; 776 reg = <51>;
776 }; 777 };
@@ -1063,7 +1064,7 @@
1063 }; 1064 };
1064 1065
1065 dbgu: serial@fc069000 { 1066 dbgu: serial@fc069000 {
1066 compatible = "atmel,at91sam9260-usart"; 1067 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1067 reg = <0xfc069000 0x200>; 1068 reg = <0xfc069000 0x200>;
1068 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; 1069 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
1069 pinctrl-names = "default"; 1070 pinctrl-names = "default";
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index f2670f638e97..811e72bbe642 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -70,6 +70,7 @@ CONFIG_SCSI=y
70CONFIG_BLK_DEV_SD=y 70CONFIG_BLK_DEV_SD=y
71# CONFIG_SCSI_LOWLEVEL is not set 71# CONFIG_SCSI_LOWLEVEL is not set
72CONFIG_NETDEVICES=y 72CONFIG_NETDEVICES=y
73CONFIG_ARM_AT91_ETHER=y
73CONFIG_MACB=y 74CONFIG_MACB=y
74# CONFIG_NET_VENDOR_BROADCOM is not set 75# CONFIG_NET_VENDOR_BROADCOM is not set
75CONFIG_DM9000=y 76CONFIG_DM9000=y
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index 41d856effe6c..510c747c65b4 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -3,8 +3,6 @@
3CONFIG_SYSVIPC=y 3CONFIG_SYSVIPC=y
4CONFIG_IRQ_DOMAIN_DEBUG=y 4CONFIG_IRQ_DOMAIN_DEBUG=y
5CONFIG_LOG_BUF_SHIFT=14 5CONFIG_LOG_BUF_SHIFT=14
6CONFIG_SYSFS_DEPRECATED=y
7CONFIG_SYSFS_DEPRECATED_V2=y
8CONFIG_BLK_DEV_INITRD=y 6CONFIG_BLK_DEV_INITRD=y
9CONFIG_EMBEDDED=y 7CONFIG_EMBEDDED=y
10CONFIG_SLAB=y 8CONFIG_SLAB=y
diff --git a/arch/arm/include/debug/at91.S b/arch/arm/include/debug/at91.S
index 80a6501b4d50..c3c45e628e33 100644
--- a/arch/arm/include/debug/at91.S
+++ b/arch/arm/include/debug/at91.S
@@ -18,8 +18,11 @@
18#define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */ 18#define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */
19#endif 19#endif
20 20
21/* Keep in sync with mach-at91/include/mach/hardware.h */ 21#ifdef CONFIG_MMU
22#define AT91_IO_P2V(x) ((x) - 0x01000000) 22#define AT91_IO_P2V(x) ((x) - 0x01000000)
23#else
24#define AT91_IO_P2V(x) (x)
25#endif
23 26
24#define AT91_DBGU_SR (0x14) /* Status Register */ 27#define AT91_DBGU_SR (0x14) /* Status Register */
25#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */ 28#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c74a44324e5b..24b59c75f6af 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -24,7 +24,7 @@ config SOC_SAMA5
24 select GENERIC_CLOCKEVENTS 24 select GENERIC_CLOCKEVENTS
25 select MEMORY 25 select MEMORY
26 select ATMEL_SDRAMC 26 select ATMEL_SDRAMC
27 select PHYLIB if NETDEVICES 27 select SRAM if PM
28 28
29menu "Atmel AT91 System-on-Chip" 29menu "Atmel AT91 System-on-Chip"
30 30
@@ -77,10 +77,13 @@ if SOC_SAM_V4_V5
77config SOC_AT91RM9200 77config SOC_AT91RM9200
78 bool "AT91RM9200" 78 bool "AT91RM9200"
79 select ATMEL_AIC_IRQ 79 select ATMEL_AIC_IRQ
80 select ATMEL_ST
80 select COMMON_CLK_AT91 81 select COMMON_CLK_AT91
81 select CPU_ARM920T 82 select CPU_ARM920T
82 select GENERIC_CLOCKEVENTS 83 select GENERIC_CLOCKEVENTS
83 select HAVE_AT91_USB_CLK 84 select HAVE_AT91_USB_CLK
85 select MIGHT_HAVE_PCI
86 select SRAM if PM
84 87
85config SOC_AT91SAM9 88config SOC_AT91SAM9
86 bool "AT91SAM9" 89 bool "AT91SAM9"
@@ -94,6 +97,7 @@ config SOC_AT91SAM9
94 select HAVE_AT91_UTMI 97 select HAVE_AT91_UTMI
95 select HAVE_FB_ATMEL 98 select HAVE_FB_ATMEL
96 select MEMORY 99 select MEMORY
100 select SRAM if PM
97 help 101 help
98 Select this if you are using one of those Atmel SoC: 102 Select this if you are using one of those Atmel SoC:
99 AT91SAM9260 103 AT91SAM9260
@@ -116,20 +120,6 @@ endif # SOC_SAM_V4_V5
116 120
117comment "AT91 Feature Selections" 121comment "AT91 Feature Selections"
118 122
119config AT91_SLOW_CLOCK
120 bool "Suspend-to-RAM disables main oscillator"
121 select SRAM
122 depends on SUSPEND
123 help
124 Select this if you want Suspend-to-RAM to save the most power
125 possible (without powering off the CPU) by disabling the PLLs
126 and main oscillator so that only the 32 KiHz clock is available.
127
128 When only that slow-clock is available, some peripherals lose
129 functionality. Many can't issue wakeup events unless faster
130 clocks are available. Some lose their operating state and
131 need to be completely re-initialized.
132
133config AT91_TIMER_HZ 123config AT91_TIMER_HZ
134 int "Kernel HZ (jiffies per second)" 124 int "Kernel HZ (jiffies per second)"
135 range 32 1024 125 range 32 1024
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 827fdbcce1c7..38aaef7b994e 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,18 +2,18 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := setup.o 5obj-y := soc.o
6 6
7obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o 7obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
8 8
9# CPU-specific support 9# CPU-specific support
10obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o 10obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
11obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o 11obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
12obj-$(CONFIG_SOC_SAMA5) += sama5.o 12obj-$(CONFIG_SOC_SAMA5) += sama5.o
13 13
14# Power Management 14# Power Management
15obj-$(CONFIG_PM) += pm.o 15obj-$(CONFIG_PM) += pm.o
16obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o 16obj-$(CONFIG_PM) += pm_suspend.o
17 17
18ifeq ($(CONFIG_PM_DEBUG),y) 18ifeq ($(CONFIG_PM_DEBUG),y)
19CFLAGS_pm.o += -DDEBUG 19CFLAGS_pm.o += -DDEBUG
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 8fcfb70f7124..eaf58f88ef5d 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -8,60 +8,42 @@
8 * Licensed under GPLv2 or later. 8 * Licensed under GPLv2 or later.
9 */ 9 */
10 10
11#include <linux/types.h> 11#include <linux/clk-provider.h>
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/gpio.h>
15#include <linux/of.h> 12#include <linux/of.h>
16#include <linux/of_irq.h>
17#include <linux/of_platform.h> 13#include <linux/of_platform.h>
18#include <linux/clk-provider.h>
19 14
20#include <asm/setup.h>
21#include <asm/irq.h>
22#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
23#include <asm/mach/map.h>
24#include <asm/mach/irq.h>
25#include <asm/system_misc.h> 16#include <asm/system_misc.h>
26 17
27#include <mach/at91_st.h>
28
29#include "generic.h" 18#include "generic.h"
19#include "soc.h"
30 20
31static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd) 21static const struct at91_soc rm9200_socs[] = {
32{ 22 AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
33 /* 23 { /* sentinel */ },
34 * Perform a hardware reset with the use of the Watchdog timer. 24};
35 */
36 at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
37 at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
38}
39
40static void __init at91rm9200_dt_timer_init(void)
41{
42 of_clk_init(NULL);
43 at91rm9200_timer_init();
44}
45 25
46static void __init at91rm9200_dt_device_init(void) 26static void __init at91rm9200_dt_device_init(void)
47{ 27{
48 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 28 struct soc_device *soc;
29 struct device *soc_dev = NULL;
30
31 soc = at91_soc_init(rm9200_socs);
32 if (soc != NULL)
33 soc_dev = soc_device_to_device(soc);
34
35 of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
49 36
50 arm_pm_idle = at91rm9200_idle; 37 arm_pm_idle = at91rm9200_idle;
51 arm_pm_restart = at91rm9200_restart;
52 at91rm9200_pm_init(); 38 at91rm9200_pm_init();
53} 39}
54 40
55
56
57static const char *at91rm9200_dt_board_compat[] __initconst = { 41static const char *at91rm9200_dt_board_compat[] __initconst = {
58 "atmel,at91rm9200", 42 "atmel,at91rm9200",
59 NULL 43 NULL
60}; 44};
61 45
62DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200") 46DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200")
63 .init_time = at91rm9200_dt_timer_init,
64 .map_io = at91_map_io,
65 .init_machine = at91rm9200_dt_device_init, 47 .init_machine = at91rm9200_dt_device_init,
66 .dt_compat = at91rm9200_dt_board_compat, 48 .dt_compat = at91rm9200_dt_board_compat,
67MACHINE_END 49MACHINE_END
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
deleted file mode 100644
index b00d09555f2b..000000000000
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ /dev/null
@@ -1,251 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/at91rm9200_time.c
3 *
4 * Copyright (C) 2003 SAN People
5 * Copyright (C) 2003 ATMEL
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/kernel.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/clockchips.h>
26#include <linux/export.h>
27#include <linux/of.h>
28#include <linux/of_address.h>
29#include <linux/of_irq.h>
30
31#include <asm/mach/time.h>
32
33#include <mach/at91_st.h>
34#include <mach/hardware.h>
35
36static unsigned long last_crtr;
37static u32 irqmask;
38static struct clock_event_device clkevt;
39
40#define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ)
41
42/*
43 * The ST_CRTR is updated asynchronously to the master clock ... but
44 * the updates as seen by the CPU don't seem to be strictly monotonic.
45 * Waiting until we read the same value twice avoids glitching.
46 */
47static inline unsigned long read_CRTR(void)
48{
49 unsigned long x1, x2;
50
51 x1 = at91_st_read(AT91_ST_CRTR);
52 do {
53 x2 = at91_st_read(AT91_ST_CRTR);
54 if (x1 == x2)
55 break;
56 x1 = x2;
57 } while (1);
58 return x1;
59}
60
61/*
62 * IRQ handler for the timer.
63 */
64static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
65{
66 u32 sr = at91_st_read(AT91_ST_SR) & irqmask;
67
68 /*
69 * irqs should be disabled here, but as the irq is shared they are only
70 * guaranteed to be off if the timer irq is registered first.
71 */
72 WARN_ON_ONCE(!irqs_disabled());
73
74 /* simulate "oneshot" timer with alarm */
75 if (sr & AT91_ST_ALMS) {
76 clkevt.event_handler(&clkevt);
77 return IRQ_HANDLED;
78 }
79
80 /* periodic mode should handle delayed ticks */
81 if (sr & AT91_ST_PITS) {
82 u32 crtr = read_CRTR();
83
84 while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) {
85 last_crtr += RM9200_TIMER_LATCH;
86 clkevt.event_handler(&clkevt);
87 }
88 return IRQ_HANDLED;
89 }
90
91 /* this irq is shared ... */
92 return IRQ_NONE;
93}
94
95static struct irqaction at91rm9200_timer_irq = {
96 .name = "at91_tick",
97 .flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
98 .handler = at91rm9200_timer_interrupt,
99 .irq = NR_IRQS_LEGACY + AT91_ID_SYS,
100};
101
102static cycle_t read_clk32k(struct clocksource *cs)
103{
104 return read_CRTR();
105}
106
107static struct clocksource clk32k = {
108 .name = "32k_counter",
109 .rating = 150,
110 .read = read_clk32k,
111 .mask = CLOCKSOURCE_MASK(20),
112 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
113};
114
115static void
116clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
117{
118 /* Disable and flush pending timer interrupts */
119 at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
120 at91_st_read(AT91_ST_SR);
121
122 last_crtr = read_CRTR();
123 switch (mode) {
124 case CLOCK_EVT_MODE_PERIODIC:
125 /* PIT for periodic irqs; fixed rate of 1/HZ */
126 irqmask = AT91_ST_PITS;
127 at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
128 break;
129 case CLOCK_EVT_MODE_ONESHOT:
130 /* ALM for oneshot irqs, set by next_event()
131 * before 32 seconds have passed
132 */
133 irqmask = AT91_ST_ALMS;
134 at91_st_write(AT91_ST_RTAR, last_crtr);
135 break;
136 case CLOCK_EVT_MODE_SHUTDOWN:
137 case CLOCK_EVT_MODE_UNUSED:
138 case CLOCK_EVT_MODE_RESUME:
139 irqmask = 0;
140 break;
141 }
142 at91_st_write(AT91_ST_IER, irqmask);
143}
144
145static int
146clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
147{
148 u32 alm;
149 int status = 0;
150
151 BUG_ON(delta < 2);
152
153 /* The alarm IRQ uses absolute time (now+delta), not the relative
154 * time (delta) in our calling convention. Like all clockevents
155 * using such "match" hardware, we have a race to defend against.
156 *
157 * Our defense here is to have set up the clockevent device so the
158 * delta is at least two. That way we never end up writing RTAR
159 * with the value then held in CRTR ... which would mean the match
160 * wouldn't trigger until 32 seconds later, after CRTR wraps.
161 */
162 alm = read_CRTR();
163
164 /* Cancel any pending alarm; flush any pending IRQ */
165 at91_st_write(AT91_ST_RTAR, alm);
166 at91_st_read(AT91_ST_SR);
167
168 /* Schedule alarm by writing RTAR. */
169 alm += delta;
170 at91_st_write(AT91_ST_RTAR, alm);
171
172 return status;
173}
174
175static struct clock_event_device clkevt = {
176 .name = "at91_tick",
177 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
178 .rating = 150,
179 .set_next_event = clkevt32k_next_event,
180 .set_mode = clkevt32k_mode,
181};
182
183void __iomem *at91_st_base;
184EXPORT_SYMBOL_GPL(at91_st_base);
185
186static const struct of_device_id at91rm9200_st_timer_ids[] = {
187 { .compatible = "atmel,at91rm9200-st" },
188 { /* sentinel */ }
189};
190
191static int __init of_at91rm9200_st_init(void)
192{
193 struct device_node *np;
194 int ret;
195
196 np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
197 if (!np)
198 goto err;
199
200 at91_st_base = of_iomap(np, 0);
201 if (!at91_st_base)
202 goto node_err;
203
204 /* Get the interrupts property */
205 ret = irq_of_parse_and_map(np, 0);
206 if (!ret)
207 goto ioremap_err;
208 at91rm9200_timer_irq.irq = ret;
209
210 of_node_put(np);
211
212 return 0;
213
214ioremap_err:
215 iounmap(at91_st_base);
216node_err:
217 of_node_put(np);
218err:
219 return -EINVAL;
220}
221
222/*
223 * ST (system timer) module supports both clockevents and clocksource.
224 */
225void __init at91rm9200_timer_init(void)
226{
227 /* For device tree enabled device: initialize here */
228 of_at91rm9200_st_init();
229
230 /* Disable all timer interrupts, and clear any pending ones */
231 at91_st_write(AT91_ST_IDR,
232 AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
233 at91_st_read(AT91_ST_SR);
234
235 /* Make IRQs happen for the system timer */
236 setup_irq(at91rm9200_timer_irq.irq, &at91rm9200_timer_irq);
237
238 /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
239 * directly for the clocksource and all clockevents, after adjusting
240 * its prescaler from the 1 Hz default.
241 */
242 at91_st_write(AT91_ST_RTMR, 1);
243
244 /* Setup timer clockevent, with minimum of two ticks (important!!) */
245 clkevt.cpumask = cpumask_of(0);
246 clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
247 2, AT91_ST_ALMV);
248
249 /* register clocksource */
250 clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
251}
diff --git a/arch/arm/mach-at91/at91sam9.c b/arch/arm/mach-at91/at91sam9.c
index 56e3ba73ec40..e47a2093a0e7 100644
--- a/arch/arm/mach-at91/at91sam9.c
+++ b/arch/arm/mach-at91/at91sam9.c
@@ -7,29 +7,68 @@
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9 9
10#include <linux/types.h>
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/gpio.h>
14#include <linux/of.h> 10#include <linux/of.h>
15#include <linux/of_irq.h>
16#include <linux/of_platform.h> 11#include <linux/of_platform.h>
17#include <linux/clk-provider.h>
18 12
19#include <asm/system_misc.h>
20#include <asm/setup.h>
21#include <asm/irq.h>
22#include <asm/mach/arch.h> 13#include <asm/mach/arch.h>
23#include <asm/mach/map.h> 14#include <asm/system_misc.h>
24#include <asm/mach/irq.h>
25 15
26#include "generic.h" 16#include "generic.h"
17#include "soc.h"
27 18
28static void __init at91sam9_dt_device_init(void) 19static const struct at91_soc at91sam9_socs[] = {
20 AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL),
21 AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL),
22 AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL),
23 AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL),
24 AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL),
25 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH,
26 "at91sam9m11", "at91sam9g45"),
27 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH,
28 "at91sam9m10", "at91sam9g45"),
29 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH,
30 "at91sam9g46", "at91sam9g45"),
31 AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH,
32 "at91sam9g45", "at91sam9g45"),
33 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH,
34 "at91sam9g15", "at91sam9x5"),
35 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH,
36 "at91sam9g35", "at91sam9x5"),
37 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH,
38 "at91sam9x35", "at91sam9x5"),
39 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH,
40 "at91sam9g25", "at91sam9x5"),
41 AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH,
42 "at91sam9x25", "at91sam9x5"),
43 AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH,
44 "at91sam9cn12", "at91sam9n12"),
45 AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH,
46 "at91sam9n12", "at91sam9n12"),
47 AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH,
48 "at91sam9cn11", "at91sam9n12"),
49 AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"),
50 AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"),
51 AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"),
52 { /* sentinel */ },
53};
54
55static void __init at91sam9_common_init(void)
29{ 56{
30 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 57 struct soc_device *soc;
58 struct device *soc_dev = NULL;
59
60 soc = at91_soc_init(at91sam9_socs);
61 if (soc != NULL)
62 soc_dev = soc_device_to_device(soc);
63
64 of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
31 65
32 arm_pm_idle = at91sam9_idle; 66 arm_pm_idle = at91sam9_idle;
67}
68
69static void __init at91sam9_dt_device_init(void)
70{
71 at91sam9_common_init();
33 at91sam9260_pm_init(); 72 at91sam9260_pm_init();
34} 73}
35 74
@@ -40,16 +79,13 @@ static const char *at91_dt_board_compat[] __initconst = {
40 79
41DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9") 80DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9")
42 /* Maintainer: Atmel */ 81 /* Maintainer: Atmel */
43 .map_io = at91_map_io,
44 .init_machine = at91sam9_dt_device_init, 82 .init_machine = at91sam9_dt_device_init,
45 .dt_compat = at91_dt_board_compat, 83 .dt_compat = at91_dt_board_compat,
46MACHINE_END 84MACHINE_END
47 85
48static void __init at91sam9g45_dt_device_init(void) 86static void __init at91sam9g45_dt_device_init(void)
49{ 87{
50 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 88 at91sam9_common_init();
51
52 arm_pm_idle = at91sam9_idle;
53 at91sam9g45_pm_init(); 89 at91sam9g45_pm_init();
54} 90}
55 91
@@ -60,16 +96,13 @@ static const char *at91sam9g45_board_compat[] __initconst = {
60 96
61DT_MACHINE_START(at91sam9g45_dt, "Atmel AT91SAM9G45") 97DT_MACHINE_START(at91sam9g45_dt, "Atmel AT91SAM9G45")
62 /* Maintainer: Atmel */ 98 /* Maintainer: Atmel */
63 .map_io = at91_map_io,
64 .init_machine = at91sam9g45_dt_device_init, 99 .init_machine = at91sam9g45_dt_device_init,
65 .dt_compat = at91sam9g45_board_compat, 100 .dt_compat = at91sam9g45_board_compat,
66MACHINE_END 101MACHINE_END
67 102
68static void __init at91sam9x5_dt_device_init(void) 103static void __init at91sam9x5_dt_device_init(void)
69{ 104{
70 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 105 at91sam9_common_init();
71
72 arm_pm_idle = at91sam9_idle;
73 at91sam9x5_pm_init(); 106 at91sam9x5_pm_init();
74} 107}
75 108
@@ -81,7 +114,6 @@ static const char *at91sam9x5_board_compat[] __initconst = {
81 114
82DT_MACHINE_START(at91sam9x5_dt, "Atmel AT91SAM9") 115DT_MACHINE_START(at91sam9x5_dt, "Atmel AT91SAM9")
83 /* Maintainer: Atmel */ 116 /* Maintainer: Atmel */
84 .map_io = at91_map_io,
85 .init_machine = at91sam9x5_dt_device_init, 117 .init_machine = at91sam9x5_dt_device_init,
86 .dt_compat = at91sam9x5_board_compat, 118 .dt_compat = at91sam9x5_board_compat,
87MACHINE_END 119MACHINE_END
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 583369ffc284..b0fa7dc7286d 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -18,17 +18,10 @@
18extern void __init at91_map_io(void); 18extern void __init at91_map_io(void);
19extern void __init at91_alt_map_io(void); 19extern void __init at91_alt_map_io(void);
20 20
21 /* Timer */
22extern void at91rm9200_timer_init(void);
23
24/* idle */ 21/* idle */
25extern void at91rm9200_idle(void); 22extern void at91rm9200_idle(void);
26extern void at91sam9_idle(void); 23extern void at91sam9_idle(void);
27 24
28/* Matrix */
29extern void at91_ioremap_matrix(u32 base_addr);
30
31
32#ifdef CONFIG_PM 25#ifdef CONFIG_PM
33extern void __init at91rm9200_pm_init(void); 26extern void __init at91rm9200_pm_init(void);
34extern void __init at91sam9260_pm_init(void); 27extern void __init at91sam9260_pm_init(void);
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h
deleted file mode 100644
index f8996c954131..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_matrix.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
3 *
4 * Under GPLv2
5 */
6
7#ifndef __MACH_AT91_MATRIX_H__
8#define __MACH_AT91_MATRIX_H__
9
10#ifndef __ASSEMBLY__
11extern void __iomem *at91_matrix_base;
12
13#define at91_matrix_read(field) \
14 __raw_readl(at91_matrix_base + field)
15
16#define at91_matrix_write(field, value) \
17 __raw_writel(value, at91_matrix_base + field)
18
19#else
20.extern at91_matrix_base
21#endif
22
23#endif /* __MACH_AT91_MATRIX_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h
deleted file mode 100644
index 67fdbd13c3ed..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_st.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_st.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * System Timer (ST) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_ST_H
17#define AT91_ST_H
18
19#ifndef __ASSEMBLY__
20extern void __iomem *at91_st_base;
21
22#define at91_st_read(field) \
23 __raw_readl(at91_st_base + field)
24
25#define at91_st_write(field, value) \
26 __raw_writel(value, at91_st_base + field)
27#else
28.extern at91_st_base
29#endif
30
31#define AT91_ST_CR 0x00 /* Control Register */
32#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
33
34#define AT91_ST_PIMR 0x04 /* Period Interval Mode Register */
35#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
36
37#define AT91_ST_WDMR 0x08 /* Watchdog Mode Register */
38#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
39#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
40#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
41
42#define AT91_ST_RTMR 0x0c /* Real-time Mode Register */
43#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
44
45#define AT91_ST_SR 0x10 /* Status Register */
46#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
47#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
48#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
49#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
50
51#define AT91_ST_IER 0x14 /* Interrupt Enable Register */
52#define AT91_ST_IDR 0x18 /* Interrupt Disable Register */
53#define AT91_ST_IMR 0x1c /* Interrupt Mask Register */
54
55#define AT91_ST_RTAR 0x20 /* Real-time Alarm Register */
56#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
57
58#define AT91_ST_CRTR 0x24 /* Current Real-time Register */
59#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
60
61#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
deleted file mode 100644
index f459df420629..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9260 datasheet revision B.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9260_MATRIX_H
16#define AT91SAM9260_MATRIX_H
17
18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
25#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
26#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
27#define AT91_MATRIX_ULBT_FOUR (2 << 0)
28#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
29#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
30
31#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
32#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
33#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
34#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
35#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
39#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
40#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
41#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
42#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
45
46#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
47#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
48#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
49#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
50#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
51#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
52#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
53#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
54#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
55#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
56#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
57
58#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
59#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
60#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
61
62#define AT91_MATRIX_EBICSA 0x11C /* EBI Chip Select Assignment Register */
63#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
64#define AT91_MATRIX_CS1A_SMC (0 << 1)
65#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
66#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
67#define AT91_MATRIX_CS3A_SMC (0 << 3)
68#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
69#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
70#define AT91_MATRIX_CS4A_SMC (0 << 4)
71#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
72#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
73#define AT91_MATRIX_CS5A_SMC (0 << 5)
74#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
75#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
76#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
77#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
78#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
79
80#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
deleted file mode 100644
index a50cdf8b8ca4..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9261 datasheet revision D.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9261_MATRIX_H
16#define AT91SAM9261_MATRIX_H
17
18#define AT91_MATRIX_MCFG 0x00 /* Master Configuration Register */
19#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
20#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
21
22#define AT91_MATRIX_SCFG0 0x04 /* Slave Configuration Register 0 */
23#define AT91_MATRIX_SCFG1 0x08 /* Slave Configuration Register 1 */
24#define AT91_MATRIX_SCFG2 0x0C /* Slave Configuration Register 2 */
25#define AT91_MATRIX_SCFG3 0x10 /* Slave Configuration Register 3 */
26#define AT91_MATRIX_SCFG4 0x14 /* Slave Configuration Register 4 */
27#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
28#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
29#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
30#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
31#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
32#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
33
34#define AT91_MATRIX_TCR 0x24 /* TCM Configuration Register */
35#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
36#define AT91_MATRIX_ITCM_0 (0 << 0)
37#define AT91_MATRIX_ITCM_16 (5 << 0)
38#define AT91_MATRIX_ITCM_32 (6 << 0)
39#define AT91_MATRIX_ITCM_64 (7 << 0)
40#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
41#define AT91_MATRIX_DTCM_0 (0 << 4)
42#define AT91_MATRIX_DTCM_16 (5 << 4)
43#define AT91_MATRIX_DTCM_32 (6 << 4)
44#define AT91_MATRIX_DTCM_64 (7 << 4)
45
46#define AT91_MATRIX_EBICSA 0x30 /* EBI Chip Select Assignment Register */
47#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
48#define AT91_MATRIX_CS1A_SMC (0 << 1)
49#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
50#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
51#define AT91_MATRIX_CS3A_SMC (0 << 3)
52#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
53#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
54#define AT91_MATRIX_CS4A_SMC (0 << 4)
55#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
56#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
57#define AT91_MATRIX_CS5A_SMC (0 << 5)
58#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
59#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
60
61#define AT91_MATRIX_USBPUCR 0x34 /* USB Pad Pull-Up Control Register */
62#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
63
64#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
deleted file mode 100644
index ebb5fdb565e0..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ /dev/null
@@ -1,129 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
3 *
4 * Copyright (C) 2006 Atmel Corporation.
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9263 datasheet revision B (Preliminary).
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9263_MATRIX_H
16#define AT91SAM9263_MATRIX_H
17
18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
27#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
28#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
29#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
30#define AT91_MATRIX_ULBT_FOUR (2 << 0)
31#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
32#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
33
34#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
35#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
36#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
37#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
38#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
39#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
40#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
41#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
42#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
43#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
45#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
46#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
47#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
48#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
51
52#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
53#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
54#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
55#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
56#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
57#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
58#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
59#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
60#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
61#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
62#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
63#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
64#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
65#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
66#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
67#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
68#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
69#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
70#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
71#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
72#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
73#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
74#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
75#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
76#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
77
78#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
79#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
80#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
81#define AT91_MATRIX_RCB2 (1 << 2)
82#define AT91_MATRIX_RCB3 (1 << 3)
83#define AT91_MATRIX_RCB4 (1 << 4)
84#define AT91_MATRIX_RCB5 (1 << 5)
85#define AT91_MATRIX_RCB6 (1 << 6)
86#define AT91_MATRIX_RCB7 (1 << 7)
87#define AT91_MATRIX_RCB8 (1 << 8)
88
89#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
90#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
91#define AT91_MATRIX_ITCM_0 (0 << 0)
92#define AT91_MATRIX_ITCM_16 (5 << 0)
93#define AT91_MATRIX_ITCM_32 (6 << 0)
94#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
95#define AT91_MATRIX_DTCM_0 (0 << 4)
96#define AT91_MATRIX_DTCM_16 (5 << 4)
97#define AT91_MATRIX_DTCM_32 (6 << 4)
98
99#define AT91_MATRIX_EBI0CSA 0x120 /* EBI0 Chip Select Assignment Register */
100#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
101#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
102#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
103#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
104#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
105#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
106#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
107#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
108#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
109#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
110#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
111#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
112#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
113#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
114#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
115#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
116
117#define AT91_MATRIX_EBI1CSA 0x124 /* EBI1 Chip Select Assignment Register */
118#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
119#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
120#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
121#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
122#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
123#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
124#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
125#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
126#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
127#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
128
129#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
deleted file mode 100644
index b76e2ed2fbc2..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * Matrix-centric header file for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2008-2009 Atmel Corporation.
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9G45 preliminary datasheet.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9G45_MATRIX_H
16#define AT91SAM9G45_MATRIX_H
17
18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
27#define AT91_MATRIX_MCFG9 0x24 /* Master Configuration Register 9 */
28#define AT91_MATRIX_MCFG10 0x28 /* Master Configuration Register 10 */
29#define AT91_MATRIX_MCFG11 0x2C /* Master Configuration Register 11 */
30#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
31#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
32#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
33#define AT91_MATRIX_ULBT_FOUR (2 << 0)
34#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
35#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
36#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
37#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
38#define AT91_MATRIX_ULBT_128 (7 << 0)
39
40#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
41#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
42#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
43#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
44#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
45#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
46#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
47#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
48#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
49#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
50#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
51#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
52#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
53#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
54
55#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
56#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
57#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
58#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
59#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
60#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
61#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
62#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
63#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
64#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
65#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
66#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
67#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
68#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
69#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
70#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
71#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
72#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
73#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
74#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
75#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
76#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
77#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
78#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
79#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
80#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
81#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
82#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
83
84#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
85#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
86#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
87#define AT91_MATRIX_RCB2 (1 << 2)
88#define AT91_MATRIX_RCB3 (1 << 3)
89#define AT91_MATRIX_RCB4 (1 << 4)
90#define AT91_MATRIX_RCB5 (1 << 5)
91#define AT91_MATRIX_RCB6 (1 << 6)
92#define AT91_MATRIX_RCB7 (1 << 7)
93#define AT91_MATRIX_RCB8 (1 << 8)
94#define AT91_MATRIX_RCB9 (1 << 9)
95#define AT91_MATRIX_RCB10 (1 << 10)
96#define AT91_MATRIX_RCB11 (1 << 11)
97
98#define AT91_MATRIX_TCMR 0x110 /* TCM Configuration Register */
99#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
100#define AT91_MATRIX_ITCM_0 (0 << 0)
101#define AT91_MATRIX_ITCM_32 (6 << 0)
102#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
103#define AT91_MATRIX_DTCM_0 (0 << 4)
104#define AT91_MATRIX_DTCM_32 (6 << 4)
105#define AT91_MATRIX_DTCM_64 (7 << 4)
106#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
107#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
108#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
109
110#define AT91_MATRIX_VIDEO 0x118 /* Video Mode Configuration Register */
111#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
112#define AT91C_VDEC_SEL_OFF (0 << 0)
113#define AT91C_VDEC_SEL_ON (1 << 0)
114
115#define AT91_MATRIX_EBICSA 0x128 /* EBI Chip Select Assignment Register */
116#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
117#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
118#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
119#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
120#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
121#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
122#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
123#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
124#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
125#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
126#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
127#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
128#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
129#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
130#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
131#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
132#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
133#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
134#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
135#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
136#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
137#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
138#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
139#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
140
141#define AT91_MATRIX_WPMR 0x1E4 /* Write Protect Mode Register */
142#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
143#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
144#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
145#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
146
147#define AT91_MATRIX_WPSR 0x1E8 /* Write Protect Status Register */
148#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
149#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
150#define AT91_MATRIX_WPSR_WPV (1 << 0)
151#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
152
153#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
deleted file mode 100644
index 40060cd62fa9..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Matrix-centric header file for the AT91SAM9N12
3 *
4 * Copyright (C) 2012 Atmel Corporation.
5 *
6 * Only EBI related registers.
7 * Write Protect register definitions may be useful.
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12#ifndef _AT91SAM9N12_MATRIX_H_
13#define _AT91SAM9N12_MATRIX_H_
14
15#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */
16#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
17#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
18#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
19#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
20#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
21#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
22#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
23#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
24#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
25#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
26#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
27#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
28#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
29#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
30#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
31#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
32#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
33#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
34#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
35#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
36#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
37#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
38#define AT91_MATRIX_MP_OFF (0 << 25)
39#define AT91_MATRIX_MP_ON (1 << 25)
40
41#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
42#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
43#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
44#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
45#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
46
47#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
48#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
49#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
50#define AT91_MATRIX_WPSR_WPV (1 << 0)
51#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
52
53#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
deleted file mode 100644
index 6d160adadafc..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9RL datasheet revision A. (Preliminary)
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14#ifndef AT91SAM9RL_MATRIX_H
15#define AT91SAM9RL_MATRIX_H
16
17#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
18#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
19#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
20#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
21#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
22#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
23#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
24#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
25#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
26#define AT91_MATRIX_ULBT_FOUR (2 << 0)
27#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
28#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
29
30#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
31#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
32#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
33#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
34#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
35#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
39#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
40#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
41#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
42#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
45
46#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
47#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
48#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
49#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
50#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
51#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
52#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
53#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
54#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
55#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
56#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
57#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
58
59#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
60#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
61#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
62#define AT91_MATRIX_RCB2 (1 << 2)
63#define AT91_MATRIX_RCB3 (1 << 3)
64#define AT91_MATRIX_RCB4 (1 << 4)
65#define AT91_MATRIX_RCB5 (1 << 5)
66
67#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
68#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
69#define AT91_MATRIX_ITCM_0 (0 << 0)
70#define AT91_MATRIX_ITCM_16 (5 << 0)
71#define AT91_MATRIX_ITCM_32 (6 << 0)
72#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
73#define AT91_MATRIX_DTCM_0 (0 << 4)
74#define AT91_MATRIX_DTCM_16 (5 << 4)
75#define AT91_MATRIX_DTCM_32 (6 << 4)
76
77#define AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */
78#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
79#define AT91_MATRIX_CS1A_SMC (0 << 1)
80#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
81#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
82#define AT91_MATRIX_CS3A_SMC (0 << 3)
83#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
84#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
85#define AT91_MATRIX_CS4A_SMC (0 << 4)
86#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
87#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
88#define AT91_MATRIX_CS5A_SMC (0 << 5)
89#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
90#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
91#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
92#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
93#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
94
95
96#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
deleted file mode 100644
index a606d3966470..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Matrix-centric header file for the AT91SAM9x5 family
3 *
4 * Copyright (C) 2009-2012 Atmel Corporation.
5 *
6 * Only EBI related registers.
7 * Write Protect register definitions may be useful.
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12#ifndef AT91SAM9X5_MATRIX_H
13#define AT91SAM9X5_MATRIX_H
14
15#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
16#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
17#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
18#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
19#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
20#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
21#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
22#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
23#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
24#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
25#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
26#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
27#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
28#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
29#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
30#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
31#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
32#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
33#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
34#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
35#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
36#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
37#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
38#define AT91_MATRIX_MP_OFF (0 << 25)
39#define AT91_MATRIX_MP_ON (1 << 25)
40
41#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
42#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
43#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
44#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
45#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
46
47#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
48#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
49#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
50#define AT91_MATRIX_WPSR_WPV (1 << 0)
51#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
52
53#endif
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
deleted file mode 100644
index 2d9ca0455745..000000000000
--- a/arch/arm/mach-at91/include/mach/io.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/io.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_IO_H
22#define __ASM_ARCH_IO_H
23
24#define IO_SPACE_LIMIT 0xFFFFFFFF
25#define __io(a) __typesafe_io(a)
26
27#endif
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 5e34fb143309..ac947cdd506c 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -29,6 +29,8 @@
29#include <linux/atomic.h> 29#include <linux/atomic.h>
30#include <asm/mach/time.h> 30#include <asm/mach/time.h>
31#include <asm/mach/irq.h> 31#include <asm/mach/irq.h>
32#include <asm/fncpy.h>
33#include <asm/cacheflush.h>
32 34
33#include <mach/cpu.h> 35#include <mach/cpu.h>
34#include <mach/hardware.h> 36#include <mach/hardware.h>
@@ -41,7 +43,6 @@ static struct {
41 int memctrl; 43 int memctrl;
42} at91_pm_data; 44} at91_pm_data;
43 45
44static void (*at91_pm_standby)(void);
45void __iomem *at91_ramc_base[2]; 46void __iomem *at91_ramc_base[2];
46 47
47static int at91_pm_valid_state(suspend_state_t state) 48static int at91_pm_valid_state(suspend_state_t state)
@@ -119,76 +120,67 @@ int at91_suspend_entering_slow_clock(void)
119} 120}
120EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 121EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
121 122
122 123static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
123static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
124 void __iomem *ramc1, int memctrl); 124 void __iomem *ramc1, int memctrl);
125 125
126#ifdef CONFIG_AT91_SLOW_CLOCK 126extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
127extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
128 void __iomem *ramc1, int memctrl); 127 void __iomem *ramc1, int memctrl);
129extern u32 at91_slow_clock_sz; 128extern u32 at91_pm_suspend_in_sram_sz;
130#endif 129
130static void at91_pm_suspend(suspend_state_t state)
131{
132 unsigned int pm_data = at91_pm_data.memctrl;
133
134 pm_data |= (state == PM_SUSPEND_MEM) ?
135 AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
136
137 flush_cache_all();
138 outer_disable();
139
140 at91_suspend_sram_fn(at91_pmc_base, at91_ramc_base[0],
141 at91_ramc_base[1], pm_data);
142
143 outer_resume();
144}
131 145
132static int at91_pm_enter(suspend_state_t state) 146static int at91_pm_enter(suspend_state_t state)
133{ 147{
134 at91_pinctrl_gpio_suspend(); 148 at91_pinctrl_gpio_suspend();
135 149
136 switch (state) { 150 switch (state) {
151 /*
152 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
153 * drivers must suspend more deeply, the master clock switches
154 * to the clk32k and turns off the main oscillator
155 */
156 case PM_SUSPEND_MEM:
137 /* 157 /*
138 * Suspend-to-RAM is like STANDBY plus slow clock mode, so 158 * Ensure that clocks are in a valid state.
139 * drivers must suspend more deeply: only the master clock
140 * controller may be using the main oscillator.
141 */ 159 */
142 case PM_SUSPEND_MEM: 160 if (!at91_pm_verify_clocks())
143 /* 161 goto error;
144 * Ensure that clocks are in a valid state.
145 */
146 if (!at91_pm_verify_clocks())
147 goto error;
148
149 /*
150 * Enter slow clock mode by switching over to clk32k and
151 * turning off the main oscillator; reverse on wakeup.
152 */
153 if (slow_clock) {
154#ifdef CONFIG_AT91_SLOW_CLOCK
155 /* copy slow_clock handler to SRAM, and call it */
156 memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
157#endif
158 slow_clock(at91_pmc_base, at91_ramc_base[0],
159 at91_ramc_base[1],
160 at91_pm_data.memctrl);
161 break;
162 } else {
163 pr_info("AT91: PM - no slow clock mode enabled ...\n");
164 /* FALLTHROUGH leaving master clock alone */
165 }
166 162
167 /* 163 at91_pm_suspend(state);
168 * STANDBY mode has *all* drivers suspended; ignores irqs not
169 * marked as 'wakeup' event sources; and reduces DRAM power.
170 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
171 * nothing fancy done with main or cpu clocks.
172 */
173 case PM_SUSPEND_STANDBY:
174 /*
175 * NOTE: the Wait-for-Interrupt instruction needs to be
176 * in icache so no SDRAM accesses are needed until the
177 * wakeup IRQ occurs and self-refresh is terminated.
178 * For ARM 926 based chips, this requirement is weaker
179 * as at91sam9 can access a RAM in self-refresh mode.
180 */
181 if (at91_pm_standby)
182 at91_pm_standby();
183 break;
184 164
185 case PM_SUSPEND_ON: 165 break;
186 cpu_do_idle();
187 break;
188 166
189 default: 167 /*
190 pr_debug("AT91: PM - bogus suspend state %d\n", state); 168 * STANDBY mode has *all* drivers suspended; ignores irqs not
191 goto error; 169 * marked as 'wakeup' event sources; and reduces DRAM power.
170 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
171 * nothing fancy done with main or cpu clocks.
172 */
173 case PM_SUSPEND_STANDBY:
174 at91_pm_suspend(state);
175 break;
176
177 case PM_SUSPEND_ON:
178 cpu_do_idle();
179 break;
180
181 default:
182 pr_debug("AT91: PM - bogus suspend state %d\n", state);
183 goto error;
192 } 184 }
193 185
194error: 186error:
@@ -218,12 +210,10 @@ static struct platform_device at91_cpuidle_device = {
218 .name = "cpuidle-at91", 210 .name = "cpuidle-at91",
219}; 211};
220 212
221void at91_pm_set_standby(void (*at91_standby)(void)) 213static void at91_pm_set_standby(void (*at91_standby)(void))
222{ 214{
223 if (at91_standby) { 215 if (at91_standby)
224 at91_cpuidle_device.dev.platform_data = at91_standby; 216 at91_cpuidle_device.dev.platform_data = at91_standby;
225 at91_pm_standby = at91_standby;
226 }
227} 217}
228 218
229static const struct of_device_id ramc_ids[] __initconst = { 219static const struct of_device_id ramc_ids[] __initconst = {
@@ -263,60 +253,63 @@ static __init void at91_dt_ramc(void)
263 at91_pm_set_standby(standby); 253 at91_pm_set_standby(standby);
264} 254}
265 255
266#ifdef CONFIG_AT91_SLOW_CLOCK
267static void __init at91_pm_sram_init(void) 256static void __init at91_pm_sram_init(void)
268{ 257{
269 struct gen_pool *sram_pool; 258 struct gen_pool *sram_pool;
270 phys_addr_t sram_pbase; 259 phys_addr_t sram_pbase;
271 unsigned long sram_base; 260 unsigned long sram_base;
272 struct device_node *node; 261 struct device_node *node;
273 struct platform_device *pdev; 262 struct platform_device *pdev = NULL;
274 263
275 node = of_find_compatible_node(NULL, NULL, "mmio-sram"); 264 for_each_compatible_node(node, NULL, "mmio-sram") {
276 if (!node) { 265 pdev = of_find_device_by_node(node);
277 pr_warn("%s: failed to find sram node!\n", __func__); 266 if (pdev) {
278 return; 267 of_node_put(node);
268 break;
269 }
279 } 270 }
280 271
281 pdev = of_find_device_by_node(node);
282 if (!pdev) { 272 if (!pdev) {
283 pr_warn("%s: failed to find sram device!\n", __func__); 273 pr_warn("%s: failed to find sram device!\n", __func__);
284 goto put_node; 274 return;
285 } 275 }
286 276
287 sram_pool = dev_get_gen_pool(&pdev->dev); 277 sram_pool = dev_get_gen_pool(&pdev->dev);
288 if (!sram_pool) { 278 if (!sram_pool) {
289 pr_warn("%s: sram pool unavailable!\n", __func__); 279 pr_warn("%s: sram pool unavailable!\n", __func__);
290 goto put_node; 280 return;
291 } 281 }
292 282
293 sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz); 283 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
294 if (!sram_base) { 284 if (!sram_base) {
295 pr_warn("%s: unable to alloc ocram!\n", __func__); 285 pr_warn("%s: unable to alloc sram!\n", __func__);
296 goto put_node; 286 return;
297 } 287 }
298 288
299 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); 289 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
300 slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false); 290 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
291 at91_pm_suspend_in_sram_sz, false);
292 if (!at91_suspend_sram_fn) {
293 pr_warn("SRAM: Could not map\n");
294 return;
295 }
301 296
302put_node: 297 /* Copy the pm suspend handler to SRAM */
303 of_node_put(node); 298 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
299 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
304} 300}
305#endif
306
307 301
308static void __init at91_pm_init(void) 302static void __init at91_pm_init(void)
309{ 303{
310#ifdef CONFIG_AT91_SLOW_CLOCK
311 at91_pm_sram_init(); 304 at91_pm_sram_init();
312#endif
313
314 pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
315 305
316 if (at91_cpuidle_device.dev.platform_data) 306 if (at91_cpuidle_device.dev.platform_data)
317 platform_device_register(&at91_cpuidle_device); 307 platform_device_register(&at91_cpuidle_device);
318 308
319 suspend_set_ops(&at91_pm_ops); 309 if (at91_suspend_sram_fn)
310 suspend_set_ops(&at91_pm_ops);
311 else
312 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
320} 313}
321 314
322void __init at91rm9200_pm_init(void) 315void __init at91rm9200_pm_init(void)
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index d2c89963af2d..dcacfa1ad3fa 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -15,11 +15,13 @@
15 15
16#include <mach/at91_ramc.h> 16#include <mach/at91_ramc.h>
17 17
18#ifdef CONFIG_PM 18#define AT91_PM_MEMTYPE_MASK 0x0f
19extern void at91_pm_set_standby(void (*at91_standby)(void)); 19
20#else 20#define AT91_PM_MODE_OFFSET 4
21static inline void at91_pm_set_standby(void (*at91_standby)(void)) { } 21#define AT91_PM_MODE_MASK 0x01
22#endif 22#define AT91_PM_MODE(x) (((x) & AT91_PM_MODE_MASK) << AT91_PM_MODE_OFFSET)
23
24#define AT91_PM_SLOW_CLOCK 0x01
23 25
24/* 26/*
25 * The AT91RM9200 goes into self-refresh mode with this command, and will 27 * The AT91RM9200 goes into self-refresh mode with this command, and will
@@ -31,6 +33,7 @@ static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
31 * still in self-refresh is "not recommended", but seems to work. 33 * still in self-refresh is "not recommended", but seems to work.
32 */ 34 */
33 35
36#ifndef __ASSEMBLY__
34static inline void at91rm9200_standby(void) 37static inline void at91rm9200_standby(void)
35{ 38{
36 u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR); 39 u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
@@ -44,7 +47,7 @@ static inline void at91rm9200_standby(void)
44 " mcr p15, 0, %0, c7, c0, 4\n\t" 47 " mcr p15, 0, %0, c7, c0, 4\n\t"
45 " str %5, [%1, %2]" 48 " str %5, [%1, %2]"
46 : 49 :
47 : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR), 50 : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
48 "r" (1), "r" (AT91RM9200_SDRAMC_SRR), 51 "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
49 "r" (lpr)); 52 "r" (lpr));
50} 53}
@@ -112,3 +115,4 @@ static inline void at91sam9_sdram_standby(void)
112} 115}
113 116
114#endif 117#endif
118#endif
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
deleted file mode 100644
index 556151e85ec4..000000000000
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ /dev/null
@@ -1,323 +0,0 @@
1/*
2 * arch/arm/mach-at91/pm_slow_clock.S
3 *
4 * Copyright (C) 2006 Savin Zlobec
5 *
6 * AT91SAM9 support:
7 * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/linkage.h>
16#include <linux/clk/at91_pmc.h>
17#include <mach/hardware.h>
18#include <mach/at91_ramc.h>
19
20/*
21 * When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master
22 * clock during suspend by adjusting its prescalar and divisor.
23 * NOTE: This hasn't been shown to be stable on SAM9s; and on the RM9200 there
24 * are errata regarding adjusting the prescalar and divisor.
25 */
26#undef SLOWDOWN_MASTER_CLOCK
27
28#define MCKRDY_TIMEOUT 1000
29#define MOSCRDY_TIMEOUT 1000
30#define PLLALOCK_TIMEOUT 1000
31#define PLLBLOCK_TIMEOUT 1000
32
33pmc .req r0
34sdramc .req r1
35ramc1 .req r2
36memctrl .req r3
37tmp1 .req r4
38tmp2 .req r5
39
40/*
41 * Wait until master clock is ready (after switching master clock source)
42 */
43 .macro wait_mckrdy
44 mov tmp2, #MCKRDY_TIMEOUT
451: sub tmp2, tmp2, #1
46 cmp tmp2, #0
47 beq 2f
48 ldr tmp1, [pmc, #AT91_PMC_SR]
49 tst tmp1, #AT91_PMC_MCKRDY
50 beq 1b
512:
52 .endm
53
54/*
55 * Wait until master oscillator has stabilized.
56 */
57 .macro wait_moscrdy
58 mov tmp2, #MOSCRDY_TIMEOUT
591: sub tmp2, tmp2, #1
60 cmp tmp2, #0
61 beq 2f
62 ldr tmp1, [pmc, #AT91_PMC_SR]
63 tst tmp1, #AT91_PMC_MOSCS
64 beq 1b
652:
66 .endm
67
68/*
69 * Wait until PLLA has locked.
70 */
71 .macro wait_pllalock
72 mov tmp2, #PLLALOCK_TIMEOUT
731: sub tmp2, tmp2, #1
74 cmp tmp2, #0
75 beq 2f
76 ldr tmp1, [pmc, #AT91_PMC_SR]
77 tst tmp1, #AT91_PMC_LOCKA
78 beq 1b
792:
80 .endm
81
82/*
83 * Wait until PLLB has locked.
84 */
85 .macro wait_pllblock
86 mov tmp2, #PLLBLOCK_TIMEOUT
871: sub tmp2, tmp2, #1
88 cmp tmp2, #0
89 beq 2f
90 ldr tmp1, [pmc, #AT91_PMC_SR]
91 tst tmp1, #AT91_PMC_LOCKB
92 beq 1b
932:
94 .endm
95
96 .text
97
98/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
99 * void __iomem *ramc1, int memctrl)
100 */
101ENTRY(at91_slow_clock)
102 /* Save registers on stack */
103 stmfd sp!, {r4 - r12, lr}
104
105 /*
106 * Register usage:
107 * R0 = Base address of AT91_PMC
108 * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
109 * R2 = Base address of second RAM Controller or 0 if not present
110 * R3 = Memory controller
111 * R4 = temporary register
112 * R5 = temporary register
113 */
114
115 /* Drain write buffer */
116 mov tmp1, #0
117 mcr p15, 0, tmp1, c7, c10, 4
118
119 cmp memctrl, #AT91_MEMCTRL_MC
120 bne ddr_sr_enable
121
122 /*
123 * at91rm9200 Memory controller
124 */
125 /* Put SDRAM in self-refresh mode */
126 mov tmp1, #1
127 str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
128 b sdr_sr_done
129
130 /*
131 * DDRSDR Memory controller
132 */
133ddr_sr_enable:
134 cmp memctrl, #AT91_MEMCTRL_DDRSDR
135 bne sdr_sr_enable
136
137 /* prepare for DDRAM self-refresh mode */
138 ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
139 str tmp1, .saved_sam9_lpr
140 bic tmp1, #AT91_DDRSDRC_LPCB
141 orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
142
143 /* figure out if we use the second ram controller */
144 cmp ramc1, #0
145 ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
146 strne tmp2, .saved_sam9_lpr1
147 bicne tmp2, #AT91_DDRSDRC_LPCB
148 orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
149
150 /* Enable DDRAM self-refresh mode */
151 str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
152 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
153
154 b sdr_sr_done
155
156 /*
157 * SDRAMC Memory controller
158 */
159sdr_sr_enable:
160 /* Enable SDRAM self-refresh mode */
161 ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
162 str tmp1, .saved_sam9_lpr
163
164 bic tmp1, #AT91_SDRAMC_LPCB
165 orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
166 str tmp1, [sdramc, #AT91_SDRAMC_LPR]
167
168sdr_sr_done:
169 /* Save Master clock setting */
170 ldr tmp1, [pmc, #AT91_PMC_MCKR]
171 str tmp1, .saved_mckr
172
173 /*
174 * Set the Master clock source to slow clock
175 */
176 bic tmp1, tmp1, #AT91_PMC_CSS
177 str tmp1, [pmc, #AT91_PMC_MCKR]
178
179 wait_mckrdy
180
181#ifdef SLOWDOWN_MASTER_CLOCK
182 /*
183 * Set the Master Clock PRES and MDIV fields.
184 *
185 * See AT91RM9200 errata #27 and #28 for details.
186 */
187 mov tmp1, #0
188 str tmp1, [pmc, #AT91_PMC_MCKR]
189
190 wait_mckrdy
191#endif
192
193 /* Save PLLA setting and disable it */
194 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
195 str tmp1, .saved_pllar
196
197 mov tmp1, #AT91_PMC_PLLCOUNT
198 orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
199 str tmp1, [pmc, #AT91_CKGR_PLLAR]
200
201 /* Save PLLB setting and disable it */
202 ldr tmp1, [pmc, #AT91_CKGR_PLLBR]
203 str tmp1, .saved_pllbr
204
205 mov tmp1, #AT91_PMC_PLLCOUNT
206 str tmp1, [pmc, #AT91_CKGR_PLLBR]
207
208 /* Turn off the main oscillator */
209 ldr tmp1, [pmc, #AT91_CKGR_MOR]
210 bic tmp1, tmp1, #AT91_PMC_MOSCEN
211 str tmp1, [pmc, #AT91_CKGR_MOR]
212
213 /* Wait for interrupt */
214 mcr p15, 0, tmp1, c7, c0, 4
215
216 /* Turn on the main oscillator */
217 ldr tmp1, [pmc, #AT91_CKGR_MOR]
218 orr tmp1, tmp1, #AT91_PMC_MOSCEN
219 str tmp1, [pmc, #AT91_CKGR_MOR]
220
221 wait_moscrdy
222
223 /* Restore PLLB setting */
224 ldr tmp1, .saved_pllbr
225 str tmp1, [pmc, #AT91_CKGR_PLLBR]
226
227 tst tmp1, #(AT91_PMC_MUL & 0xff0000)
228 bne 1f
229 tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
230 beq 2f
2311:
232 wait_pllblock
2332:
234
235 /* Restore PLLA setting */
236 ldr tmp1, .saved_pllar
237 str tmp1, [pmc, #AT91_CKGR_PLLAR]
238
239 tst tmp1, #(AT91_PMC_MUL & 0xff0000)
240 bne 3f
241 tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
242 beq 4f
2433:
244 wait_pllalock
2454:
246
247#ifdef SLOWDOWN_MASTER_CLOCK
248 /*
249 * First set PRES if it was not 0,
250 * than set CSS and MDIV fields.
251 *
252 * See AT91RM9200 errata #27 and #28 for details.
253 */
254 ldr tmp1, .saved_mckr
255 tst tmp1, #AT91_PMC_PRES
256 beq 2f
257 and tmp1, tmp1, #AT91_PMC_PRES
258 str tmp1, [pmc, #AT91_PMC_MCKR]
259
260 wait_mckrdy
261#endif
262
263 /*
264 * Restore master clock setting
265 */
2662: ldr tmp1, .saved_mckr
267 str tmp1, [pmc, #AT91_PMC_MCKR]
268
269 wait_mckrdy
270
271 /*
272 * at91rm9200 Memory controller
273 * Do nothing - self-refresh is automatically disabled.
274 */
275 cmp memctrl, #AT91_MEMCTRL_MC
276 beq ram_restored
277
278 /*
279 * DDRSDR Memory controller
280 */
281 cmp memctrl, #AT91_MEMCTRL_DDRSDR
282 bne sdr_en_restore
283 /* Restore LPR on AT91 with DDRAM */
284 ldr tmp1, .saved_sam9_lpr
285 str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
286
287 /* if we use the second ram controller */
288 cmp ramc1, #0
289 ldrne tmp2, .saved_sam9_lpr1
290 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
291
292 b ram_restored
293
294 /*
295 * SDRAMC Memory controller
296 */
297sdr_en_restore:
298 /* Restore LPR on AT91 with SDRAM */
299 ldr tmp1, .saved_sam9_lpr
300 str tmp1, [sdramc, #AT91_SDRAMC_LPR]
301
302ram_restored:
303 /* Restore registers, and return */
304 ldmfd sp!, {r4 - r12, pc}
305
306
307.saved_mckr:
308 .word 0
309
310.saved_pllar:
311 .word 0
312
313.saved_pllbr:
314 .word 0
315
316.saved_sam9_lpr:
317 .word 0
318
319.saved_sam9_lpr1:
320 .word 0
321
322ENTRY(at91_slow_clock_sz)
323 .word .-at91_slow_clock
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
new file mode 100644
index 000000000000..7c444c259740
--- /dev/null
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -0,0 +1,338 @@
1/*
2 * arch/arm/mach-at91/pm_slow_clock.S
3 *
4 * Copyright (C) 2006 Savin Zlobec
5 *
6 * AT91SAM9 support:
7 * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14#include <linux/linkage.h>
15#include <linux/clk/at91_pmc.h>
16#include <mach/hardware.h>
17#include <mach/at91_ramc.h>
18#include "pm.h"
19
20#define SRAMC_SELF_FRESH_ACTIVE 0x01
21#define SRAMC_SELF_FRESH_EXIT 0x00
22
23pmc .req r0
24tmp1 .req r4
25tmp2 .req r5
26
27/*
28 * Wait until master clock is ready (after switching master clock source)
29 */
30 .macro wait_mckrdy
311: ldr tmp1, [pmc, #AT91_PMC_SR]
32 tst tmp1, #AT91_PMC_MCKRDY
33 beq 1b
34 .endm
35
36/*
37 * Wait until master oscillator has stabilized.
38 */
39 .macro wait_moscrdy
401: ldr tmp1, [pmc, #AT91_PMC_SR]
41 tst tmp1, #AT91_PMC_MOSCS
42 beq 1b
43 .endm
44
45/*
46 * Wait until PLLA has locked.
47 */
48 .macro wait_pllalock
491: ldr tmp1, [pmc, #AT91_PMC_SR]
50 tst tmp1, #AT91_PMC_LOCKA
51 beq 1b
52 .endm
53
54/*
55 * Put the processor to enter the idle state
56 */
57 .macro at91_cpu_idle
58
59#if defined(CONFIG_CPU_V7)
60 mov tmp1, #AT91_PMC_PCK
61 str tmp1, [pmc, #AT91_PMC_SCDR]
62
63 dsb
64
65 wfi @ Wait For Interrupt
66#else
67 mcr p15, 0, tmp1, c7, c0, 4
68#endif
69
70 .endm
71
72 .text
73
74 .arm
75
76/*
77 * void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *sdramc,
78 * void __iomem *ramc1, int memctrl)
79 * @input param:
80 * @r0: base address of AT91_PMC
81 * @r1: base address of SDRAM Controller (SDRAM, DDRSDR, or AT91_SYS)
82 * @r2: base address of second SDRAM Controller or 0 if not present
83 * @r3: pm information
84 */
85ENTRY(at91_pm_suspend_in_sram)
86 /* Save registers on stack */
87 stmfd sp!, {r4 - r12, lr}
88
89 /* Drain write buffer */
90 mov tmp1, #0
91 mcr p15, 0, tmp1, c7, c10, 4
92
93 str r0, .pmc_base
94 str r1, .sramc_base
95 str r2, .sramc1_base
96
97 and r0, r3, #AT91_PM_MEMTYPE_MASK
98 str r0, .memtype
99
100 lsr r0, r3, #AT91_PM_MODE_OFFSET
101 and r0, r0, #AT91_PM_MODE_MASK
102 str r0, .pm_mode
103
104 /* Active the self-refresh mode */
105 mov r0, #SRAMC_SELF_FRESH_ACTIVE
106 bl at91_sramc_self_refresh
107
108 ldr r0, .pm_mode
109 tst r0, #AT91_PM_SLOW_CLOCK
110 beq skip_disable_main_clock
111
112 ldr pmc, .pmc_base
113
114 /* Save Master clock setting */
115 ldr tmp1, [pmc, #AT91_PMC_MCKR]
116 str tmp1, .saved_mckr
117
118 /*
119 * Set the Master clock source to slow clock
120 */
121 bic tmp1, tmp1, #AT91_PMC_CSS
122 str tmp1, [pmc, #AT91_PMC_MCKR]
123
124 wait_mckrdy
125
126 /* Save PLLA setting and disable it */
127 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
128 str tmp1, .saved_pllar
129
130 mov tmp1, #AT91_PMC_PLLCOUNT
131 orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
132 str tmp1, [pmc, #AT91_CKGR_PLLAR]
133
134 /* Turn off the main oscillator */
135 ldr tmp1, [pmc, #AT91_CKGR_MOR]
136 bic tmp1, tmp1, #AT91_PMC_MOSCEN
137 orr tmp1, tmp1, #AT91_PMC_KEY
138 str tmp1, [pmc, #AT91_CKGR_MOR]
139
140skip_disable_main_clock:
141 ldr pmc, .pmc_base
142
143 /* Wait for interrupt */
144 at91_cpu_idle
145
146 ldr r0, .pm_mode
147 tst r0, #AT91_PM_SLOW_CLOCK
148 beq skip_enable_main_clock
149
150 ldr pmc, .pmc_base
151
152 /* Turn on the main oscillator */
153 ldr tmp1, [pmc, #AT91_CKGR_MOR]
154 orr tmp1, tmp1, #AT91_PMC_MOSCEN
155 orr tmp1, tmp1, #AT91_PMC_KEY
156 str tmp1, [pmc, #AT91_CKGR_MOR]
157
158 wait_moscrdy
159
160 /* Restore PLLA setting */
161 ldr tmp1, .saved_pllar
162 str tmp1, [pmc, #AT91_CKGR_PLLAR]
163
164 tst tmp1, #(AT91_PMC_MUL & 0xff0000)
165 bne 3f
166 tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
167 beq 4f
1683:
169 wait_pllalock
1704:
171
172 /*
173 * Restore master clock setting
174 */
175 ldr tmp1, .saved_mckr
176 str tmp1, [pmc, #AT91_PMC_MCKR]
177
178 wait_mckrdy
179
180skip_enable_main_clock:
181 /* Exit the self-refresh mode */
182 mov r0, #SRAMC_SELF_FRESH_EXIT
183 bl at91_sramc_self_refresh
184
185 /* Restore registers, and return */
186 ldmfd sp!, {r4 - r12, pc}
187ENDPROC(at91_pm_suspend_in_sram)
188
189/*
190 * void at91_sramc_self_refresh(unsigned int is_active)
191 *
192 * @input param:
193 * @r0: 1 - active self-refresh mode
194 * 0 - exit self-refresh mode
195 * register usage:
196 * @r1: memory type
197 * @r2: base address of the sram controller
198 */
199
200ENTRY(at91_sramc_self_refresh)
201 ldr r1, .memtype
202 ldr r2, .sramc_base
203
204 cmp r1, #AT91_MEMCTRL_MC
205 bne ddrc_sf
206
207 /*
208 * at91rm9200 Memory controller
209 */
210
211 /*
212 * For exiting the self-refresh mode, do nothing,
213 * automatically exit the self-refresh mode.
214 */
215 tst r0, #SRAMC_SELF_FRESH_ACTIVE
216 beq exit_sramc_sf
217
218 /* Active SDRAM self-refresh mode */
219 mov r3, #1
220 str r3, [r2, #AT91RM9200_SDRAMC_SRR]
221 b exit_sramc_sf
222
223ddrc_sf:
224 cmp r1, #AT91_MEMCTRL_DDRSDR
225 bne sdramc_sf
226
227 /*
228 * DDR Memory controller
229 */
230 tst r0, #SRAMC_SELF_FRESH_ACTIVE
231 beq ddrc_exit_sf
232
233 /* LPDDR1 --> force DDR2 mode during self-refresh */
234 ldr r3, [r2, #AT91_DDRSDRC_MDR]
235 str r3, .saved_sam9_mdr
236 bic r3, r3, #~AT91_DDRSDRC_MD
237 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
238 ldreq r3, [r2, #AT91_DDRSDRC_MDR]
239 biceq r3, r3, #AT91_DDRSDRC_MD
240 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
241 streq r3, [r2, #AT91_DDRSDRC_MDR]
242
243 /* Active DDRC self-refresh mode */
244 ldr r3, [r2, #AT91_DDRSDRC_LPR]
245 str r3, .saved_sam9_lpr
246 bic r3, r3, #AT91_DDRSDRC_LPCB
247 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
248 str r3, [r2, #AT91_DDRSDRC_LPR]
249
250 /* If using the 2nd ddr controller */
251 ldr r2, .sramc1_base
252 cmp r2, #0
253 beq no_2nd_ddrc
254
255 ldr r3, [r2, #AT91_DDRSDRC_MDR]
256 str r3, .saved_sam9_mdr1
257 bic r3, r3, #~AT91_DDRSDRC_MD
258 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
259 ldreq r3, [r2, #AT91_DDRSDRC_MDR]
260 biceq r3, r3, #AT91_DDRSDRC_MD
261 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
262 streq r3, [r2, #AT91_DDRSDRC_MDR]
263
264 /* Active DDRC self-refresh mode */
265 ldr r3, [r2, #AT91_DDRSDRC_LPR]
266 str r3, .saved_sam9_lpr1
267 bic r3, r3, #AT91_DDRSDRC_LPCB
268 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
269 str r3, [r2, #AT91_DDRSDRC_LPR]
270
271no_2nd_ddrc:
272 b exit_sramc_sf
273
274ddrc_exit_sf:
275 /* Restore MDR in case of LPDDR1 */
276 ldr r3, .saved_sam9_mdr
277 str r3, [r2, #AT91_DDRSDRC_MDR]
278 /* Restore LPR on AT91 with DDRAM */
279 ldr r3, .saved_sam9_lpr
280 str r3, [r2, #AT91_DDRSDRC_LPR]
281
282 /* If using the 2nd ddr controller */
283 ldr r2, .sramc1_base
284 cmp r2, #0
285 ldrne r3, .saved_sam9_mdr1
286 strne r3, [r2, #AT91_DDRSDRC_MDR]
287 ldrne r3, .saved_sam9_lpr1
288 strne r3, [r2, #AT91_DDRSDRC_LPR]
289
290 b exit_sramc_sf
291
292 /*
293 * SDRAMC Memory controller
294 */
295sdramc_sf:
296 tst r0, #SRAMC_SELF_FRESH_ACTIVE
297 beq sdramc_exit_sf
298
299 /* Active SDRAMC self-refresh mode */
300 ldr r3, [r2, #AT91_SDRAMC_LPR]
301 str r3, .saved_sam9_lpr
302 bic r3, r3, #AT91_SDRAMC_LPCB
303 orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
304 str r3, [r2, #AT91_SDRAMC_LPR]
305
306sdramc_exit_sf:
307 ldr r3, .saved_sam9_lpr
308 str r3, [r2, #AT91_SDRAMC_LPR]
309
310exit_sramc_sf:
311 mov pc, lr
312ENDPROC(at91_sramc_self_refresh)
313
314.pmc_base:
315 .word 0
316.sramc_base:
317 .word 0
318.sramc1_base:
319 .word 0
320.memtype:
321 .word 0
322.pm_mode:
323 .word 0
324.saved_mckr:
325 .word 0
326.saved_pllar:
327 .word 0
328.saved_sam9_lpr:
329 .word 0
330.saved_sam9_lpr1:
331 .word 0
332.saved_sam9_mdr:
333 .word 0
334.saved_sam9_mdr1:
335 .word 0
336
337ENTRY(at91_pm_suspend_in_sram_sz)
338 .word .-at91_pm_suspend_in_sram
diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c
index 03dcb441f3d2..ef5d2073774b 100644
--- a/arch/arm/mach-at91/sama5.c
+++ b/arch/arm/mach-at91/sama5.c
@@ -7,48 +7,50 @@
7 * Licensed under GPLv2 or later. 7 * Licensed under GPLv2 or later.
8 */ 8 */
9 9
10#include <linux/types.h>
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/gpio.h>
14#include <linux/micrel_phy.h>
15#include <linux/of.h> 10#include <linux/of.h>
16#include <linux/of_irq.h>
17#include <linux/of_platform.h> 11#include <linux/of_platform.h>
18#include <linux/phy.h>
19#include <linux/clk-provider.h>
20#include <linux/phy.h>
21 12
22#include <mach/hardware.h>
23
24#include <asm/setup.h>
25#include <asm/irq.h>
26#include <asm/mach/arch.h> 13#include <asm/mach/arch.h>
27#include <asm/mach/map.h> 14#include <asm/mach/map.h>
28#include <asm/mach/irq.h> 15#include <asm/system_misc.h>
29
30#include "generic.h"
31 16
32static int ksz8081_phy_fixup(struct phy_device *phy) 17#include <mach/hardware.h>
33{
34 int value;
35 18
36 value = phy_read(phy, 0x16); 19#include "generic.h"
37 value &= ~0x20; 20#include "soc.h"
38 phy_write(phy, 0x16, value);
39 21
40 return 0; 22static const struct at91_soc sama5_socs[] = {
41} 23 AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,
24 "sama5d31", "sama5d3"),
25 AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,
26 "sama5d33", "sama5d3"),
27 AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH,
28 "sama5d34", "sama5d3"),
29 AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH,
30 "sama5d35", "sama5d3"),
31 AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH,
32 "sama5d36", "sama5d3"),
33 AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH,
34 "sama5d41", "sama5d4"),
35 AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH,
36 "sama5d42", "sama5d4"),
37 AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH,
38 "sama5d43", "sama5d4"),
39 AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH,
40 "sama5d44", "sama5d4"),
41 { /* sentinel */ },
42};
42 43
43static void __init sama5_dt_device_init(void) 44static void __init sama5_dt_device_init(void)
44{ 45{
45 if (of_machine_is_compatible("atmel,sama5d4ek") && 46 struct soc_device *soc;
46 IS_ENABLED(CONFIG_PHYLIB)) { 47 struct device *soc_dev = NULL;
47 phy_register_fixup_for_id("fc028000.etherne:00", 48
48 ksz8081_phy_fixup); 49 soc = at91_soc_init(sama5_socs);
49 } 50 if (soc != NULL)
51 soc_dev = soc_device_to_device(soc);
50 52
51 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 53 of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev);
52 at91sam9x5_pm_init(); 54 at91sam9x5_pm_init();
53} 55}
54 56
@@ -59,44 +61,10 @@ static const char *sama5_dt_board_compat[] __initconst = {
59 61
60DT_MACHINE_START(sama5_dt, "Atmel SAMA5") 62DT_MACHINE_START(sama5_dt, "Atmel SAMA5")
61 /* Maintainer: Atmel */ 63 /* Maintainer: Atmel */
62 .map_io = at91_map_io,
63 .init_machine = sama5_dt_device_init, 64 .init_machine = sama5_dt_device_init,
64 .dt_compat = sama5_dt_board_compat, 65 .dt_compat = sama5_dt_board_compat,
65MACHINE_END 66MACHINE_END
66 67
67static struct map_desc at91_io_desc[] __initdata = {
68 {
69 .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_MPDDRC),
70 .pfn = __phys_to_pfn(SAMA5D4_BASE_MPDDRC),
71 .length = SZ_512,
72 .type = MT_DEVICE,
73 },
74 {
75 .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_PMC),
76 .pfn = __phys_to_pfn(SAMA5D4_BASE_PMC),
77 .length = SZ_512,
78 .type = MT_DEVICE,
79 },
80 { /* On sama5d4, we use USART3 as serial console */
81 .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_USART3),
82 .pfn = __phys_to_pfn(SAMA5D4_BASE_USART3),
83 .length = SZ_256,
84 .type = MT_DEVICE,
85 },
86 { /* A bunch of peripheral with fine grained IO space */
87 .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_SYS2),
88 .pfn = __phys_to_pfn(SAMA5D4_BASE_SYS2),
89 .length = SZ_2K,
90 .type = MT_DEVICE,
91 },
92};
93
94static void __init sama5_alt_map_io(void)
95{
96 at91_alt_map_io();
97 iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc));
98}
99
100static const char *sama5_alt_dt_board_compat[] __initconst = { 68static const char *sama5_alt_dt_board_compat[] __initconst = {
101 "atmel,sama5d4", 69 "atmel,sama5d4",
102 NULL 70 NULL
@@ -104,7 +72,6 @@ static const char *sama5_alt_dt_board_compat[] __initconst = {
104 72
105DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5") 73DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5")
106 /* Maintainer: Atmel */ 74 /* Maintainer: Atmel */
107 .map_io = sama5_alt_map_io,
108 .init_machine = sama5_dt_device_init, 75 .init_machine = sama5_dt_device_init,
109 .dt_compat = sama5_alt_dt_board_compat, 76 .dt_compat = sama5_alt_dt_board_compat,
110 .l2c_aux_mask = ~0UL, 77 .l2c_aux_mask = ~0UL,
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
deleted file mode 100644
index 4e58bc90ed21..000000000000
--- a/arch/arm/mach-at91/setup.c
+++ /dev/null
@@ -1,330 +0,0 @@
1/*
2 * Copyright (C) 2007 Atmel Corporation.
3 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
4 *
5 * Under GPLv2
6 */
7
8#define pr_fmt(fmt) "AT91: " fmt
9
10#include <linux/module.h>
11#include <linux/io.h>
12#include <linux/mm.h>
13#include <linux/pm.h>
14#include <linux/of_address.h>
15#include <linux/pinctrl/machine.h>
16#include <linux/clk/at91_pmc.h>
17
18#include <asm/system_misc.h>
19#include <asm/mach/map.h>
20
21#include <mach/hardware.h>
22#include <mach/cpu.h>
23#include <mach/at91_dbgu.h>
24
25#include "generic.h"
26#include "pm.h"
27
28struct at91_socinfo at91_soc_initdata;
29EXPORT_SYMBOL(at91_soc_initdata);
30
31static struct map_desc at91_io_desc __initdata __maybe_unused = {
32 .virtual = (unsigned long)AT91_VA_BASE_SYS,
33 .pfn = __phys_to_pfn(AT91_BASE_SYS),
34 .length = SZ_16K,
35 .type = MT_DEVICE,
36};
37
38static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
39 .virtual = (unsigned long)AT91_ALT_VA_BASE_SYS,
40 .pfn = __phys_to_pfn(AT91_ALT_BASE_SYS),
41 .length = 24 * SZ_1K,
42 .type = MT_DEVICE,
43};
44
45static void __init soc_detect(u32 dbgu_base)
46{
47 u32 cidr, socid;
48
49 cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
50 socid = cidr & ~AT91_CIDR_VERSION;
51
52 switch (socid) {
53 case ARCH_ID_AT91RM9200:
54 at91_soc_initdata.type = AT91_SOC_RM9200;
55 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
56 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
57 break;
58
59 case ARCH_ID_AT91SAM9260:
60 at91_soc_initdata.type = AT91_SOC_SAM9260;
61 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
62 break;
63
64 case ARCH_ID_AT91SAM9261:
65 at91_soc_initdata.type = AT91_SOC_SAM9261;
66 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
67 break;
68
69 case ARCH_ID_AT91SAM9263:
70 at91_soc_initdata.type = AT91_SOC_SAM9263;
71 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
72 break;
73
74 case ARCH_ID_AT91SAM9G20:
75 at91_soc_initdata.type = AT91_SOC_SAM9G20;
76 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
77 break;
78
79 case ARCH_ID_AT91SAM9G45:
80 at91_soc_initdata.type = AT91_SOC_SAM9G45;
81 if (cidr == ARCH_ID_AT91SAM9G45ES)
82 at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
83 break;
84
85 case ARCH_ID_AT91SAM9RL64:
86 at91_soc_initdata.type = AT91_SOC_SAM9RL;
87 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
88 break;
89
90 case ARCH_ID_AT91SAM9X5:
91 at91_soc_initdata.type = AT91_SOC_SAM9X5;
92 break;
93
94 case ARCH_ID_AT91SAM9N12:
95 at91_soc_initdata.type = AT91_SOC_SAM9N12;
96 break;
97
98 case ARCH_ID_SAMA5:
99 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
100 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
101 at91_soc_initdata.type = AT91_SOC_SAMA5D3;
102 }
103 break;
104 }
105
106 /* at91sam9g10 */
107 if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
108 at91_soc_initdata.type = AT91_SOC_SAM9G10;
109 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
110 }
111 /* at91sam9xe */
112 else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
113 at91_soc_initdata.type = AT91_SOC_SAM9260;
114 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
115 }
116
117 if (!at91_soc_is_detected())
118 return;
119
120 at91_soc_initdata.cidr = cidr;
121
122 /* sub version of soc */
123 if (!at91_soc_initdata.exid)
124 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
125
126 if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
127 switch (at91_soc_initdata.exid) {
128 case ARCH_EXID_AT91SAM9M10:
129 at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
130 break;
131 case ARCH_EXID_AT91SAM9G46:
132 at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
133 break;
134 case ARCH_EXID_AT91SAM9M11:
135 at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
136 break;
137 }
138 }
139
140 if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
141 switch (at91_soc_initdata.exid) {
142 case ARCH_EXID_AT91SAM9G15:
143 at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
144 break;
145 case ARCH_EXID_AT91SAM9G35:
146 at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
147 break;
148 case ARCH_EXID_AT91SAM9X35:
149 at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
150 break;
151 case ARCH_EXID_AT91SAM9G25:
152 at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
153 break;
154 case ARCH_EXID_AT91SAM9X25:
155 at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
156 break;
157 }
158 }
159
160 if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
161 switch (at91_soc_initdata.exid) {
162 case ARCH_EXID_SAMA5D31:
163 at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
164 break;
165 case ARCH_EXID_SAMA5D33:
166 at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
167 break;
168 case ARCH_EXID_SAMA5D34:
169 at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
170 break;
171 case ARCH_EXID_SAMA5D35:
172 at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
173 break;
174 case ARCH_EXID_SAMA5D36:
175 at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
176 break;
177 }
178 }
179}
180
181static void __init alt_soc_detect(u32 dbgu_base)
182{
183 u32 cidr, socid;
184
185 /* SoC ID */
186 cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
187 socid = cidr & ~AT91_CIDR_VERSION;
188
189 switch (socid) {
190 case ARCH_ID_SAMA5:
191 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
192 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
193 at91_soc_initdata.type = AT91_SOC_SAMA5D3;
194 } else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
195 at91_soc_initdata.type = AT91_SOC_SAMA5D4;
196 }
197 break;
198 }
199
200 if (!at91_soc_is_detected())
201 return;
202
203 at91_soc_initdata.cidr = cidr;
204
205 /* sub version of soc */
206 if (!at91_soc_initdata.exid)
207 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
208
209 if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
210 switch (at91_soc_initdata.exid) {
211 case ARCH_EXID_SAMA5D41:
212 at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
213 break;
214 case ARCH_EXID_SAMA5D42:
215 at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
216 break;
217 case ARCH_EXID_SAMA5D43:
218 at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
219 break;
220 case ARCH_EXID_SAMA5D44:
221 at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
222 break;
223 }
224 }
225}
226
227static const char *soc_name[] = {
228 [AT91_SOC_RM9200] = "at91rm9200",
229 [AT91_SOC_SAM9260] = "at91sam9260",
230 [AT91_SOC_SAM9261] = "at91sam9261",
231 [AT91_SOC_SAM9263] = "at91sam9263",
232 [AT91_SOC_SAM9G10] = "at91sam9g10",
233 [AT91_SOC_SAM9G20] = "at91sam9g20",
234 [AT91_SOC_SAM9G45] = "at91sam9g45",
235 [AT91_SOC_SAM9RL] = "at91sam9rl",
236 [AT91_SOC_SAM9X5] = "at91sam9x5",
237 [AT91_SOC_SAM9N12] = "at91sam9n12",
238 [AT91_SOC_SAMA5D3] = "sama5d3",
239 [AT91_SOC_SAMA5D4] = "sama5d4",
240 [AT91_SOC_UNKNOWN] = "Unknown",
241};
242
243const char *at91_get_soc_type(struct at91_socinfo *c)
244{
245 return soc_name[c->type];
246}
247EXPORT_SYMBOL(at91_get_soc_type);
248
249static const char *soc_subtype_name[] = {
250 [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
251 [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
252 [AT91_SOC_SAM9XE] = "at91sam9xe",
253 [AT91_SOC_SAM9G45ES] = "at91sam9g45es",
254 [AT91_SOC_SAM9M10] = "at91sam9m10",
255 [AT91_SOC_SAM9G46] = "at91sam9g46",
256 [AT91_SOC_SAM9M11] = "at91sam9m11",
257 [AT91_SOC_SAM9G15] = "at91sam9g15",
258 [AT91_SOC_SAM9G35] = "at91sam9g35",
259 [AT91_SOC_SAM9X35] = "at91sam9x35",
260 [AT91_SOC_SAM9G25] = "at91sam9g25",
261 [AT91_SOC_SAM9X25] = "at91sam9x25",
262 [AT91_SOC_SAMA5D31] = "sama5d31",
263 [AT91_SOC_SAMA5D33] = "sama5d33",
264 [AT91_SOC_SAMA5D34] = "sama5d34",
265 [AT91_SOC_SAMA5D35] = "sama5d35",
266 [AT91_SOC_SAMA5D36] = "sama5d36",
267 [AT91_SOC_SAMA5D41] = "sama5d41",
268 [AT91_SOC_SAMA5D42] = "sama5d42",
269 [AT91_SOC_SAMA5D43] = "sama5d43",
270 [AT91_SOC_SAMA5D44] = "sama5d44",
271 [AT91_SOC_SUBTYPE_NONE] = "None",
272 [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
273};
274
275const char *at91_get_soc_subtype(struct at91_socinfo *c)
276{
277 return soc_subtype_name[c->subtype];
278}
279EXPORT_SYMBOL(at91_get_soc_subtype);
280
281void __init at91_map_io(void)
282{
283 /* Map peripherals */
284 iotable_init(&at91_io_desc, 1);
285
286 at91_soc_initdata.type = AT91_SOC_UNKNOWN;
287 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
288
289 soc_detect(AT91_BASE_DBGU0);
290 if (!at91_soc_is_detected())
291 soc_detect(AT91_BASE_DBGU1);
292
293 if (!at91_soc_is_detected())
294 panic(pr_fmt("Impossible to detect the SOC type"));
295
296 pr_info("Detected soc type: %s\n",
297 at91_get_soc_type(&at91_soc_initdata));
298 if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
299 pr_info("Detected soc subtype: %s\n",
300 at91_get_soc_subtype(&at91_soc_initdata));
301}
302
303void __init at91_alt_map_io(void)
304{
305 /* Map peripherals */
306 iotable_init(&at91_alt_io_desc, 1);
307
308 at91_soc_initdata.type = AT91_SOC_UNKNOWN;
309 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
310
311 alt_soc_detect(AT91_BASE_DBGU2);
312 if (!at91_soc_is_detected())
313 panic("AT91: Impossible to detect the SOC type");
314
315 pr_info("AT91: Detected soc type: %s\n",
316 at91_get_soc_type(&at91_soc_initdata));
317 if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
318 pr_info("AT91: Detected soc subtype: %s\n",
319 at91_get_soc_subtype(&at91_soc_initdata));
320}
321
322void __iomem *at91_matrix_base;
323EXPORT_SYMBOL_GPL(at91_matrix_base);
324
325void __init at91_ioremap_matrix(u32 base_addr)
326{
327 at91_matrix_base = ioremap(base_addr, 512);
328 if (!at91_matrix_base)
329 panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
330}
diff --git a/arch/arm/mach-at91/soc.c b/arch/arm/mach-at91/soc.c
new file mode 100644
index 000000000000..54343ffa3e53
--- /dev/null
+++ b/arch/arm/mach-at91/soc.c
@@ -0,0 +1,97 @@
1/*
2 * Copyright (C) 2015 Atmel
3 *
4 * Alexandre Belloni <alexandre.belloni@free-electrons.com
5 * Boris Brezillon <boris.brezillon@free-electrons.com
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 *
11 */
12
13#define pr_fmt(fmt) "AT91: " fmt
14
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_platform.h>
19#include <linux/slab.h>
20#include <linux/sys_soc.h>
21
22#include "soc.h"
23
24#define AT91_DBGU_CIDR 0x40
25#define AT91_DBGU_CIDR_VERSION(x) ((x) & 0x1f)
26#define AT91_DBGU_CIDR_EXT BIT(31)
27#define AT91_DBGU_CIDR_MATCH_MASK 0x7fffffe0
28#define AT91_DBGU_EXID 0x44
29
30struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
31{
32 struct soc_device_attribute *soc_dev_attr;
33 const struct at91_soc *soc;
34 struct soc_device *soc_dev;
35 struct device_node *np;
36 void __iomem *regs;
37 u32 cidr, exid;
38
39 np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu");
40 if (!np)
41 np = of_find_compatible_node(NULL, NULL,
42 "atmel,at91sam9260-dbgu");
43
44 if (!np) {
45 pr_warn("Could not find DBGU node");
46 return NULL;
47 }
48
49 regs = of_iomap(np, 0);
50 of_node_put(np);
51
52 if (!regs) {
53 pr_warn("Could not map DBGU iomem range");
54 return NULL;
55 }
56
57 cidr = readl(regs + AT91_DBGU_CIDR);
58 exid = readl(regs + AT91_DBGU_EXID);
59
60 iounmap(regs);
61
62 for (soc = socs; soc->name; soc++) {
63 if (soc->cidr_match != (cidr & AT91_DBGU_CIDR_MATCH_MASK))
64 continue;
65
66 if (!(cidr & AT91_DBGU_CIDR_EXT) || soc->exid_match == exid)
67 break;
68 }
69
70 if (!soc->name) {
71 pr_warn("Could not find matching SoC description\n");
72 return NULL;
73 }
74
75 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
76 if (!soc_dev_attr)
77 return NULL;
78
79 soc_dev_attr->family = soc->family;
80 soc_dev_attr->soc_id = soc->name;
81 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
82 AT91_DBGU_CIDR_VERSION(cidr));
83 soc_dev = soc_device_register(soc_dev_attr);
84 if (IS_ERR(soc_dev)) {
85 kfree(soc_dev_attr->revision);
86 kfree(soc_dev_attr);
87 pr_warn("Could not register SoC device\n");
88 return NULL;
89 }
90
91 if (soc->family)
92 pr_info("Detected SoC family: %s\n", soc->family);
93 pr_info("Detected SoC: %s, revision %X\n", soc->name,
94 AT91_DBGU_CIDR_VERSION(cidr));
95
96 return soc_dev;
97}
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
new file mode 100644
index 000000000000..be23c400596b
--- /dev/null
+++ b/arch/arm/mach-at91/soc.h
@@ -0,0 +1,78 @@
1/*
2 * Copyright (C) 2015 Atmel
3 *
4 * Boris Brezillon <boris.brezillon@free-electrons.com
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 */
11
12#ifndef __AT91_SOC_H
13#define __AT91_SOC_H
14
15#include <linux/sys_soc.h>
16
17struct at91_soc {
18 u32 cidr_match;
19 u32 exid_match;
20 const char *name;
21 const char *family;
22};
23
24#define AT91_SOC(__cidr, __exid, __name, __family) \
25 { \
26 .cidr_match = (__cidr), \
27 .exid_match = (__exid), \
28 .name = (__name), \
29 .family = (__family), \
30 }
31
32struct soc_device * __init
33at91_soc_init(const struct at91_soc *socs);
34
35#define AT91RM9200_CIDR_MATCH 0x09290780
36
37#define AT91SAM9260_CIDR_MATCH 0x019803a0
38#define AT91SAM9261_CIDR_MATCH 0x019703a0
39#define AT91SAM9263_CIDR_MATCH 0x019607a0
40#define AT91SAM9G20_CIDR_MATCH 0x019905a0
41#define AT91SAM9RL64_CIDR_MATCH 0x019b03a0
42#define AT91SAM9G45_CIDR_MATCH 0x019b05a0
43#define AT91SAM9X5_CIDR_MATCH 0x019a05a0
44#define AT91SAM9N12_CIDR_MATCH 0x019a07a0
45
46#define AT91SAM9M11_EXID_MATCH 0x00000001
47#define AT91SAM9M10_EXID_MATCH 0x00000002
48#define AT91SAM9G46_EXID_MATCH 0x00000003
49#define AT91SAM9G45_EXID_MATCH 0x00000004
50
51#define AT91SAM9G15_EXID_MATCH 0x00000000
52#define AT91SAM9G35_EXID_MATCH 0x00000001
53#define AT91SAM9X35_EXID_MATCH 0x00000002
54#define AT91SAM9G25_EXID_MATCH 0x00000003
55#define AT91SAM9X25_EXID_MATCH 0x00000004
56
57#define AT91SAM9CN12_EXID_MATCH 0x00000005
58#define AT91SAM9N12_EXID_MATCH 0x00000006
59#define AT91SAM9CN11_EXID_MATCH 0x00000009
60
61#define AT91SAM9XE128_CIDR_MATCH 0x329973a0
62#define AT91SAM9XE256_CIDR_MATCH 0x329a93a0
63#define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0
64
65#define SAMA5D3_CIDR_MATCH 0x0a5c07c0
66#define SAMA5D31_EXID_MATCH 0x00444300
67#define SAMA5D33_EXID_MATCH 0x00414300
68#define SAMA5D34_EXID_MATCH 0x00414301
69#define SAMA5D35_EXID_MATCH 0x00584300
70#define SAMA5D36_EXID_MATCH 0x00004301
71
72#define SAMA5D4_CIDR_MATCH 0x0a5c07c0
73#define SAMA5D41_EXID_MATCH 0x00000001
74#define SAMA5D42_EXID_MATCH 0x00000002
75#define SAMA5D43_EXID_MATCH 0x00000003
76#define SAMA5D44_EXID_MATCH 0x00000004
77
78#endif /* __AT91_SOC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 08:26:45 -0500