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authorPaul Walmsley <paul@pwsan.com>2011-09-14 18:01:21 -0400
committerPaul Walmsley <paul@pwsan.com>2011-09-14 18:01:21 -0400
commita5ffef6af127721a813d70f87cd8cc348ea9d6ab (patch)
treec68df36339ab9a6842a35813d5ec3d05683b516c /arch/arm
parent08cb9703e2922db297d8f83ec110bde37823e021 (diff)
OMAP: clockdomain code/data: remove omap_chip bitmask from struct clockdomain
At Tony's request, remove the omap_chip bitmasks from the clockdomain and clockdomain dependency definitions. Instead, initialize clockdomains based on one or more lists that are applicable to a particular SoC family, variant, and silicon revision. Tony Lindgren <tony@atomide.com> found a bug in a previous version of this patch - thanks Tony. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/Makefile5
-rw-r--r--arch/arm/mach-omap2/clockdomain.c19
-rw-r--r--arch/arm/mach-omap2/clockdomain.h15
-rw-r--r--arch/arm/mach-omap2/clockdomain2xxx_3xxx.c4
-rw-r--r--arch/arm/mach-omap2/clockdomain44xx.c2
-rw-r--r--arch/arm/mach-omap2/clockdomains2420_data.c154
-rw-r--r--arch/arm/mach-omap2/clockdomains2430_data.c181
-rw-r--r--arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c812
-rw-r--r--arch/arm/mach-omap2/clockdomains3xxx_data.c398
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c404
-rw-r--r--arch/arm/mach-omap2/io.c4
11 files changed, 842 insertions, 1156 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f34336560437..5a6fe735b566 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -116,9 +116,12 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \
116obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \ 116obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \
117 clockdomain2xxx_3xxx.o \ 117 clockdomain2xxx_3xxx.o \
118 clockdomains2xxx_3xxx_data.o 118 clockdomains2xxx_3xxx_data.o
119obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
120obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
119obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \ 121obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
120 clockdomain2xxx_3xxx.o \ 122 clockdomain2xxx_3xxx.o \
121 clockdomains2xxx_3xxx_data.o 123 clockdomains2xxx_3xxx_data.o \
124 clockdomains3xxx_data.o
122obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \ 125obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
123 clockdomain44xx.o \ 126 clockdomain44xx.o \
124 clockdomains44xx_data.o 127 clockdomains44xx_data.o
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index b73a1dc37dfb..8480ee4344ea 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -73,9 +73,6 @@ static int _clkdm_register(struct clockdomain *clkdm)
73 if (!clkdm || !clkdm->name) 73 if (!clkdm || !clkdm->name)
74 return -EINVAL; 74 return -EINVAL;
75 75
76 if (!omap_chip_is(clkdm->omap_chip))
77 return -EINVAL;
78
79 pwrdm = pwrdm_lookup(clkdm->pwrdm.name); 76 pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
80 if (!pwrdm) { 77 if (!pwrdm) {
81 pr_err("clockdomain: %s: powerdomain %s does not exist\n", 78 pr_err("clockdomain: %s: powerdomain %s does not exist\n",
@@ -105,13 +102,10 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
105{ 102{
106 struct clkdm_dep *cd; 103 struct clkdm_dep *cd;
107 104
108 if (!clkdm || !deps || !omap_chip_is(clkdm->omap_chip)) 105 if (!clkdm || !deps)
109 return ERR_PTR(-EINVAL); 106 return ERR_PTR(-EINVAL);
110 107
111 for (cd = deps; cd->clkdm_name; cd++) { 108 for (cd = deps; cd->clkdm_name; cd++) {
112 if (!omap_chip_is(cd->omap_chip))
113 continue;
114
115 if (!cd->clkdm && cd->clkdm_name) 109 if (!cd->clkdm && cd->clkdm_name)
116 cd->clkdm = _clkdm_lookup(cd->clkdm_name); 110 cd->clkdm = _clkdm_lookup(cd->clkdm_name);
117 111
@@ -148,9 +142,6 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
148 if (!autodep) 142 if (!autodep)
149 return; 143 return;
150 144
151 if (!omap_chip_is(autodep->omap_chip))
152 return;
153
154 clkdm = clkdm_lookup(autodep->clkdm.name); 145 clkdm = clkdm_lookup(autodep->clkdm.name);
155 if (!clkdm) { 146 if (!clkdm) {
156 pr_err("clockdomain: autodeps: clockdomain %s does not exist\n", 147 pr_err("clockdomain: autodeps: clockdomain %s does not exist\n",
@@ -182,9 +173,6 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm)
182 if (IS_ERR(autodep->clkdm.ptr)) 173 if (IS_ERR(autodep->clkdm.ptr))
183 continue; 174 continue;
184 175
185 if (!omap_chip_is(autodep->omap_chip))
186 continue;
187
188 pr_debug("clockdomain: adding %s sleepdep/wkdep for " 176 pr_debug("clockdomain: adding %s sleepdep/wkdep for "
189 "clkdm %s\n", autodep->clkdm.ptr->name, 177 "clkdm %s\n", autodep->clkdm.ptr->name,
190 clkdm->name); 178 clkdm->name);
@@ -216,9 +204,6 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
216 if (IS_ERR(autodep->clkdm.ptr)) 204 if (IS_ERR(autodep->clkdm.ptr))
217 continue; 205 continue;
218 206
219 if (!omap_chip_is(autodep->omap_chip))
220 continue;
221
222 pr_debug("clockdomain: removing %s sleepdep/wkdep for " 207 pr_debug("clockdomain: removing %s sleepdep/wkdep for "
223 "clkdm %s\n", autodep->clkdm.ptr->name, 208 "clkdm %s\n", autodep->clkdm.ptr->name,
224 clkdm->name); 209 clkdm->name);
@@ -243,8 +228,6 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm,
243 struct clkdm_dep *cd; 228 struct clkdm_dep *cd;
244 229
245 for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) { 230 for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
246 if (!omap_chip_is(cd->omap_chip))
247 continue;
248 if (cd->clkdm) 231 if (cd->clkdm)
249 continue; 232 continue;
250 cd->clkdm = _clkdm_lookup(cd->clkdm_name); 233 cd->clkdm = _clkdm_lookup(cd->clkdm_name);
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 0d879ff490d1..f7b58609bad8 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -45,7 +45,6 @@
45/** 45/**
46 * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode 46 * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
47 * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only 47 * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
48 * @omap_chip: OMAP chip types that this autodep is valid on
49 * 48 *
50 * A clockdomain that should have wkdeps and sleepdeps added when a 49 * A clockdomain that should have wkdeps and sleepdeps added when a
51 * clockdomain should stay active in hwsup mode; and conversely, 50 * clockdomain should stay active in hwsup mode; and conversely,
@@ -60,14 +59,12 @@ struct clkdm_autodep {
60 const char *name; 59 const char *name;
61 struct clockdomain *ptr; 60 struct clockdomain *ptr;
62 } clkdm; 61 } clkdm;
63 const struct omap_chip_id omap_chip;
64}; 62};
65 63
66/** 64/**
67 * struct clkdm_dep - encode dependencies between clockdomains 65 * struct clkdm_dep - encode dependencies between clockdomains
68 * @clkdm_name: clockdomain name 66 * @clkdm_name: clockdomain name
69 * @clkdm: pointer to the struct clockdomain of @clkdm_name 67 * @clkdm: pointer to the struct clockdomain of @clkdm_name
70 * @omap_chip: OMAP chip types that this dependency is valid on
71 * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake 68 * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
72 * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle 69 * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
73 * 70 *
@@ -81,7 +78,6 @@ struct clkdm_dep {
81 struct clockdomain *clkdm; 78 struct clockdomain *clkdm;
82 atomic_t wkdep_usecount; 79 atomic_t wkdep_usecount;
83 atomic_t sleepdep_usecount; 80 atomic_t sleepdep_usecount;
84 const struct omap_chip_id omap_chip;
85}; 81};
86 82
87/* Possible flags for struct clockdomain._flags */ 83/* Possible flags for struct clockdomain._flags */
@@ -101,7 +97,6 @@ struct clkdm_dep {
101 * @clkdm_offs: (OMAP4 only) CM clockdomain register offset 97 * @clkdm_offs: (OMAP4 only) CM clockdomain register offset
102 * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up 98 * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
103 * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact 99 * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
104 * @omap_chip: OMAP chip types that this clockdomain is valid on
105 * @usecount: Usecount tracking 100 * @usecount: Usecount tracking
106 * @node: list_head to link all clockdomains together 101 * @node: list_head to link all clockdomains together
107 * 102 *
@@ -126,7 +121,6 @@ struct clockdomain {
126 const u16 clkdm_offs; 121 const u16 clkdm_offs;
127 struct clkdm_dep *wkdep_srcs; 122 struct clkdm_dep *wkdep_srcs;
128 struct clkdm_dep *sleepdep_srcs; 123 struct clkdm_dep *sleepdep_srcs;
129 const struct omap_chip_id omap_chip;
130 atomic_t usecount; 124 atomic_t usecount;
131 struct list_head node; 125 struct list_head node;
132 spinlock_t lock; 126 spinlock_t lock;
@@ -198,7 +192,8 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
198int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh); 192int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
199int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); 193int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
200 194
201extern void __init omap2xxx_clockdomains_init(void); 195extern void __init omap242x_clockdomains_init(void);
196extern void __init omap243x_clockdomains_init(void);
202extern void __init omap3xxx_clockdomains_init(void); 197extern void __init omap3xxx_clockdomains_init(void);
203extern void __init omap44xx_clockdomains_init(void); 198extern void __init omap44xx_clockdomains_init(void);
204extern void _clkdm_add_autodeps(struct clockdomain *clkdm); 199extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
@@ -208,4 +203,10 @@ extern struct clkdm_ops omap2_clkdm_operations;
208extern struct clkdm_ops omap3_clkdm_operations; 203extern struct clkdm_ops omap3_clkdm_operations;
209extern struct clkdm_ops omap4_clkdm_operations; 204extern struct clkdm_ops omap4_clkdm_operations;
210 205
206extern struct clkdm_dep gfx_24xx_wkdeps[];
207extern struct clkdm_dep dsp_24xx_wkdeps[];
208extern struct clockdomain wkup_common_clkdm;
209extern struct clockdomain prm_common_clkdm;
210extern struct clockdomain cm_common_clkdm;
211
211#endif 212#endif
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
index f740edb111f4..a0d68dbecfa3 100644
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -52,8 +52,6 @@ static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
52 u32 mask = 0; 52 u32 mask = 0;
53 53
54 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { 54 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
55 if (!omap_chip_is(cd->omap_chip))
56 continue;
57 if (!cd->clkdm) 55 if (!cd->clkdm)
58 continue; /* only happens if data is erroneous */ 56 continue; /* only happens if data is erroneous */
59 57
@@ -98,8 +96,6 @@ static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
98 u32 mask = 0; 96 u32 mask = 0;
99 97
100 for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) { 98 for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
101 if (!omap_chip_is(cd->omap_chip))
102 continue;
103 if (!cd->clkdm) 99 if (!cd->clkdm)
104 continue; /* only happens if data is erroneous */ 100 continue; /* only happens if data is erroneous */
105 101
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index b43706aa08bd..935c7f03dab9 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -52,8 +52,6 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
52 u32 mask = 0; 52 u32 mask = 0;
53 53
54 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { 54 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
55 if (!omap_chip_is(cd->omap_chip))
56 continue;
57 if (!cd->clkdm) 55 if (!cd->clkdm)
58 continue; /* only happens if data is erroneous */ 56 continue; /* only happens if data is erroneous */
59 57
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
new file mode 100644
index 000000000000..0ab8e46d5b2b
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains2420_data.c
@@ -0,0 +1,154 @@
1/*
2 * OMAP2420 clockdomains
3 *
4 * Copyright (C) 2008-2011 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Paul Walmsley, Jouni Högander
8 *
9 * This file contains clockdomains and clockdomain wakeup dependencies
10 * for OMAP2420 chips. Some notes:
11 *
12 * A useful validation rule for struct clockdomain: Any clockdomain
13 * referenced by a wkdep_srcs must have a dep_bit assigned. So
14 * wkdep_srcs are really just software-controllable dependencies.
15 * Non-software-controllable dependencies do exist, but they are not
16 * encoded below (yet).
17 *
18 * 24xx does not support programmable sleep dependencies (SLEEPDEP)
19 *
20 * The overly-specific dep_bit names are due to a bit name collision
21 * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
22 * value are the same for all powerdomains: 2
23 *
24 * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
25 * sanity check?
26 * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
27 */
28
29/*
30 * To-Do List
31 * -> Port the Sleep/Wakeup dependencies for the domains
32 * from the Power domain framework
33 */
34
35#include <linux/kernel.h>
36#include <linux/io.h>
37
38#include "clockdomain.h"
39#include "prm2xxx_3xxx.h"
40#include "cm2xxx_3xxx.h"
41#include "cm-regbits-24xx.h"
42#include "prm-regbits-24xx.h"
43
44/*
45 * Clockdomain dependencies for wkdeps
46 *
47 * XXX Hardware dependencies (e.g., dependencies that cannot be
48 * changed in software) are not included here yet, but should be.
49 */
50
51/* Wakeup dependency source arrays */
52
53/* 2420-specific possible wakeup dependencies */
54
55/* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP */
56static struct clkdm_dep mpu_2420_wkdeps[] = {
57 { .clkdm_name = "core_l3_clkdm" },
58 { .clkdm_name = "core_l4_clkdm" },
59 { .clkdm_name = "dsp_clkdm" },
60 { .clkdm_name = "wkup_clkdm" },
61 { NULL },
62};
63
64/* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP */
65static struct clkdm_dep core_2420_wkdeps[] = {
66 { .clkdm_name = "dsp_clkdm" },
67 { .clkdm_name = "gfx_clkdm" },
68 { .clkdm_name = "mpu_clkdm" },
69 { .clkdm_name = "wkup_clkdm" },
70 { NULL },
71};
72
73/*
74 * 2420-only clockdomains
75 */
76
77static struct clockdomain mpu_2420_clkdm = {
78 .name = "mpu_clkdm",
79 .pwrdm = { .name = "mpu_pwrdm" },
80 .flags = CLKDM_CAN_HWSUP,
81 .wkdep_srcs = mpu_2420_wkdeps,
82 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
83};
84
85static struct clockdomain iva1_2420_clkdm = {
86 .name = "iva1_clkdm",
87 .pwrdm = { .name = "dsp_pwrdm" },
88 .flags = CLKDM_CAN_HWSUP_SWSUP,
89 .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
90 .wkdep_srcs = dsp_24xx_wkdeps,
91 .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
92};
93
94static struct clockdomain dsp_2420_clkdm = {
95 .name = "dsp_clkdm",
96 .pwrdm = { .name = "dsp_pwrdm" },
97 .flags = CLKDM_CAN_HWSUP_SWSUP,
98 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
99};
100
101static struct clockdomain gfx_2420_clkdm = {
102 .name = "gfx_clkdm",
103 .pwrdm = { .name = "gfx_pwrdm" },
104 .flags = CLKDM_CAN_HWSUP_SWSUP,
105 .wkdep_srcs = gfx_24xx_wkdeps,
106 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
107};
108
109static struct clockdomain core_l3_2420_clkdm = {
110 .name = "core_l3_clkdm",
111 .pwrdm = { .name = "core_pwrdm" },
112 .flags = CLKDM_CAN_HWSUP,
113 .wkdep_srcs = core_2420_wkdeps,
114 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
115};
116
117static struct clockdomain core_l4_2420_clkdm = {
118 .name = "core_l4_clkdm",
119 .pwrdm = { .name = "core_pwrdm" },
120 .flags = CLKDM_CAN_HWSUP,
121 .wkdep_srcs = core_2420_wkdeps,
122 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
123};
124
125static struct clockdomain dss_2420_clkdm = {
126 .name = "dss_clkdm",
127 .pwrdm = { .name = "core_pwrdm" },
128 .flags = CLKDM_CAN_HWSUP,
129 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
130};
131
132static struct clockdomain *clockdomains_omap242x[] __initdata = {
133 &wkup_common_clkdm,
134 &cm_common_clkdm,
135 &prm_common_clkdm,
136 &mpu_2420_clkdm,
137 &iva1_2420_clkdm,
138 &dsp_2420_clkdm,
139 &gfx_2420_clkdm,
140 &core_l3_2420_clkdm,
141 &core_l4_2420_clkdm,
142 &dss_2420_clkdm,
143 NULL,
144};
145
146void __init omap242x_clockdomains_init(void)
147{
148 if (!cpu_is_omap242x())
149 return;
150
151 clkdm_register_platform_funcs(&omap2_clkdm_operations);
152 clkdm_register_clkdms(clockdomains_omap242x);
153 clkdm_complete_init();
154}
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
new file mode 100644
index 000000000000..3645ed044890
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains2430_data.c
@@ -0,0 +1,181 @@
1/*
2 * OMAP2xxx clockdomains
3 *
4 * Copyright (C) 2008-2009 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Paul Walmsley, Jouni Högander
8 *
9 * This file contains clockdomains and clockdomain wakeup dependencies
10 * for OMAP2xxx chips. Some notes:
11 *
12 * A useful validation rule for struct clockdomain: Any clockdomain
13 * referenced by a wkdep_srcs must have a dep_bit assigned. So
14 * wkdep_srcs are really just software-controllable dependencies.
15 * Non-software-controllable dependencies do exist, but they are not
16 * encoded below (yet).
17 *
18 * 24xx does not support programmable sleep dependencies (SLEEPDEP)
19 *
20 * The overly-specific dep_bit names are due to a bit name collision
21 * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
22 * value are the same for all powerdomains: 2
23 *
24 * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
25 * sanity check?
26 * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
27 */
28
29/*
30 * To-Do List
31 * -> Port the Sleep/Wakeup dependencies for the domains
32 * from the Power domain framework
33 */
34
35#include <linux/kernel.h>
36#include <linux/io.h>
37
38#include "clockdomain.h"
39#include "prm2xxx_3xxx.h"
40#include "cm2xxx_3xxx.h"
41#include "cm-regbits-24xx.h"
42#include "prm-regbits-24xx.h"
43
44/*
45 * Clockdomain dependencies for wkdeps
46 *
47 * XXX Hardware dependencies (e.g., dependencies that cannot be
48 * changed in software) are not included here yet, but should be.
49 */
50
51/* Wakeup dependency source arrays */
52
53/* 2430-specific possible wakeup dependencies */
54
55/* 2430 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP, MDM */
56static struct clkdm_dep core_2430_wkdeps[] = {
57 { .clkdm_name = "dsp_clkdm" },
58 { .clkdm_name = "gfx_clkdm" },
59 { .clkdm_name = "mpu_clkdm" },
60 { .clkdm_name = "wkup_clkdm" },
61 { .clkdm_name = "mdm_clkdm" },
62 { NULL },
63};
64
65/* 2430 PM_WKDEP_MPU: CORE, DSP, WKUP, MDM */
66static struct clkdm_dep mpu_2430_wkdeps[] = {
67 { .clkdm_name = "core_l3_clkdm" },
68 { .clkdm_name = "core_l4_clkdm" },
69 { .clkdm_name = "dsp_clkdm" },
70 { .clkdm_name = "wkup_clkdm" },
71 { .clkdm_name = "mdm_clkdm" },
72 { NULL },
73};
74
75/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
76static struct clkdm_dep mdm_2430_wkdeps[] = {
77 { .clkdm_name = "core_l3_clkdm" },
78 { .clkdm_name = "core_l4_clkdm" },
79 { .clkdm_name = "mpu_clkdm" },
80 { .clkdm_name = "wkup_clkdm" },
81 { NULL },
82};
83
84/*
85 * 2430-only clockdomains
86 */
87
88static struct clockdomain mpu_2430_clkdm = {
89 .name = "mpu_clkdm",
90 .pwrdm = { .name = "mpu_pwrdm" },
91 .flags = CLKDM_CAN_HWSUP_SWSUP,
92 .wkdep_srcs = mpu_2430_wkdeps,
93 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
94};
95
96/* Another case of bit name collisions between several registers: EN_MDM */
97static struct clockdomain mdm_clkdm = {
98 .name = "mdm_clkdm",
99 .pwrdm = { .name = "mdm_pwrdm" },
100 .flags = CLKDM_CAN_HWSUP_SWSUP,
101 .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
102 .wkdep_srcs = mdm_2430_wkdeps,
103 .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
104};
105
106static struct clockdomain dsp_2430_clkdm = {
107 .name = "dsp_clkdm",
108 .pwrdm = { .name = "dsp_pwrdm" },
109 .flags = CLKDM_CAN_HWSUP_SWSUP,
110 .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
111 .wkdep_srcs = dsp_24xx_wkdeps,
112 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
113};
114
115static struct clockdomain gfx_2430_clkdm = {
116 .name = "gfx_clkdm",
117 .pwrdm = { .name = "gfx_pwrdm" },
118 .flags = CLKDM_CAN_HWSUP_SWSUP,
119 .wkdep_srcs = gfx_24xx_wkdeps,
120 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
121};
122
123/*
124 * XXX add usecounting for clkdm dependencies, otherwise the presence
125 * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
126 * could cause trouble
127 */
128static struct clockdomain core_l3_2430_clkdm = {
129 .name = "core_l3_clkdm",
130 .pwrdm = { .name = "core_pwrdm" },
131 .flags = CLKDM_CAN_HWSUP,
132 .dep_bit = OMAP24XX_EN_CORE_SHIFT,
133 .wkdep_srcs = core_2430_wkdeps,
134 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
135};
136
137/*
138 * XXX add usecounting for clkdm dependencies, otherwise the presence
139 * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
140 * could cause trouble
141 */
142static struct clockdomain core_l4_2430_clkdm = {
143 .name = "core_l4_clkdm",
144 .pwrdm = { .name = "core_pwrdm" },
145 .flags = CLKDM_CAN_HWSUP,
146 .dep_bit = OMAP24XX_EN_CORE_SHIFT,
147 .wkdep_srcs = core_2430_wkdeps,
148 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
149};
150
151static struct clockdomain dss_2430_clkdm = {
152 .name = "dss_clkdm",
153 .pwrdm = { .name = "core_pwrdm" },
154 .flags = CLKDM_CAN_HWSUP,
155 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
156};
157
158static struct clockdomain *clockdomains_omap243x[] __initdata = {
159 &wkup_common_clkdm,
160 &cm_common_clkdm,
161 &prm_common_clkdm,
162 &mpu_2430_clkdm,
163 &mdm_clkdm,
164 &dsp_2430_clkdm,
165 &gfx_2430_clkdm,
166 &core_l3_2430_clkdm,
167 &core_l4_2430_clkdm,
168 &dss_2430_clkdm,
169 NULL,
170};
171
172void __init omap243x_clockdomains_init(void)
173{
174 if (!cpu_is_omap243x())
175 return;
176
177 clkdm_register_platform_funcs(&omap2_clkdm_operations);
178 clkdm_register_clkdms(clockdomains_omap243x);
179 clkdm_complete_init();
180}
181
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 148a3e84162c..0a6a04897d89 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP2/3 clockdomains 2 * OMAP2/3 clockdomain common data
3 * 3 *
4 * Copyright (C) 2008-2009 Texas Instruments, Inc. 4 * Copyright (C) 2008-2011 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation 5 * Copyright (C) 2008-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley, Jouni Högander 7 * Paul Walmsley, Jouni Högander
@@ -51,374 +51,28 @@
51 * changed in software) are not included here yet, but should be. 51 * changed in software) are not included here yet, but should be.
52 */ 52 */
53 53
54/* OMAP2/3-common wakeup dependencies */
55
56/*
57 * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
58 * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
59 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
60 * These can share data since they will never be present simultaneously
61 * on the same device.
62 */
63static struct clkdm_dep gfx_sgx_wkdeps[] = {
64 {
65 .clkdm_name = "core_l3_clkdm",
66 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
67 },
68 {
69 .clkdm_name = "core_l4_clkdm",
70 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
71 },
72 {
73 .clkdm_name = "iva2_clkdm",
74 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
75 },
76 {
77 .clkdm_name = "mpu_clkdm",
78 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
79 CHIP_IS_OMAP3430)
80 },
81 {
82 .clkdm_name = "wkup_clkdm",
83 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
84 CHIP_IS_OMAP3430)
85 },
86 { NULL },
87};
88
89
90/* 24XX-specific possible dependencies */
91
92#ifdef CONFIG_ARCH_OMAP2
93
94/* Wakeup dependency source arrays */ 54/* Wakeup dependency source arrays */
95 55
96/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */ 56/* 2xxx-specific possible dependencies */
97static struct clkdm_dep dsp_24xx_wkdeps[] = {
98 {
99 .clkdm_name = "core_l3_clkdm",
100 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
101 },
102 {
103 .clkdm_name = "core_l4_clkdm",
104 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
105 },
106 {
107 .clkdm_name = "mpu_clkdm",
108 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
109 },
110 {
111 .clkdm_name = "wkup_clkdm",
112 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
113 },
114 { NULL },
115};
116
117/*
118 * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
119 * 2430 adds MDM
120 */
121static struct clkdm_dep mpu_24xx_wkdeps[] = {
122 {
123 .clkdm_name = "core_l3_clkdm",
124 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
125 },
126 {
127 .clkdm_name = "core_l4_clkdm",
128 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
129 },
130 {
131 .clkdm_name = "dsp_clkdm",
132 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
133 },
134 {
135 .clkdm_name = "wkup_clkdm",
136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
137 },
138 {
139 .clkdm_name = "mdm_clkdm",
140 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
141 },
142 { NULL },
143};
144
145/*
146 * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
147 * 2430 adds MDM
148 */
149static struct clkdm_dep core_24xx_wkdeps[] = {
150 {
151 .clkdm_name = "dsp_clkdm",
152 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
153 },
154 {
155 .clkdm_name = "gfx_clkdm",
156 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
157 },
158 {
159 .clkdm_name = "mpu_clkdm",
160 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
161 },
162 {
163 .clkdm_name = "wkup_clkdm",
164 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
165 },
166 {
167 .clkdm_name = "mdm_clkdm",
168 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
169 },
170 { NULL },
171};
172
173#endif /* CONFIG_ARCH_OMAP2 */
174
175/* 2430-specific possible wakeup dependencies */
176 57
177#ifdef CONFIG_SOC_OMAP2430 58/* 2xxx PM_WKDEP_GFX: CORE, MPU, WKUP */
178 59struct clkdm_dep gfx_24xx_wkdeps[] = {
179/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */ 60 { .clkdm_name = "core_l3_clkdm" },
180static struct clkdm_dep mdm_2430_wkdeps[] = { 61 { .clkdm_name = "core_l4_clkdm" },
181 { 62 { .clkdm_name = "mpu_clkdm" },
182 .clkdm_name = "core_l3_clkdm", 63 { .clkdm_name = "wkup_clkdm" },
183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
184 },
185 {
186 .clkdm_name = "core_l4_clkdm",
187 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
188 },
189 {
190 .clkdm_name = "mpu_clkdm",
191 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
192 },
193 {
194 .clkdm_name = "wkup_clkdm",
195 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
196 },
197 { NULL },
198};
199
200#endif /* CONFIG_SOC_OMAP2430 */
201
202
203/* OMAP3-specific possible dependencies */
204
205#ifdef CONFIG_ARCH_OMAP3
206
207/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
208static struct clkdm_dep per_wkdeps[] = {
209 {
210 .clkdm_name = "core_l3_clkdm",
211 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
212 },
213 {
214 .clkdm_name = "core_l4_clkdm",
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
216 },
217 {
218 .clkdm_name = "iva2_clkdm",
219 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
220 },
221 {
222 .clkdm_name = "mpu_clkdm",
223 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
224 },
225 {
226 .clkdm_name = "wkup_clkdm",
227 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
228 },
229 { NULL },
230};
231
232/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
233static struct clkdm_dep usbhost_wkdeps[] = {
234 {
235 .clkdm_name = "core_l3_clkdm",
236 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
237 },
238 {
239 .clkdm_name = "core_l4_clkdm",
240 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
241 },
242 {
243 .clkdm_name = "iva2_clkdm",
244 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
245 },
246 {
247 .clkdm_name = "mpu_clkdm",
248 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
249 },
250 {
251 .clkdm_name = "wkup_clkdm",
252 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
253 },
254 { NULL }, 64 { NULL },
255}; 65};
256 66
257/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */ 67/* 2xxx PM_WKDEP_DSP: CORE, MPU, WKUP */
258static struct clkdm_dep mpu_3xxx_wkdeps[] = { 68struct clkdm_dep dsp_24xx_wkdeps[] = {
259 { 69 { .clkdm_name = "core_l3_clkdm" },
260 .clkdm_name = "core_l3_clkdm", 70 { .clkdm_name = "core_l4_clkdm" },
261 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) 71 { .clkdm_name = "mpu_clkdm" },
262 }, 72 { .clkdm_name = "wkup_clkdm" },
263 {
264 .clkdm_name = "core_l4_clkdm",
265 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
266 },
267 {
268 .clkdm_name = "iva2_clkdm",
269 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
270 },
271 {
272 .clkdm_name = "dss_clkdm",
273 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
274 },
275 {
276 .clkdm_name = "per_clkdm",
277 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
278 },
279 { NULL }, 73 { NULL },
280}; 74};
281 75
282/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
283static struct clkdm_dep iva2_wkdeps[] = {
284 {
285 .clkdm_name = "core_l3_clkdm",
286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
287 },
288 {
289 .clkdm_name = "core_l4_clkdm",
290 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
291 },
292 {
293 .clkdm_name = "mpu_clkdm",
294 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
295 },
296 {
297 .clkdm_name = "wkup_clkdm",
298 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
299 },
300 {
301 .clkdm_name = "dss_clkdm",
302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
303 },
304 {
305 .clkdm_name = "per_clkdm",
306 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
307 },
308 { NULL },
309};
310
311
312/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
313static struct clkdm_dep cam_wkdeps[] = {
314 {
315 .clkdm_name = "iva2_clkdm",
316 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
317 },
318 {
319 .clkdm_name = "mpu_clkdm",
320 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
321 },
322 {
323 .clkdm_name = "wkup_clkdm",
324 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
325 },
326 { NULL },
327};
328
329/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
330static struct clkdm_dep dss_wkdeps[] = {
331 {
332 .clkdm_name = "iva2_clkdm",
333 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
334 },
335 {
336 .clkdm_name = "mpu_clkdm",
337 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
338 },
339 {
340 .clkdm_name = "wkup_clkdm",
341 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
342 },
343 { NULL },
344};
345
346/* 3430: PM_WKDEP_NEON: MPU */
347static struct clkdm_dep neon_wkdeps[] = {
348 {
349 .clkdm_name = "mpu_clkdm",
350 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
351 },
352 { NULL },
353};
354
355
356/* Sleep dependency source arrays for OMAP3-specific clkdms */
357
358/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
359static struct clkdm_dep dss_sleepdeps[] = {
360 {
361 .clkdm_name = "mpu_clkdm",
362 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
363 },
364 {
365 .clkdm_name = "iva2_clkdm",
366 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
367 },
368 { NULL },
369};
370
371/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
372static struct clkdm_dep per_sleepdeps[] = {
373 {
374 .clkdm_name = "mpu_clkdm",
375 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
376 },
377 {
378 .clkdm_name = "iva2_clkdm",
379 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
380 },
381 { NULL },
382};
383
384/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
385static struct clkdm_dep usbhost_sleepdeps[] = {
386 {
387 .clkdm_name = "mpu_clkdm",
388 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
389 },
390 {
391 .clkdm_name = "iva2_clkdm",
392 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
393 },
394 { NULL },
395};
396
397/* 3430: CM_SLEEPDEP_CAM: MPU */
398static struct clkdm_dep cam_sleepdeps[] = {
399 {
400 .clkdm_name = "mpu_clkdm",
401 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
402 },
403 { NULL },
404};
405
406/*
407 * 3430ES1: CM_SLEEPDEP_GFX: MPU
408 * 3430ES2: CM_SLEEPDEP_SGX: MPU
409 * These can share data since they will never be present simultaneously
410 * on the same device.
411 */
412static struct clkdm_dep gfx_sgx_sleepdeps[] = {
413 {
414 .clkdm_name = "mpu_clkdm",
415 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
416 },
417 { NULL },
418};
419
420#endif /* CONFIG_ARCH_OMAP3 */
421
422 76
423/* 77/*
424 * OMAP2/3-common clockdomains 78 * OMAP2/3-common clockdomains
@@ -430,448 +84,18 @@ static struct clkdm_dep gfx_sgx_sleepdeps[] = {
430 */ 84 */
431 85
432/* This is an implicit clockdomain - it is never defined as such in TRM */ 86/* This is an implicit clockdomain - it is never defined as such in TRM */
433static struct clockdomain wkup_clkdm = { 87struct clockdomain wkup_common_clkdm = {
434 .name = "wkup_clkdm", 88 .name = "wkup_clkdm",
435 .pwrdm = { .name = "wkup_pwrdm" }, 89 .pwrdm = { .name = "wkup_pwrdm" },
436 .dep_bit = OMAP_EN_WKUP_SHIFT, 90 .dep_bit = OMAP_EN_WKUP_SHIFT,
437 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
438}; 91};
439 92
440static struct clockdomain prm_clkdm = { 93struct clockdomain prm_common_clkdm = {
441 .name = "prm_clkdm", 94 .name = "prm_clkdm",
442 .pwrdm = { .name = "wkup_pwrdm" }, 95 .pwrdm = { .name = "wkup_pwrdm" },
443 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
444}; 96};
445 97
446static struct clockdomain cm_clkdm = { 98struct clockdomain cm_common_clkdm = {
447 .name = "cm_clkdm", 99 .name = "cm_clkdm",
448 .pwrdm = { .name = "core_pwrdm" }, 100 .pwrdm = { .name = "core_pwrdm" },
449 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
450};
451
452/*
453 * 2420-only clockdomains
454 */
455
456#if defined(CONFIG_SOC_OMAP2420)
457
458static struct clockdomain mpu_2420_clkdm = {
459 .name = "mpu_clkdm",
460 .pwrdm = { .name = "mpu_pwrdm" },
461 .flags = CLKDM_CAN_HWSUP,
462 .wkdep_srcs = mpu_24xx_wkdeps,
463 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
464 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
465};
466
467static struct clockdomain iva1_2420_clkdm = {
468 .name = "iva1_clkdm",
469 .pwrdm = { .name = "dsp_pwrdm" },
470 .flags = CLKDM_CAN_HWSUP_SWSUP,
471 .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
472 .wkdep_srcs = dsp_24xx_wkdeps,
473 .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
474 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
475};
476
477static struct clockdomain dsp_2420_clkdm = {
478 .name = "dsp_clkdm",
479 .pwrdm = { .name = "dsp_pwrdm" },
480 .flags = CLKDM_CAN_HWSUP_SWSUP,
481 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
482 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
483};
484
485static struct clockdomain gfx_2420_clkdm = {
486 .name = "gfx_clkdm",
487 .pwrdm = { .name = "gfx_pwrdm" },
488 .flags = CLKDM_CAN_HWSUP_SWSUP,
489 .wkdep_srcs = gfx_sgx_wkdeps,
490 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
491 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
492};
493
494static struct clockdomain core_l3_2420_clkdm = {
495 .name = "core_l3_clkdm",
496 .pwrdm = { .name = "core_pwrdm" },
497 .flags = CLKDM_CAN_HWSUP,
498 .wkdep_srcs = core_24xx_wkdeps,
499 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
500 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
501};
502
503static struct clockdomain core_l4_2420_clkdm = {
504 .name = "core_l4_clkdm",
505 .pwrdm = { .name = "core_pwrdm" },
506 .flags = CLKDM_CAN_HWSUP,
507 .wkdep_srcs = core_24xx_wkdeps,
508 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
510};
511
512static struct clockdomain dss_2420_clkdm = {
513 .name = "dss_clkdm",
514 .pwrdm = { .name = "core_pwrdm" },
515 .flags = CLKDM_CAN_HWSUP,
516 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
517 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
518};
519
520#endif /* CONFIG_SOC_OMAP2420 */
521
522
523/*
524 * 2430-only clockdomains
525 */
526
527#if defined(CONFIG_SOC_OMAP2430)
528
529static struct clockdomain mpu_2430_clkdm = {
530 .name = "mpu_clkdm",
531 .pwrdm = { .name = "mpu_pwrdm" },
532 .flags = CLKDM_CAN_HWSUP_SWSUP,
533 .wkdep_srcs = mpu_24xx_wkdeps,
534 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
535 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
536};
537
538/* Another case of bit name collisions between several registers: EN_MDM */
539static struct clockdomain mdm_clkdm = {
540 .name = "mdm_clkdm",
541 .pwrdm = { .name = "mdm_pwrdm" },
542 .flags = CLKDM_CAN_HWSUP_SWSUP,
543 .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
544 .wkdep_srcs = mdm_2430_wkdeps,
545 .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
546 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
547};
548
549static struct clockdomain dsp_2430_clkdm = {
550 .name = "dsp_clkdm",
551 .pwrdm = { .name = "dsp_pwrdm" },
552 .flags = CLKDM_CAN_HWSUP_SWSUP,
553 .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
554 .wkdep_srcs = dsp_24xx_wkdeps,
555 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
556 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
557};
558
559static struct clockdomain gfx_2430_clkdm = {
560 .name = "gfx_clkdm",
561 .pwrdm = { .name = "gfx_pwrdm" },
562 .flags = CLKDM_CAN_HWSUP_SWSUP,
563 .wkdep_srcs = gfx_sgx_wkdeps,
564 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
565 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
566};
567
568/*
569 * XXX add usecounting for clkdm dependencies, otherwise the presence
570 * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
571 * could cause trouble
572 */
573static struct clockdomain core_l3_2430_clkdm = {
574 .name = "core_l3_clkdm",
575 .pwrdm = { .name = "core_pwrdm" },
576 .flags = CLKDM_CAN_HWSUP,
577 .dep_bit = OMAP24XX_EN_CORE_SHIFT,
578 .wkdep_srcs = core_24xx_wkdeps,
579 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
580 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
581};
582
583/*
584 * XXX add usecounting for clkdm dependencies, otherwise the presence
585 * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
586 * could cause trouble
587 */
588static struct clockdomain core_l4_2430_clkdm = {
589 .name = "core_l4_clkdm",
590 .pwrdm = { .name = "core_pwrdm" },
591 .flags = CLKDM_CAN_HWSUP,
592 .dep_bit = OMAP24XX_EN_CORE_SHIFT,
593 .wkdep_srcs = core_24xx_wkdeps,
594 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
595 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
596};
597
598static struct clockdomain dss_2430_clkdm = {
599 .name = "dss_clkdm",
600 .pwrdm = { .name = "core_pwrdm" },
601 .flags = CLKDM_CAN_HWSUP,
602 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
603 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
604};
605
606#endif /* CONFIG_SOC_OMAP2430 */
607
608
609/*
610 * OMAP3 clockdomains
611 */
612
613#if defined(CONFIG_ARCH_OMAP3)
614
615static struct clockdomain mpu_3xxx_clkdm = {
616 .name = "mpu_clkdm",
617 .pwrdm = { .name = "mpu_pwrdm" },
618 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
619 .dep_bit = OMAP3430_EN_MPU_SHIFT,
620 .wkdep_srcs = mpu_3xxx_wkdeps,
621 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
622 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
623}; 101};
624
625static struct clockdomain neon_clkdm = {
626 .name = "neon_clkdm",
627 .pwrdm = { .name = "neon_pwrdm" },
628 .flags = CLKDM_CAN_HWSUP_SWSUP,
629 .wkdep_srcs = neon_wkdeps,
630 .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
631 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
632};
633
634static struct clockdomain iva2_clkdm = {
635 .name = "iva2_clkdm",
636 .pwrdm = { .name = "iva2_pwrdm" },
637 .flags = CLKDM_CAN_HWSUP_SWSUP,
638 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
639 .wkdep_srcs = iva2_wkdeps,
640 .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
641 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
642};
643
644static struct clockdomain gfx_3430es1_clkdm = {
645 .name = "gfx_clkdm",
646 .pwrdm = { .name = "gfx_pwrdm" },
647 .flags = CLKDM_CAN_HWSUP_SWSUP,
648 .wkdep_srcs = gfx_sgx_wkdeps,
649 .sleepdep_srcs = gfx_sgx_sleepdeps,
650 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
651 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
652};
653
654static struct clockdomain sgx_clkdm = {
655 .name = "sgx_clkdm",
656 .pwrdm = { .name = "sgx_pwrdm" },
657 .flags = CLKDM_CAN_HWSUP_SWSUP,
658 .wkdep_srcs = gfx_sgx_wkdeps,
659 .sleepdep_srcs = gfx_sgx_sleepdeps,
660 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
661 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
662};
663
664/*
665 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
666 * then that information was removed from the 34xx ES2+ TRM. It is
667 * unclear whether the core is still there, but the clockdomain logic
668 * is there, and must be programmed to an appropriate state if the
669 * CORE clockdomain is to become inactive.
670 */
671static struct clockdomain d2d_clkdm = {
672 .name = "d2d_clkdm",
673 .pwrdm = { .name = "core_pwrdm" },
674 .flags = CLKDM_CAN_HWSUP_SWSUP,
675 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
676 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
677};
678
679/*
680 * XXX add usecounting for clkdm dependencies, otherwise the presence
681 * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
682 * could cause trouble
683 */
684static struct clockdomain core_l3_3xxx_clkdm = {
685 .name = "core_l3_clkdm",
686 .pwrdm = { .name = "core_pwrdm" },
687 .flags = CLKDM_CAN_HWSUP,
688 .dep_bit = OMAP3430_EN_CORE_SHIFT,
689 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
690 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
691};
692
693/*
694 * XXX add usecounting for clkdm dependencies, otherwise the presence
695 * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
696 * could cause trouble
697 */
698static struct clockdomain core_l4_3xxx_clkdm = {
699 .name = "core_l4_clkdm",
700 .pwrdm = { .name = "core_pwrdm" },
701 .flags = CLKDM_CAN_HWSUP,
702 .dep_bit = OMAP3430_EN_CORE_SHIFT,
703 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
704 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
705};
706
707/* Another case of bit name collisions between several registers: EN_DSS */
708static struct clockdomain dss_3xxx_clkdm = {
709 .name = "dss_clkdm",
710 .pwrdm = { .name = "dss_pwrdm" },
711 .flags = CLKDM_CAN_HWSUP_SWSUP,
712 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
713 .wkdep_srcs = dss_wkdeps,
714 .sleepdep_srcs = dss_sleepdeps,
715 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
716 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
717};
718
719static struct clockdomain cam_clkdm = {
720 .name = "cam_clkdm",
721 .pwrdm = { .name = "cam_pwrdm" },
722 .flags = CLKDM_CAN_HWSUP_SWSUP,
723 .wkdep_srcs = cam_wkdeps,
724 .sleepdep_srcs = cam_sleepdeps,
725 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
726 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
727};
728
729static struct clockdomain usbhost_clkdm = {
730 .name = "usbhost_clkdm",
731 .pwrdm = { .name = "usbhost_pwrdm" },
732 .flags = CLKDM_CAN_HWSUP_SWSUP,
733 .wkdep_srcs = usbhost_wkdeps,
734 .sleepdep_srcs = usbhost_sleepdeps,
735 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
736 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
737};
738
739static struct clockdomain per_clkdm = {
740 .name = "per_clkdm",
741 .pwrdm = { .name = "per_pwrdm" },
742 .flags = CLKDM_CAN_HWSUP_SWSUP,
743 .dep_bit = OMAP3430_EN_PER_SHIFT,
744 .wkdep_srcs = per_wkdeps,
745 .sleepdep_srcs = per_sleepdeps,
746 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
747 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
748};
749
750/*
751 * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
752 * switched of even if sdti is in use
753 */
754static struct clockdomain emu_clkdm = {
755 .name = "emu_clkdm",
756 .pwrdm = { .name = "emu_pwrdm" },
757 .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
758 .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
759 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
760};
761
762static struct clockdomain dpll1_clkdm = {
763 .name = "dpll1_clkdm",
764 .pwrdm = { .name = "dpll1_pwrdm" },
765 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
766};
767
768static struct clockdomain dpll2_clkdm = {
769 .name = "dpll2_clkdm",
770 .pwrdm = { .name = "dpll2_pwrdm" },
771 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
772};
773
774static struct clockdomain dpll3_clkdm = {
775 .name = "dpll3_clkdm",
776 .pwrdm = { .name = "dpll3_pwrdm" },
777 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
778};
779
780static struct clockdomain dpll4_clkdm = {
781 .name = "dpll4_clkdm",
782 .pwrdm = { .name = "dpll4_pwrdm" },
783 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
784};
785
786static struct clockdomain dpll5_clkdm = {
787 .name = "dpll5_clkdm",
788 .pwrdm = { .name = "dpll5_pwrdm" },
789 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
790};
791
792#endif /* CONFIG_ARCH_OMAP3 */
793
794/*
795 * Clockdomain hwsup dependencies (OMAP3 only)
796 */
797
798static struct clkdm_autodep clkdm_autodeps[] = {
799 {
800 .clkdm = { .name = "mpu_clkdm" },
801 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
802 },
803 {
804 .clkdm = { .name = "iva2_clkdm" },
805 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
806 },
807 {
808 .clkdm = { .name = NULL },
809 }
810};
811
812static struct clockdomain *clockdomains_omap2[] __initdata = {
813 &wkup_clkdm,
814 &cm_clkdm,
815 &prm_clkdm,
816
817#ifdef CONFIG_SOC_OMAP2420
818 &mpu_2420_clkdm,
819 &iva1_2420_clkdm,
820 &dsp_2420_clkdm,
821 &gfx_2420_clkdm,
822 &core_l3_2420_clkdm,
823 &core_l4_2420_clkdm,
824 &dss_2420_clkdm,
825#endif
826
827#ifdef CONFIG_SOC_OMAP2430
828 &mpu_2430_clkdm,
829 &mdm_clkdm,
830 &dsp_2430_clkdm,
831 &gfx_2430_clkdm,
832 &core_l3_2430_clkdm,
833 &core_l4_2430_clkdm,
834 &dss_2430_clkdm,
835#endif
836
837#ifdef CONFIG_ARCH_OMAP3
838 &mpu_3xxx_clkdm,
839 &neon_clkdm,
840 &iva2_clkdm,
841 &gfx_3430es1_clkdm,
842 &sgx_clkdm,
843 &d2d_clkdm,
844 &core_l3_3xxx_clkdm,
845 &core_l4_3xxx_clkdm,
846 &dss_3xxx_clkdm,
847 &cam_clkdm,
848 &usbhost_clkdm,
849 &per_clkdm,
850 &emu_clkdm,
851 &dpll1_clkdm,
852 &dpll2_clkdm,
853 &dpll3_clkdm,
854 &dpll4_clkdm,
855 &dpll5_clkdm,
856#endif
857 NULL,
858};
859
860static void __init omap2_3_clockdomains_init(void)
861{
862 clkdm_register_clkdms(clockdomains_omap2);
863 clkdm_register_autodeps(clkdm_autodeps);
864 clkdm_complete_init();
865}
866
867void __init omap2xxx_clockdomains_init(void)
868{
869 clkdm_register_platform_funcs(&omap2_clkdm_operations);
870 omap2_3_clockdomains_init();
871}
872
873void __init omap3xxx_clockdomains_init(void)
874{
875 clkdm_register_platform_funcs(&omap3_clkdm_operations);
876 omap2_3_clockdomains_init();
877}
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
new file mode 100644
index 000000000000..b84e138d99c8
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -0,0 +1,398 @@
1/*
2 * OMAP3xxx clockdomains
3 *
4 * Copyright (C) 2008-2011 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Paul Walmsley, Jouni Högander
8 *
9 * This file contains clockdomains and clockdomain wakeup/sleep
10 * dependencies for the OMAP3xxx chips. Some notes:
11 *
12 * A useful validation rule for struct clockdomain: Any clockdomain
13 * referenced by a wkdep_srcs or sleepdep_srcs array must have a
14 * dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just
15 * software-controllable dependencies. Non-software-controllable
16 * dependencies do exist, but they are not encoded below (yet).
17 *
18 * The overly-specific dep_bit names are due to a bit name collision
19 * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
20 * value are the same for all powerdomains: 2
21 *
22 * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
23 * sanity check?
24 * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
25 */
26
27/*
28 * To-Do List
29 * -> Port the Sleep/Wakeup dependencies for the domains
30 * from the Power domain framework
31 */
32
33#include <linux/kernel.h>
34#include <linux/io.h>
35
36#include "clockdomain.h"
37#include "prm2xxx_3xxx.h"
38#include "cm2xxx_3xxx.h"
39#include "cm-regbits-34xx.h"
40#include "prm-regbits-34xx.h"
41
42/*
43 * Clockdomain dependencies for wkdeps/sleepdeps
44 *
45 * XXX Hardware dependencies (e.g., dependencies that cannot be
46 * changed in software) are not included here yet, but should be.
47 */
48
49/* OMAP3-specific possible dependencies */
50
51/*
52 * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
53 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
54 */
55static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
56 { .clkdm_name = "iva2_clkdm", },
57 { .clkdm_name = "mpu_clkdm", },
58 { .clkdm_name = "wkup_clkdm", },
59 { NULL },
60};
61
62/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
63static struct clkdm_dep per_wkdeps[] = {
64 { .clkdm_name = "core_l3_clkdm" },
65 { .clkdm_name = "core_l4_clkdm" },
66 { .clkdm_name = "iva2_clkdm" },
67 { .clkdm_name = "mpu_clkdm" },
68 { .clkdm_name = "wkup_clkdm" },
69 { NULL },
70};
71
72/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
73static struct clkdm_dep usbhost_wkdeps[] = {
74 { .clkdm_name = "core_l3_clkdm" },
75 { .clkdm_name = "core_l4_clkdm" },
76 { .clkdm_name = "iva2_clkdm" },
77 { .clkdm_name = "mpu_clkdm" },
78 { .clkdm_name = "wkup_clkdm" },
79 { NULL },
80};
81
82/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
83static struct clkdm_dep mpu_3xxx_wkdeps[] = {
84 { .clkdm_name = "core_l3_clkdm" },
85 { .clkdm_name = "core_l4_clkdm" },
86 { .clkdm_name = "iva2_clkdm" },
87 { .clkdm_name = "dss_clkdm" },
88 { .clkdm_name = "per_clkdm" },
89 { NULL },
90};
91
92/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
93static struct clkdm_dep iva2_wkdeps[] = {
94 { .clkdm_name = "core_l3_clkdm" },
95 { .clkdm_name = "core_l4_clkdm" },
96 { .clkdm_name = "mpu_clkdm" },
97 { .clkdm_name = "wkup_clkdm" },
98 { .clkdm_name = "dss_clkdm" },
99 { .clkdm_name = "per_clkdm" },
100 { NULL },
101};
102
103/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
104static struct clkdm_dep cam_wkdeps[] = {
105 { .clkdm_name = "iva2_clkdm" },
106 { .clkdm_name = "mpu_clkdm" },
107 { .clkdm_name = "wkup_clkdm" },
108 { NULL },
109};
110
111/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
112static struct clkdm_dep dss_wkdeps[] = {
113 { .clkdm_name = "iva2_clkdm" },
114 { .clkdm_name = "mpu_clkdm" },
115 { .clkdm_name = "wkup_clkdm" },
116 { NULL },
117};
118
119/* 3430: PM_WKDEP_NEON: MPU */
120static struct clkdm_dep neon_wkdeps[] = {
121 { .clkdm_name = "mpu_clkdm" },
122 { NULL },
123};
124
125/* Sleep dependency source arrays for OMAP3-specific clkdms */
126
127/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
128static struct clkdm_dep dss_sleepdeps[] = {
129 { .clkdm_name = "mpu_clkdm" },
130 { .clkdm_name = "iva2_clkdm" },
131 { NULL },
132};
133
134/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
135static struct clkdm_dep per_sleepdeps[] = {
136 { .clkdm_name = "mpu_clkdm" },
137 { .clkdm_name = "iva2_clkdm" },
138 { NULL },
139};
140
141/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
142static struct clkdm_dep usbhost_sleepdeps[] = {
143 { .clkdm_name = "mpu_clkdm" },
144 { .clkdm_name = "iva2_clkdm" },
145 { NULL },
146};
147
148/* 3430: CM_SLEEPDEP_CAM: MPU */
149static struct clkdm_dep cam_sleepdeps[] = {
150 { .clkdm_name = "mpu_clkdm" },
151 { NULL },
152};
153
154/*
155 * 3430ES1: CM_SLEEPDEP_GFX: MPU
156 * 3430ES2: CM_SLEEPDEP_SGX: MPU
157 * These can share data since they will never be present simultaneously
158 * on the same device.
159 */
160static struct clkdm_dep gfx_sgx_sleepdeps[] = {
161 { .clkdm_name = "mpu_clkdm" },
162 { NULL },
163};
164
165/*
166 * OMAP3 clockdomains
167 */
168
169static struct clockdomain mpu_3xxx_clkdm = {
170 .name = "mpu_clkdm",
171 .pwrdm = { .name = "mpu_pwrdm" },
172 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
173 .dep_bit = OMAP3430_EN_MPU_SHIFT,
174 .wkdep_srcs = mpu_3xxx_wkdeps,
175 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
176};
177
178static struct clockdomain neon_clkdm = {
179 .name = "neon_clkdm",
180 .pwrdm = { .name = "neon_pwrdm" },
181 .flags = CLKDM_CAN_HWSUP_SWSUP,
182 .wkdep_srcs = neon_wkdeps,
183 .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
184};
185
186static struct clockdomain iva2_clkdm = {
187 .name = "iva2_clkdm",
188 .pwrdm = { .name = "iva2_pwrdm" },
189 .flags = CLKDM_CAN_HWSUP_SWSUP,
190 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
191 .wkdep_srcs = iva2_wkdeps,
192 .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
193};
194
195static struct clockdomain gfx_3430es1_clkdm = {
196 .name = "gfx_clkdm",
197 .pwrdm = { .name = "gfx_pwrdm" },
198 .flags = CLKDM_CAN_HWSUP_SWSUP,
199 .wkdep_srcs = gfx_sgx_3xxx_wkdeps,
200 .sleepdep_srcs = gfx_sgx_sleepdeps,
201 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
202};
203
204static struct clockdomain sgx_clkdm = {
205 .name = "sgx_clkdm",
206 .pwrdm = { .name = "sgx_pwrdm" },
207 .flags = CLKDM_CAN_HWSUP_SWSUP,
208 .wkdep_srcs = gfx_sgx_3xxx_wkdeps,
209 .sleepdep_srcs = gfx_sgx_sleepdeps,
210 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
211};
212
213/*
214 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
215 * then that information was removed from the 34xx ES2+ TRM. It is
216 * unclear whether the core is still there, but the clockdomain logic
217 * is there, and must be programmed to an appropriate state if the
218 * CORE clockdomain is to become inactive.
219 */
220static struct clockdomain d2d_clkdm = {
221 .name = "d2d_clkdm",
222 .pwrdm = { .name = "core_pwrdm" },
223 .flags = CLKDM_CAN_HWSUP_SWSUP,
224 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
225};
226
227/*
228 * XXX add usecounting for clkdm dependencies, otherwise the presence
229 * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
230 * could cause trouble
231 */
232static struct clockdomain core_l3_3xxx_clkdm = {
233 .name = "core_l3_clkdm",
234 .pwrdm = { .name = "core_pwrdm" },
235 .flags = CLKDM_CAN_HWSUP,
236 .dep_bit = OMAP3430_EN_CORE_SHIFT,
237 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
238};
239
240/*
241 * XXX add usecounting for clkdm dependencies, otherwise the presence
242 * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
243 * could cause trouble
244 */
245static struct clockdomain core_l4_3xxx_clkdm = {
246 .name = "core_l4_clkdm",
247 .pwrdm = { .name = "core_pwrdm" },
248 .flags = CLKDM_CAN_HWSUP,
249 .dep_bit = OMAP3430_EN_CORE_SHIFT,
250 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
251};
252
253/* Another case of bit name collisions between several registers: EN_DSS */
254static struct clockdomain dss_3xxx_clkdm = {
255 .name = "dss_clkdm",
256 .pwrdm = { .name = "dss_pwrdm" },
257 .flags = CLKDM_CAN_HWSUP_SWSUP,
258 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
259 .wkdep_srcs = dss_wkdeps,
260 .sleepdep_srcs = dss_sleepdeps,
261 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
262};
263
264static struct clockdomain cam_clkdm = {
265 .name = "cam_clkdm",
266 .pwrdm = { .name = "cam_pwrdm" },
267 .flags = CLKDM_CAN_HWSUP_SWSUP,
268 .wkdep_srcs = cam_wkdeps,
269 .sleepdep_srcs = cam_sleepdeps,
270 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
271};
272
273static struct clockdomain usbhost_clkdm = {
274 .name = "usbhost_clkdm",
275 .pwrdm = { .name = "usbhost_pwrdm" },
276 .flags = CLKDM_CAN_HWSUP_SWSUP,
277 .wkdep_srcs = usbhost_wkdeps,
278 .sleepdep_srcs = usbhost_sleepdeps,
279 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
280};
281
282static struct clockdomain per_clkdm = {
283 .name = "per_clkdm",
284 .pwrdm = { .name = "per_pwrdm" },
285 .flags = CLKDM_CAN_HWSUP_SWSUP,
286 .dep_bit = OMAP3430_EN_PER_SHIFT,
287 .wkdep_srcs = per_wkdeps,
288 .sleepdep_srcs = per_sleepdeps,
289 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
290};
291
292/*
293 * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
294 * switched of even if sdti is in use
295 */
296static struct clockdomain emu_clkdm = {
297 .name = "emu_clkdm",
298 .pwrdm = { .name = "emu_pwrdm" },
299 .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
300 .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
301};
302
303static struct clockdomain dpll1_clkdm = {
304 .name = "dpll1_clkdm",
305 .pwrdm = { .name = "dpll1_pwrdm" },
306};
307
308static struct clockdomain dpll2_clkdm = {
309 .name = "dpll2_clkdm",
310 .pwrdm = { .name = "dpll2_pwrdm" },
311};
312
313static struct clockdomain dpll3_clkdm = {
314 .name = "dpll3_clkdm",
315 .pwrdm = { .name = "dpll3_pwrdm" },
316};
317
318static struct clockdomain dpll4_clkdm = {
319 .name = "dpll4_clkdm",
320 .pwrdm = { .name = "dpll4_pwrdm" },
321};
322
323static struct clockdomain dpll5_clkdm = {
324 .name = "dpll5_clkdm",
325 .pwrdm = { .name = "dpll5_pwrdm" },
326};
327
328/*
329 * Clockdomain hwsup dependencies
330 */
331
332static struct clkdm_autodep clkdm_autodeps[] = {
333 {
334 .clkdm = { .name = "mpu_clkdm" },
335 },
336 {
337 .clkdm = { .name = "iva2_clkdm" },
338 },
339 {
340 .clkdm = { .name = NULL },
341 }
342};
343
344/*
345 *
346 */
347
348static struct clockdomain *clockdomains_omap3430_common[] __initdata = {
349 &wkup_common_clkdm,
350 &cm_common_clkdm,
351 &prm_common_clkdm,
352 &mpu_3xxx_clkdm,
353 &neon_clkdm,
354 &iva2_clkdm,
355 &d2d_clkdm,
356 &core_l3_3xxx_clkdm,
357 &core_l4_3xxx_clkdm,
358 &dss_3xxx_clkdm,
359 &cam_clkdm,
360 &per_clkdm,
361 &emu_clkdm,
362 &dpll1_clkdm,
363 &dpll2_clkdm,
364 &dpll3_clkdm,
365 &dpll4_clkdm,
366 NULL
367};
368
369static struct clockdomain *clockdomains_omap3430es1[] __initdata = {
370 &gfx_3430es1_clkdm,
371 NULL,
372};
373
374static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
375 &sgx_clkdm,
376 &dpll5_clkdm,
377 &usbhost_clkdm,
378 NULL,
379};
380
381void __init omap3xxx_clockdomains_init(void)
382{
383 struct clockdomain **sc;
384
385 if (!cpu_is_omap34xx())
386 return;
387
388 clkdm_register_platform_funcs(&omap3_clkdm_operations);
389 clkdm_register_clkdms(clockdomains_omap3430_common);
390
391 sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 :
392 clockdomains_omap3430es2plus;
393
394 clkdm_register_clkdms(sc);
395
396 clkdm_register_autodeps(clkdm_autodeps);
397 clkdm_complete_init();
398}
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index c75411a62207..9299ac291d28 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -34,350 +34,122 @@
34/* Static Dependencies for OMAP4 Clock Domains */ 34/* Static Dependencies for OMAP4 Clock Domains */
35 35
36static struct clkdm_dep d2d_wkup_sleep_deps[] = { 36static struct clkdm_dep d2d_wkup_sleep_deps[] = {
37 { 37 { .clkdm_name = "abe_clkdm" },
38 .clkdm_name = "abe_clkdm", 38 { .clkdm_name = "ivahd_clkdm" },
39 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 39 { .clkdm_name = "l3_1_clkdm" },
40 }, 40 { .clkdm_name = "l3_2_clkdm" },
41 { 41 { .clkdm_name = "l3_emif_clkdm" },
42 .clkdm_name = "ivahd_clkdm", 42 { .clkdm_name = "l3_init_clkdm" },
43 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 43 { .clkdm_name = "l4_cfg_clkdm" },
44 }, 44 { .clkdm_name = "l4_per_clkdm" },
45 {
46 .clkdm_name = "l3_1_clkdm",
47 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
48 },
49 {
50 .clkdm_name = "l3_2_clkdm",
51 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
52 },
53 {
54 .clkdm_name = "l3_emif_clkdm",
55 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
56 },
57 {
58 .clkdm_name = "l3_init_clkdm",
59 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
60 },
61 {
62 .clkdm_name = "l4_cfg_clkdm",
63 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
64 },
65 {
66 .clkdm_name = "l4_per_clkdm",
67 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
68 },
69 { NULL }, 45 { NULL },
70}; 46};
71 47
72static struct clkdm_dep ducati_wkup_sleep_deps[] = { 48static struct clkdm_dep ducati_wkup_sleep_deps[] = {
73 { 49 { .clkdm_name = "abe_clkdm" },
74 .clkdm_name = "abe_clkdm", 50 { .clkdm_name = "ivahd_clkdm" },
75 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 51 { .clkdm_name = "l3_1_clkdm" },
76 }, 52 { .clkdm_name = "l3_2_clkdm" },
77 { 53 { .clkdm_name = "l3_dss_clkdm" },
78 .clkdm_name = "ivahd_clkdm", 54 { .clkdm_name = "l3_emif_clkdm" },
79 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 55 { .clkdm_name = "l3_gfx_clkdm" },
80 }, 56 { .clkdm_name = "l3_init_clkdm" },
81 { 57 { .clkdm_name = "l4_cfg_clkdm" },
82 .clkdm_name = "l3_1_clkdm", 58 { .clkdm_name = "l4_per_clkdm" },
83 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 59 { .clkdm_name = "l4_secure_clkdm" },
84 }, 60 { .clkdm_name = "l4_wkup_clkdm" },
85 { 61 { .clkdm_name = "tesla_clkdm" },
86 .clkdm_name = "l3_2_clkdm",
87 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
88 },
89 {
90 .clkdm_name = "l3_dss_clkdm",
91 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
92 },
93 {
94 .clkdm_name = "l3_emif_clkdm",
95 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
96 },
97 {
98 .clkdm_name = "l3_gfx_clkdm",
99 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
100 },
101 {
102 .clkdm_name = "l3_init_clkdm",
103 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
104 },
105 {
106 .clkdm_name = "l4_cfg_clkdm",
107 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
108 },
109 {
110 .clkdm_name = "l4_per_clkdm",
111 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
112 },
113 {
114 .clkdm_name = "l4_secure_clkdm",
115 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
116 },
117 {
118 .clkdm_name = "l4_wkup_clkdm",
119 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
120 },
121 {
122 .clkdm_name = "tesla_clkdm",
123 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
124 },
125 { NULL }, 62 { NULL },
126}; 63};
127 64
128static struct clkdm_dep iss_wkup_sleep_deps[] = { 65static struct clkdm_dep iss_wkup_sleep_deps[] = {
129 { 66 { .clkdm_name = "ivahd_clkdm" },
130 .clkdm_name = "ivahd_clkdm", 67 { .clkdm_name = "l3_1_clkdm" },
131 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 68 { .clkdm_name = "l3_emif_clkdm" },
132 },
133 {
134 .clkdm_name = "l3_1_clkdm",
135 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
136 },
137 {
138 .clkdm_name = "l3_emif_clkdm",
139 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
140 },
141 { NULL }, 69 { NULL },
142}; 70};
143 71
144static struct clkdm_dep ivahd_wkup_sleep_deps[] = { 72static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
145 { 73 { .clkdm_name = "l3_1_clkdm" },
146 .clkdm_name = "l3_1_clkdm", 74 { .clkdm_name = "l3_emif_clkdm" },
147 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
148 },
149 {
150 .clkdm_name = "l3_emif_clkdm",
151 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
152 },
153 { NULL }, 75 { NULL },
154}; 76};
155 77
156static struct clkdm_dep l3_dma_wkup_sleep_deps[] = { 78static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
157 { 79 { .clkdm_name = "abe_clkdm" },
158 .clkdm_name = "abe_clkdm", 80 { .clkdm_name = "ducati_clkdm" },
159 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 81 { .clkdm_name = "ivahd_clkdm" },
160 }, 82 { .clkdm_name = "l3_1_clkdm" },
161 { 83 { .clkdm_name = "l3_dss_clkdm" },
162 .clkdm_name = "ducati_clkdm", 84 { .clkdm_name = "l3_emif_clkdm" },
163 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 85 { .clkdm_name = "l3_init_clkdm" },
164 }, 86 { .clkdm_name = "l4_cfg_clkdm" },
165 { 87 { .clkdm_name = "l4_per_clkdm" },
166 .clkdm_name = "ivahd_clkdm", 88 { .clkdm_name = "l4_secure_clkdm" },
167 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 89 { .clkdm_name = "l4_wkup_clkdm" },
168 },
169 {
170 .clkdm_name = "l3_1_clkdm",
171 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
172 },
173 {
174 .clkdm_name = "l3_dss_clkdm",
175 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
176 },
177 {
178 .clkdm_name = "l3_emif_clkdm",
179 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
180 },
181 {
182 .clkdm_name = "l3_init_clkdm",
183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
184 },
185 {
186 .clkdm_name = "l4_cfg_clkdm",
187 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
188 },
189 {
190 .clkdm_name = "l4_per_clkdm",
191 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
192 },
193 {
194 .clkdm_name = "l4_secure_clkdm",
195 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
196 },
197 {
198 .clkdm_name = "l4_wkup_clkdm",
199 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
200 },
201 { NULL }, 90 { NULL },
202}; 91};
203 92
204static struct clkdm_dep l3_dss_wkup_sleep_deps[] = { 93static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
205 { 94 { .clkdm_name = "ivahd_clkdm" },
206 .clkdm_name = "ivahd_clkdm", 95 { .clkdm_name = "l3_2_clkdm" },
207 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 96 { .clkdm_name = "l3_emif_clkdm" },
208 },
209 {
210 .clkdm_name = "l3_2_clkdm",
211 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
212 },
213 {
214 .clkdm_name = "l3_emif_clkdm",
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
216 },
217 { NULL }, 97 { NULL },
218}; 98};
219 99
220static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = { 100static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
221 { 101 { .clkdm_name = "ivahd_clkdm" },
222 .clkdm_name = "ivahd_clkdm", 102 { .clkdm_name = "l3_1_clkdm" },
223 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 103 { .clkdm_name = "l3_emif_clkdm" },
224 },
225 {
226 .clkdm_name = "l3_1_clkdm",
227 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
228 },
229 {
230 .clkdm_name = "l3_emif_clkdm",
231 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
232 },
233 { NULL }, 104 { NULL },
234}; 105};
235 106
236static struct clkdm_dep l3_init_wkup_sleep_deps[] = { 107static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
237 { 108 { .clkdm_name = "abe_clkdm" },
238 .clkdm_name = "abe_clkdm", 109 { .clkdm_name = "ivahd_clkdm" },
239 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 110 { .clkdm_name = "l3_emif_clkdm" },
240 }, 111 { .clkdm_name = "l4_cfg_clkdm" },
241 { 112 { .clkdm_name = "l4_per_clkdm" },
242 .clkdm_name = "ivahd_clkdm", 113 { .clkdm_name = "l4_secure_clkdm" },
243 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 114 { .clkdm_name = "l4_wkup_clkdm" },
244 },
245 {
246 .clkdm_name = "l3_emif_clkdm",
247 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
248 },
249 {
250 .clkdm_name = "l4_cfg_clkdm",
251 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
252 },
253 {
254 .clkdm_name = "l4_per_clkdm",
255 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
256 },
257 {
258 .clkdm_name = "l4_secure_clkdm",
259 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
260 },
261 {
262 .clkdm_name = "l4_wkup_clkdm",
263 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
264 },
265 { NULL }, 115 { NULL },
266}; 116};
267 117
268static struct clkdm_dep l4_secure_wkup_sleep_deps[] = { 118static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
269 { 119 { .clkdm_name = "l3_1_clkdm" },
270 .clkdm_name = "l3_1_clkdm", 120 { .clkdm_name = "l3_emif_clkdm" },
271 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 121 { .clkdm_name = "l4_per_clkdm" },
272 },
273 {
274 .clkdm_name = "l3_emif_clkdm",
275 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
276 },
277 {
278 .clkdm_name = "l4_per_clkdm",
279 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
280 },
281 { NULL }, 122 { NULL },
282}; 123};
283 124
284static struct clkdm_dep mpu_wkup_sleep_deps[] = { 125static struct clkdm_dep mpu_wkup_sleep_deps[] = {
285 { 126 { .clkdm_name = "abe_clkdm" },
286 .clkdm_name = "abe_clkdm", 127 { .clkdm_name = "ducati_clkdm" },
287 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 128 { .clkdm_name = "ivahd_clkdm" },
288 }, 129 { .clkdm_name = "l3_1_clkdm" },
289 { 130 { .clkdm_name = "l3_2_clkdm" },
290 .clkdm_name = "ducati_clkdm", 131 { .clkdm_name = "l3_dss_clkdm" },
291 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 132 { .clkdm_name = "l3_emif_clkdm" },
292 }, 133 { .clkdm_name = "l3_gfx_clkdm" },
293 { 134 { .clkdm_name = "l3_init_clkdm" },
294 .clkdm_name = "ivahd_clkdm", 135 { .clkdm_name = "l4_cfg_clkdm" },
295 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 136 { .clkdm_name = "l4_per_clkdm" },
296 }, 137 { .clkdm_name = "l4_secure_clkdm" },
297 { 138 { .clkdm_name = "l4_wkup_clkdm" },
298 .clkdm_name = "l3_1_clkdm", 139 { .clkdm_name = "tesla_clkdm" },
299 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
300 },
301 {
302 .clkdm_name = "l3_2_clkdm",
303 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
304 },
305 {
306 .clkdm_name = "l3_dss_clkdm",
307 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
308 },
309 {
310 .clkdm_name = "l3_emif_clkdm",
311 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
312 },
313 {
314 .clkdm_name = "l3_gfx_clkdm",
315 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
316 },
317 {
318 .clkdm_name = "l3_init_clkdm",
319 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
320 },
321 {
322 .clkdm_name = "l4_cfg_clkdm",
323 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
324 },
325 {
326 .clkdm_name = "l4_per_clkdm",
327 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
328 },
329 {
330 .clkdm_name = "l4_secure_clkdm",
331 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
332 },
333 {
334 .clkdm_name = "l4_wkup_clkdm",
335 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
336 },
337 {
338 .clkdm_name = "tesla_clkdm",
339 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
340 },
341 { NULL }, 140 { NULL },
342}; 141};
343 142
344static struct clkdm_dep tesla_wkup_sleep_deps[] = { 143static struct clkdm_dep tesla_wkup_sleep_deps[] = {
345 { 144 { .clkdm_name = "abe_clkdm" },
346 .clkdm_name = "abe_clkdm", 145 { .clkdm_name = "ivahd_clkdm" },
347 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 146 { .clkdm_name = "l3_1_clkdm" },
348 }, 147 { .clkdm_name = "l3_2_clkdm" },
349 { 148 { .clkdm_name = "l3_emif_clkdm" },
350 .clkdm_name = "ivahd_clkdm", 149 { .clkdm_name = "l3_init_clkdm" },
351 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 150 { .clkdm_name = "l4_cfg_clkdm" },
352 }, 151 { .clkdm_name = "l4_per_clkdm" },
353 { 152 { .clkdm_name = "l4_wkup_clkdm" },
354 .clkdm_name = "l3_1_clkdm",
355 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
356 },
357 {
358 .clkdm_name = "l3_2_clkdm",
359 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
360 },
361 {
362 .clkdm_name = "l3_emif_clkdm",
363 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
364 },
365 {
366 .clkdm_name = "l3_init_clkdm",
367 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
368 },
369 {
370 .clkdm_name = "l4_cfg_clkdm",
371 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
372 },
373 {
374 .clkdm_name = "l4_per_clkdm",
375 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
376 },
377 {
378 .clkdm_name = "l4_wkup_clkdm",
379 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
380 },
381 { NULL }, 153 { NULL },
382}; 154};
383 155
@@ -388,7 +160,6 @@ static struct clockdomain l4_cefuse_44xx_clkdm = {
388 .cm_inst = OMAP4430_CM2_CEFUSE_INST, 160 .cm_inst = OMAP4430_CM2_CEFUSE_INST,
389 .clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS, 161 .clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
390 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 162 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
391 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
392}; 163};
393 164
394static struct clockdomain l4_cfg_44xx_clkdm = { 165static struct clockdomain l4_cfg_44xx_clkdm = {
@@ -399,7 +170,6 @@ static struct clockdomain l4_cfg_44xx_clkdm = {
399 .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS, 170 .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
400 .dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT, 171 .dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT,
401 .flags = CLKDM_CAN_HWSUP, 172 .flags = CLKDM_CAN_HWSUP,
402 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
403}; 173};
404 174
405static struct clockdomain tesla_44xx_clkdm = { 175static struct clockdomain tesla_44xx_clkdm = {
@@ -412,7 +182,6 @@ static struct clockdomain tesla_44xx_clkdm = {
412 .wkdep_srcs = tesla_wkup_sleep_deps, 182 .wkdep_srcs = tesla_wkup_sleep_deps,
413 .sleepdep_srcs = tesla_wkup_sleep_deps, 183 .sleepdep_srcs = tesla_wkup_sleep_deps,
414 .flags = CLKDM_CAN_HWSUP_SWSUP, 184 .flags = CLKDM_CAN_HWSUP_SWSUP,
415 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
416}; 185};
417 186
418static struct clockdomain l3_gfx_44xx_clkdm = { 187static struct clockdomain l3_gfx_44xx_clkdm = {
@@ -425,7 +194,6 @@ static struct clockdomain l3_gfx_44xx_clkdm = {
425 .wkdep_srcs = l3_gfx_wkup_sleep_deps, 194 .wkdep_srcs = l3_gfx_wkup_sleep_deps,
426 .sleepdep_srcs = l3_gfx_wkup_sleep_deps, 195 .sleepdep_srcs = l3_gfx_wkup_sleep_deps,
427 .flags = CLKDM_CAN_HWSUP_SWSUP, 196 .flags = CLKDM_CAN_HWSUP_SWSUP,
428 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
429}; 197};
430 198
431static struct clockdomain ivahd_44xx_clkdm = { 199static struct clockdomain ivahd_44xx_clkdm = {
@@ -438,7 +206,6 @@ static struct clockdomain ivahd_44xx_clkdm = {
438 .wkdep_srcs = ivahd_wkup_sleep_deps, 206 .wkdep_srcs = ivahd_wkup_sleep_deps,
439 .sleepdep_srcs = ivahd_wkup_sleep_deps, 207 .sleepdep_srcs = ivahd_wkup_sleep_deps,
440 .flags = CLKDM_CAN_HWSUP_SWSUP, 208 .flags = CLKDM_CAN_HWSUP_SWSUP,
441 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
442}; 209};
443 210
444static struct clockdomain l4_secure_44xx_clkdm = { 211static struct clockdomain l4_secure_44xx_clkdm = {
@@ -451,7 +218,6 @@ static struct clockdomain l4_secure_44xx_clkdm = {
451 .wkdep_srcs = l4_secure_wkup_sleep_deps, 218 .wkdep_srcs = l4_secure_wkup_sleep_deps,
452 .sleepdep_srcs = l4_secure_wkup_sleep_deps, 219 .sleepdep_srcs = l4_secure_wkup_sleep_deps,
453 .flags = CLKDM_CAN_HWSUP_SWSUP, 220 .flags = CLKDM_CAN_HWSUP_SWSUP,
454 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
455}; 221};
456 222
457static struct clockdomain l4_per_44xx_clkdm = { 223static struct clockdomain l4_per_44xx_clkdm = {
@@ -462,7 +228,6 @@ static struct clockdomain l4_per_44xx_clkdm = {
462 .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS, 228 .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
463 .dep_bit = OMAP4430_L4PER_STATDEP_SHIFT, 229 .dep_bit = OMAP4430_L4PER_STATDEP_SHIFT,
464 .flags = CLKDM_CAN_HWSUP_SWSUP, 230 .flags = CLKDM_CAN_HWSUP_SWSUP,
465 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
466}; 231};
467 232
468static struct clockdomain abe_44xx_clkdm = { 233static struct clockdomain abe_44xx_clkdm = {
@@ -473,7 +238,6 @@ static struct clockdomain abe_44xx_clkdm = {
473 .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS, 238 .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
474 .dep_bit = OMAP4430_ABE_STATDEP_SHIFT, 239 .dep_bit = OMAP4430_ABE_STATDEP_SHIFT,
475 .flags = CLKDM_CAN_HWSUP_SWSUP, 240 .flags = CLKDM_CAN_HWSUP_SWSUP,
476 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
477}; 241};
478 242
479static struct clockdomain l3_instr_44xx_clkdm = { 243static struct clockdomain l3_instr_44xx_clkdm = {
@@ -482,7 +246,6 @@ static struct clockdomain l3_instr_44xx_clkdm = {
482 .prcm_partition = OMAP4430_CM2_PARTITION, 246 .prcm_partition = OMAP4430_CM2_PARTITION,
483 .cm_inst = OMAP4430_CM2_CORE_INST, 247 .cm_inst = OMAP4430_CM2_CORE_INST,
484 .clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS, 248 .clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
485 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
486}; 249};
487 250
488static struct clockdomain l3_init_44xx_clkdm = { 251static struct clockdomain l3_init_44xx_clkdm = {
@@ -495,7 +258,6 @@ static struct clockdomain l3_init_44xx_clkdm = {
495 .wkdep_srcs = l3_init_wkup_sleep_deps, 258 .wkdep_srcs = l3_init_wkup_sleep_deps,
496 .sleepdep_srcs = l3_init_wkup_sleep_deps, 259 .sleepdep_srcs = l3_init_wkup_sleep_deps,
497 .flags = CLKDM_CAN_HWSUP_SWSUP, 260 .flags = CLKDM_CAN_HWSUP_SWSUP,
498 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
499}; 261};
500 262
501static struct clockdomain d2d_44xx_clkdm = { 263static struct clockdomain d2d_44xx_clkdm = {
@@ -507,7 +269,6 @@ static struct clockdomain d2d_44xx_clkdm = {
507 .wkdep_srcs = d2d_wkup_sleep_deps, 269 .wkdep_srcs = d2d_wkup_sleep_deps,
508 .sleepdep_srcs = d2d_wkup_sleep_deps, 270 .sleepdep_srcs = d2d_wkup_sleep_deps,
509 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 271 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
510 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
511}; 272};
512 273
513static struct clockdomain mpu0_44xx_clkdm = { 274static struct clockdomain mpu0_44xx_clkdm = {
@@ -517,7 +278,6 @@ static struct clockdomain mpu0_44xx_clkdm = {
517 .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST, 278 .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST,
518 .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS, 279 .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
519 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 280 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
520 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
521}; 281};
522 282
523static struct clockdomain mpu1_44xx_clkdm = { 283static struct clockdomain mpu1_44xx_clkdm = {
@@ -527,7 +287,6 @@ static struct clockdomain mpu1_44xx_clkdm = {
527 .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST, 287 .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST,
528 .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS, 288 .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
529 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 289 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
530 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
531}; 290};
532 291
533static struct clockdomain l3_emif_44xx_clkdm = { 292static struct clockdomain l3_emif_44xx_clkdm = {
@@ -538,7 +297,6 @@ static struct clockdomain l3_emif_44xx_clkdm = {
538 .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS, 297 .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
539 .dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT, 298 .dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT,
540 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 299 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
541 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
542}; 300};
543 301
544static struct clockdomain l4_ao_44xx_clkdm = { 302static struct clockdomain l4_ao_44xx_clkdm = {
@@ -548,7 +306,6 @@ static struct clockdomain l4_ao_44xx_clkdm = {
548 .cm_inst = OMAP4430_CM2_ALWAYS_ON_INST, 306 .cm_inst = OMAP4430_CM2_ALWAYS_ON_INST,
549 .clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS, 307 .clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
550 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 308 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
551 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
552}; 309};
553 310
554static struct clockdomain ducati_44xx_clkdm = { 311static struct clockdomain ducati_44xx_clkdm = {
@@ -561,7 +318,6 @@ static struct clockdomain ducati_44xx_clkdm = {
561 .wkdep_srcs = ducati_wkup_sleep_deps, 318 .wkdep_srcs = ducati_wkup_sleep_deps,
562 .sleepdep_srcs = ducati_wkup_sleep_deps, 319 .sleepdep_srcs = ducati_wkup_sleep_deps,
563 .flags = CLKDM_CAN_HWSUP_SWSUP, 320 .flags = CLKDM_CAN_HWSUP_SWSUP,
564 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
565}; 321};
566 322
567static struct clockdomain mpu_44xx_clkdm = { 323static struct clockdomain mpu_44xx_clkdm = {
@@ -573,7 +329,6 @@ static struct clockdomain mpu_44xx_clkdm = {
573 .wkdep_srcs = mpu_wkup_sleep_deps, 329 .wkdep_srcs = mpu_wkup_sleep_deps,
574 .sleepdep_srcs = mpu_wkup_sleep_deps, 330 .sleepdep_srcs = mpu_wkup_sleep_deps,
575 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 331 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
576 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
577}; 332};
578 333
579static struct clockdomain l3_2_44xx_clkdm = { 334static struct clockdomain l3_2_44xx_clkdm = {
@@ -584,7 +339,6 @@ static struct clockdomain l3_2_44xx_clkdm = {
584 .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS, 339 .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
585 .dep_bit = OMAP4430_L3_2_STATDEP_SHIFT, 340 .dep_bit = OMAP4430_L3_2_STATDEP_SHIFT,
586 .flags = CLKDM_CAN_HWSUP, 341 .flags = CLKDM_CAN_HWSUP,
587 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
588}; 342};
589 343
590static struct clockdomain l3_1_44xx_clkdm = { 344static struct clockdomain l3_1_44xx_clkdm = {
@@ -595,7 +349,6 @@ static struct clockdomain l3_1_44xx_clkdm = {
595 .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS, 349 .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
596 .dep_bit = OMAP4430_L3_1_STATDEP_SHIFT, 350 .dep_bit = OMAP4430_L3_1_STATDEP_SHIFT,
597 .flags = CLKDM_CAN_HWSUP, 351 .flags = CLKDM_CAN_HWSUP,
598 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
599}; 352};
600 353
601static struct clockdomain iss_44xx_clkdm = { 354static struct clockdomain iss_44xx_clkdm = {
@@ -607,7 +360,6 @@ static struct clockdomain iss_44xx_clkdm = {
607 .wkdep_srcs = iss_wkup_sleep_deps, 360 .wkdep_srcs = iss_wkup_sleep_deps,
608 .sleepdep_srcs = iss_wkup_sleep_deps, 361 .sleepdep_srcs = iss_wkup_sleep_deps,
609 .flags = CLKDM_CAN_HWSUP_SWSUP, 362 .flags = CLKDM_CAN_HWSUP_SWSUP,
610 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
611}; 363};
612 364
613static struct clockdomain l3_dss_44xx_clkdm = { 365static struct clockdomain l3_dss_44xx_clkdm = {
@@ -620,7 +372,6 @@ static struct clockdomain l3_dss_44xx_clkdm = {
620 .wkdep_srcs = l3_dss_wkup_sleep_deps, 372 .wkdep_srcs = l3_dss_wkup_sleep_deps,
621 .sleepdep_srcs = l3_dss_wkup_sleep_deps, 373 .sleepdep_srcs = l3_dss_wkup_sleep_deps,
622 .flags = CLKDM_CAN_HWSUP_SWSUP, 374 .flags = CLKDM_CAN_HWSUP_SWSUP,
623 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
624}; 375};
625 376
626static struct clockdomain l4_wkup_44xx_clkdm = { 377static struct clockdomain l4_wkup_44xx_clkdm = {
@@ -631,7 +382,6 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
631 .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, 382 .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
632 .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT, 383 .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT,
633 .flags = CLKDM_CAN_HWSUP, 384 .flags = CLKDM_CAN_HWSUP,
634 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
635}; 385};
636 386
637static struct clockdomain emu_sys_44xx_clkdm = { 387static struct clockdomain emu_sys_44xx_clkdm = {
@@ -641,7 +391,6 @@ static struct clockdomain emu_sys_44xx_clkdm = {
641 .cm_inst = OMAP4430_PRM_EMU_CM_INST, 391 .cm_inst = OMAP4430_PRM_EMU_CM_INST,
642 .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS, 392 .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
643 .flags = CLKDM_CAN_HWSUP, 393 .flags = CLKDM_CAN_HWSUP,
644 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
645}; 394};
646 395
647static struct clockdomain l3_dma_44xx_clkdm = { 396static struct clockdomain l3_dma_44xx_clkdm = {
@@ -653,7 +402,6 @@ static struct clockdomain l3_dma_44xx_clkdm = {
653 .wkdep_srcs = l3_dma_wkup_sleep_deps, 402 .wkdep_srcs = l3_dma_wkup_sleep_deps,
654 .sleepdep_srcs = l3_dma_wkup_sleep_deps, 403 .sleepdep_srcs = l3_dma_wkup_sleep_deps,
655 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 404 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
656 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
657}; 405};
658 406
659/* As clockdomains are added or removed above, this list must also be changed */ 407/* As clockdomains are added or removed above, this list must also be changed */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 2ce1ce6fb4db..d098c870de0b 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -342,11 +342,11 @@ void __init omap2_init_common_infrastructure(void)
342 342
343 if (cpu_is_omap242x()) { 343 if (cpu_is_omap242x()) {
344 omap2xxx_powerdomains_init(); 344 omap2xxx_powerdomains_init();
345 omap2xxx_clockdomains_init(); 345 omap242x_clockdomains_init();
346 omap2420_hwmod_init(); 346 omap2420_hwmod_init();
347 } else if (cpu_is_omap243x()) { 347 } else if (cpu_is_omap243x()) {
348 omap2xxx_powerdomains_init(); 348 omap2xxx_powerdomains_init();
349 omap2xxx_clockdomains_init(); 349 omap243x_clockdomains_init();
350 omap2430_hwmod_init(); 350 omap2430_hwmod_init();
351 } else if (cpu_is_omap34xx()) { 351 } else if (cpu_is_omap34xx()) {
352 omap3xxx_powerdomains_init(); 352 omap3xxx_powerdomains_init();
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 23:03:41 -0500