diff options
author | Lennert Buytenhek <buytenh@wantstofly.org> | 2008-03-27 14:51:41 -0400 |
---|---|---|
committer | Nicolas Pitre <nico@marvell.com> | 2008-03-27 14:51:41 -0400 |
commit | 9dd0b194bf6804b1998f0fe261b2606ec7b58d72 (patch) | |
tree | c9fd5ab51dc256818c24a8a771dc068d021039e2 /arch/arm | |
parent | 159ffb3a04f6bc619643af680df406faafd0199d (diff) |
Orion: orion -> orion5x rename
Do a global s/orion/orion5x/ of the Orion 5x-specific bits (i.e.
not the plat-orion bits.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Reviewed-by: Tzachi Perelstein <tzachi@marvell.com>
Acked-by: Saeed Bishara <saeed@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/Kconfig | 7 | ||||
-rw-r--r-- | arch/arm/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/configs/orion5x_defconfig (renamed from arch/arm/configs/orion_defconfig) | 2 | ||||
-rw-r--r-- | arch/arm/mach-orion/common.h | 72 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/Kconfig (renamed from arch/arm/mach-orion/Kconfig) | 2 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/Makefile (renamed from arch/arm/mach-orion/Makefile) | 0 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/Makefile.boot (renamed from arch/arm/mach-orion/Makefile.boot) | 0 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/addr-map.c (renamed from arch/arm/mach-orion/addr-map.c) | 108 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/common.c (renamed from arch/arm/mach-orion/common.c) | 202 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/common.h | 72 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/db88f5281-setup.c (renamed from arch/arm/mach-orion/db88f5281-setup.c) | 44 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/dns323-setup.c (renamed from arch/arm/mach-orion/dns323-setup.c) | 41 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/gpio.c (renamed from arch/arm/mach-orion/gpio.c) | 72 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/irq.c (renamed from arch/arm/mach-orion/irq.c) | 94 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/kurobox_pro-setup.c (renamed from arch/arm/mach-orion/kurobox_pro-setup.c) | 43 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/pci.c (renamed from arch/arm/mach-orion/pci.c) | 160 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/rd88f5182-setup.c (renamed from arch/arm/mach-orion/rd88f5182-setup.c) | 43 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/ts209-setup.c (renamed from arch/arm/mach-orion/ts209-setup.c) | 57 | ||||
-rw-r--r-- | arch/arm/mm/Kconfig | 2 |
19 files changed, 514 insertions, 509 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 845f96e9f0d0..2f4fb773f3e8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -377,7 +377,7 @@ config ARCH_MXC | |||
377 | help | 377 | help |
378 | Support for Freescale MXC/iMX-based family of processors | 378 | Support for Freescale MXC/iMX-based family of processors |
379 | 379 | ||
380 | config ARCH_ORION | 380 | config ARCH_ORION5X |
381 | bool "Marvell Orion" | 381 | bool "Marvell Orion" |
382 | depends on MMU | 382 | depends on MMU |
383 | select PCI | 383 | select PCI |
@@ -386,7 +386,8 @@ config ARCH_ORION | |||
386 | select GENERIC_CLOCKEVENTS | 386 | select GENERIC_CLOCKEVENTS |
387 | select PLAT_ORION | 387 | select PLAT_ORION |
388 | help | 388 | help |
389 | Support for Marvell Orion System on Chip family. | 389 | Support for the following Marvell Orion 5x series SoCs: |
390 | Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.) | ||
390 | 391 | ||
391 | config ARCH_PNX4008 | 392 | config ARCH_PNX4008 |
392 | bool "Philips Nexperia PNX4008 Mobile" | 393 | bool "Philips Nexperia PNX4008 Mobile" |
@@ -517,7 +518,7 @@ source "arch/arm/mach-omap1/Kconfig" | |||
517 | 518 | ||
518 | source "arch/arm/mach-omap2/Kconfig" | 519 | source "arch/arm/mach-omap2/Kconfig" |
519 | 520 | ||
520 | source "arch/arm/mach-orion/Kconfig" | 521 | source "arch/arm/mach-orion5x/Kconfig" |
521 | 522 | ||
522 | source "arch/arm/plat-s3c24xx/Kconfig" | 523 | source "arch/arm/plat-s3c24xx/Kconfig" |
523 | source "arch/arm/plat-s3c/Kconfig" | 524 | source "arch/arm/plat-s3c/Kconfig" |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 27866cf0c180..6f9975053759 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
@@ -139,7 +139,7 @@ endif | |||
139 | machine-$(CONFIG_ARCH_KS8695) := ks8695 | 139 | machine-$(CONFIG_ARCH_KS8695) := ks8695 |
140 | incdir-$(CONFIG_ARCH_MXC) := mxc | 140 | incdir-$(CONFIG_ARCH_MXC) := mxc |
141 | machine-$(CONFIG_ARCH_MX3) := mx3 | 141 | machine-$(CONFIG_ARCH_MX3) := mx3 |
142 | machine-$(CONFIG_ARCH_ORION) := orion | 142 | machine-$(CONFIG_ARCH_ORION5X) := orion5x |
143 | machine-$(CONFIG_ARCH_MSM7X00A) := msm | 143 | machine-$(CONFIG_ARCH_MSM7X00A) := msm |
144 | 144 | ||
145 | ifeq ($(CONFIG_ARCH_EBSA110),y) | 145 | ifeq ($(CONFIG_ARCH_EBSA110),y) |
diff --git a/arch/arm/configs/orion_defconfig b/arch/arm/configs/orion5x_defconfig index 1e5aaa645fcd..52cd99bd52fb 100644 --- a/arch/arm/configs/orion_defconfig +++ b/arch/arm/configs/orion5x_defconfig | |||
@@ -140,7 +140,7 @@ CONFIG_CLASSIC_RCU=y | |||
140 | # CONFIG_ARCH_KS8695 is not set | 140 | # CONFIG_ARCH_KS8695 is not set |
141 | # CONFIG_ARCH_NS9XXX is not set | 141 | # CONFIG_ARCH_NS9XXX is not set |
142 | # CONFIG_ARCH_MXC is not set | 142 | # CONFIG_ARCH_MXC is not set |
143 | CONFIG_ARCH_ORION=y | 143 | CONFIG_ARCH_ORION5X=y |
144 | # CONFIG_ARCH_PNX4008 is not set | 144 | # CONFIG_ARCH_PNX4008 is not set |
145 | # CONFIG_ARCH_PXA is not set | 145 | # CONFIG_ARCH_PXA is not set |
146 | # CONFIG_ARCH_RPC is not set | 146 | # CONFIG_ARCH_RPC is not set |
diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h deleted file mode 100644 index bcc31adaca15..000000000000 --- a/arch/arm/mach-orion/common.h +++ /dev/null | |||
@@ -1,72 +0,0 @@ | |||
1 | #ifndef __ARCH_ORION_COMMON_H | ||
2 | #define __ARCH_ORION_COMMON_H | ||
3 | |||
4 | /* | ||
5 | * Basic Orion init functions used early by machine-setup. | ||
6 | */ | ||
7 | |||
8 | void orion_map_io(void); | ||
9 | void orion_init_irq(void); | ||
10 | void orion_init(void); | ||
11 | extern struct sys_timer orion_timer; | ||
12 | |||
13 | /* | ||
14 | * Enumerations and functions for Orion windows mapping. Used by Orion core | ||
15 | * functions to map its interfaces and by the machine-setup to map its on- | ||
16 | * board devices. Details in /mach-orion/addr-map.c | ||
17 | */ | ||
18 | extern struct mbus_dram_target_info orion_mbus_dram_info; | ||
19 | void orion_setup_cpu_mbus_bridge(void); | ||
20 | void orion_setup_dev_boot_win(u32 base, u32 size); | ||
21 | void orion_setup_dev0_win(u32 base, u32 size); | ||
22 | void orion_setup_dev1_win(u32 base, u32 size); | ||
23 | void orion_setup_dev2_win(u32 base, u32 size); | ||
24 | void orion_setup_pcie_wa_win(u32 base, u32 size); | ||
25 | void orion_setup_eth_wins(void); | ||
26 | |||
27 | /* | ||
28 | * Shared code used internally by other Orion core functions. | ||
29 | * (/mach-orion/pci.c) | ||
30 | */ | ||
31 | |||
32 | struct pci_sys_data; | ||
33 | struct pci_bus; | ||
34 | |||
35 | void orion_pcie_id(u32 *dev, u32 *rev); | ||
36 | int orion_pcie_local_bus_nr(void); | ||
37 | int orion_pci_local_bus_nr(void); | ||
38 | int orion_pci_sys_setup(int nr, struct pci_sys_data *sys); | ||
39 | struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); | ||
40 | |||
41 | /* | ||
42 | * Valid GPIO pins according to MPP setup, used by machine-setup. | ||
43 | * (/mach-orion/gpio.c). | ||
44 | */ | ||
45 | |||
46 | void orion_gpio_set_valid_pins(u32 pins); | ||
47 | void gpio_display(void); /* debug */ | ||
48 | |||
49 | /* | ||
50 | * Pull in Orion Ethernet platform_data, used by machine-setup | ||
51 | */ | ||
52 | |||
53 | struct mv643xx_eth_platform_data; | ||
54 | |||
55 | void orion_eth_init(struct mv643xx_eth_platform_data *eth_data); | ||
56 | |||
57 | /* | ||
58 | * Orion Sata platform_data, used by machine-setup | ||
59 | */ | ||
60 | |||
61 | struct mv_sata_platform_data; | ||
62 | |||
63 | void orion_sata_init(struct mv_sata_platform_data *sata_data); | ||
64 | |||
65 | struct machine_desc; | ||
66 | struct meminfo; | ||
67 | struct tag; | ||
68 | extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, | ||
69 | char **, struct meminfo *); | ||
70 | |||
71 | |||
72 | #endif | ||
diff --git a/arch/arm/mach-orion/Kconfig b/arch/arm/mach-orion5x/Kconfig index 1dcbb6ac5a30..01c66957d8f4 100644 --- a/arch/arm/mach-orion/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig | |||
@@ -1,4 +1,4 @@ | |||
1 | if ARCH_ORION | 1 | if ARCH_ORION5X |
2 | 2 | ||
3 | menu "Orion Implementations" | 3 | menu "Orion Implementations" |
4 | 4 | ||
diff --git a/arch/arm/mach-orion/Makefile b/arch/arm/mach-orion5x/Makefile index d894caa5060f..d894caa5060f 100644 --- a/arch/arm/mach-orion/Makefile +++ b/arch/arm/mach-orion5x/Makefile | |||
diff --git a/arch/arm/mach-orion/Makefile.boot b/arch/arm/mach-orion5x/Makefile.boot index 67039c3e0c48..67039c3e0c48 100644 --- a/arch/arm/mach-orion/Makefile.boot +++ b/arch/arm/mach-orion5x/Makefile.boot | |||
diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index 738de617e3c7..6b179371e0a2 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-orion/addr-map.c | 2 | * arch/arm/mach-orion5x/addr-map.c |
3 | * | 3 | * |
4 | * Address map functions for Marvell Orion System On Chip | 4 | * Address map functions for Marvell Orion 5x SoCs |
5 | * | 5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
7 | * | 7 | * |
@@ -29,7 +29,7 @@ | |||
29 | * Setup access to PCI and PCI-E IO/MEM space is issued by this file. | 29 | * Setup access to PCI and PCI-E IO/MEM space is issued by this file. |
30 | * Setup access to various devices located on the device bus interface (e.g. | 30 | * Setup access to various devices located on the device bus interface (e.g. |
31 | * flashes, RTC, etc) should be issued by machine-setup.c according to | 31 | * flashes, RTC, etc) should be issued by machine-setup.c according to |
32 | * specific board population (by using orion_setup_*_win()). | 32 | * specific board population (by using orion5x_setup_*_win()). |
33 | * | 33 | * |
34 | * Non-CPU Masters address decoding -- | 34 | * Non-CPU Masters address decoding -- |
35 | * Unlike the CPU, we setup the access from Orion's master interfaces to DDR | 35 | * Unlike the CPU, we setup the access from Orion's master interfaces to DDR |
@@ -66,8 +66,8 @@ | |||
66 | /* | 66 | /* |
67 | * Helpers to get DDR bank info | 67 | * Helpers to get DDR bank info |
68 | */ | 68 | */ |
69 | #define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8)) | 69 | #define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8)) |
70 | #define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8)) | 70 | #define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8)) |
71 | #define DDR_MAX_CS 4 | 71 | #define DDR_MAX_CS 4 |
72 | #define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1) | 72 | #define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1) |
73 | #define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000) | 73 | #define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000) |
@@ -76,30 +76,30 @@ | |||
76 | /* | 76 | /* |
77 | * CPU Address Decode Windows registers | 77 | * CPU Address Decode Windows registers |
78 | */ | 78 | */ |
79 | #define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4)) | 79 | #define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4)) |
80 | #define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4)) | 80 | #define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4)) |
81 | #define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4)) | 81 | #define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) |
82 | #define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4)) | 82 | #define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) |
83 | 83 | ||
84 | /* | 84 | /* |
85 | * Gigabit Ethernet Address Decode Windows registers | 85 | * Gigabit Ethernet Address Decode Windows registers |
86 | */ | 86 | */ |
87 | #define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8)) | 87 | #define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8)) |
88 | #define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8)) | 88 | #define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8)) |
89 | #define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4)) | 89 | #define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4)) |
90 | #define ETH_WIN_EN ORION_ETH_REG(0x290) | 90 | #define ETH_WIN_EN ORION5X_ETH_REG(0x290) |
91 | #define ETH_WIN_PROT ORION_ETH_REG(0x294) | 91 | #define ETH_WIN_PROT ORION5X_ETH_REG(0x294) |
92 | #define ETH_MAX_WIN 6 | 92 | #define ETH_MAX_WIN 6 |
93 | #define ETH_MAX_REMAP_WIN 4 | 93 | #define ETH_MAX_REMAP_WIN 4 |
94 | 94 | ||
95 | 95 | ||
96 | struct mbus_dram_target_info orion_mbus_dram_info; | 96 | struct mbus_dram_target_info orion5x_mbus_dram_info; |
97 | 97 | ||
98 | static int __init orion_cpu_win_can_remap(int win) | 98 | static int __init orion5x_cpu_win_can_remap(int win) |
99 | { | 99 | { |
100 | u32 dev, rev; | 100 | u32 dev, rev; |
101 | 101 | ||
102 | orion_pcie_id(&dev, &rev); | 102 | orion5x_pcie_id(&dev, &rev); |
103 | if ((dev == MV88F5281_DEV_ID && win < 4) | 103 | if ((dev == MV88F5281_DEV_ID && win < 4) |
104 | || (dev == MV88F5182_DEV_ID && win < 2) | 104 | || (dev == MV88F5182_DEV_ID && win < 2) |
105 | || (dev == MV88F5181_DEV_ID && win < 2)) | 105 | || (dev == MV88F5181_DEV_ID && win < 2)) |
@@ -111,20 +111,20 @@ static int __init orion_cpu_win_can_remap(int win) | |||
111 | static void __init setup_cpu_win(int win, u32 base, u32 size, | 111 | static void __init setup_cpu_win(int win, u32 base, u32 size, |
112 | u8 target, u8 attr, int remap) | 112 | u8 target, u8 attr, int remap) |
113 | { | 113 | { |
114 | orion_write(CPU_WIN_BASE(win), base & 0xffff0000); | 114 | orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000); |
115 | orion_write(CPU_WIN_CTRL(win), | 115 | orion5x_write(CPU_WIN_CTRL(win), |
116 | ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); | 116 | ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); |
117 | 117 | ||
118 | if (orion_cpu_win_can_remap(win)) { | 118 | if (orion5x_cpu_win_can_remap(win)) { |
119 | if (remap < 0) | 119 | if (remap < 0) |
120 | remap = base; | 120 | remap = base; |
121 | 121 | ||
122 | orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); | 122 | orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); |
123 | orion_write(CPU_WIN_REMAP_HI(win), 0); | 123 | orion5x_write(CPU_WIN_REMAP_HI(win), 0); |
124 | } | 124 | } |
125 | } | 125 | } |
126 | 126 | ||
127 | void __init orion_setup_cpu_mbus_bridge(void) | 127 | void __init orion5x_setup_cpu_mbus_bridge(void) |
128 | { | 128 | { |
129 | int i; | 129 | int i; |
130 | int cs; | 130 | int cs; |
@@ -133,30 +133,30 @@ void __init orion_setup_cpu_mbus_bridge(void) | |||
133 | * First, disable and clear windows. | 133 | * First, disable and clear windows. |
134 | */ | 134 | */ |
135 | for (i = 0; i < 8; i++) { | 135 | for (i = 0; i < 8; i++) { |
136 | orion_write(CPU_WIN_BASE(i), 0); | 136 | orion5x_write(CPU_WIN_BASE(i), 0); |
137 | orion_write(CPU_WIN_CTRL(i), 0); | 137 | orion5x_write(CPU_WIN_CTRL(i), 0); |
138 | if (orion_cpu_win_can_remap(i)) { | 138 | if (orion5x_cpu_win_can_remap(i)) { |
139 | orion_write(CPU_WIN_REMAP_LO(i), 0); | 139 | orion5x_write(CPU_WIN_REMAP_LO(i), 0); |
140 | orion_write(CPU_WIN_REMAP_HI(i), 0); | 140 | orion5x_write(CPU_WIN_REMAP_HI(i), 0); |
141 | } | 141 | } |
142 | } | 142 | } |
143 | 143 | ||
144 | /* | 144 | /* |
145 | * Setup windows for PCI+PCIe IO+MEM space. | 145 | * Setup windows for PCI+PCIe IO+MEM space. |
146 | */ | 146 | */ |
147 | setup_cpu_win(0, ORION_PCIE_IO_PHYS_BASE, ORION_PCIE_IO_SIZE, | 147 | setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, |
148 | TARGET_PCIE, ATTR_PCIE_IO, ORION_PCIE_IO_BUS_BASE); | 148 | TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE); |
149 | setup_cpu_win(1, ORION_PCI_IO_PHYS_BASE, ORION_PCI_IO_SIZE, | 149 | setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE, |
150 | TARGET_PCI, ATTR_PCI_IO, ORION_PCI_IO_BUS_BASE); | 150 | TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE); |
151 | setup_cpu_win(2, ORION_PCIE_MEM_PHYS_BASE, ORION_PCIE_MEM_SIZE, | 151 | setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE, |
152 | TARGET_PCIE, ATTR_PCIE_MEM, -1); | 152 | TARGET_PCIE, ATTR_PCIE_MEM, -1); |
153 | setup_cpu_win(3, ORION_PCI_MEM_PHYS_BASE, ORION_PCI_MEM_SIZE, | 153 | setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, |
154 | TARGET_PCI, ATTR_PCI_MEM, -1); | 154 | TARGET_PCI, ATTR_PCI_MEM, -1); |
155 | 155 | ||
156 | /* | 156 | /* |
157 | * Setup MBUS dram target info. | 157 | * Setup MBUS dram target info. |
158 | */ | 158 | */ |
159 | orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; | 159 | orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; |
160 | 160 | ||
161 | for (i = 0, cs = 0; i < 4; i++) { | 161 | for (i = 0, cs = 0; i < 4; i++) { |
162 | u32 base = readl(DDR_BASE_CS(i)); | 162 | u32 base = readl(DDR_BASE_CS(i)); |
@@ -168,42 +168,42 @@ void __init orion_setup_cpu_mbus_bridge(void) | |||
168 | if (size & 1) { | 168 | if (size & 1) { |
169 | struct mbus_dram_window *w; | 169 | struct mbus_dram_window *w; |
170 | 170 | ||
171 | w = &orion_mbus_dram_info.cs[cs++]; | 171 | w = &orion5x_mbus_dram_info.cs[cs++]; |
172 | w->cs_index = i; | 172 | w->cs_index = i; |
173 | w->mbus_attr = 0xf & ~(1 << i); | 173 | w->mbus_attr = 0xf & ~(1 << i); |
174 | w->base = base & 0xff000000; | 174 | w->base = base & 0xff000000; |
175 | w->size = (size | 0x00ffffff) + 1; | 175 | w->size = (size | 0x00ffffff) + 1; |
176 | } | 176 | } |
177 | } | 177 | } |
178 | orion_mbus_dram_info.num_cs = cs; | 178 | orion5x_mbus_dram_info.num_cs = cs; |
179 | } | 179 | } |
180 | 180 | ||
181 | void __init orion_setup_dev_boot_win(u32 base, u32 size) | 181 | void __init orion5x_setup_dev_boot_win(u32 base, u32 size) |
182 | { | 182 | { |
183 | setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); | 183 | setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); |
184 | } | 184 | } |
185 | 185 | ||
186 | void __init orion_setup_dev0_win(u32 base, u32 size) | 186 | void __init orion5x_setup_dev0_win(u32 base, u32 size) |
187 | { | 187 | { |
188 | setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); | 188 | setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); |
189 | } | 189 | } |
190 | 190 | ||
191 | void __init orion_setup_dev1_win(u32 base, u32 size) | 191 | void __init orion5x_setup_dev1_win(u32 base, u32 size) |
192 | { | 192 | { |
193 | setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); | 193 | setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); |
194 | } | 194 | } |
195 | 195 | ||
196 | void __init orion_setup_dev2_win(u32 base, u32 size) | 196 | void __init orion5x_setup_dev2_win(u32 base, u32 size) |
197 | { | 197 | { |
198 | setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); | 198 | setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); |
199 | } | 199 | } |
200 | 200 | ||
201 | void __init orion_setup_pcie_wa_win(u32 base, u32 size) | 201 | void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) |
202 | { | 202 | { |
203 | setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); | 203 | setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); |
204 | } | 204 | } |
205 | 205 | ||
206 | void __init orion_setup_eth_wins(void) | 206 | void __init orion5x_setup_eth_wins(void) |
207 | { | 207 | { |
208 | int i; | 208 | int i; |
209 | 209 | ||
@@ -211,12 +211,12 @@ void __init orion_setup_eth_wins(void) | |||
211 | * First, disable and clear windows | 211 | * First, disable and clear windows |
212 | */ | 212 | */ |
213 | for (i = 0; i < ETH_MAX_WIN; i++) { | 213 | for (i = 0; i < ETH_MAX_WIN; i++) { |
214 | orion_write(ETH_WIN_BASE(i), 0); | 214 | orion5x_write(ETH_WIN_BASE(i), 0); |
215 | orion_write(ETH_WIN_SIZE(i), 0); | 215 | orion5x_write(ETH_WIN_SIZE(i), 0); |
216 | orion_setbits(ETH_WIN_EN, 1 << i); | 216 | orion5x_setbits(ETH_WIN_EN, 1 << i); |
217 | orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); | 217 | orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2)); |
218 | if (i < ETH_MAX_REMAP_WIN) | 218 | if (i < ETH_MAX_REMAP_WIN) |
219 | orion_write(ETH_WIN_REMAP(i), 0); | 219 | orion5x_write(ETH_WIN_REMAP(i), 0); |
220 | } | 220 | } |
221 | 221 | ||
222 | /* | 222 | /* |
@@ -224,17 +224,17 @@ void __init orion_setup_eth_wins(void) | |||
224 | */ | 224 | */ |
225 | for (i = 0; i < DDR_MAX_CS; i++) { | 225 | for (i = 0; i < DDR_MAX_CS; i++) { |
226 | u32 base, size; | 226 | u32 base, size; |
227 | size = orion_read(DDR_SIZE_CS(i)); | 227 | size = orion5x_read(DDR_SIZE_CS(i)); |
228 | base = orion_read(DDR_BASE_CS(i)); | 228 | base = orion5x_read(DDR_BASE_CS(i)); |
229 | if (size & DDR_BANK_EN) { | 229 | if (size & DDR_BANK_EN) { |
230 | base = DDR_REG_TO_BASE(base); | 230 | base = DDR_REG_TO_BASE(base); |
231 | size = DDR_REG_TO_SIZE(size); | 231 | size = DDR_REG_TO_SIZE(size); |
232 | orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); | 232 | orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000); |
233 | orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) | | 233 | orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) | |
234 | (ATTR_DDR_CS(i) << 8) | | 234 | (ATTR_DDR_CS(i) << 8) | |
235 | TARGET_DDR); | 235 | TARGET_DDR); |
236 | orion_clrbits(ETH_WIN_EN, 1 << i); | 236 | orion5x_clrbits(ETH_WIN_EN, 1 << i); |
237 | orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); | 237 | orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2)); |
238 | } | 238 | } |
239 | } | 239 | } |
240 | } | 240 | } |
diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion5x/common.c index 85c8f18268ad..439c7784af02 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion5x/common.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-orion/common.c | 2 | * arch/arm/mach-orion5x/common.c |
3 | * | 3 | * |
4 | * Core functions for Marvell Orion System On Chip | 4 | * Core functions for Marvell Orion 5x SoCs |
5 | * | 5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | 6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
7 | * | 7 | * |
@@ -25,7 +25,7 @@ | |||
25 | #include <asm/mach/map.h> | 25 | #include <asm/mach/map.h> |
26 | #include <asm/mach/time.h> | 26 | #include <asm/mach/time.h> |
27 | #include <asm/arch/hardware.h> | 27 | #include <asm/arch/hardware.h> |
28 | #include <asm/arch/orion.h> | 28 | #include <asm/arch/orion5x.h> |
29 | #include <asm/plat-orion/ehci-orion.h> | 29 | #include <asm/plat-orion/ehci-orion.h> |
30 | #include <asm/plat-orion/orion_nand.h> | 30 | #include <asm/plat-orion/orion_nand.h> |
31 | #include <asm/plat-orion/time.h> | 31 | #include <asm/plat-orion/time.h> |
@@ -34,51 +34,51 @@ | |||
34 | /***************************************************************************** | 34 | /***************************************************************************** |
35 | * I/O Address Mapping | 35 | * I/O Address Mapping |
36 | ****************************************************************************/ | 36 | ****************************************************************************/ |
37 | static struct map_desc orion_io_desc[] __initdata = { | 37 | static struct map_desc orion5x_io_desc[] __initdata = { |
38 | { | 38 | { |
39 | .virtual = ORION_REGS_VIRT_BASE, | 39 | .virtual = ORION5X_REGS_VIRT_BASE, |
40 | .pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE), | 40 | .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), |
41 | .length = ORION_REGS_SIZE, | 41 | .length = ORION5X_REGS_SIZE, |
42 | .type = MT_DEVICE | 42 | .type = MT_DEVICE |
43 | }, | 43 | }, |
44 | { | 44 | { |
45 | .virtual = ORION_PCIE_IO_VIRT_BASE, | 45 | .virtual = ORION5X_PCIE_IO_VIRT_BASE, |
46 | .pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE), | 46 | .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), |
47 | .length = ORION_PCIE_IO_SIZE, | 47 | .length = ORION5X_PCIE_IO_SIZE, |
48 | .type = MT_DEVICE | 48 | .type = MT_DEVICE |
49 | }, | 49 | }, |
50 | { | 50 | { |
51 | .virtual = ORION_PCI_IO_VIRT_BASE, | 51 | .virtual = ORION5X_PCI_IO_VIRT_BASE, |
52 | .pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE), | 52 | .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), |
53 | .length = ORION_PCI_IO_SIZE, | 53 | .length = ORION5X_PCI_IO_SIZE, |
54 | .type = MT_DEVICE | 54 | .type = MT_DEVICE |
55 | }, | 55 | }, |
56 | { | 56 | { |
57 | .virtual = ORION_PCIE_WA_VIRT_BASE, | 57 | .virtual = ORION5X_PCIE_WA_VIRT_BASE, |
58 | .pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE), | 58 | .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), |
59 | .length = ORION_PCIE_WA_SIZE, | 59 | .length = ORION5X_PCIE_WA_SIZE, |
60 | .type = MT_DEVICE | 60 | .type = MT_DEVICE |
61 | }, | 61 | }, |
62 | }; | 62 | }; |
63 | 63 | ||
64 | void __init orion_map_io(void) | 64 | void __init orion5x_map_io(void) |
65 | { | 65 | { |
66 | iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc)); | 66 | iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); |
67 | } | 67 | } |
68 | 68 | ||
69 | /***************************************************************************** | 69 | /***************************************************************************** |
70 | * UART | 70 | * UART |
71 | ****************************************************************************/ | 71 | ****************************************************************************/ |
72 | 72 | ||
73 | static struct resource orion_uart_resources[] = { | 73 | static struct resource orion5x_uart_resources[] = { |
74 | { | 74 | { |
75 | .start = UART0_PHYS_BASE, | 75 | .start = UART0_PHYS_BASE, |
76 | .end = UART0_PHYS_BASE + 0xff, | 76 | .end = UART0_PHYS_BASE + 0xff, |
77 | .flags = IORESOURCE_MEM, | 77 | .flags = IORESOURCE_MEM, |
78 | }, | 78 | }, |
79 | { | 79 | { |
80 | .start = IRQ_ORION_UART0, | 80 | .start = IRQ_ORION5X_UART0, |
81 | .end = IRQ_ORION_UART0, | 81 | .end = IRQ_ORION5X_UART0, |
82 | .flags = IORESOURCE_IRQ, | 82 | .flags = IORESOURCE_IRQ, |
83 | }, | 83 | }, |
84 | { | 84 | { |
@@ -87,102 +87,102 @@ static struct resource orion_uart_resources[] = { | |||
87 | .flags = IORESOURCE_MEM, | 87 | .flags = IORESOURCE_MEM, |
88 | }, | 88 | }, |
89 | { | 89 | { |
90 | .start = IRQ_ORION_UART1, | 90 | .start = IRQ_ORION5X_UART1, |
91 | .end = IRQ_ORION_UART1, | 91 | .end = IRQ_ORION5X_UART1, |
92 | .flags = IORESOURCE_IRQ, | 92 | .flags = IORESOURCE_IRQ, |
93 | }, | 93 | }, |
94 | }; | 94 | }; |
95 | 95 | ||
96 | static struct plat_serial8250_port orion_uart_data[] = { | 96 | static struct plat_serial8250_port orion5x_uart_data[] = { |
97 | { | 97 | { |
98 | .mapbase = UART0_PHYS_BASE, | 98 | .mapbase = UART0_PHYS_BASE, |
99 | .membase = (char *)UART0_VIRT_BASE, | 99 | .membase = (char *)UART0_VIRT_BASE, |
100 | .irq = IRQ_ORION_UART0, | 100 | .irq = IRQ_ORION5X_UART0, |
101 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | 101 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, |
102 | .iotype = UPIO_MEM, | 102 | .iotype = UPIO_MEM, |
103 | .regshift = 2, | 103 | .regshift = 2, |
104 | .uartclk = ORION_TCLK, | 104 | .uartclk = ORION5X_TCLK, |
105 | }, | 105 | }, |
106 | { | 106 | { |
107 | .mapbase = UART1_PHYS_BASE, | 107 | .mapbase = UART1_PHYS_BASE, |
108 | .membase = (char *)UART1_VIRT_BASE, | 108 | .membase = (char *)UART1_VIRT_BASE, |
109 | .irq = IRQ_ORION_UART1, | 109 | .irq = IRQ_ORION5X_UART1, |
110 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | 110 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, |
111 | .iotype = UPIO_MEM, | 111 | .iotype = UPIO_MEM, |
112 | .regshift = 2, | 112 | .regshift = 2, |
113 | .uartclk = ORION_TCLK, | 113 | .uartclk = ORION5X_TCLK, |
114 | }, | 114 | }, |
115 | { }, | 115 | { }, |
116 | }; | 116 | }; |
117 | 117 | ||
118 | static struct platform_device orion_uart = { | 118 | static struct platform_device orion5x_uart = { |
119 | .name = "serial8250", | 119 | .name = "serial8250", |
120 | .id = PLAT8250_DEV_PLATFORM, | 120 | .id = PLAT8250_DEV_PLATFORM, |
121 | .dev = { | 121 | .dev = { |
122 | .platform_data = orion_uart_data, | 122 | .platform_data = orion5x_uart_data, |
123 | }, | 123 | }, |
124 | .resource = orion_uart_resources, | 124 | .resource = orion5x_uart_resources, |
125 | .num_resources = ARRAY_SIZE(orion_uart_resources), | 125 | .num_resources = ARRAY_SIZE(orion5x_uart_resources), |
126 | }; | 126 | }; |
127 | 127 | ||
128 | /******************************************************************************* | 128 | /******************************************************************************* |
129 | * USB Controller - 2 interfaces | 129 | * USB Controller - 2 interfaces |
130 | ******************************************************************************/ | 130 | ******************************************************************************/ |
131 | 131 | ||
132 | static struct resource orion_ehci0_resources[] = { | 132 | static struct resource orion5x_ehci0_resources[] = { |
133 | { | 133 | { |
134 | .start = ORION_USB0_PHYS_BASE, | 134 | .start = ORION5X_USB0_PHYS_BASE, |
135 | .end = ORION_USB0_PHYS_BASE + SZ_4K, | 135 | .end = ORION5X_USB0_PHYS_BASE + SZ_4K, |
136 | .flags = IORESOURCE_MEM, | 136 | .flags = IORESOURCE_MEM, |
137 | }, | 137 | }, |
138 | { | 138 | { |
139 | .start = IRQ_ORION_USB0_CTRL, | 139 | .start = IRQ_ORION5X_USB0_CTRL, |
140 | .end = IRQ_ORION_USB0_CTRL, | 140 | .end = IRQ_ORION5X_USB0_CTRL, |
141 | .flags = IORESOURCE_IRQ, | 141 | .flags = IORESOURCE_IRQ, |
142 | }, | 142 | }, |
143 | }; | 143 | }; |
144 | 144 | ||
145 | static struct resource orion_ehci1_resources[] = { | 145 | static struct resource orion5x_ehci1_resources[] = { |
146 | { | 146 | { |
147 | .start = ORION_USB1_PHYS_BASE, | 147 | .start = ORION5X_USB1_PHYS_BASE, |
148 | .end = ORION_USB1_PHYS_BASE + SZ_4K, | 148 | .end = ORION5X_USB1_PHYS_BASE + SZ_4K, |
149 | .flags = IORESOURCE_MEM, | 149 | .flags = IORESOURCE_MEM, |
150 | }, | 150 | }, |
151 | { | 151 | { |
152 | .start = IRQ_ORION_USB1_CTRL, | 152 | .start = IRQ_ORION5X_USB1_CTRL, |
153 | .end = IRQ_ORION_USB1_CTRL, | 153 | .end = IRQ_ORION5X_USB1_CTRL, |
154 | .flags = IORESOURCE_IRQ, | 154 | .flags = IORESOURCE_IRQ, |
155 | }, | 155 | }, |
156 | }; | 156 | }; |
157 | 157 | ||
158 | static struct orion_ehci_data orion_ehci_data = { | 158 | static struct orion_ehci_data orion5x_ehci_data = { |
159 | .dram = &orion_mbus_dram_info, | 159 | .dram = &orion5x_mbus_dram_info, |
160 | }; | 160 | }; |
161 | 161 | ||
162 | static u64 ehci_dmamask = 0xffffffffUL; | 162 | static u64 ehci_dmamask = 0xffffffffUL; |
163 | 163 | ||
164 | static struct platform_device orion_ehci0 = { | 164 | static struct platform_device orion5x_ehci0 = { |
165 | .name = "orion-ehci", | 165 | .name = "orion-ehci", |
166 | .id = 0, | 166 | .id = 0, |
167 | .dev = { | 167 | .dev = { |
168 | .dma_mask = &ehci_dmamask, | 168 | .dma_mask = &ehci_dmamask, |
169 | .coherent_dma_mask = 0xffffffff, | 169 | .coherent_dma_mask = 0xffffffff, |
170 | .platform_data = &orion_ehci_data, | 170 | .platform_data = &orion5x_ehci_data, |
171 | }, | 171 | }, |
172 | .resource = orion_ehci0_resources, | 172 | .resource = orion5x_ehci0_resources, |
173 | .num_resources = ARRAY_SIZE(orion_ehci0_resources), | 173 | .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), |
174 | }; | 174 | }; |
175 | 175 | ||
176 | static struct platform_device orion_ehci1 = { | 176 | static struct platform_device orion5x_ehci1 = { |
177 | .name = "orion-ehci", | 177 | .name = "orion-ehci", |
178 | .id = 1, | 178 | .id = 1, |
179 | .dev = { | 179 | .dev = { |
180 | .dma_mask = &ehci_dmamask, | 180 | .dma_mask = &ehci_dmamask, |
181 | .coherent_dma_mask = 0xffffffff, | 181 | .coherent_dma_mask = 0xffffffff, |
182 | .platform_data = &orion_ehci_data, | 182 | .platform_data = &orion5x_ehci_data, |
183 | }, | 183 | }, |
184 | .resource = orion_ehci1_resources, | 184 | .resource = orion5x_ehci1_resources, |
185 | .num_resources = ARRAY_SIZE(orion_ehci1_resources), | 185 | .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), |
186 | }; | 186 | }; |
187 | 187 | ||
188 | /***************************************************************************** | 188 | /***************************************************************************** |
@@ -190,42 +190,42 @@ static struct platform_device orion_ehci1 = { | |||
190 | * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) | 190 | * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) |
191 | ****************************************************************************/ | 191 | ****************************************************************************/ |
192 | 192 | ||
193 | static struct resource orion_eth_shared_resources[] = { | 193 | static struct resource orion5x_eth_shared_resources[] = { |
194 | { | 194 | { |
195 | .start = ORION_ETH_PHYS_BASE + 0x2000, | 195 | .start = ORION5X_ETH_PHYS_BASE + 0x2000, |
196 | .end = ORION_ETH_PHYS_BASE + 0x3fff, | 196 | .end = ORION5X_ETH_PHYS_BASE + 0x3fff, |
197 | .flags = IORESOURCE_MEM, | 197 | .flags = IORESOURCE_MEM, |
198 | }, | 198 | }, |
199 | }; | 199 | }; |
200 | 200 | ||
201 | static struct platform_device orion_eth_shared = { | 201 | static struct platform_device orion5x_eth_shared = { |
202 | .name = MV643XX_ETH_SHARED_NAME, | 202 | .name = MV643XX_ETH_SHARED_NAME, |
203 | .id = 0, | 203 | .id = 0, |
204 | .num_resources = 1, | 204 | .num_resources = 1, |
205 | .resource = orion_eth_shared_resources, | 205 | .resource = orion5x_eth_shared_resources, |
206 | }; | 206 | }; |
207 | 207 | ||
208 | static struct resource orion_eth_resources[] = { | 208 | static struct resource orion5x_eth_resources[] = { |
209 | { | 209 | { |
210 | .name = "eth irq", | 210 | .name = "eth irq", |
211 | .start = IRQ_ORION_ETH_SUM, | 211 | .start = IRQ_ORION5X_ETH_SUM, |
212 | .end = IRQ_ORION_ETH_SUM, | 212 | .end = IRQ_ORION5X_ETH_SUM, |
213 | .flags = IORESOURCE_IRQ, | 213 | .flags = IORESOURCE_IRQ, |
214 | } | 214 | } |
215 | }; | 215 | }; |
216 | 216 | ||
217 | static struct platform_device orion_eth = { | 217 | static struct platform_device orion5x_eth = { |
218 | .name = MV643XX_ETH_NAME, | 218 | .name = MV643XX_ETH_NAME, |
219 | .id = 0, | 219 | .id = 0, |
220 | .num_resources = 1, | 220 | .num_resources = 1, |
221 | .resource = orion_eth_resources, | 221 | .resource = orion5x_eth_resources, |
222 | }; | 222 | }; |
223 | 223 | ||
224 | void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data) | 224 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
225 | { | 225 | { |
226 | orion_eth.dev.platform_data = eth_data; | 226 | orion5x_eth.dev.platform_data = eth_data; |
227 | platform_device_register(&orion_eth_shared); | 227 | platform_device_register(&orion5x_eth_shared); |
228 | platform_device_register(&orion_eth); | 228 | platform_device_register(&orion5x_eth); |
229 | } | 229 | } |
230 | 230 | ||
231 | /***************************************************************************** | 231 | /***************************************************************************** |
@@ -233,13 +233,13 @@ void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data) | |||
233 | * (The Orion and Discovery (MV643xx) families share the same I2C controller) | 233 | * (The Orion and Discovery (MV643xx) families share the same I2C controller) |
234 | ****************************************************************************/ | 234 | ****************************************************************************/ |
235 | 235 | ||
236 | static struct mv64xxx_i2c_pdata orion_i2c_pdata = { | 236 | static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { |
237 | .freq_m = 8, /* assumes 166 MHz TCLK */ | 237 | .freq_m = 8, /* assumes 166 MHz TCLK */ |
238 | .freq_n = 3, | 238 | .freq_n = 3, |
239 | .timeout = 1000, /* Default timeout of 1 second */ | 239 | .timeout = 1000, /* Default timeout of 1 second */ |
240 | }; | 240 | }; |
241 | 241 | ||
242 | static struct resource orion_i2c_resources[] = { | 242 | static struct resource orion5x_i2c_resources[] = { |
243 | { | 243 | { |
244 | .name = "i2c base", | 244 | .name = "i2c base", |
245 | .start = I2C_PHYS_BASE, | 245 | .start = I2C_PHYS_BASE, |
@@ -248,68 +248,68 @@ static struct resource orion_i2c_resources[] = { | |||
248 | }, | 248 | }, |
249 | { | 249 | { |
250 | .name = "i2c irq", | 250 | .name = "i2c irq", |
251 | .start = IRQ_ORION_I2C, | 251 | .start = IRQ_ORION5X_I2C, |
252 | .end = IRQ_ORION_I2C, | 252 | .end = IRQ_ORION5X_I2C, |
253 | .flags = IORESOURCE_IRQ, | 253 | .flags = IORESOURCE_IRQ, |
254 | }, | 254 | }, |
255 | }; | 255 | }; |
256 | 256 | ||
257 | static struct platform_device orion_i2c = { | 257 | static struct platform_device orion5x_i2c = { |
258 | .name = MV64XXX_I2C_CTLR_NAME, | 258 | .name = MV64XXX_I2C_CTLR_NAME, |
259 | .id = 0, | 259 | .id = 0, |
260 | .num_resources = ARRAY_SIZE(orion_i2c_resources), | 260 | .num_resources = ARRAY_SIZE(orion5x_i2c_resources), |
261 | .resource = orion_i2c_resources, | 261 | .resource = orion5x_i2c_resources, |
262 | .dev = { | 262 | .dev = { |
263 | .platform_data = &orion_i2c_pdata, | 263 | .platform_data = &orion5x_i2c_pdata, |
264 | }, | 264 | }, |
265 | }; | 265 | }; |
266 | 266 | ||
267 | /***************************************************************************** | 267 | /***************************************************************************** |
268 | * Sata port | 268 | * Sata port |
269 | ****************************************************************************/ | 269 | ****************************************************************************/ |
270 | static struct resource orion_sata_resources[] = { | 270 | static struct resource orion5x_sata_resources[] = { |
271 | { | 271 | { |
272 | .name = "sata base", | 272 | .name = "sata base", |
273 | .start = ORION_SATA_PHYS_BASE, | 273 | .start = ORION5X_SATA_PHYS_BASE, |
274 | .end = ORION_SATA_PHYS_BASE + 0x5000 - 1, | 274 | .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, |
275 | .flags = IORESOURCE_MEM, | 275 | .flags = IORESOURCE_MEM, |
276 | }, | 276 | }, |
277 | { | 277 | { |
278 | .name = "sata irq", | 278 | .name = "sata irq", |
279 | .start = IRQ_ORION_SATA, | 279 | .start = IRQ_ORION5X_SATA, |
280 | .end = IRQ_ORION_SATA, | 280 | .end = IRQ_ORION5X_SATA, |
281 | .flags = IORESOURCE_IRQ, | 281 | .flags = IORESOURCE_IRQ, |
282 | }, | 282 | }, |
283 | }; | 283 | }; |
284 | 284 | ||
285 | static struct platform_device orion_sata = { | 285 | static struct platform_device orion5x_sata = { |
286 | .name = "sata_mv", | 286 | .name = "sata_mv", |
287 | .id = 0, | 287 | .id = 0, |
288 | .dev = { | 288 | .dev = { |
289 | .coherent_dma_mask = 0xffffffff, | 289 | .coherent_dma_mask = 0xffffffff, |
290 | }, | 290 | }, |
291 | .num_resources = ARRAY_SIZE(orion_sata_resources), | 291 | .num_resources = ARRAY_SIZE(orion5x_sata_resources), |
292 | .resource = orion_sata_resources, | 292 | .resource = orion5x_sata_resources, |
293 | }; | 293 | }; |
294 | 294 | ||
295 | void __init orion_sata_init(struct mv_sata_platform_data *sata_data) | 295 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
296 | { | 296 | { |
297 | sata_data->dram = &orion_mbus_dram_info; | 297 | sata_data->dram = &orion5x_mbus_dram_info; |
298 | orion_sata.dev.platform_data = sata_data; | 298 | orion5x_sata.dev.platform_data = sata_data; |
299 | platform_device_register(&orion_sata); | 299 | platform_device_register(&orion5x_sata); |
300 | } | 300 | } |
301 | 301 | ||
302 | /***************************************************************************** | 302 | /***************************************************************************** |
303 | * Time handling | 303 | * Time handling |
304 | ****************************************************************************/ | 304 | ****************************************************************************/ |
305 | 305 | ||
306 | static void orion_timer_init(void) | 306 | static void orion5x_timer_init(void) |
307 | { | 307 | { |
308 | orion_time_init(IRQ_ORION_BRIDGE, ORION_TCLK); | 308 | orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK); |
309 | } | 309 | } |
310 | 310 | ||
311 | struct sys_timer orion_timer = { | 311 | struct sys_timer orion5x_timer = { |
312 | .init = orion_timer_init, | 312 | .init = orion5x_timer_init, |
313 | }; | 313 | }; |
314 | 314 | ||
315 | /***************************************************************************** | 315 | /***************************************************************************** |
@@ -319,9 +319,9 @@ struct sys_timer orion_timer = { | |||
319 | /* | 319 | /* |
320 | * Identify device ID and rev from PCIE configuration header space '0'. | 320 | * Identify device ID and rev from PCIE configuration header space '0'. |
321 | */ | 321 | */ |
322 | static void __init orion_id(u32 *dev, u32 *rev, char **dev_name) | 322 | static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) |
323 | { | 323 | { |
324 | orion_pcie_id(dev, rev); | 324 | orion5x_pcie_id(dev, rev); |
325 | 325 | ||
326 | if (*dev == MV88F5281_DEV_ID) { | 326 | if (*dev == MV88F5281_DEV_ID) { |
327 | if (*rev == MV88F5281_REV_D2) { | 327 | if (*rev == MV88F5281_REV_D2) { |
@@ -348,28 +348,28 @@ static void __init orion_id(u32 *dev, u32 *rev, char **dev_name) | |||
348 | } | 348 | } |
349 | } | 349 | } |
350 | 350 | ||
351 | void __init orion_init(void) | 351 | void __init orion5x_init(void) |
352 | { | 352 | { |
353 | char *dev_name; | 353 | char *dev_name; |
354 | u32 dev, rev; | 354 | u32 dev, rev; |
355 | 355 | ||
356 | orion_id(&dev, &rev, &dev_name); | 356 | orion5x_id(&dev, &rev, &dev_name); |
357 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK); | 357 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK); |
358 | 358 | ||
359 | /* | 359 | /* |
360 | * Setup Orion address map | 360 | * Setup Orion address map |
361 | */ | 361 | */ |
362 | orion_setup_cpu_mbus_bridge(); | 362 | orion5x_setup_cpu_mbus_bridge(); |
363 | orion_setup_eth_wins(); | 363 | orion5x_setup_eth_wins(); |
364 | 364 | ||
365 | /* | 365 | /* |
366 | * Register devices. | 366 | * Register devices. |
367 | */ | 367 | */ |
368 | platform_device_register(&orion_uart); | 368 | platform_device_register(&orion5x_uart); |
369 | platform_device_register(&orion_ehci0); | 369 | platform_device_register(&orion5x_ehci0); |
370 | if (dev == MV88F5182_DEV_ID) | 370 | if (dev == MV88F5182_DEV_ID) |
371 | platform_device_register(&orion_ehci1); | 371 | platform_device_register(&orion5x_ehci1); |
372 | platform_device_register(&orion_i2c); | 372 | platform_device_register(&orion5x_i2c); |
373 | } | 373 | } |
374 | 374 | ||
375 | /* | 375 | /* |
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h new file mode 100644 index 000000000000..f4c4c9a72a7c --- /dev/null +++ b/arch/arm/mach-orion5x/common.h | |||
@@ -0,0 +1,72 @@ | |||
1 | #ifndef __ARCH_ORION5X_COMMON_H | ||
2 | #define __ARCH_ORION5X_COMMON_H | ||
3 | |||
4 | /* | ||
5 | * Basic Orion init functions used early by machine-setup. | ||
6 | */ | ||
7 | |||
8 | void orion5x_map_io(void); | ||
9 | void orion5x_init_irq(void); | ||
10 | void orion5x_init(void); | ||
11 | extern struct sys_timer orion5x_timer; | ||
12 | |||
13 | /* | ||
14 | * Enumerations and functions for Orion windows mapping. Used by Orion core | ||
15 | * functions to map its interfaces and by the machine-setup to map its on- | ||
16 | * board devices. Details in /mach-orion/addr-map.c | ||
17 | */ | ||
18 | extern struct mbus_dram_target_info orion5x_mbus_dram_info; | ||
19 | void orion5x_setup_cpu_mbus_bridge(void); | ||
20 | void orion5x_setup_dev_boot_win(u32 base, u32 size); | ||
21 | void orion5x_setup_dev0_win(u32 base, u32 size); | ||
22 | void orion5x_setup_dev1_win(u32 base, u32 size); | ||
23 | void orion5x_setup_dev2_win(u32 base, u32 size); | ||
24 | void orion5x_setup_pcie_wa_win(u32 base, u32 size); | ||
25 | void orion5x_setup_eth_wins(void); | ||
26 | |||
27 | /* | ||
28 | * Shared code used internally by other Orion core functions. | ||
29 | * (/mach-orion/pci.c) | ||
30 | */ | ||
31 | |||
32 | struct pci_sys_data; | ||
33 | struct pci_bus; | ||
34 | |||
35 | void orion5x_pcie_id(u32 *dev, u32 *rev); | ||
36 | int orion5x_pcie_local_bus_nr(void); | ||
37 | int orion5x_pci_local_bus_nr(void); | ||
38 | int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); | ||
39 | struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); | ||
40 | |||
41 | /* | ||
42 | * Valid GPIO pins according to MPP setup, used by machine-setup. | ||
43 | * (/mach-orion/gpio.c). | ||
44 | */ | ||
45 | |||
46 | void orion5x_gpio_set_valid_pins(u32 pins); | ||
47 | void gpio_display(void); /* debug */ | ||
48 | |||
49 | /* | ||
50 | * Pull in Orion Ethernet platform_data, used by machine-setup | ||
51 | */ | ||
52 | |||
53 | struct mv643xx_eth_platform_data; | ||
54 | |||
55 | void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data); | ||
56 | |||
57 | /* | ||
58 | * Orion Sata platform_data, used by machine-setup | ||
59 | */ | ||
60 | |||
61 | struct mv_sata_platform_data; | ||
62 | |||
63 | void orion5x_sata_init(struct mv_sata_platform_data *sata_data); | ||
64 | |||
65 | struct machine_desc; | ||
66 | struct meminfo; | ||
67 | struct tag; | ||
68 | extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *, | ||
69 | char **, struct meminfo *); | ||
70 | |||
71 | |||
72 | #endif | ||
diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index a0a9e4851b5f..872aed372327 100644 --- a/arch/arm/mach-orion/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-orion/db88f5281-setup.c | 2 | * arch/arm/mach-orion5x/db88f5281-setup.c |
3 | * | 3 | * |
4 | * Marvell Orion-2 Development Board Setup | 4 | * Marvell Orion-2 Development Board Setup |
5 | * | 5 | * |
@@ -24,7 +24,7 @@ | |||
24 | #include <asm/gpio.h> | 24 | #include <asm/gpio.h> |
25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
26 | #include <asm/mach/pci.h> | 26 | #include <asm/mach/pci.h> |
27 | #include <asm/arch/orion.h> | 27 | #include <asm/arch/orion5x.h> |
28 | #include <asm/plat-orion/orion_nand.h> | 28 | #include <asm/plat-orion/orion_nand.h> |
29 | #include "common.h" | 29 | #include "common.h" |
30 | 30 | ||
@@ -244,8 +244,8 @@ static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
244 | /* | 244 | /* |
245 | * PCIE IRQ is connected internally (not GPIO) | 245 | * PCIE IRQ is connected internally (not GPIO) |
246 | */ | 246 | */ |
247 | if (dev->bus->number == orion_pcie_local_bus_nr()) | 247 | if (dev->bus->number == orion5x_pcie_local_bus_nr()) |
248 | return IRQ_ORION_PCIE0_INT; | 248 | return IRQ_ORION5X_PCIE0_INT; |
249 | 249 | ||
250 | /* | 250 | /* |
251 | * PCI IRQs are connected via GPIOs | 251 | * PCI IRQs are connected via GPIOs |
@@ -265,8 +265,8 @@ static struct hw_pci db88f5281_pci __initdata = { | |||
265 | .nr_controllers = 2, | 265 | .nr_controllers = 2, |
266 | .preinit = db88f5281_pci_preinit, | 266 | .preinit = db88f5281_pci_preinit, |
267 | .swizzle = pci_std_swizzle, | 267 | .swizzle = pci_std_swizzle, |
268 | .setup = orion_pci_sys_setup, | 268 | .setup = orion5x_pci_sys_setup, |
269 | .scan = orion_pci_sys_scan_bus, | 269 | .scan = orion5x_pci_sys_scan_bus, |
270 | .map_irq = db88f5281_pci_map_irq, | 270 | .map_irq = db88f5281_pci_map_irq, |
271 | }; | 271 | }; |
272 | 272 | ||
@@ -312,16 +312,16 @@ static void __init db88f5281_init(void) | |||
312 | /* | 312 | /* |
313 | * Basic Orion setup. Need to be called early. | 313 | * Basic Orion setup. Need to be called early. |
314 | */ | 314 | */ |
315 | orion_init(); | 315 | orion5x_init(); |
316 | 316 | ||
317 | /* | 317 | /* |
318 | * Setup the CPU address decode windows for our on-board devices | 318 | * Setup the CPU address decode windows for our on-board devices |
319 | */ | 319 | */ |
320 | orion_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, | 320 | orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, |
321 | DB88F5281_NOR_BOOT_SIZE); | 321 | DB88F5281_NOR_BOOT_SIZE); |
322 | orion_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); | 322 | orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); |
323 | orion_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); | 323 | orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); |
324 | orion_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); | 324 | orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); |
325 | 325 | ||
326 | /* | 326 | /* |
327 | * Setup Multiplexing Pins: | 327 | * Setup Multiplexing Pins: |
@@ -337,25 +337,25 @@ static void __init db88f5281_init(void) | |||
337 | * MPP18: UART1_CTS MPP19: UART1_RTS | 337 | * MPP18: UART1_CTS MPP19: UART1_RTS |
338 | * MPP-DEV: DEV_D[16:31] | 338 | * MPP-DEV: DEV_D[16:31] |
339 | */ | 339 | */ |
340 | orion_write(MPP_0_7_CTRL, 0x00222203); | 340 | orion5x_write(MPP_0_7_CTRL, 0x00222203); |
341 | orion_write(MPP_8_15_CTRL, 0x44000000); | 341 | orion5x_write(MPP_8_15_CTRL, 0x44000000); |
342 | orion_write(MPP_16_19_CTRL, 0); | 342 | orion5x_write(MPP_16_19_CTRL, 0); |
343 | orion_write(MPP_DEV_CTRL, 0); | 343 | orion5x_write(MPP_DEV_CTRL, 0); |
344 | 344 | ||
345 | orion_gpio_set_valid_pins(0x00003fc3); | 345 | orion5x_gpio_set_valid_pins(0x00003fc3); |
346 | 346 | ||
347 | platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs)); | 347 | platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs)); |
348 | i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); | 348 | i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); |
349 | orion_eth_init(&db88f5281_eth_data); | 349 | orion5x_eth_init(&db88f5281_eth_data); |
350 | } | 350 | } |
351 | 351 | ||
352 | MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") | 352 | MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") |
353 | /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */ | 353 | /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */ |
354 | .phys_io = ORION_REGS_PHYS_BASE, | 354 | .phys_io = ORION5X_REGS_PHYS_BASE, |
355 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc, | 355 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc, |
356 | .boot_params = 0x00000100, | 356 | .boot_params = 0x00000100, |
357 | .init_machine = db88f5281_init, | 357 | .init_machine = db88f5281_init, |
358 | .map_io = orion_map_io, | 358 | .map_io = orion5x_map_io, |
359 | .init_irq = orion_init_irq, | 359 | .init_irq = orion5x_init_irq, |
360 | .timer = &orion_timer, | 360 | .timer = &orion5x_timer, |
361 | MACHINE_END | 361 | MACHINE_END |
diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 88991f764794..d67790ef236e 100644 --- a/arch/arm/mach-orion/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-orion/dns323-setup.c | 2 | * arch/arm/mach-orion5x/dns323-setup.c |
3 | * | 3 | * |
4 | * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> | 4 | * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> |
5 | * | 5 | * |
@@ -25,7 +25,7 @@ | |||
25 | #include <asm/gpio.h> | 25 | #include <asm/gpio.h> |
26 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
27 | #include <asm/mach/pci.h> | 27 | #include <asm/mach/pci.h> |
28 | #include <asm/arch/orion.h> | 28 | #include <asm/arch/orion5x.h> |
29 | #include "common.h" | 29 | #include "common.h" |
30 | 30 | ||
31 | #define DNS323_GPIO_LED_RIGHT_AMBER 1 | 31 | #define DNS323_GPIO_LED_RIGHT_AMBER 1 |
@@ -44,8 +44,8 @@ | |||
44 | static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 44 | static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
45 | { | 45 | { |
46 | /* PCI-E */ | 46 | /* PCI-E */ |
47 | if (dev->bus->number == orion_pcie_local_bus_nr()) | 47 | if (dev->bus->number == orion5x_pcie_local_bus_nr()) |
48 | return IRQ_ORION_PCIE0_INT; | 48 | return IRQ_ORION5X_PCIE0_INT; |
49 | 49 | ||
50 | pr_err("%s: requested mapping for unknown bus\n", __func__); | 50 | pr_err("%s: requested mapping for unknown bus\n", __func__); |
51 | 51 | ||
@@ -55,8 +55,8 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
55 | static struct hw_pci dns323_pci __initdata = { | 55 | static struct hw_pci dns323_pci __initdata = { |
56 | .nr_controllers = 1, | 56 | .nr_controllers = 1, |
57 | .swizzle = pci_std_swizzle, | 57 | .swizzle = pci_std_swizzle, |
58 | .setup = orion_pci_sys_setup, | 58 | .setup = orion5x_pci_sys_setup, |
59 | .scan = orion_pci_sys_scan_bus, | 59 | .scan = orion5x_pci_sys_scan_bus, |
60 | .map_irq = dns323_pci_map_irq, | 60 | .map_irq = dns323_pci_map_irq, |
61 | }; | 61 | }; |
62 | 62 | ||
@@ -246,24 +246,25 @@ static void dns323_power_off(void) | |||
246 | static void __init dns323_init(void) | 246 | static void __init dns323_init(void) |
247 | { | 247 | { |
248 | /* Setup basic Orion functions. Need to be called early. */ | 248 | /* Setup basic Orion functions. Need to be called early. */ |
249 | orion_init(); | 249 | orion5x_init(); |
250 | 250 | ||
251 | /* setup flash mapping | 251 | /* setup flash mapping |
252 | * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 | 252 | * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 |
253 | */ | 253 | */ |
254 | orion_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); | 254 | orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); |
255 | 255 | ||
256 | /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE | 256 | /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE |
257 | * | 257 | * |
258 | * Open a special address decode windows for the PCIE WA. | 258 | * Open a special address decode windows for the PCIE WA. |
259 | */ | 259 | */ |
260 | orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); | 260 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
261 | ORION5X_PCIE_WA_SIZE); | ||
261 | 262 | ||
262 | /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ | 263 | /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ |
263 | orion_write(MPP_0_7_CTRL, 0); | 264 | orion5x_write(MPP_0_7_CTRL, 0); |
264 | orion_write(MPP_8_15_CTRL, 0); | 265 | orion5x_write(MPP_8_15_CTRL, 0); |
265 | orion_write(MPP_16_19_CTRL, 0); | 266 | orion5x_write(MPP_16_19_CTRL, 0); |
266 | orion_write(MPP_DEV_CTRL, 0); | 267 | orion5x_write(MPP_DEV_CTRL, 0); |
267 | 268 | ||
268 | /* Define used GPIO pins | 269 | /* Define used GPIO pins |
269 | 270 | ||
@@ -286,7 +287,7 @@ static void __init dns323_init(void) | |||
286 | | 14 | Out | //unknown// | 287 | | 14 | Out | //unknown// |
287 | | 15 | Out | //unknown// | 288 | | 15 | Out | //unknown// |
288 | */ | 289 | */ |
289 | orion_gpio_set_valid_pins(0x07f6); | 290 | orion5x_gpio_set_valid_pins(0x07f6); |
290 | 291 | ||
291 | /* register dns323 specific power-off method */ | 292 | /* register dns323 specific power-off method */ |
292 | if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0) | 293 | if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0) |
@@ -302,18 +303,18 @@ static void __init dns323_init(void) | |||
302 | i2c_register_board_info(0, dns323_i2c_devices, | 303 | i2c_register_board_info(0, dns323_i2c_devices, |
303 | ARRAY_SIZE(dns323_i2c_devices)); | 304 | ARRAY_SIZE(dns323_i2c_devices)); |
304 | 305 | ||
305 | orion_eth_init(&dns323_eth_data); | 306 | orion5x_eth_init(&dns323_eth_data); |
306 | } | 307 | } |
307 | 308 | ||
308 | /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ | 309 | /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ |
309 | MACHINE_START(DNS323, "D-Link DNS-323") | 310 | MACHINE_START(DNS323, "D-Link DNS-323") |
310 | /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ | 311 | /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ |
311 | .phys_io = ORION_REGS_PHYS_BASE, | 312 | .phys_io = ORION5X_REGS_PHYS_BASE, |
312 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, | 313 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, |
313 | .boot_params = 0x00000100, | 314 | .boot_params = 0x00000100, |
314 | .init_machine = dns323_init, | 315 | .init_machine = dns323_init, |
315 | .map_io = orion_map_io, | 316 | .map_io = orion5x_map_io, |
316 | .init_irq = orion_init_irq, | 317 | .init_irq = orion5x_init_irq, |
317 | .timer = &orion_timer, | 318 | .timer = &orion5x_timer, |
318 | .fixup = tag_fixup_mem32, | 319 | .fixup = tag_fixup_mem32, |
319 | MACHINE_END | 320 | MACHINE_END |
diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion5x/gpio.c index afc7be08b30f..8108c316c426 100644 --- a/arch/arm/mach-orion/gpio.c +++ b/arch/arm/mach-orion5x/gpio.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-orion/gpio.c | 2 | * arch/arm/mach-orion5x/gpio.c |
3 | * | 3 | * |
4 | * GPIO functions for Marvell Orion System On Chip | 4 | * GPIO functions for Marvell Orion System On Chip |
5 | * | 5 | * |
@@ -17,14 +17,14 @@ | |||
17 | #include <linux/bitops.h> | 17 | #include <linux/bitops.h> |
18 | #include <asm/gpio.h> | 18 | #include <asm/gpio.h> |
19 | #include <asm/io.h> | 19 | #include <asm/io.h> |
20 | #include <asm/arch/orion.h> | 20 | #include <asm/arch/orion5x.h> |
21 | #include "common.h" | 21 | #include "common.h" |
22 | 22 | ||
23 | static DEFINE_SPINLOCK(gpio_lock); | 23 | static DEFINE_SPINLOCK(gpio_lock); |
24 | static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; | 24 | static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; |
25 | static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ | 25 | static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ |
26 | 26 | ||
27 | void __init orion_gpio_set_valid_pins(u32 pins) | 27 | void __init orion5x_gpio_set_valid_pins(u32 pins) |
28 | { | 28 | { |
29 | gpio_valid[0] = pins; | 29 | gpio_valid[0] = pins; |
30 | } | 30 | } |
@@ -50,7 +50,7 @@ int gpio_direction_input(unsigned pin) | |||
50 | if (!gpio_label[pin]) | 50 | if (!gpio_label[pin]) |
51 | gpio_label[pin] = "?"; | 51 | gpio_label[pin] = "?"; |
52 | 52 | ||
53 | orion_setbits(GPIO_IO_CONF, 1 << pin); | 53 | orion5x_setbits(GPIO_IO_CONF, 1 << pin); |
54 | 54 | ||
55 | spin_unlock_irqrestore(&gpio_lock, flags); | 55 | spin_unlock_irqrestore(&gpio_lock, flags); |
56 | return 0; | 56 | return 0; |
@@ -77,12 +77,12 @@ int gpio_direction_output(unsigned pin, int value) | |||
77 | gpio_label[pin] = "?"; | 77 | gpio_label[pin] = "?"; |
78 | 78 | ||
79 | mask = 1 << pin; | 79 | mask = 1 << pin; |
80 | orion_clrbits(GPIO_BLINK_EN, mask); | 80 | orion5x_clrbits(GPIO_BLINK_EN, mask); |
81 | if (value) | 81 | if (value) |
82 | orion_setbits(GPIO_OUT, mask); | 82 | orion5x_setbits(GPIO_OUT, mask); |
83 | else | 83 | else |
84 | orion_clrbits(GPIO_OUT, mask); | 84 | orion5x_clrbits(GPIO_OUT, mask); |
85 | orion_clrbits(GPIO_IO_CONF, mask); | 85 | orion5x_clrbits(GPIO_IO_CONF, mask); |
86 | 86 | ||
87 | spin_unlock_irqrestore(&gpio_lock, flags); | 87 | spin_unlock_irqrestore(&gpio_lock, flags); |
88 | return 0; | 88 | return 0; |
@@ -93,10 +93,10 @@ int gpio_get_value(unsigned pin) | |||
93 | { | 93 | { |
94 | int val, mask = 1 << pin; | 94 | int val, mask = 1 << pin; |
95 | 95 | ||
96 | if (orion_read(GPIO_IO_CONF) & mask) | 96 | if (orion5x_read(GPIO_IO_CONF) & mask) |
97 | val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL); | 97 | val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL); |
98 | else | 98 | else |
99 | val = orion_read(GPIO_OUT); | 99 | val = orion5x_read(GPIO_OUT); |
100 | 100 | ||
101 | return val & mask; | 101 | return val & mask; |
102 | } | 102 | } |
@@ -109,32 +109,32 @@ void gpio_set_value(unsigned pin, int value) | |||
109 | 109 | ||
110 | spin_lock_irqsave(&gpio_lock, flags); | 110 | spin_lock_irqsave(&gpio_lock, flags); |
111 | 111 | ||
112 | orion_clrbits(GPIO_BLINK_EN, mask); | 112 | orion5x_clrbits(GPIO_BLINK_EN, mask); |
113 | if (value) | 113 | if (value) |
114 | orion_setbits(GPIO_OUT, mask); | 114 | orion5x_setbits(GPIO_OUT, mask); |
115 | else | 115 | else |
116 | orion_clrbits(GPIO_OUT, mask); | 116 | orion5x_clrbits(GPIO_OUT, mask); |
117 | 117 | ||
118 | spin_unlock_irqrestore(&gpio_lock, flags); | 118 | spin_unlock_irqrestore(&gpio_lock, flags); |
119 | } | 119 | } |
120 | EXPORT_SYMBOL(gpio_set_value); | 120 | EXPORT_SYMBOL(gpio_set_value); |
121 | 121 | ||
122 | void orion_gpio_set_blink(unsigned pin, int blink) | 122 | void orion5x_gpio_set_blink(unsigned pin, int blink) |
123 | { | 123 | { |
124 | unsigned long flags; | 124 | unsigned long flags; |
125 | int mask = 1 << pin; | 125 | int mask = 1 << pin; |
126 | 126 | ||
127 | spin_lock_irqsave(&gpio_lock, flags); | 127 | spin_lock_irqsave(&gpio_lock, flags); |
128 | 128 | ||
129 | orion_clrbits(GPIO_OUT, mask); | 129 | orion5x_clrbits(GPIO_OUT, mask); |
130 | if (blink) | 130 | if (blink) |
131 | orion_setbits(GPIO_BLINK_EN, mask); | 131 | orion5x_setbits(GPIO_BLINK_EN, mask); |
132 | else | 132 | else |
133 | orion_clrbits(GPIO_BLINK_EN, mask); | 133 | orion5x_clrbits(GPIO_BLINK_EN, mask); |
134 | 134 | ||
135 | spin_unlock_irqrestore(&gpio_lock, flags); | 135 | spin_unlock_irqrestore(&gpio_lock, flags); |
136 | } | 136 | } |
137 | EXPORT_SYMBOL(orion_gpio_set_blink); | 137 | EXPORT_SYMBOL(orion5x_gpio_set_blink); |
138 | 138 | ||
139 | int gpio_request(unsigned pin, const char *label) | 139 | int gpio_request(unsigned pin, const char *label) |
140 | { | 140 | { |
@@ -188,39 +188,39 @@ void gpio_display(void) | |||
188 | printk("GPIO, free\n"); | 188 | printk("GPIO, free\n"); |
189 | } else { | 189 | } else { |
190 | printk("GPIO, used by %s, ", gpio_label[i]); | 190 | printk("GPIO, used by %s, ", gpio_label[i]); |
191 | if (orion_read(GPIO_IO_CONF) & (1 << i)) { | 191 | if (orion5x_read(GPIO_IO_CONF) & (1 << i)) { |
192 | printk("input, active %s, level %s, edge %s\n", | 192 | printk("input, active %s, level %s, edge %s\n", |
193 | ((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", | 193 | ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", |
194 | ((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", | 194 | ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", |
195 | ((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); | 195 | ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); |
196 | } else { | 196 | } else { |
197 | printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1); | 197 | printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1); |
198 | } | 198 | } |
199 | } | 199 | } |
200 | } | 200 | } |
201 | 201 | ||
202 | printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", | 202 | printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", |
203 | MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL)); | 203 | MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL)); |
204 | printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", | 204 | printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", |
205 | MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL)); | 205 | MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL)); |
206 | printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", | 206 | printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", |
207 | MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL)); | 207 | MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL)); |
208 | printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", | 208 | printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", |
209 | MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL)); | 209 | MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL)); |
210 | printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", | 210 | printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", |
211 | GPIO_OUT, orion_read(GPIO_OUT)); | 211 | GPIO_OUT, orion5x_read(GPIO_OUT)); |
212 | printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", | 212 | printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", |
213 | GPIO_IO_CONF, orion_read(GPIO_IO_CONF)); | 213 | GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF)); |
214 | printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", | 214 | printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", |
215 | GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN)); | 215 | GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN)); |
216 | printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", | 216 | printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", |
217 | GPIO_IN_POL, orion_read(GPIO_IN_POL)); | 217 | GPIO_IN_POL, orion5x_read(GPIO_IN_POL)); |
218 | printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", | 218 | printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", |
219 | GPIO_DATA_IN, orion_read(GPIO_DATA_IN)); | 219 | GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN)); |
220 | printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", | 220 | printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", |
221 | GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK)); | 221 | GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK)); |
222 | printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", | 222 | printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", |
223 | GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE)); | 223 | GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE)); |
224 | printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", | 224 | printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", |
225 | GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK)); | 225 | GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK)); |
226 | } | 226 | } |
diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion5x/irq.c index 7033cc1360ec..dd21f38c5d37 100644 --- a/arch/arm/mach-orion/irq.c +++ b/arch/arm/mach-orion5x/irq.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-orion/irq.c | 2 | * arch/arm/mach-orion5x/irq.c |
3 | * | 3 | * |
4 | * Core IRQ functions for Marvell Orion System On Chip | 4 | * Core IRQ functions for Marvell Orion System On Chip |
5 | * | 5 | * |
@@ -15,7 +15,7 @@ | |||
15 | #include <linux/irq.h> | 15 | #include <linux/irq.h> |
16 | #include <asm/gpio.h> | 16 | #include <asm/gpio.h> |
17 | #include <asm/io.h> | 17 | #include <asm/io.h> |
18 | #include <asm/arch/orion.h> | 18 | #include <asm/arch/orion5x.h> |
19 | #include <asm/plat-orion/irq.h> | 19 | #include <asm/plat-orion/irq.h> |
20 | #include "common.h" | 20 | #include "common.h" |
21 | 21 | ||
@@ -44,46 +44,46 @@ | |||
44 | * polarity LEVEL mask | 44 | * polarity LEVEL mask |
45 | * | 45 | * |
46 | ****************************************************************************/ | 46 | ****************************************************************************/ |
47 | static void orion_gpio_irq_ack(u32 irq) | 47 | static void orion5x_gpio_irq_ack(u32 irq) |
48 | { | 48 | { |
49 | int pin = irq_to_gpio(irq); | 49 | int pin = irq_to_gpio(irq); |
50 | if (irq_desc[irq].status & IRQ_LEVEL) | 50 | if (irq_desc[irq].status & IRQ_LEVEL) |
51 | /* | 51 | /* |
52 | * Mask bit for level interrupt | 52 | * Mask bit for level interrupt |
53 | */ | 53 | */ |
54 | orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); | 54 | orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); |
55 | else | 55 | else |
56 | /* | 56 | /* |
57 | * Clear casue bit for egde interrupt | 57 | * Clear casue bit for egde interrupt |
58 | */ | 58 | */ |
59 | orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin); | 59 | orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin); |
60 | } | 60 | } |
61 | 61 | ||
62 | static void orion_gpio_irq_mask(u32 irq) | 62 | static void orion5x_gpio_irq_mask(u32 irq) |
63 | { | 63 | { |
64 | int pin = irq_to_gpio(irq); | 64 | int pin = irq_to_gpio(irq); |
65 | if (irq_desc[irq].status & IRQ_LEVEL) | 65 | if (irq_desc[irq].status & IRQ_LEVEL) |
66 | orion_clrbits(GPIO_LEVEL_MASK, 1 << pin); | 66 | orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin); |
67 | else | 67 | else |
68 | orion_clrbits(GPIO_EDGE_MASK, 1 << pin); | 68 | orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin); |
69 | } | 69 | } |
70 | 70 | ||
71 | static void orion_gpio_irq_unmask(u32 irq) | 71 | static void orion5x_gpio_irq_unmask(u32 irq) |
72 | { | 72 | { |
73 | int pin = irq_to_gpio(irq); | 73 | int pin = irq_to_gpio(irq); |
74 | if (irq_desc[irq].status & IRQ_LEVEL) | 74 | if (irq_desc[irq].status & IRQ_LEVEL) |
75 | orion_setbits(GPIO_LEVEL_MASK, 1 << pin); | 75 | orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin); |
76 | else | 76 | else |
77 | orion_setbits(GPIO_EDGE_MASK, 1 << pin); | 77 | orion5x_setbits(GPIO_EDGE_MASK, 1 << pin); |
78 | } | 78 | } |
79 | 79 | ||
80 | static int orion_gpio_set_irq_type(u32 irq, u32 type) | 80 | static int orion5x_gpio_set_irq_type(u32 irq, u32 type) |
81 | { | 81 | { |
82 | int pin = irq_to_gpio(irq); | 82 | int pin = irq_to_gpio(irq); |
83 | struct irq_desc *desc; | 83 | struct irq_desc *desc; |
84 | 84 | ||
85 | if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) { | 85 | if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) { |
86 | printk(KERN_ERR "orion_gpio_set_irq_type failed " | 86 | printk(KERN_ERR "orion5x_gpio_set_irq_type failed " |
87 | "(irq %d, pin %d).\n", irq, pin); | 87 | "(irq %d, pin %d).\n", irq, pin); |
88 | return -EINVAL; | 88 | return -EINVAL; |
89 | } | 89 | } |
@@ -94,22 +94,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) | |||
94 | case IRQT_HIGH: | 94 | case IRQT_HIGH: |
95 | desc->handle_irq = handle_level_irq; | 95 | desc->handle_irq = handle_level_irq; |
96 | desc->status |= IRQ_LEVEL; | 96 | desc->status |= IRQ_LEVEL; |
97 | orion_clrbits(GPIO_IN_POL, (1 << pin)); | 97 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); |
98 | break; | 98 | break; |
99 | case IRQT_LOW: | 99 | case IRQT_LOW: |
100 | desc->handle_irq = handle_level_irq; | 100 | desc->handle_irq = handle_level_irq; |
101 | desc->status |= IRQ_LEVEL; | 101 | desc->status |= IRQ_LEVEL; |
102 | orion_setbits(GPIO_IN_POL, (1 << pin)); | 102 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); |
103 | break; | 103 | break; |
104 | case IRQT_RISING: | 104 | case IRQT_RISING: |
105 | desc->handle_irq = handle_edge_irq; | 105 | desc->handle_irq = handle_edge_irq; |
106 | desc->status &= ~IRQ_LEVEL; | 106 | desc->status &= ~IRQ_LEVEL; |
107 | orion_clrbits(GPIO_IN_POL, (1 << pin)); | 107 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); |
108 | break; | 108 | break; |
109 | case IRQT_FALLING: | 109 | case IRQT_FALLING: |
110 | desc->handle_irq = handle_edge_irq; | 110 | desc->handle_irq = handle_edge_irq; |
111 | desc->status &= ~IRQ_LEVEL; | 111 | desc->status &= ~IRQ_LEVEL; |
112 | orion_setbits(GPIO_IN_POL, (1 << pin)); | 112 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); |
113 | break; | 113 | break; |
114 | case IRQT_BOTHEDGE: | 114 | case IRQT_BOTHEDGE: |
115 | desc->handle_irq = handle_edge_irq; | 115 | desc->handle_irq = handle_edge_irq; |
@@ -117,11 +117,11 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) | |||
117 | /* | 117 | /* |
118 | * set initial polarity based on current input level | 118 | * set initial polarity based on current input level |
119 | */ | 119 | */ |
120 | if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN)) | 120 | if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN)) |
121 | & (1 << pin)) | 121 | & (1 << pin)) |
122 | orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ | 122 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ |
123 | else | 123 | else |
124 | orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ | 124 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */ |
125 | 125 | ||
126 | break; | 126 | break; |
127 | default: | 127 | default: |
@@ -135,22 +135,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type) | |||
135 | return 0; | 135 | return 0; |
136 | } | 136 | } |
137 | 137 | ||
138 | static struct irq_chip orion_gpio_irq_chip = { | 138 | static struct irq_chip orion5x_gpio_irq_chip = { |
139 | .name = "Orion-IRQ-GPIO", | 139 | .name = "Orion-IRQ-GPIO", |
140 | .ack = orion_gpio_irq_ack, | 140 | .ack = orion5x_gpio_irq_ack, |
141 | .mask = orion_gpio_irq_mask, | 141 | .mask = orion5x_gpio_irq_mask, |
142 | .unmask = orion_gpio_irq_unmask, | 142 | .unmask = orion5x_gpio_irq_unmask, |
143 | .set_type = orion_gpio_set_irq_type, | 143 | .set_type = orion5x_gpio_set_irq_type, |
144 | }; | 144 | }; |
145 | 145 | ||
146 | static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | 146 | static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
147 | { | 147 | { |
148 | u32 cause, offs, pin; | 148 | u32 cause, offs, pin; |
149 | 149 | ||
150 | BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31); | 150 | BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); |
151 | offs = (irq - IRQ_ORION_GPIO_0_7) * 8; | 151 | offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8; |
152 | cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) | | 152 | cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) | |
153 | (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK)); | 153 | (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK)); |
154 | 154 | ||
155 | for (pin = offs; pin < offs + 8; pin++) { | 155 | for (pin = offs; pin < offs + 8; pin++) { |
156 | if (cause & (1 << pin)) { | 156 | if (cause & (1 << pin)) { |
@@ -158,16 +158,16 @@ static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
158 | desc = irq_desc + irq; | 158 | desc = irq_desc + irq; |
159 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { | 159 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { |
160 | /* Swap polarity (race with GPIO line) */ | 160 | /* Swap polarity (race with GPIO line) */ |
161 | u32 polarity = orion_read(GPIO_IN_POL); | 161 | u32 polarity = orion5x_read(GPIO_IN_POL); |
162 | polarity ^= 1 << pin; | 162 | polarity ^= 1 << pin; |
163 | orion_write(GPIO_IN_POL, polarity); | 163 | orion5x_write(GPIO_IN_POL, polarity); |
164 | } | 164 | } |
165 | desc_handle_irq(irq, desc); | 165 | desc_handle_irq(irq, desc); |
166 | } | 166 | } |
167 | } | 167 | } |
168 | } | 168 | } |
169 | 169 | ||
170 | static void __init orion_init_gpio_irq(void) | 170 | static void __init orion5x_init_gpio_irq(void) |
171 | { | 171 | { |
172 | int i; | 172 | int i; |
173 | struct irq_desc *desc; | 173 | struct irq_desc *desc; |
@@ -175,37 +175,37 @@ static void __init orion_init_gpio_irq(void) | |||
175 | /* | 175 | /* |
176 | * Mask and clear GPIO IRQ interrupts | 176 | * Mask and clear GPIO IRQ interrupts |
177 | */ | 177 | */ |
178 | orion_write(GPIO_LEVEL_MASK, 0x0); | 178 | orion5x_write(GPIO_LEVEL_MASK, 0x0); |
179 | orion_write(GPIO_EDGE_MASK, 0x0); | 179 | orion5x_write(GPIO_EDGE_MASK, 0x0); |
180 | orion_write(GPIO_EDGE_CAUSE, 0x0); | 180 | orion5x_write(GPIO_EDGE_CAUSE, 0x0); |
181 | 181 | ||
182 | /* | 182 | /* |
183 | * Register chained level handlers for GPIO IRQs by default. | 183 | * Register chained level handlers for GPIO IRQs by default. |
184 | * User can use set_type() if he wants to use edge types handlers. | 184 | * User can use set_type() if he wants to use edge types handlers. |
185 | */ | 185 | */ |
186 | for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) { | 186 | for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) { |
187 | set_irq_chip(i, &orion_gpio_irq_chip); | 187 | set_irq_chip(i, &orion5x_gpio_irq_chip); |
188 | set_irq_handler(i, handle_level_irq); | 188 | set_irq_handler(i, handle_level_irq); |
189 | desc = irq_desc + i; | 189 | desc = irq_desc + i; |
190 | desc->status |= IRQ_LEVEL; | 190 | desc->status |= IRQ_LEVEL; |
191 | set_irq_flags(i, IRQF_VALID); | 191 | set_irq_flags(i, IRQF_VALID); |
192 | } | 192 | } |
193 | set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler); | 193 | set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler); |
194 | set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler); | 194 | set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler); |
195 | set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler); | 195 | set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler); |
196 | set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler); | 196 | set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler); |
197 | } | 197 | } |
198 | 198 | ||
199 | /***************************************************************************** | 199 | /***************************************************************************** |
200 | * Orion Main IRQ | 200 | * Orion Main IRQ |
201 | ****************************************************************************/ | 201 | ****************************************************************************/ |
202 | static void __init orion_init_main_irq(void) | 202 | static void __init orion5x_init_main_irq(void) |
203 | { | 203 | { |
204 | orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); | 204 | orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); |
205 | } | 205 | } |
206 | 206 | ||
207 | void __init orion_init_irq(void) | 207 | void __init orion5x_init_irq(void) |
208 | { | 208 | { |
209 | orion_init_main_irq(); | 209 | orion5x_init_main_irq(); |
210 | orion_init_gpio_irq(); | 210 | orion5x_init_gpio_irq(); |
211 | } | 211 | } |
diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index be417e7f423d..8ad4390b4b7b 100644 --- a/arch/arm/mach-orion/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-orion/kurobox_pro-setup.c | 2 | * arch/arm/mach-orion5x/kurobox_pro-setup.c |
3 | * | 3 | * |
4 | * Maintainer: Ronen Shitrit <rshitrit@marvell.com> | 4 | * Maintainer: Ronen Shitrit <rshitrit@marvell.com> |
5 | * | 5 | * |
@@ -22,7 +22,7 @@ | |||
22 | #include <asm/gpio.h> | 22 | #include <asm/gpio.h> |
23 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
24 | #include <asm/mach/pci.h> | 24 | #include <asm/mach/pci.h> |
25 | #include <asm/arch/orion.h> | 25 | #include <asm/arch/orion5x.h> |
26 | #include <asm/plat-orion/orion_nand.h> | 26 | #include <asm/plat-orion/orion_nand.h> |
27 | #include "common.h" | 27 | #include "common.h" |
28 | 28 | ||
@@ -123,8 +123,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
123 | /* | 123 | /* |
124 | * PCI isn't used on the Kuro | 124 | * PCI isn't used on the Kuro |
125 | */ | 125 | */ |
126 | if (dev->bus->number == orion_pcie_local_bus_nr()) | 126 | if (dev->bus->number == orion5x_pcie_local_bus_nr()) |
127 | return IRQ_ORION_PCIE0_INT; | 127 | return IRQ_ORION5X_PCIE0_INT; |
128 | else | 128 | else |
129 | printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); | 129 | printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); |
130 | 130 | ||
@@ -134,8 +134,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
134 | static struct hw_pci kurobox_pro_pci __initdata = { | 134 | static struct hw_pci kurobox_pro_pci __initdata = { |
135 | .nr_controllers = 1, | 135 | .nr_controllers = 1, |
136 | .swizzle = pci_std_swizzle, | 136 | .swizzle = pci_std_swizzle, |
137 | .setup = orion_pci_sys_setup, | 137 | .setup = orion5x_pci_sys_setup, |
138 | .scan = orion_pci_sys_scan_bus, | 138 | .scan = orion5x_pci_sys_scan_bus, |
139 | .map_irq = kurobox_pro_pci_map_irq, | 139 | .map_irq = kurobox_pro_pci_map_irq, |
140 | }; | 140 | }; |
141 | 141 | ||
@@ -188,19 +188,20 @@ static void __init kurobox_pro_init(void) | |||
188 | /* | 188 | /* |
189 | * Setup basic Orion functions. Need to be called early. | 189 | * Setup basic Orion functions. Need to be called early. |
190 | */ | 190 | */ |
191 | orion_init(); | 191 | orion5x_init(); |
192 | 192 | ||
193 | /* | 193 | /* |
194 | * Setup the CPU address decode windows for our devices | 194 | * Setup the CPU address decode windows for our devices |
195 | */ | 195 | */ |
196 | orion_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, | 196 | orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, |
197 | KUROBOX_PRO_NOR_BOOT_SIZE); | 197 | KUROBOX_PRO_NOR_BOOT_SIZE); |
198 | orion_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); | 198 | orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); |
199 | 199 | ||
200 | /* | 200 | /* |
201 | * Open a special address decode windows for the PCIE WA. | 201 | * Open a special address decode windows for the PCIE WA. |
202 | */ | 202 | */ |
203 | orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); | 203 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
204 | ORION5X_PCIE_WA_SIZE); | ||
204 | 205 | ||
205 | /* | 206 | /* |
206 | * Setup Multiplexing Pins -- | 207 | * Setup Multiplexing Pins -- |
@@ -217,26 +218,26 @@ static void __init kurobox_pro_init(void) | |||
217 | * MPP[15] SATA 1 active indication | 218 | * MPP[15] SATA 1 active indication |
218 | * MPP[16-19] Not used | 219 | * MPP[16-19] Not used |
219 | */ | 220 | */ |
220 | orion_write(MPP_0_7_CTRL, 0x44220003); | 221 | orion5x_write(MPP_0_7_CTRL, 0x44220003); |
221 | orion_write(MPP_8_15_CTRL, 0x55550000); | 222 | orion5x_write(MPP_8_15_CTRL, 0x55550000); |
222 | orion_write(MPP_16_19_CTRL, 0x0); | 223 | orion5x_write(MPP_16_19_CTRL, 0x0); |
223 | 224 | ||
224 | orion_gpio_set_valid_pins(0x0000000c); | 225 | orion5x_gpio_set_valid_pins(0x0000000c); |
225 | 226 | ||
226 | platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices)); | 227 | platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices)); |
227 | i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); | 228 | i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); |
228 | orion_eth_init(&kurobox_pro_eth_data); | 229 | orion5x_eth_init(&kurobox_pro_eth_data); |
229 | orion_sata_init(&kurobox_pro_sata_data); | 230 | orion5x_sata_init(&kurobox_pro_sata_data); |
230 | } | 231 | } |
231 | 232 | ||
232 | MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") | 233 | MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") |
233 | /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ | 234 | /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ |
234 | .phys_io = ORION_REGS_PHYS_BASE, | 235 | .phys_io = ORION5X_REGS_PHYS_BASE, |
235 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, | 236 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, |
236 | .boot_params = 0x00000100, | 237 | .boot_params = 0x00000100, |
237 | .init_machine = kurobox_pro_init, | 238 | .init_machine = kurobox_pro_init, |
238 | .map_io = orion_map_io, | 239 | .map_io = orion5x_map_io, |
239 | .init_irq = orion_init_irq, | 240 | .init_irq = orion5x_init_irq, |
240 | .timer = &orion_timer, | 241 | .timer = &orion5x_timer, |
241 | .fixup = tag_fixup_mem32, | 242 | .fixup = tag_fixup_mem32, |
242 | MACHINE_END | 243 | MACHINE_END |
diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion5x/pci.c index 59684cc329bc..27b4afc8f486 100644 --- a/arch/arm/mach-orion/pci.c +++ b/arch/arm/mach-orion5x/pci.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-orion/pci.c | 2 | * arch/arm/mach-orion5x/pci.c |
3 | * | 3 | * |
4 | * PCI and PCIe functions for Marvell Orion System On Chip | 4 | * PCI and PCIe functions for Marvell Orion System On Chip |
5 | * | 5 | * |
@@ -33,15 +33,15 @@ | |||
33 | /***************************************************************************** | 33 | /***************************************************************************** |
34 | * PCIe controller | 34 | * PCIe controller |
35 | ****************************************************************************/ | 35 | ****************************************************************************/ |
36 | #define PCIE_BASE ((void __iomem *)ORION_PCIE_VIRT_BASE) | 36 | #define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) |
37 | 37 | ||
38 | void __init orion_pcie_id(u32 *dev, u32 *rev) | 38 | void __init orion5x_pcie_id(u32 *dev, u32 *rev) |
39 | { | 39 | { |
40 | *dev = orion_pcie_dev_id(PCIE_BASE); | 40 | *dev = orion_pcie_dev_id(PCIE_BASE); |
41 | *rev = orion_pcie_rev(PCIE_BASE); | 41 | *rev = orion_pcie_rev(PCIE_BASE); |
42 | } | 42 | } |
43 | 43 | ||
44 | int orion_pcie_local_bus_nr(void) | 44 | int orion5x_pcie_local_bus_nr(void) |
45 | { | 45 | { |
46 | return orion_pcie_get_local_bus_nr(PCIE_BASE); | 46 | return orion_pcie_get_local_bus_nr(PCIE_BASE); |
47 | } | 47 | } |
@@ -71,7 +71,7 @@ static int pcie_valid_config(int bus, int dev) | |||
71 | * and then reading the PCIE_CONF_DATA register. Need to make sure these | 71 | * and then reading the PCIE_CONF_DATA register. Need to make sure these |
72 | * transactions are atomic. | 72 | * transactions are atomic. |
73 | */ | 73 | */ |
74 | static DEFINE_SPINLOCK(orion_pcie_lock); | 74 | static DEFINE_SPINLOCK(orion5x_pcie_lock); |
75 | 75 | ||
76 | static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | 76 | static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
77 | int size, u32 *val) | 77 | int size, u32 *val) |
@@ -84,9 +84,9 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | |||
84 | return PCIBIOS_DEVICE_NOT_FOUND; | 84 | return PCIBIOS_DEVICE_NOT_FOUND; |
85 | } | 85 | } |
86 | 86 | ||
87 | spin_lock_irqsave(&orion_pcie_lock, flags); | 87 | spin_lock_irqsave(&orion5x_pcie_lock, flags); |
88 | ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); | 88 | ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); |
89 | spin_unlock_irqrestore(&orion_pcie_lock, flags); | 89 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); |
90 | 90 | ||
91 | return ret; | 91 | return ret; |
92 | } | 92 | } |
@@ -111,7 +111,7 @@ static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, | |||
111 | return PCIBIOS_DEVICE_NOT_FOUND; | 111 | return PCIBIOS_DEVICE_NOT_FOUND; |
112 | } | 112 | } |
113 | 113 | ||
114 | ret = orion_pcie_rd_conf_wa((void __iomem *)ORION_PCIE_WA_VIRT_BASE, | 114 | ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, |
115 | bus, devfn, where, size, val); | 115 | bus, devfn, where, size, val); |
116 | 116 | ||
117 | return ret; | 117 | return ret; |
@@ -126,9 +126,9 @@ static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, | |||
126 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) | 126 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) |
127 | return PCIBIOS_DEVICE_NOT_FOUND; | 127 | return PCIBIOS_DEVICE_NOT_FOUND; |
128 | 128 | ||
129 | spin_lock_irqsave(&orion_pcie_lock, flags); | 129 | spin_lock_irqsave(&orion5x_pcie_lock, flags); |
130 | ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); | 130 | ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); |
131 | spin_unlock_irqrestore(&orion_pcie_lock, flags); | 131 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); |
132 | 132 | ||
133 | return ret; | 133 | return ret; |
134 | } | 134 | } |
@@ -147,7 +147,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) | |||
147 | /* | 147 | /* |
148 | * Generic PCIe unit setup. | 148 | * Generic PCIe unit setup. |
149 | */ | 149 | */ |
150 | orion_pcie_setup(PCIE_BASE, &orion_mbus_dram_info); | 150 | orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); |
151 | 151 | ||
152 | /* | 152 | /* |
153 | * Check whether to apply Orion-1/Orion-NAS PCIe config | 153 | * Check whether to apply Orion-1/Orion-NAS PCIe config |
@@ -172,8 +172,8 @@ static int __init pcie_setup(struct pci_sys_data *sys) | |||
172 | */ | 172 | */ |
173 | res[0].name = "PCIe I/O Space"; | 173 | res[0].name = "PCIe I/O Space"; |
174 | res[0].flags = IORESOURCE_IO; | 174 | res[0].flags = IORESOURCE_IO; |
175 | res[0].start = ORION_PCIE_IO_BUS_BASE; | 175 | res[0].start = ORION5X_PCIE_IO_BUS_BASE; |
176 | res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1; | 176 | res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; |
177 | if (request_resource(&ioport_resource, &res[0])) | 177 | if (request_resource(&ioport_resource, &res[0])) |
178 | panic("Request PCIe IO resource failed\n"); | 178 | panic("Request PCIe IO resource failed\n"); |
179 | sys->resource[0] = &res[0]; | 179 | sys->resource[0] = &res[0]; |
@@ -183,8 +183,8 @@ static int __init pcie_setup(struct pci_sys_data *sys) | |||
183 | */ | 183 | */ |
184 | res[1].name = "PCIe Memory Space"; | 184 | res[1].name = "PCIe Memory Space"; |
185 | res[1].flags = IORESOURCE_MEM; | 185 | res[1].flags = IORESOURCE_MEM; |
186 | res[1].start = ORION_PCIE_MEM_PHYS_BASE; | 186 | res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; |
187 | res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1; | 187 | res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; |
188 | if (request_resource(&iomem_resource, &res[1])) | 188 | if (request_resource(&iomem_resource, &res[1])) |
189 | panic("Request PCIe Memory resource failed\n"); | 189 | panic("Request PCIe Memory resource failed\n"); |
190 | sys->resource[1] = &res[1]; | 190 | sys->resource[1] = &res[1]; |
@@ -198,11 +198,11 @@ static int __init pcie_setup(struct pci_sys_data *sys) | |||
198 | /***************************************************************************** | 198 | /***************************************************************************** |
199 | * PCI controller | 199 | * PCI controller |
200 | ****************************************************************************/ | 200 | ****************************************************************************/ |
201 | #define PCI_MODE ORION_PCI_REG(0xd00) | 201 | #define PCI_MODE ORION5X_PCI_REG(0xd00) |
202 | #define PCI_CMD ORION_PCI_REG(0xc00) | 202 | #define PCI_CMD ORION5X_PCI_REG(0xc00) |
203 | #define PCI_P2P_CONF ORION_PCI_REG(0x1d14) | 203 | #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) |
204 | #define PCI_CONF_ADDR ORION_PCI_REG(0xc78) | 204 | #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) |
205 | #define PCI_CONF_DATA ORION_PCI_REG(0xc7c) | 205 | #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) |
206 | 206 | ||
207 | /* | 207 | /* |
208 | * PCI_MODE bits | 208 | * PCI_MODE bits |
@@ -244,16 +244,16 @@ static int __init pcie_setup(struct pci_sys_data *sys) | |||
244 | /* | 244 | /* |
245 | * PCI Address Decode Windows registers | 245 | * PCI Address Decode Windows registers |
246 | */ | 246 | */ |
247 | #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \ | 247 | #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ |
248 | ((n) == 1) ? ORION_PCI_REG(0xd08) : \ | 248 | ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ |
249 | ((n) == 2) ? ORION_PCI_REG(0xc0c) : \ | 249 | ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ |
250 | ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0) | 250 | ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) |
251 | #define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \ | 251 | #define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) : \ |
252 | ((n) == 1) ? ORION_PCI_REG(0xd48) : \ | 252 | ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ |
253 | ((n) == 2) ? ORION_PCI_REG(0xc4c) : \ | 253 | ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ |
254 | ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0) | 254 | ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) |
255 | #define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c) | 255 | #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) |
256 | #define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c) | 256 | #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) |
257 | 257 | ||
258 | /* | 258 | /* |
259 | * PCI configuration helpers for BAR settings | 259 | * PCI configuration helpers for BAR settings |
@@ -267,45 +267,45 @@ static int __init pcie_setup(struct pci_sys_data *sys) | |||
267 | * and then reading the PCI_CONF_DATA register. Need to make sure these | 267 | * and then reading the PCI_CONF_DATA register. Need to make sure these |
268 | * transactions are atomic. | 268 | * transactions are atomic. |
269 | */ | 269 | */ |
270 | static DEFINE_SPINLOCK(orion_pci_lock); | 270 | static DEFINE_SPINLOCK(orion5x_pci_lock); |
271 | 271 | ||
272 | int orion_pci_local_bus_nr(void) | 272 | int orion5x_pci_local_bus_nr(void) |
273 | { | 273 | { |
274 | u32 conf = orion_read(PCI_P2P_CONF); | 274 | u32 conf = orion5x_read(PCI_P2P_CONF); |
275 | return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); | 275 | return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); |
276 | } | 276 | } |
277 | 277 | ||
278 | static int orion_pci_hw_rd_conf(int bus, int dev, u32 func, | 278 | static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, |
279 | u32 where, u32 size, u32 *val) | 279 | u32 where, u32 size, u32 *val) |
280 | { | 280 | { |
281 | unsigned long flags; | 281 | unsigned long flags; |
282 | spin_lock_irqsave(&orion_pci_lock, flags); | 282 | spin_lock_irqsave(&orion5x_pci_lock, flags); |
283 | 283 | ||
284 | orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | | 284 | orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | |
285 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | 285 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | |
286 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); | 286 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); |
287 | 287 | ||
288 | *val = orion_read(PCI_CONF_DATA); | 288 | *val = orion5x_read(PCI_CONF_DATA); |
289 | 289 | ||
290 | if (size == 1) | 290 | if (size == 1) |
291 | *val = (*val >> (8*(where & 0x3))) & 0xff; | 291 | *val = (*val >> (8*(where & 0x3))) & 0xff; |
292 | else if (size == 2) | 292 | else if (size == 2) |
293 | *val = (*val >> (8*(where & 0x3))) & 0xffff; | 293 | *val = (*val >> (8*(where & 0x3))) & 0xffff; |
294 | 294 | ||
295 | spin_unlock_irqrestore(&orion_pci_lock, flags); | 295 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); |
296 | 296 | ||
297 | return PCIBIOS_SUCCESSFUL; | 297 | return PCIBIOS_SUCCESSFUL; |
298 | } | 298 | } |
299 | 299 | ||
300 | static int orion_pci_hw_wr_conf(int bus, int dev, u32 func, | 300 | static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, |
301 | u32 where, u32 size, u32 val) | 301 | u32 where, u32 size, u32 val) |
302 | { | 302 | { |
303 | unsigned long flags; | 303 | unsigned long flags; |
304 | int ret = PCIBIOS_SUCCESSFUL; | 304 | int ret = PCIBIOS_SUCCESSFUL; |
305 | 305 | ||
306 | spin_lock_irqsave(&orion_pci_lock, flags); | 306 | spin_lock_irqsave(&orion5x_pci_lock, flags); |
307 | 307 | ||
308 | orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | | 308 | orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | |
309 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | 309 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | |
310 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); | 310 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); |
311 | 311 | ||
@@ -319,82 +319,82 @@ static int orion_pci_hw_wr_conf(int bus, int dev, u32 func, | |||
319 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | 319 | ret = PCIBIOS_BAD_REGISTER_NUMBER; |
320 | } | 320 | } |
321 | 321 | ||
322 | spin_unlock_irqrestore(&orion_pci_lock, flags); | 322 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); |
323 | 323 | ||
324 | return ret; | 324 | return ret; |
325 | } | 325 | } |
326 | 326 | ||
327 | static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn, | 327 | static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, |
328 | int where, int size, u32 *val) | 328 | int where, int size, u32 *val) |
329 | { | 329 | { |
330 | /* | 330 | /* |
331 | * Don't go out for local device | 331 | * Don't go out for local device |
332 | */ | 332 | */ |
333 | if (bus->number == orion_pci_local_bus_nr() && | 333 | if (bus->number == orion5x_pci_local_bus_nr() && |
334 | PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) { | 334 | PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) { |
335 | *val = 0xffffffff; | 335 | *val = 0xffffffff; |
336 | return PCIBIOS_DEVICE_NOT_FOUND; | 336 | return PCIBIOS_DEVICE_NOT_FOUND; |
337 | } | 337 | } |
338 | 338 | ||
339 | return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), | 339 | return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), |
340 | PCI_FUNC(devfn), where, size, val); | 340 | PCI_FUNC(devfn), where, size, val); |
341 | } | 341 | } |
342 | 342 | ||
343 | static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn, | 343 | static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, |
344 | int where, int size, u32 val) | 344 | int where, int size, u32 val) |
345 | { | 345 | { |
346 | if (bus->number == orion_pci_local_bus_nr() && | 346 | if (bus->number == orion5x_pci_local_bus_nr() && |
347 | PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) | 347 | PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) |
348 | return PCIBIOS_DEVICE_NOT_FOUND; | 348 | return PCIBIOS_DEVICE_NOT_FOUND; |
349 | 349 | ||
350 | return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), | 350 | return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), |
351 | PCI_FUNC(devfn), where, size, val); | 351 | PCI_FUNC(devfn), where, size, val); |
352 | } | 352 | } |
353 | 353 | ||
354 | static struct pci_ops pci_ops = { | 354 | static struct pci_ops pci_ops = { |
355 | .read = orion_pci_rd_conf, | 355 | .read = orion5x_pci_rd_conf, |
356 | .write = orion_pci_wr_conf, | 356 | .write = orion5x_pci_wr_conf, |
357 | }; | 357 | }; |
358 | 358 | ||
359 | static void __init orion_pci_set_bus_nr(int nr) | 359 | static void __init orion5x_pci_set_bus_nr(int nr) |
360 | { | 360 | { |
361 | u32 p2p = orion_read(PCI_P2P_CONF); | 361 | u32 p2p = orion5x_read(PCI_P2P_CONF); |
362 | 362 | ||
363 | if (orion_read(PCI_MODE) & PCI_MODE_PCIX) { | 363 | if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) { |
364 | /* | 364 | /* |
365 | * PCI-X mode | 365 | * PCI-X mode |
366 | */ | 366 | */ |
367 | u32 pcix_status, bus, dev; | 367 | u32 pcix_status, bus, dev; |
368 | bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; | 368 | bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; |
369 | dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; | 369 | dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; |
370 | orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); | 370 | orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); |
371 | pcix_status &= ~PCIX_STAT_BUS_MASK; | 371 | pcix_status &= ~PCIX_STAT_BUS_MASK; |
372 | pcix_status |= (nr << PCIX_STAT_BUS_OFFS); | 372 | pcix_status |= (nr << PCIX_STAT_BUS_OFFS); |
373 | orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); | 373 | orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); |
374 | } else { | 374 | } else { |
375 | /* | 375 | /* |
376 | * PCI Conventional mode | 376 | * PCI Conventional mode |
377 | */ | 377 | */ |
378 | p2p &= ~PCI_P2P_BUS_MASK; | 378 | p2p &= ~PCI_P2P_BUS_MASK; |
379 | p2p |= (nr << PCI_P2P_BUS_OFFS); | 379 | p2p |= (nr << PCI_P2P_BUS_OFFS); |
380 | orion_write(PCI_P2P_CONF, p2p); | 380 | orion5x_write(PCI_P2P_CONF, p2p); |
381 | } | 381 | } |
382 | } | 382 | } |
383 | 383 | ||
384 | static void __init orion_pci_master_slave_enable(void) | 384 | static void __init orion5x_pci_master_slave_enable(void) |
385 | { | 385 | { |
386 | int bus_nr, func, reg; | 386 | int bus_nr, func, reg; |
387 | u32 val; | 387 | u32 val; |
388 | 388 | ||
389 | bus_nr = orion_pci_local_bus_nr(); | 389 | bus_nr = orion5x_pci_local_bus_nr(); |
390 | func = PCI_CONF_FUNC_STAT_CMD; | 390 | func = PCI_CONF_FUNC_STAT_CMD; |
391 | reg = PCI_CONF_REG_STAT_CMD; | 391 | reg = PCI_CONF_REG_STAT_CMD; |
392 | orion_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); | 392 | orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); |
393 | val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | 393 | val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
394 | orion_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); | 394 | orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); |
395 | } | 395 | } |
396 | 396 | ||
397 | static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) | 397 | static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) |
398 | { | 398 | { |
399 | u32 win_enable; | 399 | u32 win_enable; |
400 | int bus; | 400 | int bus; |
@@ -404,12 +404,12 @@ static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) | |||
404 | * First, disable windows. | 404 | * First, disable windows. |
405 | */ | 405 | */ |
406 | win_enable = 0xffffffff; | 406 | win_enable = 0xffffffff; |
407 | orion_write(PCI_BAR_ENABLE, win_enable); | 407 | orion5x_write(PCI_BAR_ENABLE, win_enable); |
408 | 408 | ||
409 | /* | 409 | /* |
410 | * Setup windows for DDR banks. | 410 | * Setup windows for DDR banks. |
411 | */ | 411 | */ |
412 | bus = orion_pci_local_bus_nr(); | 412 | bus = orion5x_pci_local_bus_nr(); |
413 | 413 | ||
414 | for (i = 0; i < dram->num_cs; i++) { | 414 | for (i = 0; i < dram->num_cs; i++) { |
415 | struct mbus_dram_window *cs = dram->cs + i; | 415 | struct mbus_dram_window *cs = dram->cs + i; |
@@ -421,18 +421,18 @@ static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) | |||
421 | * Write DRAM bank base address register. | 421 | * Write DRAM bank base address register. |
422 | */ | 422 | */ |
423 | reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); | 423 | reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); |
424 | orion_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); | 424 | orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); |
425 | val = (cs->base & 0xfffff000) | (val & 0xfff); | 425 | val = (cs->base & 0xfffff000) | (val & 0xfff); |
426 | orion_pci_hw_wr_conf(bus, 0, func, reg, 4, val); | 426 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); |
427 | 427 | ||
428 | /* | 428 | /* |
429 | * Write DRAM bank size register. | 429 | * Write DRAM bank size register. |
430 | */ | 430 | */ |
431 | reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); | 431 | reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); |
432 | orion_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); | 432 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); |
433 | orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), | 433 | orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), |
434 | (cs->size - 1) & 0xfffff000); | 434 | (cs->size - 1) & 0xfffff000); |
435 | orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), | 435 | orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), |
436 | cs->base & 0xfffff000); | 436 | cs->base & 0xfffff000); |
437 | 437 | ||
438 | /* | 438 | /* |
@@ -444,12 +444,12 @@ static void __init orion_setup_pci_wins(struct mbus_dram_target_info *dram) | |||
444 | /* | 444 | /* |
445 | * Re-enable decode windows. | 445 | * Re-enable decode windows. |
446 | */ | 446 | */ |
447 | orion_write(PCI_BAR_ENABLE, win_enable); | 447 | orion5x_write(PCI_BAR_ENABLE, win_enable); |
448 | 448 | ||
449 | /* | 449 | /* |
450 | * Disable automatic update of address remaping when writing to BARs. | 450 | * Disable automatic update of address remaping when writing to BARs. |
451 | */ | 451 | */ |
452 | orion_setbits(PCI_ADDR_DECODE_CTRL, 1); | 452 | orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); |
453 | } | 453 | } |
454 | 454 | ||
455 | static int __init pci_setup(struct pci_sys_data *sys) | 455 | static int __init pci_setup(struct pci_sys_data *sys) |
@@ -459,17 +459,17 @@ static int __init pci_setup(struct pci_sys_data *sys) | |||
459 | /* | 459 | /* |
460 | * Point PCI unit MBUS decode windows to DRAM space. | 460 | * Point PCI unit MBUS decode windows to DRAM space. |
461 | */ | 461 | */ |
462 | orion_setup_pci_wins(&orion_mbus_dram_info); | 462 | orion5x_setup_pci_wins(&orion5x_mbus_dram_info); |
463 | 463 | ||
464 | /* | 464 | /* |
465 | * Master + Slave enable | 465 | * Master + Slave enable |
466 | */ | 466 | */ |
467 | orion_pci_master_slave_enable(); | 467 | orion5x_pci_master_slave_enable(); |
468 | 468 | ||
469 | /* | 469 | /* |
470 | * Force ordering | 470 | * Force ordering |
471 | */ | 471 | */ |
472 | orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); | 472 | orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); |
473 | 473 | ||
474 | /* | 474 | /* |
475 | * Request resources | 475 | * Request resources |
@@ -483,8 +483,8 @@ static int __init pci_setup(struct pci_sys_data *sys) | |||
483 | */ | 483 | */ |
484 | res[0].name = "PCI I/O Space"; | 484 | res[0].name = "PCI I/O Space"; |
485 | res[0].flags = IORESOURCE_IO; | 485 | res[0].flags = IORESOURCE_IO; |
486 | res[0].start = ORION_PCI_IO_BUS_BASE; | 486 | res[0].start = ORION5X_PCI_IO_BUS_BASE; |
487 | res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1; | 487 | res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; |
488 | if (request_resource(&ioport_resource, &res[0])) | 488 | if (request_resource(&ioport_resource, &res[0])) |
489 | panic("Request PCI IO resource failed\n"); | 489 | panic("Request PCI IO resource failed\n"); |
490 | sys->resource[0] = &res[0]; | 490 | sys->resource[0] = &res[0]; |
@@ -494,8 +494,8 @@ static int __init pci_setup(struct pci_sys_data *sys) | |||
494 | */ | 494 | */ |
495 | res[1].name = "PCI Memory Space"; | 495 | res[1].name = "PCI Memory Space"; |
496 | res[1].flags = IORESOURCE_MEM; | 496 | res[1].flags = IORESOURCE_MEM; |
497 | res[1].start = ORION_PCI_MEM_PHYS_BASE; | 497 | res[1].start = ORION5X_PCI_MEM_PHYS_BASE; |
498 | res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1; | 498 | res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; |
499 | if (request_resource(&iomem_resource, &res[1])) | 499 | if (request_resource(&iomem_resource, &res[1])) |
500 | panic("Request PCI Memory resource failed\n"); | 500 | panic("Request PCI Memory resource failed\n"); |
501 | sys->resource[1] = &res[1]; | 501 | sys->resource[1] = &res[1]; |
@@ -527,7 +527,7 @@ static void __devinit rc_pci_fixup(struct pci_dev *dev) | |||
527 | } | 527 | } |
528 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); | 528 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); |
529 | 529 | ||
530 | int __init orion_pci_sys_setup(int nr, struct pci_sys_data *sys) | 530 | int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) |
531 | { | 531 | { |
532 | int ret = 0; | 532 | int ret = 0; |
533 | 533 | ||
@@ -535,14 +535,14 @@ int __init orion_pci_sys_setup(int nr, struct pci_sys_data *sys) | |||
535 | orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); | 535 | orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); |
536 | ret = pcie_setup(sys); | 536 | ret = pcie_setup(sys); |
537 | } else if (nr == 1) { | 537 | } else if (nr == 1) { |
538 | orion_pci_set_bus_nr(sys->busnr); | 538 | orion5x_pci_set_bus_nr(sys->busnr); |
539 | ret = pci_setup(sys); | 539 | ret = pci_setup(sys); |
540 | } | 540 | } |
541 | 541 | ||
542 | return ret; | 542 | return ret; |
543 | } | 543 | } |
544 | 544 | ||
545 | struct pci_bus __init *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) | 545 | struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) |
546 | { | 546 | { |
547 | struct pci_bus *bus; | 547 | struct pci_bus *bus; |
548 | 548 | ||
diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index f3e38ecda1ce..37e8b2dc3ed5 100644 --- a/arch/arm/mach-orion/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-orion/rd88f5182-setup.c | 2 | * arch/arm/mach-orion5x/rd88f5182-setup.c |
3 | * | 3 | * |
4 | * Marvell Orion-NAS Reference Design Setup | 4 | * Marvell Orion-NAS Reference Design Setup |
5 | * | 5 | * |
@@ -24,7 +24,7 @@ | |||
24 | #include <asm/leds.h> | 24 | #include <asm/leds.h> |
25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
26 | #include <asm/mach/pci.h> | 26 | #include <asm/mach/pci.h> |
27 | #include <asm/arch/orion.h> | 27 | #include <asm/arch/orion5x.h> |
28 | #include "common.h" | 28 | #include "common.h" |
29 | 29 | ||
30 | /***************************************************************************** | 30 | /***************************************************************************** |
@@ -175,8 +175,8 @@ static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
175 | /* | 175 | /* |
176 | * PCI-E isn't used on the RD2 | 176 | * PCI-E isn't used on the RD2 |
177 | */ | 177 | */ |
178 | if (dev->bus->number == orion_pcie_local_bus_nr()) | 178 | if (dev->bus->number == orion5x_pcie_local_bus_nr()) |
179 | return IRQ_ORION_PCIE0_INT; | 179 | return IRQ_ORION5X_PCIE0_INT; |
180 | 180 | ||
181 | /* | 181 | /* |
182 | * PCI IRQs are connected via GPIOs | 182 | * PCI IRQs are connected via GPIOs |
@@ -196,8 +196,8 @@ static struct hw_pci rd88f5182_pci __initdata = { | |||
196 | .nr_controllers = 2, | 196 | .nr_controllers = 2, |
197 | .preinit = rd88f5182_pci_preinit, | 197 | .preinit = rd88f5182_pci_preinit, |
198 | .swizzle = pci_std_swizzle, | 198 | .swizzle = pci_std_swizzle, |
199 | .setup = orion_pci_sys_setup, | 199 | .setup = orion5x_pci_sys_setup, |
200 | .scan = orion_pci_sys_scan_bus, | 200 | .scan = orion5x_pci_sys_scan_bus, |
201 | .map_irq = rd88f5182_pci_map_irq, | 201 | .map_irq = rd88f5182_pci_map_irq, |
202 | }; | 202 | }; |
203 | 203 | ||
@@ -249,19 +249,20 @@ static void __init rd88f5182_init(void) | |||
249 | /* | 249 | /* |
250 | * Setup basic Orion functions. Need to be called early. | 250 | * Setup basic Orion functions. Need to be called early. |
251 | */ | 251 | */ |
252 | orion_init(); | 252 | orion5x_init(); |
253 | 253 | ||
254 | /* | 254 | /* |
255 | * Setup the CPU address decode windows for our devices | 255 | * Setup the CPU address decode windows for our devices |
256 | */ | 256 | */ |
257 | orion_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, | 257 | orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, |
258 | RD88F5182_NOR_BOOT_SIZE); | 258 | RD88F5182_NOR_BOOT_SIZE); |
259 | orion_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); | 259 | orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); |
260 | 260 | ||
261 | /* | 261 | /* |
262 | * Open a special address decode windows for the PCIE WA. | 262 | * Open a special address decode windows for the PCIE WA. |
263 | */ | 263 | */ |
264 | orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); | 264 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
265 | ORION5X_PCIE_WA_SIZE); | ||
265 | 266 | ||
266 | /* | 267 | /* |
267 | * Setup Multiplexing Pins -- | 268 | * Setup Multiplexing Pins -- |
@@ -287,25 +288,25 @@ static void __init rd88f5182_init(void) | |||
287 | * MPP[25] USB 0 over current enable | 288 | * MPP[25] USB 0 over current enable |
288 | */ | 289 | */ |
289 | 290 | ||
290 | orion_write(MPP_0_7_CTRL, 0x00000003); | 291 | orion5x_write(MPP_0_7_CTRL, 0x00000003); |
291 | orion_write(MPP_8_15_CTRL, 0x55550000); | 292 | orion5x_write(MPP_8_15_CTRL, 0x55550000); |
292 | orion_write(MPP_16_19_CTRL, 0x5555); | 293 | orion5x_write(MPP_16_19_CTRL, 0x5555); |
293 | 294 | ||
294 | orion_gpio_set_valid_pins(0x000000fb); | 295 | orion5x_gpio_set_valid_pins(0x000000fb); |
295 | 296 | ||
296 | platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); | 297 | platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); |
297 | i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); | 298 | i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); |
298 | orion_eth_init(&rd88f5182_eth_data); | 299 | orion5x_eth_init(&rd88f5182_eth_data); |
299 | orion_sata_init(&rd88f5182_sata_data); | 300 | orion5x_sata_init(&rd88f5182_sata_data); |
300 | } | 301 | } |
301 | 302 | ||
302 | MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") | 303 | MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") |
303 | /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ | 304 | /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ |
304 | .phys_io = ORION_REGS_PHYS_BASE, | 305 | .phys_io = ORION5X_REGS_PHYS_BASE, |
305 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, | 306 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, |
306 | .boot_params = 0x00000100, | 307 | .boot_params = 0x00000100, |
307 | .init_machine = rd88f5182_init, | 308 | .init_machine = rd88f5182_init, |
308 | .map_io = orion_map_io, | 309 | .map_io = orion5x_map_io, |
309 | .init_irq = orion_init_irq, | 310 | .init_irq = orion5x_init_irq, |
310 | .timer = &orion_timer, | 311 | .timer = &orion5x_timer, |
311 | MACHINE_END | 312 | MACHINE_END |
diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 8eca070006f1..71b0cffa2fe0 100644 --- a/arch/arm/mach-orion/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c | |||
@@ -26,7 +26,7 @@ | |||
26 | #include <asm/gpio.h> | 26 | #include <asm/gpio.h> |
27 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
28 | #include <asm/mach/pci.h> | 28 | #include <asm/mach/pci.h> |
29 | #include <asm/arch/orion.h> | 29 | #include <asm/arch/orion5x.h> |
30 | #include "common.h" | 30 | #include "common.h" |
31 | 31 | ||
32 | #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 | 32 | #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 |
@@ -144,8 +144,8 @@ static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
144 | /* | 144 | /* |
145 | * PCIE IRQ is connected internally (not GPIO) | 145 | * PCIE IRQ is connected internally (not GPIO) |
146 | */ | 146 | */ |
147 | if (dev->bus->number == orion_pcie_local_bus_nr()) | 147 | if (dev->bus->number == orion5x_pcie_local_bus_nr()) |
148 | return IRQ_ORION_PCIE0_INT; | 148 | return IRQ_ORION5X_PCIE0_INT; |
149 | 149 | ||
150 | /* | 150 | /* |
151 | * PCI IRQs are connected via GPIOs | 151 | * PCI IRQs are connected via GPIOs |
@@ -164,8 +164,8 @@ static struct hw_pci qnap_ts209_pci __initdata = { | |||
164 | .nr_controllers = 2, | 164 | .nr_controllers = 2, |
165 | .preinit = qnap_ts209_pci_preinit, | 165 | .preinit = qnap_ts209_pci_preinit, |
166 | .swizzle = pci_std_swizzle, | 166 | .swizzle = pci_std_swizzle, |
167 | .setup = orion_pci_sys_setup, | 167 | .setup = orion5x_pci_sys_setup, |
168 | .scan = orion_pci_sys_scan_bus, | 168 | .scan = orion5x_pci_sys_scan_bus, |
169 | .map_irq = qnap_ts209_pci_map_irq, | 169 | .map_irq = qnap_ts209_pci_map_irq, |
170 | }; | 170 | }; |
171 | 171 | ||
@@ -261,21 +261,21 @@ static struct platform_device *qnap_ts209_devices[] __initdata = { | |||
261 | static void qnap_ts209_power_off(void) | 261 | static void qnap_ts209_power_off(void) |
262 | { | 262 | { |
263 | /* 19200 baud divisor */ | 263 | /* 19200 baud divisor */ |
264 | const unsigned divisor = ((ORION_TCLK + (8 * 19200)) / (16 * 19200)); | 264 | const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200)); |
265 | 265 | ||
266 | pr_info("%s: triggering power-off...\n", __func__); | 266 | pr_info("%s: triggering power-off...\n", __func__); |
267 | 267 | ||
268 | /* hijack uart1 and reset into sane state (19200,8n1) */ | 268 | /* hijack uart1 and reset into sane state (19200,8n1) */ |
269 | orion_write(UART1_REG(LCR), 0x83); | 269 | orion5x_write(UART1_REG(LCR), 0x83); |
270 | orion_write(UART1_REG(DLL), divisor & 0xff); | 270 | orion5x_write(UART1_REG(DLL), divisor & 0xff); |
271 | orion_write(UART1_REG(DLM), (divisor >> 8) & 0xff); | 271 | orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff); |
272 | orion_write(UART1_REG(LCR), 0x03); | 272 | orion5x_write(UART1_REG(LCR), 0x03); |
273 | orion_write(UART1_REG(IER), 0x00); | 273 | orion5x_write(UART1_REG(IER), 0x00); |
274 | orion_write(UART1_REG(FCR), 0x00); | 274 | orion5x_write(UART1_REG(FCR), 0x00); |
275 | orion_write(UART1_REG(MCR), 0x00); | 275 | orion5x_write(UART1_REG(MCR), 0x00); |
276 | 276 | ||
277 | /* send the power-off command 'A' to PIC */ | 277 | /* send the power-off command 'A' to PIC */ |
278 | orion_write(UART1_REG(TX), 'A'); | 278 | orion5x_write(UART1_REG(TX), 'A'); |
279 | } | 279 | } |
280 | 280 | ||
281 | static void __init qnap_ts209_init(void) | 281 | static void __init qnap_ts209_init(void) |
@@ -283,18 +283,19 @@ static void __init qnap_ts209_init(void) | |||
283 | /* | 283 | /* |
284 | * Setup basic Orion functions. Need to be called early. | 284 | * Setup basic Orion functions. Need to be called early. |
285 | */ | 285 | */ |
286 | orion_init(); | 286 | orion5x_init(); |
287 | 287 | ||
288 | /* | 288 | /* |
289 | * Setup flash mapping | 289 | * Setup flash mapping |
290 | */ | 290 | */ |
291 | orion_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, | 291 | orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, |
292 | QNAP_TS209_NOR_BOOT_SIZE); | 292 | QNAP_TS209_NOR_BOOT_SIZE); |
293 | 293 | ||
294 | /* | 294 | /* |
295 | * Open a special address decode windows for the PCIE WA. | 295 | * Open a special address decode windows for the PCIE WA. |
296 | */ | 296 | */ |
297 | orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); | 297 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
298 | ORION5X_PCIE_WA_SIZE); | ||
298 | 299 | ||
299 | /* | 300 | /* |
300 | * Setup Multiplexing Pins -- | 301 | * Setup Multiplexing Pins -- |
@@ -319,10 +320,10 @@ static void __init qnap_ts209_init(void) | |||
319 | * MPP[22] USB 0 over current | 320 | * MPP[22] USB 0 over current |
320 | * MPP[23-25] Reserved | 321 | * MPP[23-25] Reserved |
321 | */ | 322 | */ |
322 | orion_write(MPP_0_7_CTRL, 0x3); | 323 | orion5x_write(MPP_0_7_CTRL, 0x3); |
323 | orion_write(MPP_8_15_CTRL, 0x55550000); | 324 | orion5x_write(MPP_8_15_CTRL, 0x55550000); |
324 | orion_write(MPP_16_19_CTRL, 0x5500); | 325 | orion5x_write(MPP_16_19_CTRL, 0x5500); |
325 | orion_gpio_set_valid_pins(0x3cc0fff); | 326 | orion5x_gpio_set_valid_pins(0x3cc0fff); |
326 | 327 | ||
327 | /* register ts209 specific power-off method */ | 328 | /* register ts209 specific power-off method */ |
328 | pm_power_off = qnap_ts209_power_off; | 329 | pm_power_off = qnap_ts209_power_off; |
@@ -341,18 +342,18 @@ static void __init qnap_ts209_init(void) | |||
341 | pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); | 342 | pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); |
342 | i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); | 343 | i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); |
343 | 344 | ||
344 | orion_eth_init(&qnap_ts209_eth_data); | 345 | orion5x_eth_init(&qnap_ts209_eth_data); |
345 | orion_sata_init(&qnap_ts209_sata_data); | 346 | orion5x_sata_init(&qnap_ts209_sata_data); |
346 | } | 347 | } |
347 | 348 | ||
348 | MACHINE_START(TS209, "QNAP TS-109/TS-209") | 349 | MACHINE_START(TS209, "QNAP TS-109/TS-209") |
349 | /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ | 350 | /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ |
350 | .phys_io = ORION_REGS_PHYS_BASE, | 351 | .phys_io = ORION5X_REGS_PHYS_BASE, |
351 | .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC, | 352 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, |
352 | .boot_params = 0x00000100, | 353 | .boot_params = 0x00000100, |
353 | .init_machine = qnap_ts209_init, | 354 | .init_machine = qnap_ts209_init, |
354 | .map_io = orion_map_io, | 355 | .map_io = orion5x_map_io, |
355 | .init_irq = orion_init_irq, | 356 | .init_irq = orion5x_init_irq, |
356 | .timer = &orion_timer, | 357 | .timer = &orion5x_timer, |
357 | .fixup = tag_fixup_mem32, | 358 | .fixup = tag_fixup_mem32, |
358 | MACHINE_END | 359 | MACHINE_END |
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 76348f060f27..64d09244df46 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
@@ -345,7 +345,7 @@ config CPU_XSC3 | |||
345 | # Feroceon | 345 | # Feroceon |
346 | config CPU_FEROCEON | 346 | config CPU_FEROCEON |
347 | bool | 347 | bool |
348 | depends on ARCH_ORION | 348 | depends on ARCH_ORION5X |
349 | default y | 349 | default y |
350 | select CPU_32v5 | 350 | select CPU_32v5 |
351 | select CPU_ABRT_EV5T | 351 | select CPU_ABRT_EV5T |