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authorRafael J. Wysocki <rjw@sisk.pl>2012-07-11 17:03:54 -0400
committerRafael J. Wysocki <rjw@sisk.pl>2012-07-11 17:03:54 -0400
commit9d0db7abbdebc90150f3b98e9bc76626eaf01bd3 (patch)
tree6330aefd8d2a0d5c99b913a57445e5fe9705807a /arch/arm
parentf5e8779a5e3e40cf1bf97dfe00ae24d681b66396 (diff)
parent0df8fa46611abc56e39f541495d667e4bf4f1060 (diff)
Merge branch 'renesas-soc' into renesas-board
* renesas-soc: (31 commits) ARM: shmobile: Fix build problem in pm-sh7372.c for unusual .config ARM: shmobile: Take cpuidle dependencies into account correctly ARM: mach-shmobile: sh7377 generic board support via DT ARM: mach-shmobile: r8a7740 generic board support via DT ARM: shmobile: sh7372: completely switch over to using pm-rmobile API ARM: shmobile: ap4evb: switch to using pm-rmobile API ARM: shmobile: mackerel: switch to using pm-rmobile API ARM: shmobile: sh7372: add pm-rmobile domain support ARM: shmobile: r8a7740: add A4LC pm domain support ARM: shmobile: r8a7740: add A3SP pm domain support ARM: shmobile: r8a7740: add A4S pm domain support ARM: shmobile: r8a7740: fixup: MSEL1CR 7bit control ARM: shmobile: soc-core: add R-mobile PM domain common APIs ARM: shmobile: sh7372 A3SM CPUIdle support ARM: shmobile: Use INTCA with sh7372 A3SM power domain ARM: mach-shmobile: Convert sh_clk_mstp32_register to sh_clk_mstp_register ARM: shmobile: use common DMAEngine definitions on sh7372 ARM: shmobile: use common DMAEngine definitions on sh73a0 ARM: shmobile: sh73a0: add DMAEngine support for MPDMAC ARM: shmobile: sh73a0: add USB clock support ...
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi21
-rw-r--r--arch/arm/boot/dts/sh7377.dtsi21
-rw-r--r--arch/arm/mach-shmobile/Kconfig1
-rw-r--r--arch/arm/mach-shmobile/Makefile2
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c16
-rw-r--r--arch/arm/mach-shmobile/board-armadillo800eva.c1
-rw-r--r--arch/arm/mach-shmobile/board-kzm9d.c1
-rw-r--r--arch/arm/mach-shmobile/board-kzm9g.c1
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c24
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c12
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c2
-rw-r--r--arch/arm/mach-shmobile/clock-sh7367.c2
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c2
-rw-r--r--arch/arm/mach-shmobile/clock-sh7377.c2
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c10
-rw-r--r--arch/arm/mach-shmobile/include/mach/dma-register.h84
-rw-r--r--arch/arm/mach-shmobile/include/mach/gpio.h32
-rw-r--r--arch/arm/mach-shmobile/include/mach/pm-rmobile.h44
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7740.h24
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7372.h45
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh73a0.h7
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7779.c7
-rw-r--r--arch/arm/mach-shmobile/pfc-r8a7740.c4
-rw-r--r--arch/arm/mach-shmobile/pm-r8a7740.c54
-rw-r--r--arch/arm/mach-shmobile/pm-rmobile.c167
-rw-r--r--arch/arm/mach-shmobile/pm-sh7372.c297
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c342
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c209
-rw-r--r--arch/arm/mach-shmobile/setup-sh7377.c47
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c152
30 files changed, 1199 insertions, 434 deletions
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
new file mode 100644
index 000000000000..798fa35c0005
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -0,0 +1,21 @@
1/*
2 * Device Tree Source for the r8a7740 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "renesas,r8a7740";
15
16 cpus {
17 cpu@0 {
18 compatible = "arm,cortex-a9";
19 };
20 };
21};
diff --git a/arch/arm/boot/dts/sh7377.dtsi b/arch/arm/boot/dts/sh7377.dtsi
new file mode 100644
index 000000000000..767ee0796daa
--- /dev/null
+++ b/arch/arm/boot/dts/sh7377.dtsi
@@ -0,0 +1,21 @@
1/*
2 * Device Tree Source for the sh7377 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "renesas,sh7377";
15
16 cpus {
17 cpu@0 {
18 compatible = "arm,cortex-a8";
19 };
20 };
21};
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 4c3b031be6f3..379cefd0ed83 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -19,6 +19,7 @@ config ARCH_SH7372
19 select CPU_V7 19 select CPU_V7
20 select SH_CLK_CPG 20 select SH_CLK_CPG
21 select ARCH_WANT_OPTIONAL_GPIOLIB 21 select ARCH_WANT_OPTIONAL_GPIOLIB
22 select ARM_CPU_SUSPEND if PM || CPU_IDLE
22 23
23config ARCH_SH73A0 24config ARCH_SH73A0
24 bool "SH-Mobile AG5 (R8A73A00)" 25 bool "SH-Mobile AG5 (R8A73A00)"
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 8aa1962c22a2..0df5ae6740c6 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -39,7 +39,9 @@ obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o
39# PM objects 39# PM objects
40obj-$(CONFIG_SUSPEND) += suspend.o 40obj-$(CONFIG_SUSPEND) += suspend.o
41obj-$(CONFIG_CPU_IDLE) += cpuidle.o 41obj-$(CONFIG_CPU_IDLE) += cpuidle.o
42obj-$(CONFIG_ARCH_SHMOBILE) += pm-rmobile.o
42obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o 43obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o
44obj-$(CONFIG_ARCH_R8A7740) += pm-r8a7740.o
43obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o 45obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o
44 46
45# Board objects 47# Board objects
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index ace60246a5df..7cac1df3085c 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1447,14 +1447,14 @@ static void __init ap4evb_init(void)
1447 1447
1448 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices)); 1448 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
1449 1449
1450 sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc1_device); 1450 rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc1_device);
1451 sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device); 1451 rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device);
1452 sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device); 1452 rmobile_add_device_to_domain(&sh7372_pd_a4mp, &fsi_device);
1453 1453
1454 sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device); 1454 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sh_mmcif_device);
1455 sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device); 1455 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi0_device);
1456 sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device); 1456 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi1_device);
1457 sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device); 1457 rmobile_add_device_to_domain(&sh7372_pd_a4r, &ceu_device);
1458 1458
1459 hdmi_init_pm_clock(); 1459 hdmi_init_pm_clock();
1460 fsi_init_pm_clock(); 1460 fsi_init_pm_clock();
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 2cce28b2e40a..a513ebee98d5 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -989,6 +989,7 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
989 .init_irq = r8a7740_init_irq, 989 .init_irq = r8a7740_init_irq,
990 .handle_irq = shmobile_handle_irq_intc, 990 .handle_irq = shmobile_handle_irq_intc,
991 .init_machine = eva_init, 991 .init_machine = eva_init,
992 .init_late = shmobile_init_late,
992 .timer = &shmobile_timer, 993 .timer = &shmobile_timer,
993 .dt_compat = eva_boards_compat_dt, 994 .dt_compat = eva_boards_compat_dt,
994MACHINE_END 995MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index 7bc5e7d39f9b..6a33cf393428 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -80,6 +80,7 @@ DT_MACHINE_START(KZM9D_DT, "kzm9d")
80 .init_irq = emev2_init_irq, 80 .init_irq = emev2_init_irq,
81 .handle_irq = gic_handle_irq, 81 .handle_irq = gic_handle_irq,
82 .init_machine = kzm9d_add_standard_devices, 82 .init_machine = kzm9d_add_standard_devices,
83 .init_late = shmobile_init_late,
83 .timer = &shmobile_timer, 84 .timer = &shmobile_timer,
84 .dt_compat = kzm9d_boards_compat_dt, 85 .dt_compat = kzm9d_boards_compat_dt,
85MACHINE_END 86MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index a5cb11358e00..c06d04b11b0e 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -537,6 +537,7 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g")
537 .init_irq = sh73a0_init_irq, 537 .init_irq = sh73a0_init_irq,
538 .handle_irq = gic_handle_irq, 538 .handle_irq = gic_handle_irq,
539 .init_machine = kzm_init, 539 .init_machine = kzm_init,
540 .init_late = shmobile_init_late,
540 .timer = &shmobile_timer, 541 .timer = &shmobile_timer,
541 .dt_compat = kzm9g_boards_compat_dt, 542 .dt_compat = kzm9g_boards_compat_dt,
542MACHINE_END 543MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 150122a44630..9640f34122bd 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1614,20 +1614,20 @@ static void __init mackerel_init(void)
1614 1614
1615 platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices)); 1615 platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
1616 1616
1617 sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device); 1617 rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device);
1618 sh7372_add_device_to_domain(&sh7372_a4lc, &hdmi_lcdc_device); 1618 rmobile_add_device_to_domain(&sh7372_pd_a4lc, &hdmi_lcdc_device);
1619 sh7372_add_device_to_domain(&sh7372_a4lc, &meram_device); 1619 rmobile_add_device_to_domain(&sh7372_pd_a4lc, &meram_device);
1620 sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device); 1620 rmobile_add_device_to_domain(&sh7372_pd_a4mp, &fsi_device);
1621 sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs0_device); 1621 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usbhs0_device);
1622 sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs1_device); 1622 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usbhs1_device);
1623 sh7372_add_device_to_domain(&sh7372_a3sp, &nand_flash_device); 1623 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &nand_flash_device);
1624 sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device); 1624 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sh_mmcif_device);
1625 sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device); 1625 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi0_device);
1626#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) 1626#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
1627 sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device); 1627 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi1_device);
1628#endif 1628#endif
1629 sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device); 1629 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi2_device);
1630 sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device); 1630 rmobile_add_device_to_domain(&sh7372_pd_a4r, &ceu_device);
1631 1631
1632 hdmi_init_pm_clock(); 1632 hdmi_init_pm_clock();
1633 sh7372_pm_init(); 1633 sh7372_pm_init();
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 7b9e4ab34fa2..ad5fccc7b5e7 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -463,6 +463,7 @@ enum {
463 463
464 MSTP230, 464 MSTP230,
465 MSTP222, 465 MSTP222,
466 MSTP218, MSTP217, MSTP216, MSTP214,
466 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, 467 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
467 468
468 MSTP329, MSTP328, MSTP323, MSTP320, 469 MSTP329, MSTP328, MSTP323, MSTP320,
@@ -485,6 +486,10 @@ static struct clk mstp_clks[MSTP_NR] = {
485 486
486 [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */ 487 [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
487 [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */ 488 [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
489 [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
490 [MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
491 [MSTP216] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
492 [MSTP214] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
488 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ 493 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
489 [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ 494 [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
490 [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ 495 [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
@@ -563,7 +568,10 @@ static struct clk_lookup lookups[] = {
563 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), 568 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
564 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), 569 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
565 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), 570 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
566 571 CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]),
572 CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]),
573 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]),
574 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
567 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]), 575 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
568 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]), 576 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
569 577
@@ -628,7 +636,7 @@ void __init r8a7740_clock_init(u8 md_ck)
628 DIV6_REPARENT_NR); 636 DIV6_REPARENT_NR);
629 637
630 if (!ret) 638 if (!ret)
631 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); 639 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
632 640
633 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) 641 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
634 ret = clk_register(late_main_clks[k]); 642 ret = clk_register(late_main_clks[k]);
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 7d6e9fe47b56..339c62c824d5 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -162,7 +162,7 @@ void __init r8a7779_clock_init(void)
162 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 162 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
163 163
164 if (!ret) 164 if (!ret)
165 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); 165 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
166 166
167 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) 167 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
168 ret = clk_register(late_main_clks[k]); 168 ret = clk_register(late_main_clks[k]);
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
index 006e7b5d304c..162b791b8984 100644
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -344,7 +344,7 @@ void __init sh7367_clock_init(void)
344 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 344 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
345 345
346 if (!ret) 346 if (!ret)
347 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); 347 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
348 348
349 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 349 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
350 350
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 94d1f88246d3..5a2894b1c965 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -704,7 +704,7 @@ void __init sh7372_clock_init(void)
704 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR); 704 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
705 705
706 if (!ret) 706 if (!ret)
707 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); 707 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
708 708
709 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) 709 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
710 ret = clk_register(late_main_clks[k]); 710 ret = clk_register(late_main_clks[k]);
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
index 0798a15936c3..85f2a3ec2c44 100644
--- a/arch/arm/mach-shmobile/clock-sh7377.c
+++ b/arch/arm/mach-shmobile/clock-sh7377.c
@@ -355,7 +355,7 @@ void __init sh7377_clock_init(void)
355 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 355 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
356 356
357 if (!ret) 357 if (!ret)
358 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); 358 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
359 359
360 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 360 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
361 361
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index ad6f9ade7402..7f8da18a8580 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -475,9 +475,9 @@ static struct clk *late_main_clks[] = {
475 475
476enum { MSTP001, 476enum { MSTP001,
477 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100, 477 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
478 MSTP219, MSTP218, 478 MSTP219, MSTP218, MSTP217,
479 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, 479 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
480 MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, 480 MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
481 MSTP314, MSTP313, MSTP312, MSTP311, 481 MSTP314, MSTP313, MSTP312, MSTP311,
482 MSTP303, MSTP302, MSTP301, MSTP300, 482 MSTP303, MSTP302, MSTP301, MSTP300,
483 MSTP411, MSTP410, MSTP403, 483 MSTP411, MSTP410, MSTP403,
@@ -498,6 +498,7 @@ static struct clk mstp_clks[MSTP_NR] = {
498 [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ 498 [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
499 [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */ 499 [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
500 [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */ 500 [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
501 [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* MP-DMAC */
501 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ 502 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
502 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ 503 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
503 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ 504 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
@@ -510,6 +511,7 @@ static struct clk mstp_clks[MSTP_NR] = {
510 [MSTP328] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /*FSI*/ 511 [MSTP328] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /*FSI*/
511 [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */ 512 [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
512 [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ 513 [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
514 [MSTP322] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 22, 0), /* USB */
513 [MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */ 515 [MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */
514 [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */ 516 [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
515 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */ 517 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
@@ -554,6 +556,7 @@ static struct clk_lookup lookups[] = {
554 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */ 556 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
555 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */ 557 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
556 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */ 558 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */
559 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* MP-DMAC */
557 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ 560 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
558 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */ 561 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
559 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ 562 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
@@ -566,6 +569,7 @@ static struct clk_lookup lookups[] = {
566 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */ 569 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
567 CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */ 570 CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
568 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ 571 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
572 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
569 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ 573 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
570 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ 574 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
571 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ 575 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
@@ -614,7 +618,7 @@ void __init sh73a0_clock_init(void)
614 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); 618 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
615 619
616 if (!ret) 620 if (!ret)
617 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); 621 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
618 622
619 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) 623 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
620 ret = clk_register(late_main_clks[k]); 624 ret = clk_register(late_main_clks[k]);
diff --git a/arch/arm/mach-shmobile/include/mach/dma-register.h b/arch/arm/mach-shmobile/include/mach/dma-register.h
new file mode 100644
index 000000000000..97c40bd9b94f
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/dma-register.h
@@ -0,0 +1,84 @@
1/*
2 * SH-ARM CPU-specific DMA definitions, used by both DMA drivers
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp
5 *
6 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 *
8 * Based on arch/sh/include/cpu-sh4/cpu/dma-register.h
9 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef DMA_REGISTER_H
17#define DMA_REGISTER_H
18
19/*
20 * Direct Memory Access Controller
21 */
22
23/* Transmit sizes and respective CHCR register values */
24enum {
25 XMIT_SZ_8BIT = 0,
26 XMIT_SZ_16BIT = 1,
27 XMIT_SZ_32BIT = 2,
28 XMIT_SZ_64BIT = 7,
29 XMIT_SZ_128BIT = 3,
30 XMIT_SZ_256BIT = 4,
31 XMIT_SZ_512BIT = 5,
32};
33
34/* log2(size / 8) - used to calculate number of transfers */
35static const unsigned int dma_ts_shift[] = {
36 [XMIT_SZ_8BIT] = 0,
37 [XMIT_SZ_16BIT] = 1,
38 [XMIT_SZ_32BIT] = 2,
39 [XMIT_SZ_64BIT] = 3,
40 [XMIT_SZ_128BIT] = 4,
41 [XMIT_SZ_256BIT] = 5,
42 [XMIT_SZ_512BIT] = 6,
43};
44
45#define TS_LOW_BIT 0x3 /* --xx */
46#define TS_HI_BIT 0xc /* xx-- */
47
48#define TS_LOW_SHIFT (3)
49#define TS_HI_SHIFT (20 - 2) /* 2 bits for shifted low TS */
50
51#define TS_INDEX2VAL(i) \
52 ((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
53 (((i) & TS_HI_BIT) << TS_HI_SHIFT))
54
55#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
56#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
57
58
59/*
60 * USB High-Speed DMAC
61 */
62/* Transmit sizes and respective CHCR register values */
63enum {
64 USBTS_XMIT_SZ_8BYTE = 0,
65 USBTS_XMIT_SZ_16BYTE = 1,
66 USBTS_XMIT_SZ_32BYTE = 2,
67};
68
69/* log2(size / 8) - used to calculate number of transfers */
70static const unsigned int dma_usbts_shift[] = {
71 [USBTS_XMIT_SZ_8BYTE] = 3,
72 [USBTS_XMIT_SZ_16BYTE] = 4,
73 [USBTS_XMIT_SZ_32BYTE] = 5,
74};
75
76#define USBTS_LOW_BIT 0x3 /* --xx */
77#define USBTS_HI_BIT 0x0 /* ---- */
78
79#define USBTS_LOW_SHIFT 6
80#define USBTS_HI_SHIFT 0
81
82#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
83
84#endif /* DMA_REGISTER_H */
diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h
index de795b42232a..844507d937cb 100644
--- a/arch/arm/mach-shmobile/include/mach/gpio.h
+++ b/arch/arm/mach-shmobile/include/mach/gpio.h
@@ -13,6 +13,7 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/errno.h> 14#include <linux/errno.h>
15#include <linux/sh_pfc.h> 15#include <linux/sh_pfc.h>
16#include <linux/io.h>
16 17
17#ifdef CONFIG_GPIOLIB 18#ifdef CONFIG_GPIOLIB
18 19
@@ -27,4 +28,35 @@ static inline int irq_to_gpio(unsigned int irq)
27 28
28#endif /* CONFIG_GPIOLIB */ 29#endif /* CONFIG_GPIOLIB */
29 30
31/*
32 * FIXME !!
33 *
34 * current gpio frame work doesn't have
35 * the method to control only pull up/down/free.
36 * this function should be replaced by correct gpio function
37 */
38static inline void __init gpio_direction_none(u32 addr)
39{
40 __raw_writeb(0x00, addr);
41}
42
43static inline void __init gpio_request_pullup(u32 addr)
44{
45 u8 data = __raw_readb(addr);
46
47 data &= 0x0F;
48 data |= 0xC0;
49 __raw_writeb(data, addr);
50}
51
52static inline void __init gpio_request_pulldown(u32 addr)
53{
54 u8 data = __raw_readb(addr);
55
56 data &= 0x0F;
57 data |= 0xA0;
58
59 __raw_writeb(data, addr);
60}
61
30#endif /* __ASM_ARCH_GPIO_H */ 62#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-shmobile/include/mach/pm-rmobile.h b/arch/arm/mach-shmobile/include/mach/pm-rmobile.h
new file mode 100644
index 000000000000..5a402840fe28
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/pm-rmobile.h
@@ -0,0 +1,44 @@
1/*
2 * Copyright (C) 2012 Renesas Solutions Corp.
3 *
4 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef PM_RMOBILE_H
11#define PM_RMOBILE_H
12
13#include <linux/pm_domain.h>
14
15struct platform_device;
16
17struct rmobile_pm_domain {
18 struct generic_pm_domain genpd;
19 struct dev_power_governor *gov;
20 int (*suspend)(void);
21 void (*resume)(void);
22 unsigned int bit_shift;
23 bool no_debug;
24};
25
26static inline
27struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d)
28{
29 return container_of(d, struct rmobile_pm_domain, genpd);
30}
31
32#ifdef CONFIG_PM
33extern void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd);
34extern void rmobile_add_device_to_domain(struct rmobile_pm_domain *rmobile_pd,
35 struct platform_device *pdev);
36extern void rmobile_pm_add_subdomain(struct rmobile_pm_domain *rmobile_pd,
37 struct rmobile_pm_domain *rmobile_sd);
38#else
39#define rmobile_init_pm_domain(pd) do { } while (0)
40#define rmobile_add_device_to_domain(pd, pdev) do { } while (0)
41#define rmobile_pm_add_subdomain(pd, sd) do { } while (0)
42#endif /* CONFIG_PM */
43
44#endif /* PM_RMOBILE_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 6468fcc5ee49..7143147780df 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -19,6 +19,8 @@
19#ifndef __ASM_R8A7740_H__ 19#ifndef __ASM_R8A7740_H__
20#define __ASM_R8A7740_H__ 20#define __ASM_R8A7740_H__
21 21
22#include <mach/pm-rmobile.h>
23
22/* 24/*
23 * MD_CKx pin 25 * MD_CKx pin
24 */ 26 */
@@ -588,4 +590,26 @@ enum {
588 GPIO_FN_TRACEAUD_FROM_MEMC, 590 GPIO_FN_TRACEAUD_FROM_MEMC,
589}; 591};
590 592
593/* DMA slave IDs */
594enum {
595 SHDMA_SLAVE_INVALID,
596 SHDMA_SLAVE_SDHI0_RX,
597 SHDMA_SLAVE_SDHI0_TX,
598 SHDMA_SLAVE_SDHI1_RX,
599 SHDMA_SLAVE_SDHI1_TX,
600 SHDMA_SLAVE_SDHI2_RX,
601 SHDMA_SLAVE_SDHI2_TX,
602 SHDMA_SLAVE_FSIA_RX,
603 SHDMA_SLAVE_FSIA_TX,
604 SHDMA_SLAVE_FSIB_TX,
605 SHDMA_SLAVE_USBHS_TX,
606 SHDMA_SLAVE_USBHS_RX,
607};
608
609#ifdef CONFIG_PM
610extern struct rmobile_pm_domain r8a7740_pd_a4s;
611extern struct rmobile_pm_domain r8a7740_pd_a3sp;
612extern struct rmobile_pm_domain r8a7740_pd_a4lc;
613#endif /* CONFIG_PM */
614
591#endif /* __ASM_R8A7740_H__ */ 615#endif /* __ASM_R8A7740_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index 915d0093da08..b59048e6d8fd 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -13,6 +13,7 @@
13 13
14#include <linux/sh_clk.h> 14#include <linux/sh_clk.h>
15#include <linux/pm_domain.h> 15#include <linux/pm_domain.h>
16#include <mach/pm-rmobile.h>
16 17
17/* 18/*
18 * Pin Function Controller: 19 * Pin Function Controller:
@@ -477,42 +478,16 @@ extern struct clk sh7372_fsibck_clk;
477extern struct clk sh7372_fsidiva_clk; 478extern struct clk sh7372_fsidiva_clk;
478extern struct clk sh7372_fsidivb_clk; 479extern struct clk sh7372_fsidivb_clk;
479 480
480struct platform_device;
481
482struct sh7372_pm_domain {
483 struct generic_pm_domain genpd;
484 struct dev_power_governor *gov;
485 int (*suspend)(void);
486 void (*resume)(void);
487 unsigned int bit_shift;
488 bool no_debug;
489};
490
491static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d)
492{
493 return container_of(d, struct sh7372_pm_domain, genpd);
494}
495
496#ifdef CONFIG_PM 481#ifdef CONFIG_PM
497extern struct sh7372_pm_domain sh7372_a4lc; 482extern struct rmobile_pm_domain sh7372_pd_a4lc;
498extern struct sh7372_pm_domain sh7372_a4mp; 483extern struct rmobile_pm_domain sh7372_pd_a4mp;
499extern struct sh7372_pm_domain sh7372_d4; 484extern struct rmobile_pm_domain sh7372_pd_d4;
500extern struct sh7372_pm_domain sh7372_a4r; 485extern struct rmobile_pm_domain sh7372_pd_a4r;
501extern struct sh7372_pm_domain sh7372_a3rv; 486extern struct rmobile_pm_domain sh7372_pd_a3rv;
502extern struct sh7372_pm_domain sh7372_a3ri; 487extern struct rmobile_pm_domain sh7372_pd_a3ri;
503extern struct sh7372_pm_domain sh7372_a4s; 488extern struct rmobile_pm_domain sh7372_pd_a4s;
504extern struct sh7372_pm_domain sh7372_a3sp; 489extern struct rmobile_pm_domain sh7372_pd_a3sp;
505extern struct sh7372_pm_domain sh7372_a3sg; 490extern struct rmobile_pm_domain sh7372_pd_a3sg;
506
507extern void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd);
508extern void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
509 struct platform_device *pdev);
510extern void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
511 struct sh7372_pm_domain *sh7372_sd);
512#else
513#define sh7372_init_pm_domain(pd) do { } while(0)
514#define sh7372_add_device_to_domain(pd, pdev) do { } while(0)
515#define sh7372_pm_add_subdomain(pd, sd) do { } while(0)
516#endif /* CONFIG_PM */ 491#endif /* CONFIG_PM */
517 492
518extern void sh7372_intcs_suspend(void); 493extern void sh7372_intcs_suspend(void);
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 398e2c10913b..fe950f25d793 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -516,6 +516,13 @@ enum {
516 SHDMA_SLAVE_SDHI2_RX, 516 SHDMA_SLAVE_SDHI2_RX,
517 SHDMA_SLAVE_MMCIF_TX, 517 SHDMA_SLAVE_MMCIF_TX,
518 SHDMA_SLAVE_MMCIF_RX, 518 SHDMA_SLAVE_MMCIF_RX,
519 SHDMA_SLAVE_FSI2A_TX,
520 SHDMA_SLAVE_FSI2A_RX,
521 SHDMA_SLAVE_FSI2B_TX,
522 SHDMA_SLAVE_FSI2B_RX,
523 SHDMA_SLAVE_FSI2C_TX,
524 SHDMA_SLAVE_FSI2C_RX,
525 SHDMA_SLAVE_FSI2D_RX,
519}; 526};
520 527
521/* 528/*
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index 550b23df4fd4..f04fad4ec4fb 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -35,6 +35,9 @@
35#define INT2SMSKCR3 0xfe7822ac 35#define INT2SMSKCR3 0xfe7822ac
36#define INT2SMSKCR4 0xfe7822b0 36#define INT2SMSKCR4 0xfe7822b0
37 37
38#define INT2NTSR0 0xfe700060
39#define INT2NTSR1 0xfe700064
40
38static int r8a7779_set_wake(struct irq_data *data, unsigned int on) 41static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
39{ 42{
40 return 0; /* always allow wakeup */ 43 return 0; /* always allow wakeup */
@@ -49,6 +52,10 @@ void __init r8a7779_init_irq(void)
49 gic_init(0, 29, gic_dist_base, gic_cpu_base); 52 gic_init(0, 29, gic_dist_base, gic_cpu_base);
50 gic_arch_extn.irq_set_wake = r8a7779_set_wake; 53 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
51 54
55 /* route all interrupts to ARM */
56 __raw_writel(0xffffffff, INT2NTSR0);
57 __raw_writel(0x3fffffff, INT2NTSR1);
58
52 /* unmask all known interrupts in INTCS2 */ 59 /* unmask all known interrupts in INTCS2 */
53 __raw_writel(0xfffffff0, INT2SMSKCR0); 60 __raw_writel(0xfffffff0, INT2SMSKCR0);
54 __raw_writel(0xfff7ffff, INT2SMSKCR1); 61 __raw_writel(0xfff7ffff, INT2SMSKCR1);
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c
index 03def0fd7a05..ce9e7fa5cc8a 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7740.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7740.c
@@ -1261,7 +1261,7 @@ static pinmux_enum_t pinmux_data[] = {
1261 PINMUX_DATA(A21_MARK, PORT120_FN1), 1261 PINMUX_DATA(A21_MARK, PORT120_FN1),
1262 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2), 1262 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1263 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0), 1263 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1264 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_0), 1264 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
1265 1265
1266 /* Port121 */ 1266 /* Port121 */
1267 PINMUX_DATA(A20_MARK, PORT121_FN1), 1267 PINMUX_DATA(A20_MARK, PORT121_FN1),
@@ -1623,7 +1623,7 @@ static pinmux_enum_t pinmux_data[] = {
1623 1623
1624 /* Port209 */ 1624 /* Port209 */
1625 PINMUX_DATA(VBUS_MARK, PORT209_FN1), 1625 PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1626 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_1), 1626 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
1627 1627
1628 /* Port210 */ 1628 /* Port210 */
1629 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1), 1629 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
new file mode 100644
index 000000000000..893504d012a6
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-r8a7740.c
@@ -0,0 +1,54 @@
1/*
2 * r8a7740 power management support
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/console.h>
12#include <mach/pm-rmobile.h>
13
14#ifdef CONFIG_PM
15static int r8a7740_pd_a4s_suspend(void)
16{
17 /*
18 * The A4S domain contains the CPU core and therefore it should
19 * only be turned off if the CPU is in use.
20 */
21 return -EBUSY;
22}
23
24struct rmobile_pm_domain r8a7740_pd_a4s = {
25 .genpd.name = "A4S",
26 .bit_shift = 10,
27 .gov = &pm_domain_always_on_gov,
28 .no_debug = true,
29 .suspend = r8a7740_pd_a4s_suspend,
30};
31
32static int r8a7740_pd_a3sp_suspend(void)
33{
34 /*
35 * Serial consoles make use of SCIF hardware located in A3SP,
36 * keep such power domain on if "no_console_suspend" is set.
37 */
38 return console_suspend_enabled ? 0 : -EBUSY;
39}
40
41struct rmobile_pm_domain r8a7740_pd_a3sp = {
42 .genpd.name = "A3SP",
43 .bit_shift = 11,
44 .gov = &pm_domain_always_on_gov,
45 .no_debug = true,
46 .suspend = r8a7740_pd_a3sp_suspend,
47};
48
49struct rmobile_pm_domain r8a7740_pd_a4lc = {
50 .genpd.name = "A4LC",
51 .bit_shift = 1,
52};
53
54#endif /* CONFIG_PM */
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
new file mode 100644
index 000000000000..a8562540f1d6
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -0,0 +1,167 @@
1/*
2 * rmobile power management support
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * based on pm-sh7372.c
8 * Copyright (C) 2011 Magnus Damm
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <linux/console.h>
15#include <linux/delay.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/pm_clock.h>
19#include <asm/io.h>
20#include <mach/pm-rmobile.h>
21
22/* SYSC */
23#define SPDCR 0xe6180008
24#define SWUCR 0xe6180014
25#define PSTR 0xe6180080
26
27#define PSTR_RETRIES 100
28#define PSTR_DELAY_US 10
29
30#ifdef CONFIG_PM
31static int rmobile_pd_power_down(struct generic_pm_domain *genpd)
32{
33 struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd);
34 unsigned int mask = 1 << rmobile_pd->bit_shift;
35
36 if (rmobile_pd->suspend) {
37 int ret = rmobile_pd->suspend();
38
39 if (ret)
40 return ret;
41 }
42
43 if (__raw_readl(PSTR) & mask) {
44 unsigned int retry_count;
45 __raw_writel(mask, SPDCR);
46
47 for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
48 if (!(__raw_readl(SPDCR) & mask))
49 break;
50 cpu_relax();
51 }
52 }
53
54 if (!rmobile_pd->no_debug)
55 pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n",
56 genpd->name, mask, __raw_readl(PSTR));
57
58 return 0;
59}
60
61static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd,
62 bool do_resume)
63{
64 unsigned int mask = 1 << rmobile_pd->bit_shift;
65 unsigned int retry_count;
66 int ret = 0;
67
68 if (__raw_readl(PSTR) & mask)
69 goto out;
70
71 __raw_writel(mask, SWUCR);
72
73 for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
74 if (!(__raw_readl(SWUCR) & mask))
75 break;
76 if (retry_count > PSTR_RETRIES)
77 udelay(PSTR_DELAY_US);
78 else
79 cpu_relax();
80 }
81 if (!retry_count)
82 ret = -EIO;
83
84 if (!rmobile_pd->no_debug)
85 pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
86 rmobile_pd->genpd.name, mask, __raw_readl(PSTR));
87
88out:
89 if (ret == 0 && rmobile_pd->resume && do_resume)
90 rmobile_pd->resume();
91
92 return ret;
93}
94
95static int rmobile_pd_power_up(struct generic_pm_domain *genpd)
96{
97 return __rmobile_pd_power_up(to_rmobile_pd(genpd), true);
98}
99
100static bool rmobile_pd_active_wakeup(struct device *dev)
101{
102 bool (*active_wakeup)(struct device *dev);
103
104 active_wakeup = dev_gpd_data(dev)->ops.active_wakeup;
105 return active_wakeup ? active_wakeup(dev) : true;
106}
107
108static int rmobile_pd_stop_dev(struct device *dev)
109{
110 int (*stop)(struct device *dev);
111
112 stop = dev_gpd_data(dev)->ops.stop;
113 if (stop) {
114 int ret = stop(dev);
115 if (ret)
116 return ret;
117 }
118 return pm_clk_suspend(dev);
119}
120
121static int rmobile_pd_start_dev(struct device *dev)
122{
123 int (*start)(struct device *dev);
124 int ret;
125
126 ret = pm_clk_resume(dev);
127 if (ret)
128 return ret;
129
130 start = dev_gpd_data(dev)->ops.start;
131 if (start)
132 ret = start(dev);
133
134 return ret;
135}
136
137void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
138{
139 struct generic_pm_domain *genpd = &rmobile_pd->genpd;
140 struct dev_power_governor *gov = rmobile_pd->gov;
141
142 pm_genpd_init(genpd, gov ? : &simple_qos_governor, false);
143 genpd->dev_ops.stop = rmobile_pd_stop_dev;
144 genpd->dev_ops.start = rmobile_pd_start_dev;
145 genpd->dev_ops.active_wakeup = rmobile_pd_active_wakeup;
146 genpd->dev_irq_safe = true;
147 genpd->power_off = rmobile_pd_power_down;
148 genpd->power_on = rmobile_pd_power_up;
149 __rmobile_pd_power_up(rmobile_pd, false);
150}
151
152void rmobile_add_device_to_domain(struct rmobile_pm_domain *rmobile_pd,
153 struct platform_device *pdev)
154{
155 struct device *dev = &pdev->dev;
156
157 pm_genpd_add_device(&rmobile_pd->genpd, dev);
158 if (pm_clk_no_clocks(dev))
159 pm_clk_add(dev, NULL);
160}
161
162void rmobile_pm_add_subdomain(struct rmobile_pm_domain *rmobile_pd,
163 struct rmobile_pm_domain *rmobile_sd)
164{
165 pm_genpd_add_subdomain(&rmobile_pd->genpd, &rmobile_sd->genpd);
166}
167#endif /* CONFIG_PM */
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index a3bdb12acde9..792037069226 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -26,6 +26,7 @@
26#include <asm/suspend.h> 26#include <asm/suspend.h>
27#include <mach/common.h> 27#include <mach/common.h>
28#include <mach/sh7372.h> 28#include <mach/sh7372.h>
29#include <mach/pm-rmobile.h>
29 30
30/* DBG */ 31/* DBG */
31#define DBGREG1 0xe6100020 32#define DBGREG1 0xe6100020
@@ -41,13 +42,10 @@
41#define PLLC01STPCR 0xe61500c8 42#define PLLC01STPCR 0xe61500c8
42 43
43/* SYSC */ 44/* SYSC */
44#define SPDCR 0xe6180008
45#define SWUCR 0xe6180014
46#define SBAR 0xe6180020 45#define SBAR 0xe6180020
47#define WUPRMSK 0xe6180028 46#define WUPRMSK 0xe6180028
48#define WUPSMSK 0xe618002c 47#define WUPSMSK 0xe618002c
49#define WUPSMSK2 0xe6180048 48#define WUPSMSK2 0xe6180048
50#define PSTR 0xe6180080
51#define WUPSFAC 0xe6180098 49#define WUPSFAC 0xe6180098
52#define IRQCR 0xe618022c 50#define IRQCR 0xe618022c
53#define IRQCR2 0xe6180238 51#define IRQCR2 0xe6180238
@@ -71,188 +69,48 @@
71/* AP-System Core */ 69/* AP-System Core */
72#define APARMBAREA 0xe6f10020 70#define APARMBAREA 0xe6f10020
73 71
74#define PSTR_RETRIES 100
75#define PSTR_DELAY_US 10
76
77#ifdef CONFIG_PM 72#ifdef CONFIG_PM
78 73
79static int pd_power_down(struct generic_pm_domain *genpd) 74struct rmobile_pm_domain sh7372_pd_a4lc = {
80{
81 struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
82 unsigned int mask = 1 << sh7372_pd->bit_shift;
83
84 if (sh7372_pd->suspend) {
85 int ret = sh7372_pd->suspend();
86
87 if (ret)
88 return ret;
89 }
90
91 if (__raw_readl(PSTR) & mask) {
92 unsigned int retry_count;
93
94 __raw_writel(mask, SPDCR);
95
96 for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
97 if (!(__raw_readl(SPDCR) & mask))
98 break;
99 cpu_relax();
100 }
101 }
102
103 if (!sh7372_pd->no_debug)
104 pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n",
105 genpd->name, mask, __raw_readl(PSTR));
106
107 return 0;
108}
109
110static int __pd_power_up(struct sh7372_pm_domain *sh7372_pd, bool do_resume)
111{
112 unsigned int mask = 1 << sh7372_pd->bit_shift;
113 unsigned int retry_count;
114 int ret = 0;
115
116 if (__raw_readl(PSTR) & mask)
117 goto out;
118
119 __raw_writel(mask, SWUCR);
120
121 for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
122 if (!(__raw_readl(SWUCR) & mask))
123 break;
124 if (retry_count > PSTR_RETRIES)
125 udelay(PSTR_DELAY_US);
126 else
127 cpu_relax();
128 }
129 if (!retry_count)
130 ret = -EIO;
131
132 if (!sh7372_pd->no_debug)
133 pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
134 sh7372_pd->genpd.name, mask, __raw_readl(PSTR));
135
136 out:
137 if (ret == 0 && sh7372_pd->resume && do_resume)
138 sh7372_pd->resume();
139
140 return ret;
141}
142
143static int pd_power_up(struct generic_pm_domain *genpd)
144{
145 return __pd_power_up(to_sh7372_pd(genpd), true);
146}
147
148static int sh7372_a4r_suspend(void)
149{
150 sh7372_intcs_suspend();
151 __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
152 return 0;
153}
154
155static bool pd_active_wakeup(struct device *dev)
156{
157 bool (*active_wakeup)(struct device *dev);
158
159 active_wakeup = dev_gpd_data(dev)->ops.active_wakeup;
160 return active_wakeup ? active_wakeup(dev) : true;
161}
162
163static int sh7372_stop_dev(struct device *dev)
164{
165 int (*stop)(struct device *dev);
166
167 stop = dev_gpd_data(dev)->ops.stop;
168 if (stop) {
169 int ret = stop(dev);
170 if (ret)
171 return ret;
172 }
173 return pm_clk_suspend(dev);
174}
175
176static int sh7372_start_dev(struct device *dev)
177{
178 int (*start)(struct device *dev);
179 int ret;
180
181 ret = pm_clk_resume(dev);
182 if (ret)
183 return ret;
184
185 start = dev_gpd_data(dev)->ops.start;
186 if (start)
187 ret = start(dev);
188
189 return ret;
190}
191
192void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
193{
194 struct generic_pm_domain *genpd = &sh7372_pd->genpd;
195 struct dev_power_governor *gov = sh7372_pd->gov;
196
197 pm_genpd_init(genpd, gov ? : &simple_qos_governor, false);
198 genpd->dev_ops.stop = sh7372_stop_dev;
199 genpd->dev_ops.start = sh7372_start_dev;
200 genpd->dev_ops.active_wakeup = pd_active_wakeup;
201 genpd->dev_irq_safe = true;
202 genpd->power_off = pd_power_down;
203 genpd->power_on = pd_power_up;
204 __pd_power_up(sh7372_pd, false);
205}
206
207void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
208 struct platform_device *pdev)
209{
210 struct device *dev = &pdev->dev;
211
212 pm_genpd_add_device(&sh7372_pd->genpd, dev);
213 if (pm_clk_no_clocks(dev))
214 pm_clk_add(dev, NULL);
215}
216
217void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
218 struct sh7372_pm_domain *sh7372_sd)
219{
220 pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd);
221}
222
223struct sh7372_pm_domain sh7372_a4lc = {
224 .genpd.name = "A4LC", 75 .genpd.name = "A4LC",
225 .bit_shift = 1, 76 .bit_shift = 1,
226}; 77};
227 78
228struct sh7372_pm_domain sh7372_a4mp = { 79struct rmobile_pm_domain sh7372_pd_a4mp = {
229 .genpd.name = "A4MP", 80 .genpd.name = "A4MP",
230 .bit_shift = 2, 81 .bit_shift = 2,
231}; 82};
232 83
233struct sh7372_pm_domain sh7372_d4 = { 84struct rmobile_pm_domain sh7372_pd_d4 = {
234 .genpd.name = "D4", 85 .genpd.name = "D4",
235 .bit_shift = 3, 86 .bit_shift = 3,
236}; 87};
237 88
238struct sh7372_pm_domain sh7372_a4r = { 89static int sh7372_a4r_pd_suspend(void)
90{
91 sh7372_intcs_suspend();
92 __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
93 return 0;
94}
95
96struct rmobile_pm_domain sh7372_pd_a4r = {
239 .genpd.name = "A4R", 97 .genpd.name = "A4R",
240 .bit_shift = 5, 98 .bit_shift = 5,
241 .suspend = sh7372_a4r_suspend, 99 .suspend = sh7372_a4r_pd_suspend,
242 .resume = sh7372_intcs_resume, 100 .resume = sh7372_intcs_resume,
243}; 101};
244 102
245struct sh7372_pm_domain sh7372_a3rv = { 103struct rmobile_pm_domain sh7372_pd_a3rv = {
246 .genpd.name = "A3RV", 104 .genpd.name = "A3RV",
247 .bit_shift = 6, 105 .bit_shift = 6,
248}; 106};
249 107
250struct sh7372_pm_domain sh7372_a3ri = { 108struct rmobile_pm_domain sh7372_pd_a3ri = {
251 .genpd.name = "A3RI", 109 .genpd.name = "A3RI",
252 .bit_shift = 8, 110 .bit_shift = 8,
253}; 111};
254 112
255static int sh7372_a4s_suspend(void) 113static int sh7372_pd_a4s_suspend(void)
256{ 114{
257 /* 115 /*
258 * The A4S domain contains the CPU core and therefore it should 116 * The A4S domain contains the CPU core and therefore it should
@@ -261,15 +119,15 @@ static int sh7372_a4s_suspend(void)
261 return -EBUSY; 119 return -EBUSY;
262} 120}
263 121
264struct sh7372_pm_domain sh7372_a4s = { 122struct rmobile_pm_domain sh7372_pd_a4s = {
265 .genpd.name = "A4S", 123 .genpd.name = "A4S",
266 .bit_shift = 10, 124 .bit_shift = 10,
267 .gov = &pm_domain_always_on_gov, 125 .gov = &pm_domain_always_on_gov,
268 .no_debug = true, 126 .no_debug = true,
269 .suspend = sh7372_a4s_suspend, 127 .suspend = sh7372_pd_a4s_suspend,
270}; 128};
271 129
272static int sh7372_a3sp_suspend(void) 130static int sh7372_a3sp_pd_suspend(void)
273{ 131{
274 /* 132 /*
275 * Serial consoles make use of SCIF hardware located in A3SP, 133 * Serial consoles make use of SCIF hardware located in A3SP,
@@ -278,32 +136,22 @@ static int sh7372_a3sp_suspend(void)
278 return console_suspend_enabled ? 0 : -EBUSY; 136 return console_suspend_enabled ? 0 : -EBUSY;
279} 137}
280 138
281struct sh7372_pm_domain sh7372_a3sp = { 139struct rmobile_pm_domain sh7372_pd_a3sp = {
282 .genpd.name = "A3SP", 140 .genpd.name = "A3SP",
283 .bit_shift = 11, 141 .bit_shift = 11,
284 .gov = &pm_domain_always_on_gov, 142 .gov = &pm_domain_always_on_gov,
285 .no_debug = true, 143 .no_debug = true,
286 .suspend = sh7372_a3sp_suspend, 144 .suspend = sh7372_a3sp_pd_suspend,
287}; 145};
288 146
289struct sh7372_pm_domain sh7372_a3sg = { 147struct rmobile_pm_domain sh7372_pd_a3sg = {
290 .genpd.name = "A3SG", 148 .genpd.name = "A3SG",
291 .bit_shift = 13, 149 .bit_shift = 13,
292}; 150};
293 151
294#else /* !CONFIG_PM */ 152#endif /* CONFIG_PM */
295
296static inline void sh7372_a3sp_init(void) {}
297
298#endif /* !CONFIG_PM */
299 153
300#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) 154#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
301static int sh7372_do_idle_core_standby(unsigned long unused)
302{
303 cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
304 return 0;
305}
306
307static void sh7372_set_reset_vector(unsigned long address) 155static void sh7372_set_reset_vector(unsigned long address)
308{ 156{
309 /* set reset vector, translate 4k */ 157 /* set reset vector, translate 4k */
@@ -311,21 +159,6 @@ static void sh7372_set_reset_vector(unsigned long address)
311 __raw_writel(0, APARMBAREA); 159 __raw_writel(0, APARMBAREA);
312} 160}
313 161
314static void sh7372_enter_core_standby(void)
315{
316 sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
317
318 /* enter sleep mode with SYSTBCR to 0x10 */
319 __raw_writel(0x10, SYSTBCR);
320 cpu_suspend(0, sh7372_do_idle_core_standby);
321 __raw_writel(0, SYSTBCR);
322
323 /* disable reset vector translation */
324 __raw_writel(0, SBAR);
325}
326#endif
327
328#ifdef CONFIG_SUSPEND
329static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode) 162static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode)
330{ 163{
331 if (pllc0_on) 164 if (pllc0_on)
@@ -465,22 +298,42 @@ static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2)
465 298
466static void sh7372_enter_a3sm_common(int pllc0_on) 299static void sh7372_enter_a3sm_common(int pllc0_on)
467{ 300{
301 /* use INTCA together with SYSC for wakeup */
302 sh7372_setup_sysc(1 << 0, 0);
468 sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc)); 303 sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
469 sh7372_enter_sysc(pllc0_on, 1 << 12); 304 sh7372_enter_sysc(pllc0_on, 1 << 12);
470} 305}
306#endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */
471 307
472static void sh7372_enter_a4s_common(int pllc0_on) 308#ifdef CONFIG_CPU_IDLE
309static int sh7372_do_idle_core_standby(unsigned long unused)
473{ 310{
474 sh7372_intca_suspend(); 311 cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
475 memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100); 312 return 0;
476 sh7372_set_reset_vector(SMFRAM);
477 sh7372_enter_sysc(pllc0_on, 1 << 10);
478 sh7372_intca_resume();
479} 313}
480 314
481#endif 315static void sh7372_enter_core_standby(void)
316{
317 sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
482 318
483#ifdef CONFIG_CPU_IDLE 319 /* enter sleep mode with SYSTBCR to 0x10 */
320 __raw_writel(0x10, SYSTBCR);
321 cpu_suspend(0, sh7372_do_idle_core_standby);
322 __raw_writel(0, SYSTBCR);
323
324 /* disable reset vector translation */
325 __raw_writel(0, SBAR);
326}
327
328static void sh7372_enter_a3sm_pll_on(void)
329{
330 sh7372_enter_a3sm_common(1);
331}
332
333static void sh7372_enter_a3sm_pll_off(void)
334{
335 sh7372_enter_a3sm_common(0);
336}
484 337
485static void sh7372_cpuidle_setup(struct cpuidle_driver *drv) 338static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
486{ 339{
@@ -492,7 +345,24 @@ static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
492 state->target_residency = 20 + 10; 345 state->target_residency = 20 + 10;
493 state->flags = CPUIDLE_FLAG_TIME_VALID; 346 state->flags = CPUIDLE_FLAG_TIME_VALID;
494 shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby; 347 shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby;
348 drv->state_count++;
349
350 state = &drv->states[drv->state_count];
351 snprintf(state->name, CPUIDLE_NAME_LEN, "C3");
352 strncpy(state->desc, "A3SM PLL ON", CPUIDLE_DESC_LEN);
353 state->exit_latency = 20;
354 state->target_residency = 30 + 20;
355 state->flags = CPUIDLE_FLAG_TIME_VALID;
356 shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_on;
357 drv->state_count++;
495 358
359 state = &drv->states[drv->state_count];
360 snprintf(state->name, CPUIDLE_NAME_LEN, "C4");
361 strncpy(state->desc, "A3SM PLL OFF", CPUIDLE_DESC_LEN);
362 state->exit_latency = 120;
363 state->target_residency = 30 + 120;
364 state->flags = CPUIDLE_FLAG_TIME_VALID;
365 shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_off;
496 drv->state_count++; 366 drv->state_count++;
497} 367}
498 368
@@ -505,6 +375,14 @@ static void sh7372_cpuidle_init(void) {}
505#endif 375#endif
506 376
507#ifdef CONFIG_SUSPEND 377#ifdef CONFIG_SUSPEND
378static void sh7372_enter_a4s_common(int pllc0_on)
379{
380 sh7372_intca_suspend();
381 memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
382 sh7372_set_reset_vector(SMFRAM);
383 sh7372_enter_sysc(pllc0_on, 1 << 10);
384 sh7372_intca_resume();
385}
508 386
509static int sh7372_enter_suspend(suspend_state_t suspend_state) 387static int sh7372_enter_suspend(suspend_state_t suspend_state)
510{ 388{
@@ -512,24 +390,21 @@ static int sh7372_enter_suspend(suspend_state_t suspend_state)
512 390
513 /* check active clocks to determine potential wakeup sources */ 391 /* check active clocks to determine potential wakeup sources */
514 if (sh7372_sysc_valid(&msk, &msk2)) { 392 if (sh7372_sysc_valid(&msk, &msk2)) {
515 /* convert INTC mask and sense to SYSC mask and sense */
516 sh7372_setup_sysc(msk, msk2);
517
518 if (!console_suspend_enabled && 393 if (!console_suspend_enabled &&
519 sh7372_a4s.genpd.status == GPD_STATE_POWER_OFF) { 394 sh7372_pd_a4s.genpd.status == GPD_STATE_POWER_OFF) {
395 /* convert INTC mask/sense to SYSC mask/sense */
396 sh7372_setup_sysc(msk, msk2);
397
520 /* enter A4S sleep with PLLC0 off */ 398 /* enter A4S sleep with PLLC0 off */
521 pr_debug("entering A4S\n"); 399 pr_debug("entering A4S\n");
522 sh7372_enter_a4s_common(0); 400 sh7372_enter_a4s_common(0);
523 } else { 401 return 0;
524 /* enter A3SM sleep with PLLC0 off */
525 pr_debug("entering A3SM\n");
526 sh7372_enter_a3sm_common(0);
527 } 402 }
528 } else {
529 /* default to Core Standby that supports all wakeup sources */
530 pr_debug("entering Core Standby\n");
531 sh7372_enter_core_standby();
532 } 403 }
404
405 /* default to enter A3SM sleep with PLLC0 off */
406 pr_debug("entering A3SM\n");
407 sh7372_enter_a3sm_common(0);
533 return 0; 408 return 0;
534} 409}
535 410
@@ -550,7 +425,7 @@ static int sh7372_pm_notifier_fn(struct notifier_block *notifier,
550 * executed during system suspend and resume, respectively, so 425 * executed during system suspend and resume, respectively, so
551 * that those functions don't crash while accessing the INTCS. 426 * that those functions don't crash while accessing the INTCS.
552 */ 427 */
553 pm_genpd_poweron(&sh7372_a4r.genpd); 428 pm_genpd_poweron(&sh7372_pd_a4r.genpd);
554 break; 429 break;
555 case PM_POST_SUSPEND: 430 case PM_POST_SUSPEND:
556 pm_genpd_poweroff_unused(); 431 pm_genpd_poweroff_unused();
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 366311b3dc73..78948a9dba0e 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -23,9 +23,14 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/of_platform.h>
26#include <linux/serial_sci.h> 27#include <linux/serial_sci.h>
28#include <linux/sh_dma.h>
27#include <linux/sh_timer.h> 29#include <linux/sh_timer.h>
30#include <linux/dma-mapping.h>
31#include <mach/dma-register.h>
28#include <mach/r8a7740.h> 32#include <mach/r8a7740.h>
33#include <mach/pm-rmobile.h>
29#include <mach/common.h> 34#include <mach/common.h>
30#include <mach/irqs.h> 35#include <mach/irqs.h>
31#include <asm/mach-types.h> 36#include <asm/mach-types.h>
@@ -276,6 +281,272 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
276 &cmt10_device, 281 &cmt10_device,
277}; 282};
278 283
284/* DMA */
285static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
286 {
287 .slave_id = SHDMA_SLAVE_SDHI0_TX,
288 .addr = 0xe6850030,
289 .chcr = CHCR_TX(XMIT_SZ_16BIT),
290 .mid_rid = 0xc1,
291 }, {
292 .slave_id = SHDMA_SLAVE_SDHI0_RX,
293 .addr = 0xe6850030,
294 .chcr = CHCR_RX(XMIT_SZ_16BIT),
295 .mid_rid = 0xc2,
296 }, {
297 .slave_id = SHDMA_SLAVE_SDHI1_TX,
298 .addr = 0xe6860030,
299 .chcr = CHCR_TX(XMIT_SZ_16BIT),
300 .mid_rid = 0xc9,
301 }, {
302 .slave_id = SHDMA_SLAVE_SDHI1_RX,
303 .addr = 0xe6860030,
304 .chcr = CHCR_RX(XMIT_SZ_16BIT),
305 .mid_rid = 0xca,
306 }, {
307 .slave_id = SHDMA_SLAVE_SDHI2_TX,
308 .addr = 0xe6870030,
309 .chcr = CHCR_TX(XMIT_SZ_16BIT),
310 .mid_rid = 0xcd,
311 }, {
312 .slave_id = SHDMA_SLAVE_SDHI2_RX,
313 .addr = 0xe6870030,
314 .chcr = CHCR_RX(XMIT_SZ_16BIT),
315 .mid_rid = 0xce,
316 }, {
317 .slave_id = SHDMA_SLAVE_FSIA_TX,
318 .addr = 0xfe1f0024,
319 .chcr = CHCR_TX(XMIT_SZ_32BIT),
320 .mid_rid = 0xb1,
321 }, {
322 .slave_id = SHDMA_SLAVE_FSIA_RX,
323 .addr = 0xfe1f0020,
324 .chcr = CHCR_RX(XMIT_SZ_32BIT),
325 .mid_rid = 0xb2,
326 }, {
327 .slave_id = SHDMA_SLAVE_FSIB_TX,
328 .addr = 0xfe1f0064,
329 .chcr = CHCR_TX(XMIT_SZ_32BIT),
330 .mid_rid = 0xb5,
331 },
332};
333
334#define DMA_CHANNEL(a, b, c) \
335{ \
336 .offset = a, \
337 .dmars = b, \
338 .dmars_bit = c, \
339 .chclr_offset = (0x220 - 0x20) + a \
340}
341
342static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
343 DMA_CHANNEL(0x00, 0, 0),
344 DMA_CHANNEL(0x10, 0, 8),
345 DMA_CHANNEL(0x20, 4, 0),
346 DMA_CHANNEL(0x30, 4, 8),
347 DMA_CHANNEL(0x50, 8, 0),
348 DMA_CHANNEL(0x60, 8, 8),
349};
350
351static struct sh_dmae_pdata dma_platform_data = {
352 .slave = r8a7740_dmae_slaves,
353 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
354 .channel = r8a7740_dmae_channels,
355 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
356 .ts_low_shift = TS_LOW_SHIFT,
357 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
358 .ts_high_shift = TS_HI_SHIFT,
359 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
360 .ts_shift = dma_ts_shift,
361 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
362 .dmaor_init = DMAOR_DME,
363 .chclr_present = 1,
364};
365
366/* Resource order important! */
367static struct resource r8a7740_dmae0_resources[] = {
368 {
369 /* Channel registers and DMAOR */
370 .start = 0xfe008020,
371 .end = 0xfe00828f,
372 .flags = IORESOURCE_MEM,
373 },
374 {
375 /* DMARSx */
376 .start = 0xfe009000,
377 .end = 0xfe00900b,
378 .flags = IORESOURCE_MEM,
379 },
380 {
381 .name = "error_irq",
382 .start = evt2irq(0x20c0),
383 .end = evt2irq(0x20c0),
384 .flags = IORESOURCE_IRQ,
385 },
386 {
387 /* IRQ for channels 0-5 */
388 .start = evt2irq(0x2000),
389 .end = evt2irq(0x20a0),
390 .flags = IORESOURCE_IRQ,
391 },
392};
393
394/* Resource order important! */
395static struct resource r8a7740_dmae1_resources[] = {
396 {
397 /* Channel registers and DMAOR */
398 .start = 0xfe018020,
399 .end = 0xfe01828f,
400 .flags = IORESOURCE_MEM,
401 },
402 {
403 /* DMARSx */
404 .start = 0xfe019000,
405 .end = 0xfe01900b,
406 .flags = IORESOURCE_MEM,
407 },
408 {
409 .name = "error_irq",
410 .start = evt2irq(0x21c0),
411 .end = evt2irq(0x21c0),
412 .flags = IORESOURCE_IRQ,
413 },
414 {
415 /* IRQ for channels 0-5 */
416 .start = evt2irq(0x2100),
417 .end = evt2irq(0x21a0),
418 .flags = IORESOURCE_IRQ,
419 },
420};
421
422/* Resource order important! */
423static struct resource r8a7740_dmae2_resources[] = {
424 {
425 /* Channel registers and DMAOR */
426 .start = 0xfe028020,
427 .end = 0xfe02828f,
428 .flags = IORESOURCE_MEM,
429 },
430 {
431 /* DMARSx */
432 .start = 0xfe029000,
433 .end = 0xfe02900b,
434 .flags = IORESOURCE_MEM,
435 },
436 {
437 .name = "error_irq",
438 .start = evt2irq(0x22c0),
439 .end = evt2irq(0x22c0),
440 .flags = IORESOURCE_IRQ,
441 },
442 {
443 /* IRQ for channels 0-5 */
444 .start = evt2irq(0x2200),
445 .end = evt2irq(0x22a0),
446 .flags = IORESOURCE_IRQ,
447 },
448};
449
450static struct platform_device dma0_device = {
451 .name = "sh-dma-engine",
452 .id = 0,
453 .resource = r8a7740_dmae0_resources,
454 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
455 .dev = {
456 .platform_data = &dma_platform_data,
457 },
458};
459
460static struct platform_device dma1_device = {
461 .name = "sh-dma-engine",
462 .id = 1,
463 .resource = r8a7740_dmae1_resources,
464 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
465 .dev = {
466 .platform_data = &dma_platform_data,
467 },
468};
469
470static struct platform_device dma2_device = {
471 .name = "sh-dma-engine",
472 .id = 2,
473 .resource = r8a7740_dmae2_resources,
474 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
475 .dev = {
476 .platform_data = &dma_platform_data,
477 },
478};
479
480/* USB-DMAC */
481static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
482 {
483 .offset = 0,
484 }, {
485 .offset = 0x20,
486 },
487};
488
489static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
490 {
491 .slave_id = SHDMA_SLAVE_USBHS_TX,
492 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
493 }, {
494 .slave_id = SHDMA_SLAVE_USBHS_RX,
495 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
496 },
497};
498
499static struct sh_dmae_pdata usb_dma_platform_data = {
500 .slave = r8a7740_usb_dma_slaves,
501 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
502 .channel = r8a7740_usb_dma_channels,
503 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
504 .ts_low_shift = USBTS_LOW_SHIFT,
505 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
506 .ts_high_shift = USBTS_HI_SHIFT,
507 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
508 .ts_shift = dma_usbts_shift,
509 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
510 .dmaor_init = DMAOR_DME,
511 .chcr_offset = 0x14,
512 .chcr_ie_bit = 1 << 5,
513 .dmaor_is_32bit = 1,
514 .needs_tend_set = 1,
515 .no_dmars = 1,
516 .slave_only = 1,
517};
518
519static struct resource r8a7740_usb_dma_resources[] = {
520 {
521 /* Channel registers and DMAOR */
522 .start = 0xe68a0020,
523 .end = 0xe68a0064 - 1,
524 .flags = IORESOURCE_MEM,
525 },
526 {
527 /* VCR/SWR/DMICR */
528 .start = 0xe68a0000,
529 .end = 0xe68a0014 - 1,
530 .flags = IORESOURCE_MEM,
531 },
532 {
533 /* IRQ for channels */
534 .start = evt2irq(0x0a00),
535 .end = evt2irq(0x0a00),
536 .flags = IORESOURCE_IRQ,
537 },
538};
539
540static struct platform_device usb_dma_device = {
541 .name = "sh-dma-engine",
542 .id = 3,
543 .resource = r8a7740_usb_dma_resources,
544 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
545 .dev = {
546 .platform_data = &usb_dma_platform_data,
547 },
548};
549
279/* I2C */ 550/* I2C */
280static struct resource i2c0_resources[] = { 551static struct resource i2c0_resources[] = {
281 [0] = { 552 [0] = {
@@ -322,6 +593,10 @@ static struct platform_device i2c1_device = {
322static struct platform_device *r8a7740_late_devices[] __initdata = { 593static struct platform_device *r8a7740_late_devices[] __initdata = {
323 &i2c0_device, 594 &i2c0_device,
324 &i2c1_device, 595 &i2c1_device,
596 &dma0_device,
597 &dma1_device,
598 &dma2_device,
599 &usb_dma_device,
325}; 600};
326 601
327/* 602/*
@@ -398,10 +673,31 @@ void __init r8a7740_add_standard_devices(void)
398 r8a7740_i2c_workaround(&i2c0_device); 673 r8a7740_i2c_workaround(&i2c0_device);
399 r8a7740_i2c_workaround(&i2c1_device); 674 r8a7740_i2c_workaround(&i2c1_device);
400 675
676 /* PM domain */
677 rmobile_init_pm_domain(&r8a7740_pd_a4s);
678 rmobile_init_pm_domain(&r8a7740_pd_a3sp);
679 rmobile_init_pm_domain(&r8a7740_pd_a4lc);
680
681 rmobile_pm_add_subdomain(&r8a7740_pd_a4s, &r8a7740_pd_a3sp);
682
683 /* add devices */
401 platform_add_devices(r8a7740_early_devices, 684 platform_add_devices(r8a7740_early_devices,
402 ARRAY_SIZE(r8a7740_early_devices)); 685 ARRAY_SIZE(r8a7740_early_devices));
403 platform_add_devices(r8a7740_late_devices, 686 platform_add_devices(r8a7740_late_devices,
404 ARRAY_SIZE(r8a7740_late_devices)); 687 ARRAY_SIZE(r8a7740_late_devices));
688
689 /* add devices to PM domain */
690
691 rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif0_device);
692 rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif1_device);
693 rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif2_device);
694 rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif3_device);
695 rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif4_device);
696 rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif5_device);
697 rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif6_device);
698 rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif7_device);
699 rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scifb_device);
700 rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &i2c1_device);
405} 701}
406 702
407static void __init r8a7740_earlytimer_init(void) 703static void __init r8a7740_earlytimer_init(void)
@@ -421,3 +717,49 @@ void __init r8a7740_add_early_devices(void)
421 /* override timer setup with soc-specific code */ 717 /* override timer setup with soc-specific code */
422 shmobile_timer.init = r8a7740_earlytimer_init; 718 shmobile_timer.init = r8a7740_earlytimer_init;
423} 719}
720
721#ifdef CONFIG_USE_OF
722
723void __init r8a7740_add_early_devices_dt(void)
724{
725 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
726
727 early_platform_add_devices(r8a7740_early_devices,
728 ARRAY_SIZE(r8a7740_early_devices));
729
730 /* setup early console here as well */
731 shmobile_setup_console();
732}
733
734static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
735 { }
736};
737
738void __init r8a7740_add_standard_devices_dt(void)
739{
740 /* clocks are setup late during boot in the case of DT */
741 r8a7740_clock_init(0);
742
743 platform_add_devices(r8a7740_early_devices,
744 ARRAY_SIZE(r8a7740_early_devices));
745
746 of_platform_populate(NULL, of_default_bus_match_table,
747 r8a7740_auxdata_lookup, NULL);
748}
749
750static const char *r8a7740_boards_compat_dt[] __initdata = {
751 "renesas,r8a7740",
752 NULL,
753};
754
755DT_MACHINE_START(SH7372_DT, "Generic R8A7740 (Flattened Device Tree)")
756 .map_io = r8a7740_map_io,
757 .init_early = r8a7740_add_early_devices_dt,
758 .init_irq = r8a7740_init_irq,
759 .handle_irq = shmobile_handle_irq_intc,
760 .init_machine = r8a7740_add_standard_devices_dt,
761 .timer = &shmobile_timer,
762 .dt_compat = r8a7740_boards_compat_dt,
763MACHINE_END
764
765#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index fafce9ce8218..838a87be1d5c 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -33,6 +33,7 @@
33#include <linux/sh_timer.h> 33#include <linux/sh_timer.h>
34#include <linux/pm_domain.h> 34#include <linux/pm_domain.h>
35#include <linux/dma-mapping.h> 35#include <linux/dma-mapping.h>
36#include <mach/dma-register.h>
36#include <mach/hardware.h> 37#include <mach/hardware.h>
37#include <mach/irqs.h> 38#include <mach/irqs.h>
38#include <mach/sh7372.h> 39#include <mach/sh7372.h>
@@ -335,151 +336,126 @@ static struct platform_device iic1_device = {
335}; 336};
336 337
337/* DMA */ 338/* DMA */
338/* Transmit sizes and respective CHCR register values */
339enum {
340 XMIT_SZ_8BIT = 0,
341 XMIT_SZ_16BIT = 1,
342 XMIT_SZ_32BIT = 2,
343 XMIT_SZ_64BIT = 7,
344 XMIT_SZ_128BIT = 3,
345 XMIT_SZ_256BIT = 4,
346 XMIT_SZ_512BIT = 5,
347};
348
349/* log2(size / 8) - used to calculate number of transfers */
350#define TS_SHIFT { \
351 [XMIT_SZ_8BIT] = 0, \
352 [XMIT_SZ_16BIT] = 1, \
353 [XMIT_SZ_32BIT] = 2, \
354 [XMIT_SZ_64BIT] = 3, \
355 [XMIT_SZ_128BIT] = 4, \
356 [XMIT_SZ_256BIT] = 5, \
357 [XMIT_SZ_512BIT] = 6, \
358}
359
360#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
361 (((i) & 0xc) << (20 - 2)))
362
363static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = { 339static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
364 { 340 {
365 .slave_id = SHDMA_SLAVE_SCIF0_TX, 341 .slave_id = SHDMA_SLAVE_SCIF0_TX,
366 .addr = 0xe6c40020, 342 .addr = 0xe6c40020,
367 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 343 .chcr = CHCR_TX(XMIT_SZ_8BIT),
368 .mid_rid = 0x21, 344 .mid_rid = 0x21,
369 }, { 345 }, {
370 .slave_id = SHDMA_SLAVE_SCIF0_RX, 346 .slave_id = SHDMA_SLAVE_SCIF0_RX,
371 .addr = 0xe6c40024, 347 .addr = 0xe6c40024,
372 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 348 .chcr = CHCR_RX(XMIT_SZ_8BIT),
373 .mid_rid = 0x22, 349 .mid_rid = 0x22,
374 }, { 350 }, {
375 .slave_id = SHDMA_SLAVE_SCIF1_TX, 351 .slave_id = SHDMA_SLAVE_SCIF1_TX,
376 .addr = 0xe6c50020, 352 .addr = 0xe6c50020,
377 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 353 .chcr = CHCR_TX(XMIT_SZ_8BIT),
378 .mid_rid = 0x25, 354 .mid_rid = 0x25,
379 }, { 355 }, {
380 .slave_id = SHDMA_SLAVE_SCIF1_RX, 356 .slave_id = SHDMA_SLAVE_SCIF1_RX,
381 .addr = 0xe6c50024, 357 .addr = 0xe6c50024,
382 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 358 .chcr = CHCR_RX(XMIT_SZ_8BIT),
383 .mid_rid = 0x26, 359 .mid_rid = 0x26,
384 }, { 360 }, {
385 .slave_id = SHDMA_SLAVE_SCIF2_TX, 361 .slave_id = SHDMA_SLAVE_SCIF2_TX,
386 .addr = 0xe6c60020, 362 .addr = 0xe6c60020,
387 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 363 .chcr = CHCR_TX(XMIT_SZ_8BIT),
388 .mid_rid = 0x29, 364 .mid_rid = 0x29,
389 }, { 365 }, {
390 .slave_id = SHDMA_SLAVE_SCIF2_RX, 366 .slave_id = SHDMA_SLAVE_SCIF2_RX,
391 .addr = 0xe6c60024, 367 .addr = 0xe6c60024,
392 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 368 .chcr = CHCR_RX(XMIT_SZ_8BIT),
393 .mid_rid = 0x2a, 369 .mid_rid = 0x2a,
394 }, { 370 }, {
395 .slave_id = SHDMA_SLAVE_SCIF3_TX, 371 .slave_id = SHDMA_SLAVE_SCIF3_TX,
396 .addr = 0xe6c70020, 372 .addr = 0xe6c70020,
397 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 373 .chcr = CHCR_TX(XMIT_SZ_8BIT),
398 .mid_rid = 0x2d, 374 .mid_rid = 0x2d,
399 }, { 375 }, {
400 .slave_id = SHDMA_SLAVE_SCIF3_RX, 376 .slave_id = SHDMA_SLAVE_SCIF3_RX,
401 .addr = 0xe6c70024, 377 .addr = 0xe6c70024,
402 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 378 .chcr = CHCR_RX(XMIT_SZ_8BIT),
403 .mid_rid = 0x2e, 379 .mid_rid = 0x2e,
404 }, { 380 }, {
405 .slave_id = SHDMA_SLAVE_SCIF4_TX, 381 .slave_id = SHDMA_SLAVE_SCIF4_TX,
406 .addr = 0xe6c80020, 382 .addr = 0xe6c80020,
407 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 383 .chcr = CHCR_TX(XMIT_SZ_8BIT),
408 .mid_rid = 0x39, 384 .mid_rid = 0x39,
409 }, { 385 }, {
410 .slave_id = SHDMA_SLAVE_SCIF4_RX, 386 .slave_id = SHDMA_SLAVE_SCIF4_RX,
411 .addr = 0xe6c80024, 387 .addr = 0xe6c80024,
412 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 388 .chcr = CHCR_RX(XMIT_SZ_8BIT),
413 .mid_rid = 0x3a, 389 .mid_rid = 0x3a,
414 }, { 390 }, {
415 .slave_id = SHDMA_SLAVE_SCIF5_TX, 391 .slave_id = SHDMA_SLAVE_SCIF5_TX,
416 .addr = 0xe6cb0020, 392 .addr = 0xe6cb0020,
417 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 393 .chcr = CHCR_TX(XMIT_SZ_8BIT),
418 .mid_rid = 0x35, 394 .mid_rid = 0x35,
419 }, { 395 }, {
420 .slave_id = SHDMA_SLAVE_SCIF5_RX, 396 .slave_id = SHDMA_SLAVE_SCIF5_RX,
421 .addr = 0xe6cb0024, 397 .addr = 0xe6cb0024,
422 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 398 .chcr = CHCR_RX(XMIT_SZ_8BIT),
423 .mid_rid = 0x36, 399 .mid_rid = 0x36,
424 }, { 400 }, {
425 .slave_id = SHDMA_SLAVE_SCIF6_TX, 401 .slave_id = SHDMA_SLAVE_SCIF6_TX,
426 .addr = 0xe6c30040, 402 .addr = 0xe6c30040,
427 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 403 .chcr = CHCR_TX(XMIT_SZ_8BIT),
428 .mid_rid = 0x3d, 404 .mid_rid = 0x3d,
429 }, { 405 }, {
430 .slave_id = SHDMA_SLAVE_SCIF6_RX, 406 .slave_id = SHDMA_SLAVE_SCIF6_RX,
431 .addr = 0xe6c30060, 407 .addr = 0xe6c30060,
432 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 408 .chcr = CHCR_RX(XMIT_SZ_8BIT),
433 .mid_rid = 0x3e, 409 .mid_rid = 0x3e,
434 }, { 410 }, {
435 .slave_id = SHDMA_SLAVE_SDHI0_TX, 411 .slave_id = SHDMA_SLAVE_SDHI0_TX,
436 .addr = 0xe6850030, 412 .addr = 0xe6850030,
437 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 413 .chcr = CHCR_TX(XMIT_SZ_16BIT),
438 .mid_rid = 0xc1, 414 .mid_rid = 0xc1,
439 }, { 415 }, {
440 .slave_id = SHDMA_SLAVE_SDHI0_RX, 416 .slave_id = SHDMA_SLAVE_SDHI0_RX,
441 .addr = 0xe6850030, 417 .addr = 0xe6850030,
442 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 418 .chcr = CHCR_RX(XMIT_SZ_16BIT),
443 .mid_rid = 0xc2, 419 .mid_rid = 0xc2,
444 }, { 420 }, {
445 .slave_id = SHDMA_SLAVE_SDHI1_TX, 421 .slave_id = SHDMA_SLAVE_SDHI1_TX,
446 .addr = 0xe6860030, 422 .addr = 0xe6860030,
447 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 423 .chcr = CHCR_TX(XMIT_SZ_16BIT),
448 .mid_rid = 0xc9, 424 .mid_rid = 0xc9,
449 }, { 425 }, {
450 .slave_id = SHDMA_SLAVE_SDHI1_RX, 426 .slave_id = SHDMA_SLAVE_SDHI1_RX,
451 .addr = 0xe6860030, 427 .addr = 0xe6860030,
452 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 428 .chcr = CHCR_RX(XMIT_SZ_16BIT),
453 .mid_rid = 0xca, 429 .mid_rid = 0xca,
454 }, { 430 }, {
455 .slave_id = SHDMA_SLAVE_SDHI2_TX, 431 .slave_id = SHDMA_SLAVE_SDHI2_TX,
456 .addr = 0xe6870030, 432 .addr = 0xe6870030,
457 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 433 .chcr = CHCR_TX(XMIT_SZ_16BIT),
458 .mid_rid = 0xcd, 434 .mid_rid = 0xcd,
459 }, { 435 }, {
460 .slave_id = SHDMA_SLAVE_SDHI2_RX, 436 .slave_id = SHDMA_SLAVE_SDHI2_RX,
461 .addr = 0xe6870030, 437 .addr = 0xe6870030,
462 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 438 .chcr = CHCR_RX(XMIT_SZ_16BIT),
463 .mid_rid = 0xce, 439 .mid_rid = 0xce,
464 }, { 440 }, {
465 .slave_id = SHDMA_SLAVE_FSIA_TX, 441 .slave_id = SHDMA_SLAVE_FSIA_TX,
466 .addr = 0xfe1f0024, 442 .addr = 0xfe1f0024,
467 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 443 .chcr = CHCR_TX(XMIT_SZ_32BIT),
468 .mid_rid = 0xb1, 444 .mid_rid = 0xb1,
469 }, { 445 }, {
470 .slave_id = SHDMA_SLAVE_FSIA_RX, 446 .slave_id = SHDMA_SLAVE_FSIA_RX,
471 .addr = 0xfe1f0020, 447 .addr = 0xfe1f0020,
472 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 448 .chcr = CHCR_RX(XMIT_SZ_32BIT),
473 .mid_rid = 0xb2, 449 .mid_rid = 0xb2,
474 }, { 450 }, {
475 .slave_id = SHDMA_SLAVE_MMCIF_TX, 451 .slave_id = SHDMA_SLAVE_MMCIF_TX,
476 .addr = 0xe6bd0034, 452 .addr = 0xe6bd0034,
477 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 453 .chcr = CHCR_TX(XMIT_SZ_32BIT),
478 .mid_rid = 0xd1, 454 .mid_rid = 0xd1,
479 }, { 455 }, {
480 .slave_id = SHDMA_SLAVE_MMCIF_RX, 456 .slave_id = SHDMA_SLAVE_MMCIF_RX,
481 .addr = 0xe6bd0034, 457 .addr = 0xe6bd0034,
482 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 458 .chcr = CHCR_RX(XMIT_SZ_32BIT),
483 .mid_rid = 0xd2, 459 .mid_rid = 0xd2,
484 }, 460 },
485}; 461};
@@ -520,19 +496,17 @@ static const struct sh_dmae_channel sh7372_dmae_channels[] = {
520 } 496 }
521}; 497};
522 498
523static const unsigned int ts_shift[] = TS_SHIFT;
524
525static struct sh_dmae_pdata dma_platform_data = { 499static struct sh_dmae_pdata dma_platform_data = {
526 .slave = sh7372_dmae_slaves, 500 .slave = sh7372_dmae_slaves,
527 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves), 501 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
528 .channel = sh7372_dmae_channels, 502 .channel = sh7372_dmae_channels,
529 .channel_num = ARRAY_SIZE(sh7372_dmae_channels), 503 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
530 .ts_low_shift = 3, 504 .ts_low_shift = TS_LOW_SHIFT,
531 .ts_low_mask = 0x18, 505 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
532 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */ 506 .ts_high_shift = TS_HI_SHIFT,
533 .ts_high_mask = 0x00300000, 507 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
534 .ts_shift = ts_shift, 508 .ts_shift = dma_ts_shift,
535 .ts_shift_num = ARRAY_SIZE(ts_shift), 509 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
536 .dmaor_init = DMAOR_DME, 510 .dmaor_init = DMAOR_DME,
537 .chclr_present = 1, 511 .chclr_present = 1,
538}; 512};
@@ -654,17 +628,6 @@ static struct platform_device dma2_device = {
654/* 628/*
655 * USB-DMAC 629 * USB-DMAC
656 */ 630 */
657
658unsigned int usbts_shift[] = {3, 4, 5};
659
660enum {
661 XMIT_SZ_8BYTE = 0,
662 XMIT_SZ_16BYTE = 1,
663 XMIT_SZ_32BYTE = 2,
664};
665
666#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
667
668static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = { 631static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
669 { 632 {
670 .offset = 0, 633 .offset = 0,
@@ -677,10 +640,10 @@ static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
677static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = { 640static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
678 { 641 {
679 .slave_id = SHDMA_SLAVE_USB0_TX, 642 .slave_id = SHDMA_SLAVE_USB0_TX,
680 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), 643 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
681 }, { 644 }, {
682 .slave_id = SHDMA_SLAVE_USB0_RX, 645 .slave_id = SHDMA_SLAVE_USB0_RX,
683 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), 646 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
684 }, 647 },
685}; 648};
686 649
@@ -689,12 +652,12 @@ static struct sh_dmae_pdata usb_dma0_platform_data = {
689 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves), 652 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
690 .channel = sh7372_usb_dmae_channels, 653 .channel = sh7372_usb_dmae_channels,
691 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels), 654 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
692 .ts_low_shift = 6, 655 .ts_low_shift = USBTS_LOW_SHIFT,
693 .ts_low_mask = 0xc0, 656 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
694 .ts_high_shift = 0, 657 .ts_high_shift = USBTS_HI_SHIFT,
695 .ts_high_mask = 0, 658 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
696 .ts_shift = usbts_shift, 659 .ts_shift = dma_usbts_shift,
697 .ts_shift_num = ARRAY_SIZE(usbts_shift), 660 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
698 .dmaor_init = DMAOR_DME, 661 .dmaor_init = DMAOR_DME,
699 .chcr_offset = 0x14, 662 .chcr_offset = 0x14,
700 .chcr_ie_bit = 1 << 5, 663 .chcr_ie_bit = 1 << 5,
@@ -739,10 +702,10 @@ static struct platform_device usb_dma0_device = {
739static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = { 702static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
740 { 703 {
741 .slave_id = SHDMA_SLAVE_USB1_TX, 704 .slave_id = SHDMA_SLAVE_USB1_TX,
742 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), 705 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
743 }, { 706 }, {
744 .slave_id = SHDMA_SLAVE_USB1_RX, 707 .slave_id = SHDMA_SLAVE_USB1_RX,
745 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), 708 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
746 }, 709 },
747}; 710};
748 711
@@ -751,12 +714,12 @@ static struct sh_dmae_pdata usb_dma1_platform_data = {
751 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves), 714 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
752 .channel = sh7372_usb_dmae_channels, 715 .channel = sh7372_usb_dmae_channels,
753 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels), 716 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
754 .ts_low_shift = 6, 717 .ts_low_shift = USBTS_LOW_SHIFT,
755 .ts_low_mask = 0xc0, 718 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
756 .ts_high_shift = 0, 719 .ts_high_shift = USBTS_HI_SHIFT,
757 .ts_high_mask = 0, 720 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
758 .ts_shift = usbts_shift, 721 .ts_shift = dma_usbts_shift,
759 .ts_shift_num = ARRAY_SIZE(usbts_shift), 722 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
760 .dmaor_init = DMAOR_DME, 723 .dmaor_init = DMAOR_DME,
761 .chcr_offset = 0x14, 724 .chcr_offset = 0x14,
762 .chcr_ie_bit = 1 << 5, 725 .chcr_ie_bit = 1 << 5,
@@ -1038,21 +1001,21 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
1038 1001
1039void __init sh7372_add_standard_devices(void) 1002void __init sh7372_add_standard_devices(void)
1040{ 1003{
1041 sh7372_init_pm_domain(&sh7372_a4lc); 1004 rmobile_init_pm_domain(&sh7372_pd_a4lc);
1042 sh7372_init_pm_domain(&sh7372_a4mp); 1005 rmobile_init_pm_domain(&sh7372_pd_a4mp);
1043 sh7372_init_pm_domain(&sh7372_d4); 1006 rmobile_init_pm_domain(&sh7372_pd_d4);
1044 sh7372_init_pm_domain(&sh7372_a4r); 1007 rmobile_init_pm_domain(&sh7372_pd_a4r);
1045 sh7372_init_pm_domain(&sh7372_a3rv); 1008 rmobile_init_pm_domain(&sh7372_pd_a3rv);
1046 sh7372_init_pm_domain(&sh7372_a3ri); 1009 rmobile_init_pm_domain(&sh7372_pd_a3ri);
1047 sh7372_init_pm_domain(&sh7372_a4s); 1010 rmobile_init_pm_domain(&sh7372_pd_a4s);
1048 sh7372_init_pm_domain(&sh7372_a3sp); 1011 rmobile_init_pm_domain(&sh7372_pd_a3sp);
1049 sh7372_init_pm_domain(&sh7372_a3sg); 1012 rmobile_init_pm_domain(&sh7372_pd_a3sg);
1050 1013
1051 sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv); 1014 rmobile_pm_add_subdomain(&sh7372_pd_a4lc, &sh7372_pd_a3rv);
1052 sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc); 1015 rmobile_pm_add_subdomain(&sh7372_pd_a4r, &sh7372_pd_a4lc);
1053 1016
1054 sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg); 1017 rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sg);
1055 sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp); 1018 rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sp);
1056 1019
1057 platform_add_devices(sh7372_early_devices, 1020 platform_add_devices(sh7372_early_devices,
1058 ARRAY_SIZE(sh7372_early_devices)); 1021 ARRAY_SIZE(sh7372_early_devices));
@@ -1060,30 +1023,30 @@ void __init sh7372_add_standard_devices(void)
1060 platform_add_devices(sh7372_late_devices, 1023 platform_add_devices(sh7372_late_devices,
1061 ARRAY_SIZE(sh7372_late_devices)); 1024 ARRAY_SIZE(sh7372_late_devices));
1062 1025
1063 sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device); 1026 rmobile_add_device_to_domain(&sh7372_pd_a3rv, &vpu_device);
1064 sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device); 1027 rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu0_device);
1065 sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device); 1028 rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu1_device);
1066 sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device); 1029 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif0_device);
1067 sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device); 1030 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif1_device);
1068 sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device); 1031 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif2_device);
1069 sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device); 1032 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif3_device);
1070 sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device); 1033 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif4_device);
1071 sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device); 1034 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif5_device);
1072 sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device); 1035 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif6_device);
1073 sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device); 1036 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &iic1_device);
1074 sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device); 1037 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma0_device);
1075 sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device); 1038 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma1_device);
1076 sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device); 1039 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma2_device);
1077 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device); 1040 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma0_device);
1078 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device); 1041 rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma1_device);
1079 sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device); 1042 rmobile_add_device_to_domain(&sh7372_pd_a4r, &iic0_device);
1080 sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device); 1043 rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu0_device);
1081 sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device); 1044 rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu1_device);
1082 sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device); 1045 rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu2_device);
1083 sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device); 1046 rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu3_device);
1084 sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device); 1047 rmobile_add_device_to_domain(&sh7372_pd_a4r, &jpu_device);
1085 sh7372_add_device_to_domain(&sh7372_a4r, &tmu00_device); 1048 rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu00_device);
1086 sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device); 1049 rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu01_device);
1087} 1050}
1088 1051
1089static void __init sh7372_earlytimer_init(void) 1052static void __init sh7372_earlytimer_init(void)
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index d576a6abbade..855b1506caf8 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -22,6 +22,7 @@
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/of_platform.h>
25#include <linux/uio_driver.h> 26#include <linux/uio_driver.h>
26#include <linux/delay.h> 27#include <linux/delay.h>
27#include <linux/input.h> 28#include <linux/input.h>
@@ -500,3 +501,49 @@ void __init sh7377_add_early_devices(void)
500 /* override timer setup with soc-specific code */ 501 /* override timer setup with soc-specific code */
501 shmobile_timer.init = sh7377_earlytimer_init; 502 shmobile_timer.init = sh7377_earlytimer_init;
502} 503}
504
505#ifdef CONFIG_USE_OF
506
507void __init sh7377_add_early_devices_dt(void)
508{
509 shmobile_setup_delay(600, 1, 3); /* Cortex-A8 @ 600MHz */
510
511 early_platform_add_devices(sh7377_early_devices,
512 ARRAY_SIZE(sh7377_early_devices));
513
514 /* setup early console here as well */
515 shmobile_setup_console();
516}
517
518static const struct of_dev_auxdata sh7377_auxdata_lookup[] __initconst = {
519 { }
520};
521
522void __init sh7377_add_standard_devices_dt(void)
523{
524 /* clocks are setup late during boot in the case of DT */
525 sh7377_clock_init();
526
527 platform_add_devices(sh7377_early_devices,
528 ARRAY_SIZE(sh7377_early_devices));
529
530 of_platform_populate(NULL, of_default_bus_match_table,
531 sh7377_auxdata_lookup, NULL);
532}
533
534static const char *sh7377_boards_compat_dt[] __initdata = {
535 "renesas,sh7377",
536 NULL,
537};
538
539DT_MACHINE_START(SH7377_DT, "Generic SH7377 (Flattened Device Tree)")
540 .map_io = sh7377_map_io,
541 .init_early = sh7377_add_early_devices_dt,
542 .init_irq = sh7377_init_irq,
543 .handle_irq = shmobile_handle_irq_intc,
544 .init_machine = sh7377_add_standard_devices_dt,
545 .timer = &shmobile_timer,
546 .dt_compat = sh7377_boards_compat_dt,
547MACHINE_END
548
549#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 04a0dfe75493..d230af656fc9 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -30,6 +30,7 @@
30#include <linux/sh_dma.h> 30#include <linux/sh_dma.h>
31#include <linux/sh_intc.h> 31#include <linux/sh_intc.h>
32#include <linux/sh_timer.h> 32#include <linux/sh_timer.h>
33#include <mach/dma-register.h>
33#include <mach/hardware.h> 34#include <mach/hardware.h>
34#include <mach/irqs.h> 35#include <mach/irqs.h>
35#include <mach/sh73a0.h> 36#include <mach/sh73a0.h>
@@ -415,32 +416,6 @@ static struct platform_device i2c4_device = {
415 .num_resources = ARRAY_SIZE(i2c4_resources), 416 .num_resources = ARRAY_SIZE(i2c4_resources),
416}; 417};
417 418
418/* Transmit sizes and respective CHCR register values */
419enum {
420 XMIT_SZ_8BIT = 0,
421 XMIT_SZ_16BIT = 1,
422 XMIT_SZ_32BIT = 2,
423 XMIT_SZ_64BIT = 7,
424 XMIT_SZ_128BIT = 3,
425 XMIT_SZ_256BIT = 4,
426 XMIT_SZ_512BIT = 5,
427};
428
429/* log2(size / 8) - used to calculate number of transfers */
430#define TS_SHIFT { \
431 [XMIT_SZ_8BIT] = 0, \
432 [XMIT_SZ_16BIT] = 1, \
433 [XMIT_SZ_32BIT] = 2, \
434 [XMIT_SZ_64BIT] = 3, \
435 [XMIT_SZ_128BIT] = 4, \
436 [XMIT_SZ_256BIT] = 5, \
437 [XMIT_SZ_512BIT] = 6, \
438}
439
440#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
441#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
442#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
443
444static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = { 419static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
445 { 420 {
446 .slave_id = SHDMA_SLAVE_SCIF0_TX, 421 .slave_id = SHDMA_SLAVE_SCIF0_TX,
@@ -604,19 +579,17 @@ static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
604 DMAE_CHANNEL(0x8980), 579 DMAE_CHANNEL(0x8980),
605}; 580};
606 581
607static const unsigned int ts_shift[] = TS_SHIFT;
608
609static struct sh_dmae_pdata sh73a0_dmae_platform_data = { 582static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
610 .slave = sh73a0_dmae_slaves, 583 .slave = sh73a0_dmae_slaves,
611 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves), 584 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
612 .channel = sh73a0_dmae_channels, 585 .channel = sh73a0_dmae_channels,
613 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels), 586 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
614 .ts_low_shift = 3, 587 .ts_low_shift = TS_LOW_SHIFT,
615 .ts_low_mask = 0x18, 588 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
616 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */ 589 .ts_high_shift = TS_HI_SHIFT,
617 .ts_high_mask = 0x00300000, 590 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
618 .ts_shift = ts_shift, 591 .ts_shift = dma_ts_shift,
619 .ts_shift_num = ARRAY_SIZE(ts_shift), 592 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
620 .dmaor_init = DMAOR_DME, 593 .dmaor_init = DMAOR_DME,
621}; 594};
622 595
@@ -651,6 +624,116 @@ static struct platform_device dma0_device = {
651 }, 624 },
652}; 625};
653 626
627/* MPDMAC */
628static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
629 {
630 .slave_id = SHDMA_SLAVE_FSI2A_RX,
631 .addr = 0xec230020,
632 .chcr = CHCR_RX(XMIT_SZ_32BIT),
633 .mid_rid = 0xd6, /* CHECK ME */
634 }, {
635 .slave_id = SHDMA_SLAVE_FSI2A_TX,
636 .addr = 0xec230024,
637 .chcr = CHCR_TX(XMIT_SZ_32BIT),
638 .mid_rid = 0xd5, /* CHECK ME */
639 }, {
640 .slave_id = SHDMA_SLAVE_FSI2C_RX,
641 .addr = 0xec230060,
642 .chcr = CHCR_RX(XMIT_SZ_32BIT),
643 .mid_rid = 0xda, /* CHECK ME */
644 }, {
645 .slave_id = SHDMA_SLAVE_FSI2C_TX,
646 .addr = 0xec230064,
647 .chcr = CHCR_TX(XMIT_SZ_32BIT),
648 .mid_rid = 0xd9, /* CHECK ME */
649 }, {
650 .slave_id = SHDMA_SLAVE_FSI2B_RX,
651 .addr = 0xec240020,
652 .chcr = CHCR_RX(XMIT_SZ_32BIT),
653 .mid_rid = 0x8e, /* CHECK ME */
654 }, {
655 .slave_id = SHDMA_SLAVE_FSI2B_TX,
656 .addr = 0xec240024,
657 .chcr = CHCR_RX(XMIT_SZ_32BIT),
658 .mid_rid = 0x8d, /* CHECK ME */
659 }, {
660 .slave_id = SHDMA_SLAVE_FSI2D_RX,
661 .addr = 0xec240060,
662 .chcr = CHCR_RX(XMIT_SZ_32BIT),
663 .mid_rid = 0x9a, /* CHECK ME */
664 },
665};
666
667#define MPDMA_CHANNEL(a, b, c) \
668{ \
669 .offset = a, \
670 .dmars = b, \
671 .dmars_bit = c, \
672 .chclr_offset = (0x220 - 0x20) + a \
673}
674
675static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
676 MPDMA_CHANNEL(0x00, 0, 0),
677 MPDMA_CHANNEL(0x10, 0, 8),
678 MPDMA_CHANNEL(0x20, 4, 0),
679 MPDMA_CHANNEL(0x30, 4, 8),
680 MPDMA_CHANNEL(0x50, 8, 0),
681 MPDMA_CHANNEL(0x70, 8, 8),
682};
683
684static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
685 .slave = sh73a0_mpdma_slaves,
686 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
687 .channel = sh73a0_mpdma_channels,
688 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
689 .ts_low_shift = TS_LOW_SHIFT,
690 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
691 .ts_high_shift = TS_HI_SHIFT,
692 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
693 .ts_shift = dma_ts_shift,
694 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
695 .dmaor_init = DMAOR_DME,
696 .chclr_present = 1,
697};
698
699/* Resource order important! */
700static struct resource sh73a0_mpdma_resources[] = {
701 {
702 /* Channel registers and DMAOR */
703 .start = 0xec618020,
704 .end = 0xec61828f,
705 .flags = IORESOURCE_MEM,
706 },
707 {
708 /* DMARSx */
709 .start = 0xec619000,
710 .end = 0xec61900b,
711 .flags = IORESOURCE_MEM,
712 },
713 {
714 .name = "error_irq",
715 .start = gic_spi(181),
716 .end = gic_spi(181),
717 .flags = IORESOURCE_IRQ,
718 },
719 {
720 /* IRQ for channels 0-5 */
721 .start = gic_spi(175),
722 .end = gic_spi(180),
723 .flags = IORESOURCE_IRQ,
724 },
725};
726
727static struct platform_device mpdma0_device = {
728 .name = "sh-dma-engine",
729 .id = 1,
730 .resource = sh73a0_mpdma_resources,
731 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
732 .dev = {
733 .platform_data = &sh73a0_mpdma_platform_data,
734 },
735};
736
654static struct platform_device *sh73a0_early_devices[] __initdata = { 737static struct platform_device *sh73a0_early_devices[] __initdata = {
655 &scif0_device, 738 &scif0_device,
656 &scif1_device, 739 &scif1_device,
@@ -673,6 +756,7 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
673 &i2c3_device, 756 &i2c3_device,
674 &i2c4_device, 757 &i2c4_device,
675 &dma0_device, 758 &dma0_device,
759 &mpdma0_device,
676}; 760};
677 761
678#define SRCR2 0xe61580b0 762#define SRCR2 0xe61580b0
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 05:20:49 -0400