diff options
author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-10-22 08:49:45 -0400 |
---|---|---|
committer | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-11-17 02:57:22 -0500 |
commit | 9651b7db59893e796dfdd170485543b9863be9d8 (patch) | |
tree | 68e2d969b2fa2dd447fcb5fad994fc811d0c7980 /arch/arm | |
parent | be6786ac738801d39cfd264ec88c352efd029578 (diff) |
ARM: mx3: fix the last users of IMX_NEEDS_DEPRECATED_SYMBOLS
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-mx3/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/mach-mx3/devices.c | 69 | ||||
-rw-r--r-- | arch/arm/mach-mx3/mm.c | 48 |
3 files changed, 61 insertions, 59 deletions
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 8a182d0a3fcf..7feb6c4f628f 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile | |||
@@ -5,8 +5,6 @@ | |||
5 | # Object file lists. | 5 | # Object file lists. |
6 | 6 | ||
7 | obj-y := mm.o devices.o cpu.o | 7 | obj-y := mm.o devices.o cpu.o |
8 | CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS | ||
9 | CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS | ||
10 | obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o | 8 | obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o |
11 | obj-$(CONFIG_ARCH_MX35) += clock-imx35.o | 9 | obj-$(CONFIG_ARCH_MX35) += clock-imx35.o |
12 | obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o | 10 | obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o |
@@ -15,7 +13,6 @@ obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o | |||
15 | obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o | 13 | obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o |
16 | obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o | 14 | obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o |
17 | obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o | 15 | obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o |
18 | CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS | ||
19 | obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ | 16 | obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ |
20 | mx31moboard-marxbot.o mx31moboard-smartbot.o | 17 | mx31moboard-marxbot.o mx31moboard-smartbot.o |
21 | obj-$(CONFIG_MACH_QONG) += mach-qong.o | 18 | obj-$(CONFIG_MACH_QONG) += mach-qong.o |
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index d4da9496089a..74f74f4fcff0 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c | |||
@@ -33,18 +33,18 @@ | |||
33 | static struct mxc_gpio_port imx_gpio_ports[] = { | 33 | static struct mxc_gpio_port imx_gpio_ports[] = { |
34 | { | 34 | { |
35 | .chip.label = "gpio-0", | 35 | .chip.label = "gpio-0", |
36 | .base = IO_ADDRESS(GPIO1_BASE_ADDR), | 36 | .base = MX31_IO_ADDRESS(MX31_GPIO1_BASE_ADDR), |
37 | .irq = MXC_INT_GPIO1, | 37 | .irq = MX3x_INT_GPIO1, |
38 | .virtual_irq_start = MXC_GPIO_IRQ_START, | 38 | .virtual_irq_start = MXC_GPIO_IRQ_START, |
39 | }, { | 39 | }, { |
40 | .chip.label = "gpio-1", | 40 | .chip.label = "gpio-1", |
41 | .base = IO_ADDRESS(GPIO2_BASE_ADDR), | 41 | .base = MX31_IO_ADDRESS(MX31_GPIO2_BASE_ADDR), |
42 | .irq = MXC_INT_GPIO2, | 42 | .irq = MX3x_INT_GPIO2, |
43 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, | 43 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, |
44 | }, { | 44 | }, { |
45 | .chip.label = "gpio-2", | 45 | .chip.label = "gpio-2", |
46 | .base = IO_ADDRESS(GPIO3_BASE_ADDR), | 46 | .base = MX31_IO_ADDRESS(MX31_GPIO3_BASE_ADDR), |
47 | .irq = MXC_INT_GPIO3, | 47 | .irq = MX3x_INT_GPIO3, |
48 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, | 48 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, |
49 | } | 49 | } |
50 | }; | 50 | }; |
@@ -56,8 +56,8 @@ int __init imx3x_register_gpios(void) | |||
56 | 56 | ||
57 | static struct resource mxc_w1_master_resources[] = { | 57 | static struct resource mxc_w1_master_resources[] = { |
58 | { | 58 | { |
59 | .start = OWIRE_BASE_ADDR, | 59 | .start = MX3x_OWIRE_BASE_ADDR, |
60 | .end = OWIRE_BASE_ADDR + SZ_4K - 1, | 60 | .end = MX3x_OWIRE_BASE_ADDR + SZ_4K - 1, |
61 | .flags = IORESOURCE_MEM, | 61 | .flags = IORESOURCE_MEM, |
62 | }, | 62 | }, |
63 | }; | 63 | }; |
@@ -110,8 +110,8 @@ struct platform_device mxcsdhc_device1 = { | |||
110 | 110 | ||
111 | static struct resource rnga_resources[] = { | 111 | static struct resource rnga_resources[] = { |
112 | { | 112 | { |
113 | .start = RNGA_BASE_ADDR, | 113 | .start = MX3x_RNGA_BASE_ADDR, |
114 | .end = RNGA_BASE_ADDR + 0x28, | 114 | .end = MX3x_RNGA_BASE_ADDR + 0x28, |
115 | .flags = IORESOURCE_MEM, | 115 | .flags = IORESOURCE_MEM, |
116 | }, | 116 | }, |
117 | }; | 117 | }; |
@@ -129,20 +129,20 @@ struct platform_device mxc_rnga_device = { | |||
129 | /* The resource order is important! */ | 129 | /* The resource order is important! */ |
130 | static struct resource mx3_ipu_rsrc[] = { | 130 | static struct resource mx3_ipu_rsrc[] = { |
131 | { | 131 | { |
132 | .start = IPU_CTRL_BASE_ADDR, | 132 | .start = MX3x_IPU_CTRL_BASE_ADDR, |
133 | .end = IPU_CTRL_BASE_ADDR + 0x5F, | 133 | .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F, |
134 | .flags = IORESOURCE_MEM, | 134 | .flags = IORESOURCE_MEM, |
135 | }, { | 135 | }, { |
136 | .start = IPU_CTRL_BASE_ADDR + 0x88, | 136 | .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88, |
137 | .end = IPU_CTRL_BASE_ADDR + 0xB3, | 137 | .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3, |
138 | .flags = IORESOURCE_MEM, | 138 | .flags = IORESOURCE_MEM, |
139 | }, { | 139 | }, { |
140 | .start = MXC_INT_IPU_SYN, | 140 | .start = MX3x_INT_IPU_SYN, |
141 | .end = MXC_INT_IPU_SYN, | 141 | .end = MX3x_INT_IPU_SYN, |
142 | .flags = IORESOURCE_IRQ, | 142 | .flags = IORESOURCE_IRQ, |
143 | }, { | 143 | }, { |
144 | .start = MXC_INT_IPU_ERR, | 144 | .start = MX3x_INT_IPU_ERR, |
145 | .end = MXC_INT_IPU_ERR, | 145 | .end = MX3x_INT_IPU_ERR, |
146 | .flags = IORESOURCE_IRQ, | 146 | .flags = IORESOURCE_IRQ, |
147 | }, | 147 | }, |
148 | }; | 148 | }; |
@@ -156,8 +156,8 @@ struct platform_device mx3_ipu = { | |||
156 | 156 | ||
157 | static struct resource fb_resources[] = { | 157 | static struct resource fb_resources[] = { |
158 | { | 158 | { |
159 | .start = IPU_CTRL_BASE_ADDR + 0xB4, | 159 | .start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4, |
160 | .end = IPU_CTRL_BASE_ADDR + 0x1BF, | 160 | .end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF, |
161 | .flags = IORESOURCE_MEM, | 161 | .flags = IORESOURCE_MEM, |
162 | }, | 162 | }, |
163 | }; | 163 | }; |
@@ -174,8 +174,8 @@ struct platform_device mx3_fb = { | |||
174 | 174 | ||
175 | static struct resource camera_resources[] = { | 175 | static struct resource camera_resources[] = { |
176 | { | 176 | { |
177 | .start = IPU_CTRL_BASE_ADDR + 0x60, | 177 | .start = MX3x_IPU_CTRL_BASE_ADDR + 0x60, |
178 | .end = IPU_CTRL_BASE_ADDR + 0x87, | 178 | .end = MX3x_IPU_CTRL_BASE_ADDR + 0x87, |
179 | .flags = IORESOURCE_MEM, | 179 | .flags = IORESOURCE_MEM, |
180 | }, | 180 | }, |
181 | }; | 181 | }; |
@@ -196,8 +196,8 @@ static struct resource otg_resources[] = { | |||
196 | .end = MX31_OTG_BASE_ADDR + 0x1ff, | 196 | .end = MX31_OTG_BASE_ADDR + 0x1ff, |
197 | .flags = IORESOURCE_MEM, | 197 | .flags = IORESOURCE_MEM, |
198 | }, { | 198 | }, { |
199 | .start = MXC_INT_USB3, | 199 | .start = MX31_INT_USB3, |
200 | .end = MXC_INT_USB3, | 200 | .end = MX31_INT_USB3, |
201 | .flags = IORESOURCE_IRQ, | 201 | .flags = IORESOURCE_IRQ, |
202 | }, | 202 | }, |
203 | }; | 203 | }; |
@@ -238,8 +238,8 @@ static struct resource mxc_usbh1_resources[] = { | |||
238 | .end = MX31_OTG_BASE_ADDR + 0x3ff, | 238 | .end = MX31_OTG_BASE_ADDR + 0x3ff, |
239 | .flags = IORESOURCE_MEM, | 239 | .flags = IORESOURCE_MEM, |
240 | }, { | 240 | }, { |
241 | .start = MXC_INT_USB1, | 241 | .start = MX31_INT_USB1, |
242 | .end = MXC_INT_USB1, | 242 | .end = MX31_INT_USB1, |
243 | .flags = IORESOURCE_IRQ, | 243 | .flags = IORESOURCE_IRQ, |
244 | }, | 244 | }, |
245 | }; | 245 | }; |
@@ -255,6 +255,7 @@ struct platform_device mxc_usbh1 = { | |||
255 | .num_resources = ARRAY_SIZE(mxc_usbh1_resources), | 255 | .num_resources = ARRAY_SIZE(mxc_usbh1_resources), |
256 | }; | 256 | }; |
257 | 257 | ||
258 | #ifdef CONFIG_ARCH_MX31 | ||
258 | /* USB host 2 */ | 259 | /* USB host 2 */ |
259 | static u64 usbh2_dmamask = ~(u32)0; | 260 | static u64 usbh2_dmamask = ~(u32)0; |
260 | 261 | ||
@@ -264,8 +265,8 @@ static struct resource mxc_usbh2_resources[] = { | |||
264 | .end = MX31_OTG_BASE_ADDR + 0x5ff, | 265 | .end = MX31_OTG_BASE_ADDR + 0x5ff, |
265 | .flags = IORESOURCE_MEM, | 266 | .flags = IORESOURCE_MEM, |
266 | }, { | 267 | }, { |
267 | .start = MXC_INT_USB2, | 268 | .start = MX31_INT_USB2, |
268 | .end = MXC_INT_USB2, | 269 | .end = MX31_INT_USB2, |
269 | .flags = IORESOURCE_IRQ, | 270 | .flags = IORESOURCE_IRQ, |
270 | }, | 271 | }, |
271 | }; | 272 | }; |
@@ -280,6 +281,7 @@ struct platform_device mxc_usbh2 = { | |||
280 | .resource = mxc_usbh2_resources, | 281 | .resource = mxc_usbh2_resources, |
281 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), | 282 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), |
282 | }; | 283 | }; |
284 | #endif | ||
283 | 285 | ||
284 | static struct resource imx_wdt_resources[] = { | 286 | static struct resource imx_wdt_resources[] = { |
285 | { | 287 | { |
@@ -343,14 +345,17 @@ static int __init mx3_devices_init(void) | |||
343 | #endif | 345 | #endif |
344 | #if defined(CONFIG_ARCH_MX35) | 346 | #if defined(CONFIG_ARCH_MX35) |
345 | if (cpu_is_mx35()) { | 347 | if (cpu_is_mx35()) { |
348 | imx_gpio_ports[0].base = MX35_IO_ADDRESS(MX35_GPIO1_BASE_ADDR), | ||
349 | imx_gpio_ports[1].base = MX35_IO_ADDRESS(MX35_GPIO2_BASE_ADDR), | ||
350 | imx_gpio_ports[2].base = MX35_IO_ADDRESS(MX35_GPIO3_BASE_ADDR), | ||
346 | otg_resources[0].start = MX35_OTG_BASE_ADDR; | 351 | otg_resources[0].start = MX35_OTG_BASE_ADDR; |
347 | otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; | 352 | otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; |
348 | otg_resources[1].start = MXC_INT_USBOTG; | 353 | otg_resources[1].start = MX35_INT_USBOTG; |
349 | otg_resources[1].end = MXC_INT_USBOTG; | 354 | otg_resources[1].end = MX35_INT_USBOTG; |
350 | mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400; | 355 | mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400; |
351 | mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; | 356 | mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; |
352 | mxc_usbh1_resources[1].start = MXC_INT_USBHS; | 357 | mxc_usbh1_resources[1].start = MX35_INT_USBHS; |
353 | mxc_usbh1_resources[1].end = MXC_INT_USBHS; | 358 | mxc_usbh1_resources[1].end = MX35_INT_USBHS; |
354 | imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; | 359 | imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; |
355 | imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; | 360 | imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; |
356 | } | 361 | } |
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c index b4ffc531a82c..809ee40b9f0e 100644 --- a/arch/arm/mach-mx3/mm.c +++ b/arch/arm/mach-mx3/mm.c | |||
@@ -42,29 +42,29 @@ | |||
42 | */ | 42 | */ |
43 | static struct map_desc mxc_io_desc[] __initdata = { | 43 | static struct map_desc mxc_io_desc[] __initdata = { |
44 | { | 44 | { |
45 | .virtual = X_MEMC_BASE_ADDR_VIRT, | 45 | .virtual = MX3x_X_MEMC_BASE_ADDR_VIRT, |
46 | .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), | 46 | .pfn = __phys_to_pfn(MX3x_X_MEMC_BASE_ADDR), |
47 | .length = X_MEMC_SIZE, | 47 | .length = MX3x_X_MEMC_SIZE, |
48 | .type = MT_DEVICE | 48 | .type = MT_DEVICE |
49 | }, { | 49 | }, { |
50 | .virtual = AVIC_BASE_ADDR_VIRT, | 50 | .virtual = MX3x_AVIC_BASE_ADDR_VIRT, |
51 | .pfn = __phys_to_pfn(AVIC_BASE_ADDR), | 51 | .pfn = __phys_to_pfn(MX3x_AVIC_BASE_ADDR), |
52 | .length = AVIC_SIZE, | 52 | .length = MX3x_AVIC_SIZE, |
53 | .type = MT_DEVICE_NONSHARED | 53 | .type = MT_DEVICE_NONSHARED |
54 | }, { | 54 | }, { |
55 | .virtual = AIPS1_BASE_ADDR_VIRT, | 55 | .virtual = MX3x_AIPS1_BASE_ADDR_VIRT, |
56 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | 56 | .pfn = __phys_to_pfn(MX3x_AIPS1_BASE_ADDR), |
57 | .length = AIPS1_SIZE, | 57 | .length = MX3x_AIPS1_SIZE, |
58 | .type = MT_DEVICE_NONSHARED | 58 | .type = MT_DEVICE_NONSHARED |
59 | }, { | 59 | }, { |
60 | .virtual = AIPS2_BASE_ADDR_VIRT, | 60 | .virtual = MX3x_AIPS2_BASE_ADDR_VIRT, |
61 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | 61 | .pfn = __phys_to_pfn(MX3x_AIPS2_BASE_ADDR), |
62 | .length = AIPS2_SIZE, | 62 | .length = MX3x_AIPS2_SIZE, |
63 | .type = MT_DEVICE_NONSHARED | 63 | .type = MT_DEVICE_NONSHARED |
64 | }, { | 64 | }, { |
65 | .virtual = SPBA0_BASE_ADDR_VIRT, | 65 | .virtual = MX3x_SPBA0_BASE_ADDR_VIRT, |
66 | .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), | 66 | .pfn = __phys_to_pfn(MX3x_SPBA0_BASE_ADDR), |
67 | .length = SPBA0_SIZE, | 67 | .length = MX3x_SPBA0_SIZE, |
68 | .type = MT_DEVICE_NONSHARED | 68 | .type = MT_DEVICE_NONSHARED |
69 | }, | 69 | }, |
70 | }; | 70 | }; |
@@ -77,7 +77,7 @@ static struct map_desc mxc_io_desc[] __initdata = { | |||
77 | void __init mx31_map_io(void) | 77 | void __init mx31_map_io(void) |
78 | { | 78 | { |
79 | mxc_set_cpu_type(MXC_CPU_MX31); | 79 | mxc_set_cpu_type(MXC_CPU_MX31); |
80 | mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); | 80 | mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); |
81 | 81 | ||
82 | iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); | 82 | iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); |
83 | } | 83 | } |
@@ -86,8 +86,8 @@ void __init mx31_map_io(void) | |||
86 | void __init mx35_map_io(void) | 86 | void __init mx35_map_io(void) |
87 | { | 87 | { |
88 | mxc_set_cpu_type(MXC_CPU_MX35); | 88 | mxc_set_cpu_type(MXC_CPU_MX35); |
89 | mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR)); | 89 | mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); |
90 | mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); | 90 | mxc_arch_reset_init(MX35_IO_ADDRESS(MX3x_WDOG_BASE_ADDR)); |
91 | 91 | ||
92 | iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); | 92 | iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); |
93 | } | 93 | } |
@@ -97,7 +97,7 @@ int imx3x_register_gpios(void); | |||
97 | 97 | ||
98 | void __init mx31_init_irq(void) | 98 | void __init mx31_init_irq(void) |
99 | { | 99 | { |
100 | mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); | 100 | mxc_init_irq(MX31_IO_ADDRESS(MX3x_AVIC_BASE_ADDR)); |
101 | imx3x_register_gpios(); | 101 | imx3x_register_gpios(); |
102 | } | 102 | } |
103 | 103 | ||
@@ -129,7 +129,7 @@ static int mxc_init_l2x0(void) | |||
129 | pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); | 129 | pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); |
130 | } | 130 | } |
131 | 131 | ||
132 | l2x0_base = ioremap(L2CC_BASE_ADDR, 4096); | 132 | l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); |
133 | if (IS_ERR(l2x0_base)) { | 133 | if (IS_ERR(l2x0_base)) { |
134 | printk(KERN_ERR "remapping L2 cache area failed with %ld\n", | 134 | printk(KERN_ERR "remapping L2 cache area failed with %ld\n", |
135 | PTR_ERR(l2x0_base)); | 135 | PTR_ERR(l2x0_base)); |