diff options
author | Philipp Zabel <p.zabel@pengutronix.de> | 2013-03-27 05:51:33 -0400 |
---|---|---|
committer | Shawn Guo <shawn.guo@linaro.org> | 2013-04-12 07:01:44 -0400 |
commit | 8ecb167f4978d86fa39d6a9c533a4c1ef3169c81 (patch) | |
tree | 94d552762a11f8c32eb64de460aa2f18a34449bf /arch/arm | |
parent | fcc4f9fc5b23e6bb80f2c7833da323a485cad1b6 (diff) |
ARM i.MX53: Add GPU clocks to clock tree
This patch adds the missing GPU2D and GPU3D mux and gate clocks,
and the graphics arbiter gate clock.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-imx/clk-imx51-imx53.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 0f39f8c93b94..fdd86571aa6a 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c | |||
@@ -47,6 +47,8 @@ static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", }; | |||
47 | static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", }; | 47 | static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", }; |
48 | static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", }; | 48 | static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", }; |
49 | static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; | 49 | static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; |
50 | static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" }; | ||
51 | static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" }; | ||
50 | static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; | 52 | static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; |
51 | static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", }; | 53 | static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", }; |
52 | 54 | ||
@@ -83,7 +85,7 @@ enum imx5_clks { | |||
83 | ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, | 85 | ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, |
84 | epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate, | 86 | epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate, |
85 | can_sel, can1_serial_gate, can1_ipg_gate, | 87 | can_sel, can1_serial_gate, can1_ipg_gate, |
86 | owire_gate, | 88 | owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate, |
87 | clk_max | 89 | clk_max |
88 | }; | 90 | }; |
89 | 91 | ||
@@ -200,6 +202,11 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, | |||
200 | clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20); | 202 | clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20); |
201 | clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); | 203 | clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); |
202 | clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12); | 204 | clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12); |
205 | clk[gpu3d_s] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel)); | ||
206 | clk[gpu2d_s] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel)); | ||
207 | clk[gpu3d_gate] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2); | ||
208 | clk[garb_gate] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4); | ||
209 | clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14); | ||
203 | clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel)); | 210 | clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel)); |
204 | clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6); | 211 | clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6); |
205 | clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8); | 212 | clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8); |