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authorPadmavathi Venna <padma.v@samsung.com>2011-12-22 20:14:31 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-12-22 20:49:53 -0500
commit875a59374cd10200ac24f03877ccd8f73af590cc (patch)
treea7a933bd6a567fd2daa51439bcb17597aa337814 /arch/arm
parenta153e31abb01484d0088ac28425dc98204848ad4 (diff)
ARM: SAMSUNG: Consolidation of SPI platform devices to plat-samsung
SPI platform device definitions consolidated from respective machine folder to plat-samsung Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-s3c64xx/Makefile1
-rw-r--r--arch/arm/mach-s3c64xx/dev-spi.c173
-rw-r--r--arch/arm/mach-s5p64x0/Makefile1
-rw-r--r--arch/arm/mach-s5p64x0/dev-spi.c218
-rw-r--r--arch/arm/mach-s5pc100/Makefile1
-rw-r--r--arch/arm/mach-s5pc100/dev-spi.c220
-rw-r--r--arch/arm/mach-s5pv210/Makefile1
-rw-r--r--arch/arm/mach-s5pv210/dev-spi.c169
-rw-r--r--arch/arm/plat-samsung/Kconfig16
-rw-r--r--arch/arm/plat-samsung/devs.c118
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h8
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h15
12 files changed, 141 insertions, 800 deletions
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index e32093c58b2f..d1d0f09f3b30 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -59,4 +59,3 @@ obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
59 59
60obj-y += dev-uart.o 60obj-y += dev-uart.o
61obj-y += dev-audio.o 61obj-y += dev-audio.o
62obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
deleted file mode 100644
index 3f437e7a6ba5..000000000000
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ /dev/null
@@ -1,173 +0,0 @@
1/* linux/arch/arm/plat-s3c64xx/dev-spi.c
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/export.h>
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17
18#include <mach/dma.h>
19#include <mach/map.h>
20#include <mach/spi-clocks.h>
21#include <mach/irqs.h>
22
23#include <plat/s3c64xx-spi.h>
24#include <plat/gpio-cfg.h>
25#include <plat/devs.h>
26
27/* SPI Controller platform_devices */
28
29/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
30 * The emulated CS is toggled by board specific mechanism, as it can
31 * be either some immediate GPIO or some signal out of some other
32 * chip in between ... or some yet another way.
33 * We simply do not assume anything about CS.
34 */
35static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
36{
37 unsigned int base;
38
39 switch (pdev->id) {
40 case 0:
41 base = S3C64XX_GPC(0);
42 break;
43
44 case 1:
45 base = S3C64XX_GPC(4);
46 break;
47
48 default:
49 dev_err(&pdev->dev, "Invalid SPI Controller number!");
50 return -EINVAL;
51 }
52
53 s3c_gpio_cfgall_range(base, 3,
54 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
55
56 return 0;
57}
58
59static struct resource s3c64xx_spi0_resource[] = {
60 [0] = {
61 .start = S3C64XX_PA_SPI0,
62 .end = S3C64XX_PA_SPI0 + 0x100 - 1,
63 .flags = IORESOURCE_MEM,
64 },
65 [1] = {
66 .start = DMACH_SPI0_TX,
67 .end = DMACH_SPI0_TX,
68 .flags = IORESOURCE_DMA,
69 },
70 [2] = {
71 .start = DMACH_SPI0_RX,
72 .end = DMACH_SPI0_RX,
73 .flags = IORESOURCE_DMA,
74 },
75 [3] = {
76 .start = IRQ_SPI0,
77 .end = IRQ_SPI0,
78 .flags = IORESOURCE_IRQ,
79 },
80};
81
82static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
83 .cfg_gpio = s3c64xx_spi_cfg_gpio,
84 .fifo_lvl_mask = 0x7f,
85 .rx_lvl_offset = 13,
86 .tx_st_done = 21,
87};
88
89static u64 spi_dmamask = DMA_BIT_MASK(32);
90
91struct platform_device s3c64xx_device_spi0 = {
92 .name = "s3c64xx-spi",
93 .id = 0,
94 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
95 .resource = s3c64xx_spi0_resource,
96 .dev = {
97 .dma_mask = &spi_dmamask,
98 .coherent_dma_mask = DMA_BIT_MASK(32),
99 .platform_data = &s3c64xx_spi0_pdata,
100 },
101};
102EXPORT_SYMBOL(s3c64xx_device_spi0);
103
104static struct resource s3c64xx_spi1_resource[] = {
105 [0] = {
106 .start = S3C64XX_PA_SPI1,
107 .end = S3C64XX_PA_SPI1 + 0x100 - 1,
108 .flags = IORESOURCE_MEM,
109 },
110 [1] = {
111 .start = DMACH_SPI1_TX,
112 .end = DMACH_SPI1_TX,
113 .flags = IORESOURCE_DMA,
114 },
115 [2] = {
116 .start = DMACH_SPI1_RX,
117 .end = DMACH_SPI1_RX,
118 .flags = IORESOURCE_DMA,
119 },
120 [3] = {
121 .start = IRQ_SPI1,
122 .end = IRQ_SPI1,
123 .flags = IORESOURCE_IRQ,
124 },
125};
126
127static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
128 .cfg_gpio = s3c64xx_spi_cfg_gpio,
129 .fifo_lvl_mask = 0x7f,
130 .rx_lvl_offset = 13,
131 .tx_st_done = 21,
132};
133
134struct platform_device s3c64xx_device_spi1 = {
135 .name = "s3c64xx-spi",
136 .id = 1,
137 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
138 .resource = s3c64xx_spi1_resource,
139 .dev = {
140 .dma_mask = &spi_dmamask,
141 .coherent_dma_mask = DMA_BIT_MASK(32),
142 .platform_data = &s3c64xx_spi1_pdata,
143 },
144};
145EXPORT_SYMBOL(s3c64xx_device_spi1);
146
147void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
148{
149 struct s3c64xx_spi_info *pd;
150
151 /* Reject invalid configuration */
152 if (!num_cs || src_clk_nr < 0
153 || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) {
154 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
155 return;
156 }
157
158 switch (cntrlr) {
159 case 0:
160 pd = &s3c64xx_spi0_pdata;
161 break;
162 case 1:
163 pd = &s3c64xx_spi1_pdata;
164 break;
165 default:
166 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
167 __func__, cntrlr);
168 return;
169 }
170
171 pd->num_cs = num_cs;
172 pd->src_clk_nr = src_clk_nr;
173}
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index a1324d8dc4e0..e24d316e544b 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_MACH_SMDK6450) += mach-smdk6450.o
26# device support 26# device support
27 27
28obj-y += dev-audio.o 28obj-y += dev-audio.o
29obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
30 29
31obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o 30obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o
32obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o 31obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
deleted file mode 100644
index 5b5d3c083644..000000000000
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ /dev/null
@@ -1,218 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/dev-spi.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17
18#include <mach/dma.h>
19#include <mach/map.h>
20#include <mach/irqs.h>
21#include <mach/regs-clock.h>
22#include <mach/spi-clocks.h>
23
24#include <plat/cpu.h>
25#include <plat/s3c64xx-spi.h>
26#include <plat/gpio-cfg.h>
27
28/* SPI Controller platform_devices */
29
30/* Since we emulate multi-cs capability, we do not touch the CS.
31 * The emulated CS is toggled by board specific mechanism, as it can
32 * be either some immediate GPIO or some signal out of some other
33 * chip in between ... or some yet another way.
34 * We simply do not assume anything about CS.
35 */
36static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
37{
38 unsigned int base;
39
40 switch (pdev->id) {
41 case 0:
42 base = S5P6440_GPC(0);
43 break;
44
45 case 1:
46 base = S5P6440_GPC(4);
47 break;
48
49 default:
50 dev_err(&pdev->dev, "Invalid SPI Controller number!");
51 return -EINVAL;
52 }
53
54 s3c_gpio_cfgall_range(base, 3,
55 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
56
57 return 0;
58}
59
60static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
61{
62 unsigned int base;
63
64 switch (pdev->id) {
65 case 0:
66 base = S5P6450_GPC(0);
67 break;
68
69 case 1:
70 base = S5P6450_GPC(4);
71 break;
72
73 default:
74 dev_err(&pdev->dev, "Invalid SPI Controller number!");
75 return -EINVAL;
76 }
77
78 s3c_gpio_cfgall_range(base, 3,
79 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
80
81 return 0;
82}
83
84static struct resource s5p64x0_spi0_resource[] = {
85 [0] = {
86 .start = S5P64X0_PA_SPI0,
87 .end = S5P64X0_PA_SPI0 + 0x100 - 1,
88 .flags = IORESOURCE_MEM,
89 },
90 [1] = {
91 .start = DMACH_SPI0_TX,
92 .end = DMACH_SPI0_TX,
93 .flags = IORESOURCE_DMA,
94 },
95 [2] = {
96 .start = DMACH_SPI0_RX,
97 .end = DMACH_SPI0_RX,
98 .flags = IORESOURCE_DMA,
99 },
100 [3] = {
101 .start = IRQ_SPI0,
102 .end = IRQ_SPI0,
103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
108 .cfg_gpio = s5p6440_spi_cfg_gpio,
109 .fifo_lvl_mask = 0x1ff,
110 .rx_lvl_offset = 15,
111 .tx_st_done = 25,
112};
113
114static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
115 .cfg_gpio = s5p6450_spi_cfg_gpio,
116 .fifo_lvl_mask = 0x1ff,
117 .rx_lvl_offset = 15,
118 .tx_st_done = 25,
119};
120
121static u64 spi_dmamask = DMA_BIT_MASK(32);
122
123struct platform_device s5p64x0_device_spi0 = {
124 .name = "s3c64xx-spi",
125 .id = 0,
126 .num_resources = ARRAY_SIZE(s5p64x0_spi0_resource),
127 .resource = s5p64x0_spi0_resource,
128 .dev = {
129 .dma_mask = &spi_dmamask,
130 .coherent_dma_mask = DMA_BIT_MASK(32),
131 },
132};
133
134static struct resource s5p64x0_spi1_resource[] = {
135 [0] = {
136 .start = S5P64X0_PA_SPI1,
137 .end = S5P64X0_PA_SPI1 + 0x100 - 1,
138 .flags = IORESOURCE_MEM,
139 },
140 [1] = {
141 .start = DMACH_SPI1_TX,
142 .end = DMACH_SPI1_TX,
143 .flags = IORESOURCE_DMA,
144 },
145 [2] = {
146 .start = DMACH_SPI1_RX,
147 .end = DMACH_SPI1_RX,
148 .flags = IORESOURCE_DMA,
149 },
150 [3] = {
151 .start = IRQ_SPI1,
152 .end = IRQ_SPI1,
153 .flags = IORESOURCE_IRQ,
154 },
155};
156
157static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
158 .cfg_gpio = s5p6440_spi_cfg_gpio,
159 .fifo_lvl_mask = 0x7f,
160 .rx_lvl_offset = 15,
161 .tx_st_done = 25,
162};
163
164static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
165 .cfg_gpio = s5p6450_spi_cfg_gpio,
166 .fifo_lvl_mask = 0x7f,
167 .rx_lvl_offset = 15,
168 .tx_st_done = 25,
169};
170
171struct platform_device s5p64x0_device_spi1 = {
172 .name = "s3c64xx-spi",
173 .id = 1,
174 .num_resources = ARRAY_SIZE(s5p64x0_spi1_resource),
175 .resource = s5p64x0_spi1_resource,
176 .dev = {
177 .dma_mask = &spi_dmamask,
178 .coherent_dma_mask = DMA_BIT_MASK(32),
179 },
180};
181
182void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
183{
184 struct s3c64xx_spi_info *pd;
185
186 /* Reject invalid configuration */
187 if (!num_cs || src_clk_nr < 0
188 || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
189 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
190 return;
191 }
192
193 switch (cntrlr) {
194 case 0:
195 if (soc_is_s5p6450())
196 pd = &s5p6450_spi0_pdata;
197 else
198 pd = &s5p6440_spi0_pdata;
199
200 s5p64x0_device_spi0.dev.platform_data = pd;
201 break;
202 case 1:
203 if (soc_is_s5p6450())
204 pd = &s5p6450_spi1_pdata;
205 else
206 pd = &s5p6440_spi1_pdata;
207
208 s5p64x0_device_spi1.dev.platform_data = pd;
209 break;
210 default:
211 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
212 __func__, cntrlr);
213 return;
214 }
215
216 pd->num_cs = num_cs;
217 pd->src_clk_nr = src_clk_nr;
218}
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 2320e5495a55..238a836b3f7f 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
25 25
26# device support 26# device support
27obj-y += dev-audio.o 27obj-y += dev-audio.o
28obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
29 28
30# machine support 29# machine support
31 30
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
deleted file mode 100644
index 155f50da2d78..000000000000
--- a/arch/arm/mach-s5pc100/dev-spi.c
+++ /dev/null
@@ -1,220 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/spi-clocks.h>
18#include <mach/irqs.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22#include <plat/irqs.h>
23
24/* SPI Controller platform_devices */
25
26/* Since we emulate multi-cs capability, we do not touch the CS.
27 * The emulated CS is toggled by board specific mechanism, as it can
28 * be either some immediate GPIO or some signal out of some other
29 * chip in between ... or some yet another way.
30 * We simply do not assume anything about CS.
31 */
32static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
33{
34 switch (pdev->id) {
35 case 0:
36 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
37 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
38 break;
39
40 case 1:
41 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
42 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
43 break;
44
45 case 2:
46 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
47 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
48 s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
49 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
50 break;
51
52 default:
53 dev_err(&pdev->dev, "Invalid SPI Controller number!");
54 return -EINVAL;
55 }
56
57 return 0;
58}
59
60static struct resource s5pc100_spi0_resource[] = {
61 [0] = {
62 .start = S5PC100_PA_SPI0,
63 .end = S5PC100_PA_SPI0 + 0x100 - 1,
64 .flags = IORESOURCE_MEM,
65 },
66 [1] = {
67 .start = DMACH_SPI0_TX,
68 .end = DMACH_SPI0_TX,
69 .flags = IORESOURCE_DMA,
70 },
71 [2] = {
72 .start = DMACH_SPI0_RX,
73 .end = DMACH_SPI0_RX,
74 .flags = IORESOURCE_DMA,
75 },
76 [3] = {
77 .start = IRQ_SPI0,
78 .end = IRQ_SPI0,
79 .flags = IORESOURCE_IRQ,
80 },
81};
82
83static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
84 .cfg_gpio = s5pc100_spi_cfg_gpio,
85 .fifo_lvl_mask = 0x7f,
86 .rx_lvl_offset = 13,
87 .high_speed = 1,
88 .tx_st_done = 21,
89};
90
91static u64 spi_dmamask = DMA_BIT_MASK(32);
92
93struct platform_device s5pc100_device_spi0 = {
94 .name = "s3c64xx-spi",
95 .id = 0,
96 .num_resources = ARRAY_SIZE(s5pc100_spi0_resource),
97 .resource = s5pc100_spi0_resource,
98 .dev = {
99 .dma_mask = &spi_dmamask,
100 .coherent_dma_mask = DMA_BIT_MASK(32),
101 .platform_data = &s5pc100_spi0_pdata,
102 },
103};
104
105static struct resource s5pc100_spi1_resource[] = {
106 [0] = {
107 .start = S5PC100_PA_SPI1,
108 .end = S5PC100_PA_SPI1 + 0x100 - 1,
109 .flags = IORESOURCE_MEM,
110 },
111 [1] = {
112 .start = DMACH_SPI1_TX,
113 .end = DMACH_SPI1_TX,
114 .flags = IORESOURCE_DMA,
115 },
116 [2] = {
117 .start = DMACH_SPI1_RX,
118 .end = DMACH_SPI1_RX,
119 .flags = IORESOURCE_DMA,
120 },
121 [3] = {
122 .start = IRQ_SPI1,
123 .end = IRQ_SPI1,
124 .flags = IORESOURCE_IRQ,
125 },
126};
127
128static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
129 .cfg_gpio = s5pc100_spi_cfg_gpio,
130 .fifo_lvl_mask = 0x7f,
131 .rx_lvl_offset = 13,
132 .high_speed = 1,
133 .tx_st_done = 21,
134};
135
136struct platform_device s5pc100_device_spi1 = {
137 .name = "s3c64xx-spi",
138 .id = 1,
139 .num_resources = ARRAY_SIZE(s5pc100_spi1_resource),
140 .resource = s5pc100_spi1_resource,
141 .dev = {
142 .dma_mask = &spi_dmamask,
143 .coherent_dma_mask = DMA_BIT_MASK(32),
144 .platform_data = &s5pc100_spi1_pdata,
145 },
146};
147
148static struct resource s5pc100_spi2_resource[] = {
149 [0] = {
150 .start = S5PC100_PA_SPI2,
151 .end = S5PC100_PA_SPI2 + 0x100 - 1,
152 .flags = IORESOURCE_MEM,
153 },
154 [1] = {
155 .start = DMACH_SPI2_TX,
156 .end = DMACH_SPI2_TX,
157 .flags = IORESOURCE_DMA,
158 },
159 [2] = {
160 .start = DMACH_SPI2_RX,
161 .end = DMACH_SPI2_RX,
162 .flags = IORESOURCE_DMA,
163 },
164 [3] = {
165 .start = IRQ_SPI2,
166 .end = IRQ_SPI2,
167 .flags = IORESOURCE_IRQ,
168 },
169};
170
171static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
172 .cfg_gpio = s5pc100_spi_cfg_gpio,
173 .fifo_lvl_mask = 0x7f,
174 .rx_lvl_offset = 13,
175 .high_speed = 1,
176 .tx_st_done = 21,
177};
178
179struct platform_device s5pc100_device_spi2 = {
180 .name = "s3c64xx-spi",
181 .id = 2,
182 .num_resources = ARRAY_SIZE(s5pc100_spi2_resource),
183 .resource = s5pc100_spi2_resource,
184 .dev = {
185 .dma_mask = &spi_dmamask,
186 .coherent_dma_mask = DMA_BIT_MASK(32),
187 .platform_data = &s5pc100_spi2_pdata,
188 },
189};
190
191void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
192{
193 struct s3c64xx_spi_info *pd;
194
195 /* Reject invalid configuration */
196 if (!num_cs || src_clk_nr < 0
197 || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) {
198 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
199 return;
200 }
201
202 switch (cntrlr) {
203 case 0:
204 pd = &s5pc100_spi0_pdata;
205 break;
206 case 1:
207 pd = &s5pc100_spi1_pdata;
208 break;
209 case 2:
210 pd = &s5pc100_spi2_pdata;
211 break;
212 default:
213 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
214 __func__, cntrlr);
215 return;
216 }
217
218 pd->num_cs = num_cs;
219 pd->src_clk_nr = src_clk_nr;
220}
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 53c346a4cbb1..7eb8677d3ac0 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -27,7 +27,6 @@ obj-$(CONFIG_MACH_TORBRECK) += mach-torbreck.o
27# device support 27# device support
28 28
29obj-y += dev-audio.o 29obj-y += dev-audio.o
30obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
31 30
32obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o 31obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o
33obj-$(CONFIG_S5PV210_SETUP_FIMC) += setup-fimc.o 32obj-$(CONFIG_S5PV210_SETUP_FIMC) += setup-fimc.o
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c
deleted file mode 100644
index 39bef19dbd68..000000000000
--- a/arch/arm/mach-s5pv210/dev-spi.c
+++ /dev/null
@@ -1,169 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/irqs.h>
18#include <mach/spi-clocks.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22
23/* SPI Controller platform_devices */
24
25/* Since we emulate multi-cs capability, we do not touch the CS.
26 * The emulated CS is toggled by board specific mechanism, as it can
27 * be either some immediate GPIO or some signal out of some other
28 * chip in between ... or some yet another way.
29 * We simply do not assume anything about CS.
30 */
31static int s5pv210_spi_cfg_gpio(struct platform_device *pdev)
32{
33 unsigned int base;
34
35 switch (pdev->id) {
36 case 0:
37 base = S5PV210_GPB(0);
38 break;
39
40 case 1:
41 base = S5PV210_GPB(4);
42 break;
43
44 default:
45 dev_err(&pdev->dev, "Invalid SPI Controller number!");
46 return -EINVAL;
47 }
48
49 s3c_gpio_cfgall_range(base, 3,
50 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
51
52 return 0;
53}
54
55static struct resource s5pv210_spi0_resource[] = {
56 [0] = {
57 .start = S5PV210_PA_SPI0,
58 .end = S5PV210_PA_SPI0 + 0x100 - 1,
59 .flags = IORESOURCE_MEM,
60 },
61 [1] = {
62 .start = DMACH_SPI0_TX,
63 .end = DMACH_SPI0_TX,
64 .flags = IORESOURCE_DMA,
65 },
66 [2] = {
67 .start = DMACH_SPI0_RX,
68 .end = DMACH_SPI0_RX,
69 .flags = IORESOURCE_DMA,
70 },
71 [3] = {
72 .start = IRQ_SPI0,
73 .end = IRQ_SPI0,
74 .flags = IORESOURCE_IRQ,
75 },
76};
77
78static struct s3c64xx_spi_info s5pv210_spi0_pdata = {
79 .cfg_gpio = s5pv210_spi_cfg_gpio,
80 .fifo_lvl_mask = 0x1ff,
81 .rx_lvl_offset = 15,
82 .high_speed = 1,
83 .tx_st_done = 25,
84};
85
86static u64 spi_dmamask = DMA_BIT_MASK(32);
87
88struct platform_device s5pv210_device_spi0 = {
89 .name = "s3c64xx-spi",
90 .id = 0,
91 .num_resources = ARRAY_SIZE(s5pv210_spi0_resource),
92 .resource = s5pv210_spi0_resource,
93 .dev = {
94 .dma_mask = &spi_dmamask,
95 .coherent_dma_mask = DMA_BIT_MASK(32),
96 .platform_data = &s5pv210_spi0_pdata,
97 },
98};
99
100static struct resource s5pv210_spi1_resource[] = {
101 [0] = {
102 .start = S5PV210_PA_SPI1,
103 .end = S5PV210_PA_SPI1 + 0x100 - 1,
104 .flags = IORESOURCE_MEM,
105 },
106 [1] = {
107 .start = DMACH_SPI1_TX,
108 .end = DMACH_SPI1_TX,
109 .flags = IORESOURCE_DMA,
110 },
111 [2] = {
112 .start = DMACH_SPI1_RX,
113 .end = DMACH_SPI1_RX,
114 .flags = IORESOURCE_DMA,
115 },
116 [3] = {
117 .start = IRQ_SPI1,
118 .end = IRQ_SPI1,
119 .flags = IORESOURCE_IRQ,
120 },
121};
122
123static struct s3c64xx_spi_info s5pv210_spi1_pdata = {
124 .cfg_gpio = s5pv210_spi_cfg_gpio,
125 .fifo_lvl_mask = 0x7f,
126 .rx_lvl_offset = 15,
127 .high_speed = 1,
128 .tx_st_done = 25,
129};
130
131struct platform_device s5pv210_device_spi1 = {
132 .name = "s3c64xx-spi",
133 .id = 1,
134 .num_resources = ARRAY_SIZE(s5pv210_spi1_resource),
135 .resource = s5pv210_spi1_resource,
136 .dev = {
137 .dma_mask = &spi_dmamask,
138 .coherent_dma_mask = DMA_BIT_MASK(32),
139 .platform_data = &s5pv210_spi1_pdata,
140 },
141};
142
143void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
144{
145 struct s3c64xx_spi_info *pd;
146
147 /* Reject invalid configuration */
148 if (!num_cs || src_clk_nr < 0
149 || src_clk_nr > S5PV210_SPI_SRCCLK_SCLK) {
150 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
151 return;
152 }
153
154 switch (cntrlr) {
155 case 0:
156 pd = &s5pv210_spi0_pdata;
157 break;
158 case 1:
159 pd = &s5pv210_spi1_pdata;
160 break;
161 default:
162 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
163 __func__, cntrlr);
164 return;
165 }
166
167 pd->num_cs = num_cs;
168 pd->src_clk_nr = src_clk_nr;
169}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 313eb26cfa62..160eea15a6ef 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -226,11 +226,23 @@ config SAMSUNG_DEV_IDE
226 help 226 help
227 Compile in platform device definitions for IDE 227 Compile in platform device definitions for IDE
228 228
229config S3C64XX_DEV_SPI 229config S3C64XX_DEV_SPI0
230 bool 230 bool
231 help 231 help
232 Compile in platform device definitions for S3C64XX's type 232 Compile in platform device definitions for S3C64XX's type
233 SPI controllers. 233 SPI controller 0
234
235config S3C64XX_DEV_SPI1
236 bool
237 help
238 Compile in platform device definitions for S3C64XX's type
239 SPI controller 1
240
241config S3C64XX_DEV_SPI2
242 bool
243 help
244 Compile in platform device definitions for S3C64XX's type
245 SPI controller 2
234 246
235config SAMSUNG_DEV_TS 247config SAMSUNG_DEV_TS
236 bool 248 bool
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 4ca8b571f971..8b27e61d0345 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -61,6 +61,7 @@
61#include <plat/regs-iic.h> 61#include <plat/regs-iic.h>
62#include <plat/regs-serial.h> 62#include <plat/regs-serial.h>
63#include <plat/regs-spi.h> 63#include <plat/regs-spi.h>
64#include <plat/s3c64xx-spi.h>
64 65
65static u64 samsung_device_dma_mask = DMA_BIT_MASK(32); 66static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
66 67
@@ -1461,3 +1462,120 @@ struct platform_device s3c_device_wdt = {
1461 .resource = s3c_wdt_resource, 1462 .resource = s3c_wdt_resource,
1462}; 1463};
1463#endif /* CONFIG_S3C_DEV_WDT */ 1464#endif /* CONFIG_S3C_DEV_WDT */
1465
1466#ifdef CONFIG_S3C64XX_DEV_SPI0
1467static struct resource s3c64xx_spi0_resource[] = {
1468 [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
1469 [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
1470 [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
1471 [3] = DEFINE_RES_IRQ(IRQ_SPI0),
1472};
1473
1474struct platform_device s3c64xx_device_spi0 = {
1475 .name = "s3c64xx-spi",
1476 .id = 0,
1477 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
1478 .resource = s3c64xx_spi0_resource,
1479 .dev = {
1480 .dma_mask = &samsung_device_dma_mask,
1481 .coherent_dma_mask = DMA_BIT_MASK(32),
1482 },
1483};
1484
1485void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
1486 int src_clk_nr, int num_cs)
1487{
1488 if (!pd) {
1489 pr_err("%s:Need to pass platform data\n", __func__);
1490 return;
1491 }
1492
1493 /* Reject invalid configuration */
1494 if (!num_cs || src_clk_nr < 0) {
1495 pr_err("%s: Invalid SPI configuration\n", __func__);
1496 return;
1497 }
1498
1499 pd->num_cs = num_cs;
1500 pd->src_clk_nr = src_clk_nr;
1501 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0);
1502}
1503#endif /* CONFIG_S3C64XX_DEV_SPI0 */
1504
1505#ifdef CONFIG_S3C64XX_DEV_SPI1
1506static struct resource s3c64xx_spi1_resource[] = {
1507 [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
1508 [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
1509 [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
1510 [3] = DEFINE_RES_IRQ(IRQ_SPI1),
1511};
1512
1513struct platform_device s3c64xx_device_spi1 = {
1514 .name = "s3c64xx-spi",
1515 .id = 1,
1516 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
1517 .resource = s3c64xx_spi1_resource,
1518 .dev = {
1519 .dma_mask = &samsung_device_dma_mask,
1520 .coherent_dma_mask = DMA_BIT_MASK(32),
1521 },
1522};
1523
1524void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
1525 int src_clk_nr, int num_cs)
1526{
1527 if (!pd) {
1528 pr_err("%s:Need to pass platform data\n", __func__);
1529 return;
1530 }
1531
1532 /* Reject invalid configuration */
1533 if (!num_cs || src_clk_nr < 0) {
1534 pr_err("%s: Invalid SPI configuration\n", __func__);
1535 return;
1536 }
1537
1538 pd->num_cs = num_cs;
1539 pd->src_clk_nr = src_clk_nr;
1540 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1);
1541}
1542#endif /* CONFIG_S3C64XX_DEV_SPI1 */
1543
1544#ifdef CONFIG_S3C64XX_DEV_SPI2
1545static struct resource s3c64xx_spi2_resource[] = {
1546 [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
1547 [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
1548 [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
1549 [3] = DEFINE_RES_IRQ(IRQ_SPI2),
1550};
1551
1552struct platform_device s3c64xx_device_spi2 = {
1553 .name = "s3c64xx-spi",
1554 .id = 2,
1555 .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
1556 .resource = s3c64xx_spi2_resource,
1557 .dev = {
1558 .dma_mask = &samsung_device_dma_mask,
1559 .coherent_dma_mask = DMA_BIT_MASK(32),
1560 },
1561};
1562
1563void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
1564 int src_clk_nr, int num_cs)
1565{
1566 if (!pd) {
1567 pr_err("%s:Need to pass platform data\n", __func__);
1568 return;
1569 }
1570
1571 /* Reject invalid configuration */
1572 if (!num_cs || src_clk_nr < 0) {
1573 pr_err("%s: Invalid SPI configuration\n", __func__);
1574 return;
1575 }
1576
1577 pd->num_cs = num_cs;
1578 pd->src_clk_nr = src_clk_nr;
1579 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2);
1580}
1581#endif /* CONFIG_S3C64XX_DEV_SPI2 */
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index ab633c9c2aec..83b1e31696d9 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -39,6 +39,7 @@ extern struct platform_device s3c64xx_device_pcm0;
39extern struct platform_device s3c64xx_device_pcm1; 39extern struct platform_device s3c64xx_device_pcm1;
40extern struct platform_device s3c64xx_device_spi0; 40extern struct platform_device s3c64xx_device_spi0;
41extern struct platform_device s3c64xx_device_spi1; 41extern struct platform_device s3c64xx_device_spi1;
42extern struct platform_device s3c64xx_device_spi2;
42 43
43extern struct platform_device s3c_device_adc; 44extern struct platform_device s3c_device_adc;
44extern struct platform_device s3c_device_cfcon; 45extern struct platform_device s3c_device_cfcon;
@@ -98,8 +99,6 @@ extern struct platform_device s5p6450_device_iis1;
98extern struct platform_device s5p6450_device_iis2; 99extern struct platform_device s5p6450_device_iis2;
99extern struct platform_device s5p6450_device_pcm0; 100extern struct platform_device s5p6450_device_pcm0;
100 101
101extern struct platform_device s5p64x0_device_spi0;
102extern struct platform_device s5p64x0_device_spi1;
103 102
104extern struct platform_device s5pc100_device_ac97; 103extern struct platform_device s5pc100_device_ac97;
105extern struct platform_device s5pc100_device_iis0; 104extern struct platform_device s5pc100_device_iis0;
@@ -108,9 +107,6 @@ extern struct platform_device s5pc100_device_iis2;
108extern struct platform_device s5pc100_device_pcm0; 107extern struct platform_device s5pc100_device_pcm0;
109extern struct platform_device s5pc100_device_pcm1; 108extern struct platform_device s5pc100_device_pcm1;
110extern struct platform_device s5pc100_device_spdif; 109extern struct platform_device s5pc100_device_spdif;
111extern struct platform_device s5pc100_device_spi0;
112extern struct platform_device s5pc100_device_spi1;
113extern struct platform_device s5pc100_device_spi2;
114 110
115extern struct platform_device s5pv210_device_ac97; 111extern struct platform_device s5pv210_device_ac97;
116extern struct platform_device s5pv210_device_iis0; 112extern struct platform_device s5pv210_device_iis0;
@@ -120,8 +116,6 @@ extern struct platform_device s5pv210_device_pcm0;
120extern struct platform_device s5pv210_device_pcm1; 116extern struct platform_device s5pv210_device_pcm1;
121extern struct platform_device s5pv210_device_pcm2; 117extern struct platform_device s5pv210_device_pcm2;
122extern struct platform_device s5pv210_device_spdif; 118extern struct platform_device s5pv210_device_spdif;
123extern struct platform_device s5pv210_device_spi0;
124extern struct platform_device s5pv210_device_spi1;
125 119
126extern struct platform_device exynos4_device_ac97; 120extern struct platform_device exynos4_device_ac97;
127extern struct platform_device exynos4_device_ahci; 121extern struct platform_device exynos4_device_ahci;
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index c3d82a5f5630..effca5394d19 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -56,18 +56,19 @@ struct s3c64xx_spi_info {
56}; 56};
57 57
58/** 58/**
59 * s3c64xx_spi_set_info - SPI Controller configure callback by the board 59 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
60 * initialization code. 60 * initialization code.
61 * @cntrlr: SPI controller number the configuration is for. 61 * @pd: SPI platform data to set.
62 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. 62 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
63 * @num_cs: Number of elements in the 'cs' array. 63 * @num_cs: Number of elements in the 'cs' array.
64 * 64 *
65 * Call this from machine init code for each SPI Controller that 65 * Call this from machine init code for each SPI Controller that
66 * has some chips attached to it. 66 * has some chips attached to it.
67 */ 67 */
68extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 68extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
69extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 69 int src_clk_nr, int num_cs);
70extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 70extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
71extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 71 int src_clk_nr, int num_cs);
72 72extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
73 int src_clk_nr, int num_cs);
73#endif /* __S3C64XX_PLAT_SPI_H */ 74#endif /* __S3C64XX_PLAT_SPI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 13:10:23 -0400