diff options
| author | Wei Shuai <cpuwolf@gmail.com> | 2008-08-26 17:54:08 -0400 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2008-08-26 17:56:22 -0400 |
| commit | 78af47353065ea776d537f6e8b32c7c15b6ea169 (patch) | |
| tree | a16fdb6b54b9a691e8ca03e68227593e5de4fcbf /arch/arm | |
| parent | df9f17e20e3180572fe26f60ec4e5ba7db0377a7 (diff) | |
[ARM] S3C2443: Fix the S3C2443 clock register definitions
Fix the S3C2443 clock register definitions for selecting the EPLL
reference clock described by S3C2443_CLKSRC_EPLLREF.
Signed-off-by: Wei Shuai <cpuwolf@gmail.com>
[ben-linux@fluff.org: minor description fixes]
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h index 7dd458363a51..6026d091a2fe 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h | |||
| @@ -48,11 +48,11 @@ | |||
| 48 | #define S3C2443_CLKSRC_I2S_EPLLREF3 (3<<14) | 48 | #define S3C2443_CLKSRC_I2S_EPLLREF3 (3<<14) |
| 49 | #define S3C2443_CLKSRC_I2S_MASK (3<<14) | 49 | #define S3C2443_CLKSRC_I2S_MASK (3<<14) |
| 50 | 50 | ||
| 51 | #define S3C2443_CLKSRC_EPLLREF_XTAL (2<<8) | 51 | #define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7) |
| 52 | #define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<8) | 52 | #define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7) |
| 53 | #define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<8) | 53 | #define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7) |
| 54 | #define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<8) | 54 | #define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7) |
| 55 | #define S3C2443_CLKSRC_EPLLREF_MASK (3<<8) | 55 | #define S3C2443_CLKSRC_EPLLREF_MASK (3<<7) |
| 56 | 56 | ||
| 57 | #define S3C2443_CLKSRC_ESYSCLK_EPLL (1<<6) | 57 | #define S3C2443_CLKSRC_ESYSCLK_EPLL (1<<6) |
| 58 | #define S3C2443_CLKSRC_MSYSCLK_MPLL (1<<4) | 58 | #define S3C2443_CLKSRC_MSYSCLK_MPLL (1<<4) |