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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-12-05 18:20:17 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-12-05 18:20:17 -0500
commit742eaa6a6e356a16788ce6530271de89bc4f8fb5 (patch)
tree12fc040daab06ac796c61c1d92bfad9bb054d1c1 /arch/arm
parentba8bb18a03f8c7508565c385576a5431a4ad804a (diff)
parentae72fd588a2b302222769b44775912b83f0785eb (diff)
Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into devel-stable
Conflicts: arch/arm/common/gic.c arch/arm/plat-omap/include/plat/common.h
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig20
-rw-r--r--arch/arm/boot/Makefile2
-rw-r--r--arch/arm/common/gic.c15
-rw-r--r--arch/arm/common/pl330.c12
-rw-r--r--arch/arm/configs/at91cap9_defconfig (renamed from arch/arm/configs/at91cap9adk_defconfig)7
-rw-r--r--arch/arm/configs/at91rm9200_defconfig47
-rw-r--r--arch/arm/configs/at91sam9260_defconfig (renamed from arch/arm/configs/at91sam9260ek_defconfig)16
-rw-r--r--arch/arm/configs/at91sam9g20_defconfig (renamed from arch/arm/configs/at91sam9g20ek_defconfig)23
-rw-r--r--arch/arm/configs/at91sam9g45_defconfig7
-rw-r--r--arch/arm/configs/at91sam9rl_defconfig (renamed from arch/arm/configs/at91sam9rlek_defconfig)5
-rw-r--r--arch/arm/configs/ezx_defconfig2
-rw-r--r--arch/arm/configs/imote2_defconfig2
-rw-r--r--arch/arm/configs/magician_defconfig2
-rw-r--r--arch/arm/configs/omap1_defconfig1
-rw-r--r--arch/arm/configs/u300_defconfig13
-rw-r--r--arch/arm/configs/u8500_defconfig14
-rw-r--r--arch/arm/configs/zeus_defconfig2
-rw-r--r--arch/arm/include/asm/cti.h179
-rw-r--r--arch/arm/include/asm/hardware/cache-l2x0.h2
-rw-r--r--arch/arm/include/asm/mach/arch.h1
-rw-r--r--arch/arm/include/asm/perf_event.h3
-rw-r--r--arch/arm/include/asm/pmu.h25
-rw-r--r--arch/arm/include/asm/topology.h2
-rw-r--r--arch/arm/include/asm/unistd.h2
-rw-r--r--arch/arm/kernel/calls.S2
-rw-r--r--arch/arm/kernel/entry-armv.S2
-rw-r--r--arch/arm/kernel/head.S2
-rw-r--r--arch/arm/kernel/kprobes-arm.c4
-rw-r--r--arch/arm/kernel/kprobes-test-arm.c27
-rw-r--r--arch/arm/kernel/kprobes-test-thumb.c16
-rw-r--r--arch/arm/kernel/kprobes-test.h100
-rw-r--r--arch/arm/kernel/machine_kexec.c35
-rw-r--r--arch/arm/kernel/perf_event.c30
-rw-r--r--arch/arm/kernel/perf_event_v6.c32
-rw-r--r--arch/arm/kernel/perf_event_v7.c401
-rw-r--r--arch/arm/kernel/perf_event_xscale.c16
-rw-r--r--arch/arm/kernel/pmu.c1
-rw-r--r--arch/arm/kernel/process.c3
-rw-r--r--arch/arm/kernel/setup.c6
-rw-r--r--arch/arm/kernel/topology.c2
-rw-r--r--arch/arm/lib/bitops.h26
-rw-r--r--arch/arm/lib/changebit.S4
-rw-r--r--arch/arm/lib/clearbit.S4
-rw-r--r--arch/arm/lib/setbit.S4
-rw-r--r--arch/arm/lib/testchangebit.S4
-rw-r--r--arch/arm/lib/testclearbit.S4
-rw-r--r--arch/arm/lib/testsetbit.S4
-rw-r--r--arch/arm/mach-bcmring/core.c2
-rw-r--r--arch/arm/mach-bcmring/dma.c1
-rw-r--r--arch/arm/mach-exynos/cpuidle.c2
-rw-r--r--arch/arm/mach-highbank/highbank.c4
-rw-r--r--arch/arm/mach-imx/Kconfig13
-rw-r--r--arch/arm/mach-imx/clock-imx6q.c7
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c1
-rw-r--r--arch/arm/mach-imx/mm-imx3.c109
-rw-r--r--arch/arm/mach-imx/src.c7
-rw-r--r--arch/arm/mach-mmp/gplugd.c2
-rw-r--r--arch/arm/mach-mmp/include/mach/gpio-pxa.h2
-rw-r--r--arch/arm/mach-mx5/cpu.c5
-rw-r--r--arch/arm/mach-mx5/mm.c6
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c2
-rw-r--r--arch/arm/mach-omap1/Kconfig8
-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c10
-rw-r--r--arch/arm/mach-omap1/clock.h3
-rw-r--r--arch/arm/mach-omap1/clock_data.c53
-rw-r--r--arch/arm/mach-omap1/devices.c3
-rw-r--r--arch/arm/mach-omap2/Kconfig1
-rw-r--r--arch/arm/mach-omap2/Makefile5
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c1
-rw-r--r--arch/arm/mach-omap2/display.c159
-rw-r--r--arch/arm/mach-omap2/display.h29
-rw-r--r--arch/arm/mach-omap2/io.h0
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c6
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c17
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c17
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c5
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c37
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c24
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.c4
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h4
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.c2
-rw-r--r--arch/arm/mach-omap2/pm.c6
-rw-r--r--arch/arm/mach-omap2/smartreflex.c2
-rw-r--r--arch/arm/mach-omap2/twl-common.c11
-rw-r--r--arch/arm/mach-omap2/twl-common.h3
-rw-r--r--arch/arm/mach-pxa/balloon3.c2
-rw-r--r--arch/arm/mach-pxa/colibri-pxa320.c2
-rw-r--r--arch/arm/mach-pxa/gumstix.c2
-rw-r--r--arch/arm/mach-pxa/include/mach/palm27x.h4
-rw-r--r--arch/arm/mach-pxa/palm27x.c4
-rw-r--r--arch/arm/mach-pxa/palmtc.c2
-rw-r--r--arch/arm/mach-pxa/vpac270.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410-module.c2
-rw-r--r--arch/arm/mach-shmobile/pm-sh7372.c33
-rw-r--r--arch/arm/mach-w90x900/dev.c4
-rw-r--r--arch/arm/mach-w90x900/include/mach/mfp.h3
-rw-r--r--arch/arm/mach-w90x900/include/mach/nuc900_spi.h2
-rw-r--r--arch/arm/mach-w90x900/mfp.c48
-rw-r--r--arch/arm/mm/cache-l2x0.c2
-rw-r--r--arch/arm/mm/dma-mapping.c11
-rw-r--r--arch/arm/mm/mmap.c23
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h7
-rw-r--r--arch/arm/plat-mxc/system.c3
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h2
-rw-r--r--arch/arm/plat-omap/include/plat/common.h3
-rw-r--r--arch/arm/plat-s3c24xx/cpu-freq-debugfs.c2
-rw-r--r--arch/arm/plat-s5p/sysmmu.c1
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg.h2
-rw-r--r--arch/arm/plat-samsung/pd.c2
-rw-r--r--arch/arm/plat-samsung/pwm.c2
-rw-r--r--arch/arm/tools/mach-types1
113 files changed, 1188 insertions, 705 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 44789eff983f..e084b7e981e8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1231,7 +1231,7 @@ config ARM_ERRATA_742231
1231 capabilities of the processor. 1231 capabilities of the processor.
1232 1232
1233config PL310_ERRATA_588369 1233config PL310_ERRATA_588369
1234 bool "Clean & Invalidate maintenance operations do not invalidate clean lines" 1234 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1235 depends on CACHE_L2X0 1235 depends on CACHE_L2X0
1236 help 1236 help
1237 The PL310 L2 cache controller implements three types of Clean & 1237 The PL310 L2 cache controller implements three types of Clean &
@@ -1256,7 +1256,7 @@ config ARM_ERRATA_720789
1256 entries regardless of the ASID. 1256 entries regardless of the ASID.
1257 1257
1258config PL310_ERRATA_727915 1258config PL310_ERRATA_727915
1259 bool "Background Clean & Invalidate by Way operation can cause data corruption" 1259 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1260 depends on CACHE_L2X0 1260 depends on CACHE_L2X0
1261 help 1261 help
1262 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1262 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
@@ -1289,8 +1289,8 @@ config ARM_ERRATA_751472
1289 operation is received by a CPU before the ICIALLUIS has completed, 1289 operation is received by a CPU before the ICIALLUIS has completed,
1290 potentially leading to corrupted entries in the cache or TLB. 1290 potentially leading to corrupted entries in the cache or TLB.
1291 1291
1292config ARM_ERRATA_753970 1292config PL310_ERRATA_753970
1293 bool "ARM errata: cache sync operation may be faulty" 1293 bool "PL310 errata: cache sync operation may be faulty"
1294 depends on CACHE_PL310 1294 depends on CACHE_PL310
1295 help 1295 help
1296 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1296 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
@@ -1352,6 +1352,18 @@ config ARM_ERRATA_764369
1352 relevant cache maintenance functions and sets a specific bit 1352 relevant cache maintenance functions and sets a specific bit
1353 in the diagnostic control register of the SCU. 1353 in the diagnostic control register of the SCU.
1354 1354
1355config PL310_ERRATA_769419
1356 bool "PL310 errata: no automatic Store Buffer drain"
1357 depends on CACHE_L2X0
1358 help
1359 On revisions of the PL310 prior to r3p2, the Store Buffer does
1360 not automatically drain. This can cause normal, non-cacheable
1361 writes to be retained when the memory system is idle, leading
1362 to suboptimal I/O performance for drivers using coherent DMA.
1363 This option adds a write barrier to the cpu_idle loop so that,
1364 on systems with an outer cache, the store buffer is drained
1365 explicitly.
1366
1355endmenu 1367endmenu
1356 1368
1357source "arch/arm/common/Kconfig" 1369source "arch/arm/common/Kconfig"
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 176062ac7f07..5df26a9976a2 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -65,6 +65,8 @@ $(obj)/%.dtb: $(src)/dts/%.dts
65 65
66$(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y)) 66$(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
67 67
68clean-files := *.dtb
69
68quiet_cmd_uimage = UIMAGE $@ 70quiet_cmd_uimage = UIMAGE $@
69 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \ 71 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
70 -C none -a $(LOADADDR) -e $(STARTADDR) \ 72 -C none -a $(LOADADDR) -e $(STARTADDR) \
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index a1feb6b4f9f5..b2dc2dd7f1df 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -612,7 +612,8 @@ static void __init gic_pm_init(struct gic_chip_data *gic)
612 sizeof(u32)); 612 sizeof(u32));
613 BUG_ON(!gic->saved_ppi_conf); 613 BUG_ON(!gic->saved_ppi_conf);
614 614
615 cpu_pm_register_notifier(&gic_notifier_block); 615 if (gic == &gic_data[0])
616 cpu_pm_register_notifier(&gic_notifier_block);
616} 617}
617#else 618#else
618static void __init gic_pm_init(struct gic_chip_data *gic) 619static void __init gic_pm_init(struct gic_chip_data *gic)
@@ -696,12 +697,14 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
696 * For primary GICs, skip over SGIs. 697 * For primary GICs, skip over SGIs.
697 * For secondary GICs, skip over PPIs, too. 698 * For secondary GICs, skip over PPIs, too.
698 */ 699 */
700 domain->hwirq_base = 32;
699 if (gic_nr == 0) { 701 if (gic_nr == 0) {
700 domain->hwirq_base = 16; 702 if ((irq_start & 31) > 0) {
701 if (irq_start > 0) 703 domain->hwirq_base = 16;
702 irq_start = (irq_start & ~31) + 16; 704 if (irq_start != -1)
703 } else 705 irq_start = (irq_start & ~31) + 16;
704 domain->hwirq_base = 32; 706 }
707 }
705 708
706 /* 709 /*
707 * Find out how many interrupts are supported. 710 * Find out how many interrupts are supported.
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c
index 7129cfbdacd6..f407a6b35d3d 100644
--- a/arch/arm/common/pl330.c
+++ b/arch/arm/common/pl330.c
@@ -1211,8 +1211,8 @@ static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1211 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); 1211 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1212 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); 1212 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1213 1213
1214 ccr |= (rqc->dcctl << CC_SRCCCTRL_SHFT); 1214 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1215 ccr |= (rqc->scctl << CC_DSTCCTRL_SHFT); 1215 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1216 1216
1217 ccr |= (rqc->swap << CC_SWAP_SHFT); 1217 ccr |= (rqc->swap << CC_SWAP_SHFT);
1218 1218
@@ -1623,6 +1623,11 @@ static inline int _alloc_event(struct pl330_thread *thrd)
1623 return -1; 1623 return -1;
1624} 1624}
1625 1625
1626static bool _chan_ns(const struct pl330_info *pi, int i)
1627{
1628 return pi->pcfg.irq_ns & (1 << i);
1629}
1630
1626/* Upon success, returns IdentityToken for the 1631/* Upon success, returns IdentityToken for the
1627 * allocated channel, NULL otherwise. 1632 * allocated channel, NULL otherwise.
1628 */ 1633 */
@@ -1647,7 +1652,8 @@ void *pl330_request_channel(const struct pl330_info *pi)
1647 1652
1648 for (i = 0; i < chans; i++) { 1653 for (i = 0; i < chans; i++) {
1649 thrd = &pl330->channels[i]; 1654 thrd = &pl330->channels[i];
1650 if (thrd->free) { 1655 if ((thrd->free) && (!_manager_ns(thrd) ||
1656 _chan_ns(pi, i))) {
1651 thrd->ev = _alloc_event(thrd); 1657 thrd->ev = _alloc_event(thrd);
1652 if (thrd->ev >= 0) { 1658 if (thrd->ev >= 0) {
1653 thrd->free = false; 1659 thrd->free = false;
diff --git a/arch/arm/configs/at91cap9adk_defconfig b/arch/arm/configs/at91cap9_defconfig
index ffb1edd93363..8826eb218e73 100644
--- a/arch/arm/configs/at91cap9adk_defconfig
+++ b/arch/arm/configs/at91cap9_defconfig
@@ -38,7 +38,6 @@ CONFIG_IP_PNP_RARP=y
38# CONFIG_IPV6 is not set 38# CONFIG_IPV6 is not set
39CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 39CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
40CONFIG_MTD=y 40CONFIG_MTD=y
41CONFIG_MTD_PARTITIONS=y
42CONFIG_MTD_CMDLINE_PARTS=y 41CONFIG_MTD_CMDLINE_PARTS=y
43CONFIG_MTD_CHAR=y 42CONFIG_MTD_CHAR=y
44CONFIG_MTD_BLOCK=y 43CONFIG_MTD_BLOCK=y
@@ -52,16 +51,12 @@ CONFIG_MTD_NAND_ATMEL=y
52CONFIG_BLK_DEV_LOOP=y 51CONFIG_BLK_DEV_LOOP=y
53CONFIG_BLK_DEV_RAM=y 52CONFIG_BLK_DEV_RAM=y
54CONFIG_BLK_DEV_RAM_SIZE=8192 53CONFIG_BLK_DEV_RAM_SIZE=8192
55CONFIG_ATMEL_SSC=y
56CONFIG_SCSI=y 54CONFIG_SCSI=y
57CONFIG_BLK_DEV_SD=y 55CONFIG_BLK_DEV_SD=y
58CONFIG_SCSI_MULTI_LUN=y 56CONFIG_SCSI_MULTI_LUN=y
59CONFIG_NETDEVICES=y 57CONFIG_NETDEVICES=y
60CONFIG_NET_ETHERNET=y
61CONFIG_MII=y 58CONFIG_MII=y
62CONFIG_MACB=y 59CONFIG_MACB=y
63# CONFIG_NETDEV_1000 is not set
64# CONFIG_NETDEV_10000 is not set
65# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 60# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
66CONFIG_INPUT_EVDEV=y 61CONFIG_INPUT_EVDEV=y
67# CONFIG_INPUT_KEYBOARD is not set 62# CONFIG_INPUT_KEYBOARD is not set
@@ -81,7 +76,6 @@ CONFIG_WATCHDOG=y
81CONFIG_WATCHDOG_NOWAYOUT=y 76CONFIG_WATCHDOG_NOWAYOUT=y
82CONFIG_FB=y 77CONFIG_FB=y
83CONFIG_FB_ATMEL=y 78CONFIG_FB_ATMEL=y
84# CONFIG_VGA_CONSOLE is not set
85CONFIG_LOGO=y 79CONFIG_LOGO=y
86# CONFIG_LOGO_LINUX_MONO is not set 80# CONFIG_LOGO_LINUX_MONO is not set
87# CONFIG_LOGO_LINUX_CLUT224 is not set 81# CONFIG_LOGO_LINUX_CLUT224 is not set
@@ -99,7 +93,6 @@ CONFIG_MMC_AT91=m
99CONFIG_RTC_CLASS=y 93CONFIG_RTC_CLASS=y
100CONFIG_RTC_DRV_AT91SAM9=y 94CONFIG_RTC_DRV_AT91SAM9=y
101CONFIG_EXT2_FS=y 95CONFIG_EXT2_FS=y
102CONFIG_INOTIFY=y
103CONFIG_VFAT_FS=y 96CONFIG_VFAT_FS=y
104CONFIG_TMPFS=y 97CONFIG_TMPFS=y
105CONFIG_JFFS2_FS=y 98CONFIG_JFFS2_FS=y
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
index 38cb7c985426..bbe4e1a1f5d8 100644
--- a/arch/arm/configs/at91rm9200_defconfig
+++ b/arch/arm/configs/at91rm9200_defconfig
@@ -5,7 +5,6 @@ CONFIG_SYSVIPC=y
5CONFIG_IKCONFIG=y 5CONFIG_IKCONFIG=y
6CONFIG_IKCONFIG_PROC=y 6CONFIG_IKCONFIG_PROC=y
7CONFIG_LOG_BUF_SHIFT=14 7CONFIG_LOG_BUF_SHIFT=14
8CONFIG_SYSFS_DEPRECATED_V2=y
9CONFIG_BLK_DEV_INITRD=y 8CONFIG_BLK_DEV_INITRD=y
10CONFIG_MODULES=y 9CONFIG_MODULES=y
11CONFIG_MODULE_FORCE_LOAD=y 10CONFIG_MODULE_FORCE_LOAD=y
@@ -56,7 +55,6 @@ CONFIG_IP_PNP=y
56CONFIG_IP_PNP_DHCP=y 55CONFIG_IP_PNP_DHCP=y
57CONFIG_IP_PNP_BOOTP=y 56CONFIG_IP_PNP_BOOTP=y
58CONFIG_NET_IPIP=m 57CONFIG_NET_IPIP=m
59CONFIG_NET_IPGRE=m
60CONFIG_INET_AH=m 58CONFIG_INET_AH=m
61CONFIG_INET_ESP=m 59CONFIG_INET_ESP=m
62CONFIG_INET_IPCOMP=m 60CONFIG_INET_IPCOMP=m
@@ -75,18 +73,8 @@ CONFIG_IPV6_TUNNEL=m
75CONFIG_BRIDGE=m 73CONFIG_BRIDGE=m
76CONFIG_VLAN_8021Q=m 74CONFIG_VLAN_8021Q=m
77CONFIG_BT=m 75CONFIG_BT=m
78CONFIG_BT_L2CAP=m
79CONFIG_BT_SCO=m
80CONFIG_BT_RFCOMM=m
81CONFIG_BT_RFCOMM_TTY=y
82CONFIG_BT_BNEP=m
83CONFIG_BT_BNEP_MC_FILTER=y
84CONFIG_BT_BNEP_PROTO_FILTER=y
85CONFIG_BT_HIDP=m
86CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 76CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
87CONFIG_MTD=y 77CONFIG_MTD=y
88CONFIG_MTD_CONCAT=y
89CONFIG_MTD_PARTITIONS=y
90CONFIG_MTD_CMDLINE_PARTS=y 78CONFIG_MTD_CMDLINE_PARTS=y
91CONFIG_MTD_AFS_PARTS=y 79CONFIG_MTD_AFS_PARTS=y
92CONFIG_MTD_CHAR=y 80CONFIG_MTD_CHAR=y
@@ -108,8 +96,6 @@ CONFIG_BLK_DEV_LOOP=y
108CONFIG_BLK_DEV_NBD=y 96CONFIG_BLK_DEV_NBD=y
109CONFIG_BLK_DEV_RAM=y 97CONFIG_BLK_DEV_RAM=y
110CONFIG_BLK_DEV_RAM_SIZE=8192 98CONFIG_BLK_DEV_RAM_SIZE=8192
111CONFIG_ATMEL_TCLIB=y
112CONFIG_EEPROM_LEGACY=m
113CONFIG_SCSI=y 99CONFIG_SCSI=y
114CONFIG_BLK_DEV_SD=y 100CONFIG_BLK_DEV_SD=y
115CONFIG_BLK_DEV_SR=m 101CONFIG_BLK_DEV_SR=m
@@ -119,14 +105,23 @@ CONFIG_SCSI_MULTI_LUN=y
119# CONFIG_SCSI_LOWLEVEL is not set 105# CONFIG_SCSI_LOWLEVEL is not set
120CONFIG_NETDEVICES=y 106CONFIG_NETDEVICES=y
121CONFIG_TUN=m 107CONFIG_TUN=m
108CONFIG_ARM_AT91_ETHER=y
122CONFIG_PHYLIB=y 109CONFIG_PHYLIB=y
123CONFIG_DAVICOM_PHY=y 110CONFIG_DAVICOM_PHY=y
124CONFIG_SMSC_PHY=y 111CONFIG_SMSC_PHY=y
125CONFIG_MICREL_PHY=y 112CONFIG_MICREL_PHY=y
126CONFIG_NET_ETHERNET=y 113CONFIG_PPP=y
127CONFIG_ARM_AT91_ETHER=y 114CONFIG_PPP_BSDCOMP=y
128# CONFIG_NETDEV_1000 is not set 115CONFIG_PPP_DEFLATE=y
129# CONFIG_NETDEV_10000 is not set 116CONFIG_PPP_FILTER=y
117CONFIG_PPP_MPPE=m
118CONFIG_PPP_MULTILINK=y
119CONFIG_PPPOE=m
120CONFIG_PPP_ASYNC=y
121CONFIG_SLIP=m
122CONFIG_SLIP_COMPRESSED=y
123CONFIG_SLIP_SMART=y
124CONFIG_SLIP_MODE_SLIP6=y
130CONFIG_USB_CATC=m 125CONFIG_USB_CATC=m
131CONFIG_USB_KAWETH=m 126CONFIG_USB_KAWETH=m
132CONFIG_USB_PEGASUS=m 127CONFIG_USB_PEGASUS=m
@@ -139,18 +134,6 @@ CONFIG_USB_NET_RNDIS_HOST=m
139CONFIG_USB_ALI_M5632=y 134CONFIG_USB_ALI_M5632=y
140CONFIG_USB_AN2720=y 135CONFIG_USB_AN2720=y
141CONFIG_USB_EPSON2888=y 136CONFIG_USB_EPSON2888=y
142CONFIG_PPP=y
143CONFIG_PPP_MULTILINK=y
144CONFIG_PPP_FILTER=y
145CONFIG_PPP_ASYNC=y
146CONFIG_PPP_DEFLATE=y
147CONFIG_PPP_BSDCOMP=y
148CONFIG_PPP_MPPE=m
149CONFIG_PPPOE=m
150CONFIG_SLIP=m
151CONFIG_SLIP_COMPRESSED=y
152CONFIG_SLIP_SMART=y
153CONFIG_SLIP_MODE_SLIP6=y
154# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 137# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
155CONFIG_INPUT_MOUSEDEV_SCREEN_X=640 138CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
156CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 139CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
@@ -158,9 +141,9 @@ CONFIG_INPUT_EVDEV=y
158CONFIG_KEYBOARD_GPIO=y 141CONFIG_KEYBOARD_GPIO=y
159# CONFIG_INPUT_MOUSE is not set 142# CONFIG_INPUT_MOUSE is not set
160CONFIG_INPUT_TOUCHSCREEN=y 143CONFIG_INPUT_TOUCHSCREEN=y
144CONFIG_LEGACY_PTY_COUNT=32
161CONFIG_SERIAL_ATMEL=y 145CONFIG_SERIAL_ATMEL=y
162CONFIG_SERIAL_ATMEL_CONSOLE=y 146CONFIG_SERIAL_ATMEL_CONSOLE=y
163CONFIG_LEGACY_PTY_COUNT=32
164CONFIG_HW_RANDOM=y 147CONFIG_HW_RANDOM=y
165CONFIG_I2C=y 148CONFIG_I2C=y
166CONFIG_I2C_CHARDEV=y 149CONFIG_I2C_CHARDEV=y
@@ -290,7 +273,6 @@ CONFIG_NFS_V3_ACL=y
290CONFIG_NFS_V4=y 273CONFIG_NFS_V4=y
291CONFIG_ROOT_NFS=y 274CONFIG_ROOT_NFS=y
292CONFIG_NFSD=y 275CONFIG_NFSD=y
293CONFIG_SMB_FS=m
294CONFIG_CIFS=m 276CONFIG_CIFS=m
295CONFIG_PARTITION_ADVANCED=y 277CONFIG_PARTITION_ADVANCED=y
296CONFIG_MAC_PARTITION=y 278CONFIG_MAC_PARTITION=y
@@ -335,7 +317,6 @@ CONFIG_NLS_UTF8=y
335CONFIG_MAGIC_SYSRQ=y 317CONFIG_MAGIC_SYSRQ=y
336CONFIG_DEBUG_FS=y 318CONFIG_DEBUG_FS=y
337CONFIG_DEBUG_KERNEL=y 319CONFIG_DEBUG_KERNEL=y
338# CONFIG_RCU_CPU_STALL_DETECTOR is not set
339# CONFIG_FTRACE is not set 320# CONFIG_FTRACE is not set
340CONFIG_CRYPTO_PCBC=y 321CONFIG_CRYPTO_PCBC=y
341CONFIG_CRYPTO_SHA1=y 322CONFIG_CRYPTO_SHA1=y
diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260_defconfig
index f8a9226413bf..505b3765f87e 100644
--- a/arch/arm/configs/at91sam9260ek_defconfig
+++ b/arch/arm/configs/at91sam9260_defconfig
@@ -12,11 +12,23 @@ CONFIG_MODULE_UNLOAD=y
12# CONFIG_IOSCHED_CFQ is not set 12# CONFIG_IOSCHED_CFQ is not set
13CONFIG_ARCH_AT91=y 13CONFIG_ARCH_AT91=y
14CONFIG_ARCH_AT91SAM9260=y 14CONFIG_ARCH_AT91SAM9260=y
15CONFIG_ARCH_AT91SAM9260_SAM9XE=y
15CONFIG_MACH_AT91SAM9260EK=y 16CONFIG_MACH_AT91SAM9260EK=y
17CONFIG_MACH_CAM60=y
18CONFIG_MACH_SAM9_L9260=y
19CONFIG_MACH_AFEB9260=y
20CONFIG_MACH_USB_A9260=y
21CONFIG_MACH_QIL_A9260=y
22CONFIG_MACH_CPU9260=y
23CONFIG_MACH_FLEXIBITY=y
24CONFIG_MACH_SNAPPER_9260=y
25CONFIG_MACH_AT91SAM_DT=y
16CONFIG_AT91_PROGRAMMABLE_CLOCKS=y 26CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
17# CONFIG_ARM_THUMB is not set 27# CONFIG_ARM_THUMB is not set
18CONFIG_ZBOOT_ROM_TEXT=0x0 28CONFIG_ZBOOT_ROM_TEXT=0x0
19CONFIG_ZBOOT_ROM_BSS=0x0 29CONFIG_ZBOOT_ROM_BSS=0x0
30CONFIG_ARM_APPENDED_DTB=y
31CONFIG_ARM_ATAG_DTB_COMPAT=y
20CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" 32CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
21CONFIG_FPE_NWFPE=y 33CONFIG_FPE_NWFPE=y
22CONFIG_NET=y 34CONFIG_NET=y
@@ -33,12 +45,10 @@ CONFIG_IP_PNP_BOOTP=y
33CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 45CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
34CONFIG_BLK_DEV_RAM=y 46CONFIG_BLK_DEV_RAM=y
35CONFIG_BLK_DEV_RAM_SIZE=8192 47CONFIG_BLK_DEV_RAM_SIZE=8192
36CONFIG_ATMEL_SSC=y
37CONFIG_SCSI=y 48CONFIG_SCSI=y
38CONFIG_BLK_DEV_SD=y 49CONFIG_BLK_DEV_SD=y
39CONFIG_SCSI_MULTI_LUN=y 50CONFIG_SCSI_MULTI_LUN=y
40CONFIG_NETDEVICES=y 51CONFIG_NETDEVICES=y
41CONFIG_NET_ETHERNET=y
42CONFIG_MII=y 52CONFIG_MII=y
43CONFIG_MACB=y 53CONFIG_MACB=y
44# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 54# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
@@ -55,7 +65,6 @@ CONFIG_I2C_GPIO=y
55CONFIG_WATCHDOG=y 65CONFIG_WATCHDOG=y
56CONFIG_WATCHDOG_NOWAYOUT=y 66CONFIG_WATCHDOG_NOWAYOUT=y
57CONFIG_AT91SAM9X_WATCHDOG=y 67CONFIG_AT91SAM9X_WATCHDOG=y
58# CONFIG_VGA_CONSOLE is not set
59# CONFIG_USB_HID is not set 68# CONFIG_USB_HID is not set
60CONFIG_USB=y 69CONFIG_USB=y
61CONFIG_USB_DEVICEFS=y 70CONFIG_USB_DEVICEFS=y
@@ -71,7 +80,6 @@ CONFIG_USB_G_SERIAL=m
71CONFIG_RTC_CLASS=y 80CONFIG_RTC_CLASS=y
72CONFIG_RTC_DRV_AT91SAM9=y 81CONFIG_RTC_DRV_AT91SAM9=y
73CONFIG_EXT2_FS=y 82CONFIG_EXT2_FS=y
74CONFIG_INOTIFY=y
75CONFIG_VFAT_FS=y 83CONFIG_VFAT_FS=y
76CONFIG_TMPFS=y 84CONFIG_TMPFS=y
77CONFIG_CRAMFS=y 85CONFIG_CRAMFS=y
diff --git a/arch/arm/configs/at91sam9g20ek_defconfig b/arch/arm/configs/at91sam9g20_defconfig
index 9e90e6d79297..9123568d9a8d 100644
--- a/arch/arm/configs/at91sam9g20ek_defconfig
+++ b/arch/arm/configs/at91sam9g20_defconfig
@@ -14,6 +14,15 @@ CONFIG_ARCH_AT91=y
14CONFIG_ARCH_AT91SAM9G20=y 14CONFIG_ARCH_AT91SAM9G20=y
15CONFIG_MACH_AT91SAM9G20EK=y 15CONFIG_MACH_AT91SAM9G20EK=y
16CONFIG_MACH_AT91SAM9G20EK_2MMC=y 16CONFIG_MACH_AT91SAM9G20EK_2MMC=y
17CONFIG_MACH_CPU9G20=y
18CONFIG_MACH_ACMENETUSFOXG20=y
19CONFIG_MACH_PORTUXG20=y
20CONFIG_MACH_STAMP9G20=y
21CONFIG_MACH_PCONTROL_G20=y
22CONFIG_MACH_GSIA18S=y
23CONFIG_MACH_USB_A9G20=y
24CONFIG_MACH_SNAPPER_9260=y
25CONFIG_MACH_AT91SAM_DT=y
17CONFIG_AT91_PROGRAMMABLE_CLOCKS=y 26CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
18# CONFIG_ARM_THUMB is not set 27# CONFIG_ARM_THUMB is not set
19CONFIG_AEABI=y 28CONFIG_AEABI=y
@@ -21,9 +30,10 @@ CONFIG_LEDS=y
21CONFIG_LEDS_CPU=y 30CONFIG_LEDS_CPU=y
22CONFIG_ZBOOT_ROM_TEXT=0x0 31CONFIG_ZBOOT_ROM_TEXT=0x0
23CONFIG_ZBOOT_ROM_BSS=0x0 32CONFIG_ZBOOT_ROM_BSS=0x0
33CONFIG_ARM_APPENDED_DTB=y
34CONFIG_ARM_ATAG_DTB_COMPAT=y
24CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw" 35CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
25CONFIG_FPE_NWFPE=y 36CONFIG_FPE_NWFPE=y
26CONFIG_PM=y
27CONFIG_NET=y 37CONFIG_NET=y
28CONFIG_PACKET=y 38CONFIG_PACKET=y
29CONFIG_UNIX=y 39CONFIG_UNIX=y
@@ -37,8 +47,6 @@ CONFIG_IP_PNP_BOOTP=y
37# CONFIG_IPV6 is not set 47# CONFIG_IPV6 is not set
38CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 48CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
39CONFIG_MTD=y 49CONFIG_MTD=y
40CONFIG_MTD_CONCAT=y
41CONFIG_MTD_PARTITIONS=y
42CONFIG_MTD_CMDLINE_PARTS=y 50CONFIG_MTD_CMDLINE_PARTS=y
43CONFIG_MTD_CHAR=y 51CONFIG_MTD_CHAR=y
44CONFIG_MTD_BLOCK=y 52CONFIG_MTD_BLOCK=y
@@ -48,17 +56,13 @@ CONFIG_MTD_NAND_ATMEL=y
48CONFIG_BLK_DEV_LOOP=y 56CONFIG_BLK_DEV_LOOP=y
49CONFIG_BLK_DEV_RAM=y 57CONFIG_BLK_DEV_RAM=y
50CONFIG_BLK_DEV_RAM_SIZE=8192 58CONFIG_BLK_DEV_RAM_SIZE=8192
51CONFIG_ATMEL_SSC=y
52CONFIG_SCSI=y 59CONFIG_SCSI=y
53CONFIG_BLK_DEV_SD=y 60CONFIG_BLK_DEV_SD=y
54CONFIG_SCSI_MULTI_LUN=y 61CONFIG_SCSI_MULTI_LUN=y
55# CONFIG_SCSI_LOWLEVEL is not set 62# CONFIG_SCSI_LOWLEVEL is not set
56CONFIG_NETDEVICES=y 63CONFIG_NETDEVICES=y
57CONFIG_NET_ETHERNET=y
58CONFIG_MII=y 64CONFIG_MII=y
59CONFIG_MACB=y 65CONFIG_MACB=y
60# CONFIG_NETDEV_1000 is not set
61# CONFIG_NETDEV_10000 is not set
62# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 66# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
63CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 67CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
64CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 68CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
@@ -66,15 +70,14 @@ CONFIG_INPUT_EVDEV=y
66# CONFIG_KEYBOARD_ATKBD is not set 70# CONFIG_KEYBOARD_ATKBD is not set
67CONFIG_KEYBOARD_GPIO=y 71CONFIG_KEYBOARD_GPIO=y
68# CONFIG_INPUT_MOUSE is not set 72# CONFIG_INPUT_MOUSE is not set
73CONFIG_LEGACY_PTY_COUNT=16
69CONFIG_SERIAL_ATMEL=y 74CONFIG_SERIAL_ATMEL=y
70CONFIG_SERIAL_ATMEL_CONSOLE=y 75CONFIG_SERIAL_ATMEL_CONSOLE=y
71CONFIG_LEGACY_PTY_COUNT=16
72CONFIG_HW_RANDOM=y 76CONFIG_HW_RANDOM=y
73CONFIG_SPI=y 77CONFIG_SPI=y
74CONFIG_SPI_ATMEL=y 78CONFIG_SPI_ATMEL=y
75CONFIG_SPI_SPIDEV=y 79CONFIG_SPI_SPIDEV=y
76# CONFIG_HWMON is not set 80# CONFIG_HWMON is not set
77# CONFIG_VGA_CONSOLE is not set
78CONFIG_SOUND=y 81CONFIG_SOUND=y
79CONFIG_SND=y 82CONFIG_SND=y
80CONFIG_SND_SEQUENCER=y 83CONFIG_SND_SEQUENCER=y
@@ -82,7 +85,6 @@ CONFIG_SND_MIXER_OSS=y
82CONFIG_SND_PCM_OSS=y 85CONFIG_SND_PCM_OSS=y
83CONFIG_SND_SEQUENCER_OSS=y 86CONFIG_SND_SEQUENCER_OSS=y
84# CONFIG_SND_VERBOSE_PROCFS is not set 87# CONFIG_SND_VERBOSE_PROCFS is not set
85CONFIG_SND_AT73C213=y
86CONFIG_USB=y 88CONFIG_USB=y
87CONFIG_USB_DEVICEFS=y 89CONFIG_USB_DEVICEFS=y
88# CONFIG_USB_DEVICE_CLASS is not set 90# CONFIG_USB_DEVICE_CLASS is not set
@@ -105,7 +107,6 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
105CONFIG_RTC_CLASS=y 107CONFIG_RTC_CLASS=y
106CONFIG_RTC_DRV_AT91SAM9=y 108CONFIG_RTC_DRV_AT91SAM9=y
107CONFIG_EXT2_FS=y 109CONFIG_EXT2_FS=y
108CONFIG_INOTIFY=y
109CONFIG_MSDOS_FS=y 110CONFIG_MSDOS_FS=y
110CONFIG_VFAT_FS=y 111CONFIG_VFAT_FS=y
111CONFIG_TMPFS=y 112CONFIG_TMPFS=y
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
index c5876d244f4b..606d48f3b8f8 100644
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -18,6 +18,7 @@ CONFIG_MODULE_UNLOAD=y
18CONFIG_ARCH_AT91=y 18CONFIG_ARCH_AT91=y
19CONFIG_ARCH_AT91SAM9G45=y 19CONFIG_ARCH_AT91SAM9G45=y
20CONFIG_MACH_AT91SAM9M10G45EK=y 20CONFIG_MACH_AT91SAM9M10G45EK=y
21CONFIG_MACH_AT91SAM_DT=y
21CONFIG_AT91_PROGRAMMABLE_CLOCKS=y 22CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
22CONFIG_AT91_SLOW_CLOCK=y 23CONFIG_AT91_SLOW_CLOCK=y
23CONFIG_AEABI=y 24CONFIG_AEABI=y
@@ -73,11 +74,8 @@ CONFIG_SCSI_MULTI_LUN=y
73# CONFIG_SCSI_LOWLEVEL is not set 74# CONFIG_SCSI_LOWLEVEL is not set
74CONFIG_NETDEVICES=y 75CONFIG_NETDEVICES=y
75CONFIG_MII=y 76CONFIG_MII=y
76CONFIG_DAVICOM_PHY=y
77CONFIG_NET_ETHERNET=y
78CONFIG_MACB=y 77CONFIG_MACB=y
79# CONFIG_NETDEV_1000 is not set 78CONFIG_DAVICOM_PHY=y
80# CONFIG_NETDEV_10000 is not set
81CONFIG_LIBERTAS_THINFIRM=m 79CONFIG_LIBERTAS_THINFIRM=m
82CONFIG_LIBERTAS_THINFIRM_USB=m 80CONFIG_LIBERTAS_THINFIRM_USB=m
83CONFIG_AT76C50X_USB=m 81CONFIG_AT76C50X_USB=m
@@ -131,7 +129,6 @@ CONFIG_I2C_GPIO=y
131CONFIG_SPI=y 129CONFIG_SPI=y
132CONFIG_SPI_ATMEL=y 130CONFIG_SPI_ATMEL=y
133# CONFIG_HWMON is not set 131# CONFIG_HWMON is not set
134# CONFIG_MFD_SUPPORT is not set
135CONFIG_FB=y 132CONFIG_FB=y
136CONFIG_FB_ATMEL=y 133CONFIG_FB_ATMEL=y
137CONFIG_FB_UDL=m 134CONFIG_FB_UDL=m
diff --git a/arch/arm/configs/at91sam9rlek_defconfig b/arch/arm/configs/at91sam9rl_defconfig
index 75621e4d03fc..ad562ee64209 100644
--- a/arch/arm/configs/at91sam9rlek_defconfig
+++ b/arch/arm/configs/at91sam9rl_defconfig
@@ -23,8 +23,6 @@ CONFIG_NET=y
23CONFIG_UNIX=y 23CONFIG_UNIX=y
24CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 24CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
25CONFIG_MTD=y 25CONFIG_MTD=y
26CONFIG_MTD_CONCAT=y
27CONFIG_MTD_PARTITIONS=y
28CONFIG_MTD_CMDLINE_PARTS=y 26CONFIG_MTD_CMDLINE_PARTS=y
29CONFIG_MTD_CHAR=y 27CONFIG_MTD_CHAR=y
30CONFIG_MTD_BLOCK=y 28CONFIG_MTD_BLOCK=y
@@ -35,7 +33,6 @@ CONFIG_BLK_DEV_LOOP=y
35CONFIG_BLK_DEV_RAM=y 33CONFIG_BLK_DEV_RAM=y
36CONFIG_BLK_DEV_RAM_COUNT=4 34CONFIG_BLK_DEV_RAM_COUNT=4
37CONFIG_BLK_DEV_RAM_SIZE=24576 35CONFIG_BLK_DEV_RAM_SIZE=24576
38CONFIG_ATMEL_SSC=y
39CONFIG_SCSI=y 36CONFIG_SCSI=y
40CONFIG_BLK_DEV_SD=y 37CONFIG_BLK_DEV_SD=y
41CONFIG_SCSI_MULTI_LUN=y 38CONFIG_SCSI_MULTI_LUN=y
@@ -62,13 +59,11 @@ CONFIG_WATCHDOG_NOWAYOUT=y
62CONFIG_AT91SAM9X_WATCHDOG=y 59CONFIG_AT91SAM9X_WATCHDOG=y
63CONFIG_FB=y 60CONFIG_FB=y
64CONFIG_FB_ATMEL=y 61CONFIG_FB_ATMEL=y
65# CONFIG_VGA_CONSOLE is not set
66CONFIG_MMC=y 62CONFIG_MMC=y
67CONFIG_MMC_AT91=m 63CONFIG_MMC_AT91=m
68CONFIG_RTC_CLASS=y 64CONFIG_RTC_CLASS=y
69CONFIG_RTC_DRV_AT91SAM9=y 65CONFIG_RTC_DRV_AT91SAM9=y
70CONFIG_EXT2_FS=y 66CONFIG_EXT2_FS=y
71CONFIG_INOTIFY=y
72CONFIG_MSDOS_FS=y 67CONFIG_MSDOS_FS=y
73CONFIG_VFAT_FS=y 68CONFIG_VFAT_FS=y
74CONFIG_TMPFS=y 69CONFIG_TMPFS=y
diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig
index 227a477346ed..d95763d5f0d8 100644
--- a/arch/arm/configs/ezx_defconfig
+++ b/arch/arm/configs/ezx_defconfig
@@ -287,7 +287,7 @@ CONFIG_USB=y
287# CONFIG_USB_DEVICE_CLASS is not set 287# CONFIG_USB_DEVICE_CLASS is not set
288CONFIG_USB_OHCI_HCD=y 288CONFIG_USB_OHCI_HCD=y
289CONFIG_USB_GADGET=y 289CONFIG_USB_GADGET=y
290CONFIG_USB_GADGET_PXA27X=y 290CONFIG_USB_PXA27X=y
291CONFIG_USB_ETH=m 291CONFIG_USB_ETH=m
292# CONFIG_USB_ETH_RNDIS is not set 292# CONFIG_USB_ETH_RNDIS is not set
293CONFIG_MMC=y 293CONFIG_MMC=y
diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig
index 176ec22af034..fd996bb13022 100644
--- a/arch/arm/configs/imote2_defconfig
+++ b/arch/arm/configs/imote2_defconfig
@@ -263,7 +263,7 @@ CONFIG_USB=y
263# CONFIG_USB_DEVICE_CLASS is not set 263# CONFIG_USB_DEVICE_CLASS is not set
264CONFIG_USB_OHCI_HCD=y 264CONFIG_USB_OHCI_HCD=y
265CONFIG_USB_GADGET=y 265CONFIG_USB_GADGET=y
266CONFIG_USB_GADGET_PXA27X=y 266CONFIG_USB_PXA27X=y
267CONFIG_USB_ETH=m 267CONFIG_USB_ETH=m
268# CONFIG_USB_ETH_RNDIS is not set 268# CONFIG_USB_ETH_RNDIS is not set
269CONFIG_MMC=y 269CONFIG_MMC=y
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
index a88e64d4e9a5..443675d317e6 100644
--- a/arch/arm/configs/magician_defconfig
+++ b/arch/arm/configs/magician_defconfig
@@ -132,7 +132,7 @@ CONFIG_USB_MON=m
132CONFIG_USB_OHCI_HCD=y 132CONFIG_USB_OHCI_HCD=y
133CONFIG_USB_GADGET=y 133CONFIG_USB_GADGET=y
134CONFIG_USB_GADGET_VBUS_DRAW=500 134CONFIG_USB_GADGET_VBUS_DRAW=500
135CONFIG_USB_GADGET_PXA27X=y 135CONFIG_USB_PXA27X=y
136CONFIG_USB_ETH=m 136CONFIG_USB_ETH=m
137# CONFIG_USB_ETH_RNDIS is not set 137# CONFIG_USB_ETH_RNDIS is not set
138CONFIG_USB_GADGETFS=m 138CONFIG_USB_GADGETFS=m
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index 7b63462b349d..a7e777581378 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -48,7 +48,6 @@ CONFIG_MACH_SX1=y
48CONFIG_MACH_NOKIA770=y 48CONFIG_MACH_NOKIA770=y
49CONFIG_MACH_AMS_DELTA=y 49CONFIG_MACH_AMS_DELTA=y
50CONFIG_MACH_OMAP_GENERIC=y 50CONFIG_MACH_OMAP_GENERIC=y
51CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
52CONFIG_OMAP_ARM_216MHZ=y 51CONFIG_OMAP_ARM_216MHZ=y
53CONFIG_OMAP_ARM_195MHZ=y 52CONFIG_OMAP_ARM_195MHZ=y
54CONFIG_OMAP_ARM_192MHZ=y 53CONFIG_OMAP_ARM_192MHZ=y
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 4a5a12681be2..374000ec4e4e 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -14,8 +14,6 @@ CONFIG_MODULE_UNLOAD=y
14CONFIG_ARCH_U300=y 14CONFIG_ARCH_U300=y
15CONFIG_MACH_U300=y 15CONFIG_MACH_U300=y
16CONFIG_MACH_U300_BS335=y 16CONFIG_MACH_U300_BS335=y
17CONFIG_MACH_U300_DUAL_RAM=y
18CONFIG_U300_DEBUG=y
19CONFIG_MACH_U300_SPIDUMMY=y 17CONFIG_MACH_U300_SPIDUMMY=y
20CONFIG_NO_HZ=y 18CONFIG_NO_HZ=y
21CONFIG_HIGH_RES_TIMERS=y 19CONFIG_HIGH_RES_TIMERS=y
@@ -26,19 +24,21 @@ CONFIG_ZBOOT_ROM_BSS=0x0
26CONFIG_CMDLINE="root=/dev/ram0 rw rootfstype=rootfs console=ttyAMA0,115200n8 lpj=515072" 24CONFIG_CMDLINE="root=/dev/ram0 rw rootfstype=rootfs console=ttyAMA0,115200n8 lpj=515072"
27CONFIG_CPU_IDLE=y 25CONFIG_CPU_IDLE=y
28CONFIG_FPE_NWFPE=y 26CONFIG_FPE_NWFPE=y
29CONFIG_PM=y
30# CONFIG_SUSPEND is not set 27# CONFIG_SUSPEND is not set
31CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 28CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
32# CONFIG_PREVENT_FIRMWARE_BUILD is not set 29# CONFIG_PREVENT_FIRMWARE_BUILD is not set
33# CONFIG_MISC_DEVICES is not set 30CONFIG_MTD=y
31CONFIG_MTD_CMDLINE_PARTS=y
32CONFIG_MTD_NAND=y
33CONFIG_MTD_NAND_FSMC=y
34# CONFIG_INPUT_MOUSEDEV is not set 34# CONFIG_INPUT_MOUSEDEV is not set
35CONFIG_INPUT_EVDEV=y 35CONFIG_INPUT_EVDEV=y
36# CONFIG_KEYBOARD_ATKBD is not set 36# CONFIG_KEYBOARD_ATKBD is not set
37# CONFIG_INPUT_MOUSE is not set 37# CONFIG_INPUT_MOUSE is not set
38# CONFIG_SERIO is not set 38# CONFIG_SERIO is not set
39CONFIG_LEGACY_PTY_COUNT=16
39CONFIG_SERIAL_AMBA_PL011=y 40CONFIG_SERIAL_AMBA_PL011=y
40CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 41CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
41CONFIG_LEGACY_PTY_COUNT=16
42# CONFIG_HW_RANDOM is not set 42# CONFIG_HW_RANDOM is not set
43CONFIG_I2C=y 43CONFIG_I2C=y
44# CONFIG_HWMON is not set 44# CONFIG_HWMON is not set
@@ -51,6 +51,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y
51# CONFIG_HID_SUPPORT is not set 51# CONFIG_HID_SUPPORT is not set
52# CONFIG_USB_SUPPORT is not set 52# CONFIG_USB_SUPPORT is not set
53CONFIG_MMC=y 53CONFIG_MMC=y
54CONFIG_MMC_CLKGATE=y
54CONFIG_MMC_ARMMMCI=y 55CONFIG_MMC_ARMMMCI=y
55CONFIG_RTC_CLASS=y 56CONFIG_RTC_CLASS=y
56# CONFIG_RTC_HCTOSYS is not set 57# CONFIG_RTC_HCTOSYS is not set
@@ -65,10 +66,8 @@ CONFIG_NLS_CODEPAGE_437=y
65CONFIG_NLS_ISO8859_1=y 66CONFIG_NLS_ISO8859_1=y
66CONFIG_PRINTK_TIME=y 67CONFIG_PRINTK_TIME=y
67CONFIG_DEBUG_FS=y 68CONFIG_DEBUG_FS=y
68CONFIG_DEBUG_KERNEL=y
69# CONFIG_SCHED_DEBUG is not set 69# CONFIG_SCHED_DEBUG is not set
70CONFIG_TIMER_STATS=y 70CONFIG_TIMER_STATS=y
71# CONFIG_DEBUG_PREEMPT is not set 71# CONFIG_DEBUG_PREEMPT is not set
72CONFIG_DEBUG_INFO=y 72CONFIG_DEBUG_INFO=y
73# CONFIG_RCU_CPU_STALL_DETECTOR is not set
74# CONFIG_CRC32 is not set 73# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 97d31a4663da..2d7b6e7b7271 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -10,7 +10,7 @@ CONFIG_MODULE_UNLOAD=y
10CONFIG_ARCH_U8500=y 10CONFIG_ARCH_U8500=y
11CONFIG_UX500_SOC_DB5500=y 11CONFIG_UX500_SOC_DB5500=y
12CONFIG_UX500_SOC_DB8500=y 12CONFIG_UX500_SOC_DB8500=y
13CONFIG_MACH_U8500=y 13CONFIG_MACH_HREFV60=y
14CONFIG_MACH_SNOWBALL=y 14CONFIG_MACH_SNOWBALL=y
15CONFIG_MACH_U5500=y 15CONFIG_MACH_U5500=y
16CONFIG_NO_HZ=y 16CONFIG_NO_HZ=y
@@ -24,6 +24,7 @@ CONFIG_CPU_FREQ=y
24CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y 24CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
25CONFIG_VFP=y 25CONFIG_VFP=y
26CONFIG_NEON=y 26CONFIG_NEON=y
27CONFIG_PM_RUNTIME=y
27CONFIG_NET=y 28CONFIG_NET=y
28CONFIG_PACKET=y 29CONFIG_PACKET=y
29CONFIG_UNIX=y 30CONFIG_UNIX=y
@@ -41,11 +42,8 @@ CONFIG_MISC_DEVICES=y
41CONFIG_AB8500_PWM=y 42CONFIG_AB8500_PWM=y
42CONFIG_SENSORS_BH1780=y 43CONFIG_SENSORS_BH1780=y
43CONFIG_NETDEVICES=y 44CONFIG_NETDEVICES=y
44CONFIG_SMSC_PHY=y
45CONFIG_NET_ETHERNET=y
46CONFIG_SMSC911X=y 45CONFIG_SMSC911X=y
47# CONFIG_NETDEV_1000 is not set 46CONFIG_SMSC_PHY=y
48# CONFIG_NETDEV_10000 is not set
49# CONFIG_WLAN is not set 47# CONFIG_WLAN is not set
50# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 48# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
51CONFIG_INPUT_EVDEV=y 49CONFIG_INPUT_EVDEV=y
@@ -72,15 +70,12 @@ CONFIG_SPI=y
72CONFIG_SPI_PL022=y 70CONFIG_SPI_PL022=y
73CONFIG_GPIO_STMPE=y 71CONFIG_GPIO_STMPE=y
74CONFIG_GPIO_TC3589X=y 72CONFIG_GPIO_TC3589X=y
75# CONFIG_HWMON is not set
76CONFIG_MFD_STMPE=y 73CONFIG_MFD_STMPE=y
77CONFIG_MFD_TC3589X=y 74CONFIG_MFD_TC3589X=y
75CONFIG_AB5500_CORE=y
78CONFIG_AB8500_CORE=y 76CONFIG_AB8500_CORE=y
79CONFIG_REGULATOR_AB8500=y 77CONFIG_REGULATOR_AB8500=y
80# CONFIG_HID_SUPPORT is not set 78# CONFIG_HID_SUPPORT is not set
81CONFIG_USB_MUSB_HDRC=y
82CONFIG_USB_GADGET_MUSB_HDRC=y
83CONFIG_MUSB_PIO_ONLY=y
84CONFIG_USB_GADGET=y 79CONFIG_USB_GADGET=y
85CONFIG_AB8500_USB=y 80CONFIG_AB8500_USB=y
86CONFIG_MMC=y 81CONFIG_MMC=y
@@ -97,6 +92,7 @@ CONFIG_DMADEVICES=y
97CONFIG_STE_DMA40=y 92CONFIG_STE_DMA40=y
98CONFIG_STAGING=y 93CONFIG_STAGING=y
99CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y 94CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y
95CONFIG_HSEM_U8500=y
100CONFIG_EXT2_FS=y 96CONFIG_EXT2_FS=y
101CONFIG_EXT2_FS_XATTR=y 97CONFIG_EXT2_FS_XATTR=y
102CONFIG_EXT2_FS_POSIX_ACL=y 98CONFIG_EXT2_FS_POSIX_ACL=y
diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig
index 59577ad3f4ef..547a3c1e59db 100644
--- a/arch/arm/configs/zeus_defconfig
+++ b/arch/arm/configs/zeus_defconfig
@@ -140,7 +140,7 @@ CONFIG_USB_SERIAL=m
140CONFIG_USB_SERIAL_GENERIC=y 140CONFIG_USB_SERIAL_GENERIC=y
141CONFIG_USB_SERIAL_MCT_U232=m 141CONFIG_USB_SERIAL_MCT_U232=m
142CONFIG_USB_GADGET=m 142CONFIG_USB_GADGET=m
143CONFIG_USB_GADGET_PXA27X=y 143CONFIG_USB_PXA27X=y
144CONFIG_USB_ETH=m 144CONFIG_USB_ETH=m
145CONFIG_USB_GADGETFS=m 145CONFIG_USB_GADGETFS=m
146CONFIG_USB_FILE_STORAGE=m 146CONFIG_USB_FILE_STORAGE=m
diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
new file mode 100644
index 000000000000..a0ada3ea4358
--- /dev/null
+++ b/arch/arm/include/asm/cti.h
@@ -0,0 +1,179 @@
1#ifndef __ASMARM_CTI_H
2#define __ASMARM_CTI_H
3
4#include <asm/io.h>
5
6/* The registers' definition is from section 3.2 of
7 * Embedded Cross Trigger Revision: r0p0
8 */
9#define CTICONTROL 0x000
10#define CTISTATUS 0x004
11#define CTILOCK 0x008
12#define CTIPROTECTION 0x00C
13#define CTIINTACK 0x010
14#define CTIAPPSET 0x014
15#define CTIAPPCLEAR 0x018
16#define CTIAPPPULSE 0x01c
17#define CTIINEN 0x020
18#define CTIOUTEN 0x0A0
19#define CTITRIGINSTATUS 0x130
20#define CTITRIGOUTSTATUS 0x134
21#define CTICHINSTATUS 0x138
22#define CTICHOUTSTATUS 0x13c
23#define CTIPERIPHID0 0xFE0
24#define CTIPERIPHID1 0xFE4
25#define CTIPERIPHID2 0xFE8
26#define CTIPERIPHID3 0xFEC
27#define CTIPCELLID0 0xFF0
28#define CTIPCELLID1 0xFF4
29#define CTIPCELLID2 0xFF8
30#define CTIPCELLID3 0xFFC
31
32/* The below are from section 3.6.4 of
33 * CoreSight v1.0 Architecture Specification
34 */
35#define LOCKACCESS 0xFB0
36#define LOCKSTATUS 0xFB4
37
38/* write this value to LOCKACCESS will unlock the module, and
39 * other value will lock the module
40 */
41#define LOCKCODE 0xC5ACCE55
42
43/**
44 * struct cti - cross trigger interface struct
45 * @base: mapped virtual address for the cti base
46 * @irq: irq number for the cti
47 * @trig_out_for_irq: triger out number which will cause
48 * the @irq happen
49 *
50 * cti struct used to operate cti registers.
51 */
52struct cti {
53 void __iomem *base;
54 int irq;
55 int trig_out_for_irq;
56};
57
58/**
59 * cti_init - initialize the cti instance
60 * @cti: cti instance
61 * @base: mapped virtual address for the cti base
62 * @irq: irq number for the cti
63 * @trig_out: triger out number which will cause
64 * the @irq happen
65 *
66 * called by machine code to pass the board dependent
67 * @base, @irq and @trig_out to cti.
68 */
69static inline void cti_init(struct cti *cti,
70 void __iomem *base, int irq, int trig_out)
71{
72 cti->base = base;
73 cti->irq = irq;
74 cti->trig_out_for_irq = trig_out;
75}
76
77/**
78 * cti_map_trigger - use the @chan to map @trig_in to @trig_out
79 * @cti: cti instance
80 * @trig_in: trigger in number
81 * @trig_out: trigger out number
82 * @channel: channel number
83 *
84 * This function maps one trigger in of @trig_in to one trigger
85 * out of @trig_out using the channel @chan.
86 */
87static inline void cti_map_trigger(struct cti *cti,
88 int trig_in, int trig_out, int chan)
89{
90 void __iomem *base = cti->base;
91 unsigned long val;
92
93 val = __raw_readl(base + CTIINEN + trig_in * 4);
94 val |= BIT(chan);
95 __raw_writel(val, base + CTIINEN + trig_in * 4);
96
97 val = __raw_readl(base + CTIOUTEN + trig_out * 4);
98 val |= BIT(chan);
99 __raw_writel(val, base + CTIOUTEN + trig_out * 4);
100}
101
102/**
103 * cti_enable - enable the cti module
104 * @cti: cti instance
105 *
106 * enable the cti module
107 */
108static inline void cti_enable(struct cti *cti)
109{
110 __raw_writel(0x1, cti->base + CTICONTROL);
111}
112
113/**
114 * cti_disable - disable the cti module
115 * @cti: cti instance
116 *
117 * enable the cti module
118 */
119static inline void cti_disable(struct cti *cti)
120{
121 __raw_writel(0, cti->base + CTICONTROL);
122}
123
124/**
125 * cti_irq_ack - clear the cti irq
126 * @cti: cti instance
127 *
128 * clear the cti irq
129 */
130static inline void cti_irq_ack(struct cti *cti)
131{
132 void __iomem *base = cti->base;
133 unsigned long val;
134
135 val = __raw_readl(base + CTIINTACK);
136 val |= BIT(cti->trig_out_for_irq);
137 __raw_writel(val, base + CTIINTACK);
138}
139
140/**
141 * cti_unlock - unlock cti module
142 * @cti: cti instance
143 *
144 * unlock the cti module, or else any writes to the cti
145 * module is not allowed.
146 */
147static inline void cti_unlock(struct cti *cti)
148{
149 void __iomem *base = cti->base;
150 unsigned long val;
151
152 val = __raw_readl(base + LOCKSTATUS);
153
154 if (val & 1) {
155 val = LOCKCODE;
156 __raw_writel(val, base + LOCKACCESS);
157 }
158}
159
160/**
161 * cti_lock - lock cti module
162 * @cti: cti instance
163 *
164 * lock the cti module, so any writes to the cti
165 * module will be not allowed.
166 */
167static inline void cti_lock(struct cti *cti)
168{
169 void __iomem *base = cti->base;
170 unsigned long val;
171
172 val = __raw_readl(base + LOCKSTATUS);
173
174 if (!(val & 1)) {
175 val = ~LOCKCODE;
176 __raw_writel(val, base + LOCKACCESS);
177 }
178}
179#endif
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 1db1143a9483..7df239bcdf27 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -20,6 +20,8 @@
20#ifndef __ASM_ARM_HARDWARE_L2X0_H 20#ifndef __ASM_ARM_HARDWARE_L2X0_H
21#define __ASM_ARM_HARDWARE_L2X0_H 21#define __ASM_ARM_HARDWARE_L2X0_H
22 22
23#include <linux/errno.h>
24
23#define L2X0_CACHE_ID 0x000 25#define L2X0_CACHE_ID 0x000
24#define L2X0_CACHE_TYPE 0x004 26#define L2X0_CACHE_TYPE 0x004
25#define L2X0_CTRL 0x100 27#define L2X0_CTRL 0x100
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 6fe6cf0895c9..bcb0c883e21e 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -13,6 +13,7 @@
13struct tag; 13struct tag;
14struct meminfo; 14struct meminfo;
15struct sys_timer; 15struct sys_timer;
16struct pt_regs;
16 17
17struct machine_desc { 18struct machine_desc {
18 unsigned int nr; /* architecture number */ 19 unsigned int nr; /* architecture number */
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index 0f8e3827a89b..99cfe3607989 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -32,7 +32,4 @@ enum arm_perf_pmu_ids {
32extern enum arm_perf_pmu_ids 32extern enum arm_perf_pmu_ids
33armpmu_get_pmu_id(void); 33armpmu_get_pmu_id(void);
34 34
35extern int
36armpmu_get_max_events(void);
37
38#endif /* __ARM_PERF_EVENT_H__ */ 35#endif /* __ARM_PERF_EVENT_H__ */
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 71d99b83cdb9..b5a5be2536c1 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -27,13 +27,22 @@ enum arm_pmu_type {
27/* 27/*
28 * struct arm_pmu_platdata - ARM PMU platform data 28 * struct arm_pmu_platdata - ARM PMU platform data
29 * 29 *
30 * @handle_irq: an optional handler which will be called from the interrupt and 30 * @handle_irq: an optional handler which will be called from the
31 * passed the address of the low level handler, and can be used to implement 31 * interrupt and passed the address of the low level handler,
32 * any platform specific handling before or after calling it. 32 * and can be used to implement any platform specific handling
33 * before or after calling it.
34 * @enable_irq: an optional handler which will be called after
35 * request_irq and be used to handle some platform specific
36 * irq enablement
37 * @disable_irq: an optional handler which will be called before
38 * free_irq and be used to handle some platform specific
39 * irq disablement
33 */ 40 */
34struct arm_pmu_platdata { 41struct arm_pmu_platdata {
35 irqreturn_t (*handle_irq)(int irq, void *dev, 42 irqreturn_t (*handle_irq)(int irq, void *dev,
36 irq_handler_t pmu_handler); 43 irq_handler_t pmu_handler);
44 void (*enable_irq)(int irq);
45 void (*disable_irq)(int irq);
37}; 46};
38 47
39#ifdef CONFIG_CPU_HAS_PMU 48#ifdef CONFIG_CPU_HAS_PMU
@@ -55,16 +64,6 @@ reserve_pmu(enum arm_pmu_type type);
55extern void 64extern void
56release_pmu(enum arm_pmu_type type); 65release_pmu(enum arm_pmu_type type);
57 66
58/**
59 * init_pmu() - Initialise the PMU.
60 *
61 * Initialise the system ready for PMU enabling. This should typically set the
62 * IRQ affinity and nothing else. The users (oprofile/perf events etc) will do
63 * the actual hardware initialisation.
64 */
65extern int
66init_pmu(enum arm_pmu_type type);
67
68#else /* CONFIG_CPU_HAS_PMU */ 67#else /* CONFIG_CPU_HAS_PMU */
69 68
70#include <linux/err.h> 69#include <linux/err.h>
diff --git a/arch/arm/include/asm/topology.h b/arch/arm/include/asm/topology.h
index a7e457ed27c3..58b8b84adcd2 100644
--- a/arch/arm/include/asm/topology.h
+++ b/arch/arm/include/asm/topology.h
@@ -25,7 +25,7 @@ extern struct cputopo_arm cpu_topology[NR_CPUS];
25 25
26void init_cpu_topology(void); 26void init_cpu_topology(void);
27void store_cpu_topology(unsigned int cpuid); 27void store_cpu_topology(unsigned int cpuid);
28const struct cpumask *cpu_coregroup_mask(unsigned int cpu); 28const struct cpumask *cpu_coregroup_mask(int cpu);
29 29
30#else 30#else
31 31
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index c60a2944f95b..4a1123783806 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -402,6 +402,8 @@
402#define __NR_syncfs (__NR_SYSCALL_BASE+373) 402#define __NR_syncfs (__NR_SYSCALL_BASE+373)
403#define __NR_sendmmsg (__NR_SYSCALL_BASE+374) 403#define __NR_sendmmsg (__NR_SYSCALL_BASE+374)
404#define __NR_setns (__NR_SYSCALL_BASE+375) 404#define __NR_setns (__NR_SYSCALL_BASE+375)
405#define __NR_process_vm_readv (__NR_SYSCALL_BASE+376)
406#define __NR_process_vm_writev (__NR_SYSCALL_BASE+377)
405 407
406/* 408/*
407 * The following SWIs are ARM private. 409 * The following SWIs are ARM private.
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 9943e9e74a1b..463ff4a0ec8a 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -385,6 +385,8 @@
385 CALL(sys_syncfs) 385 CALL(sys_syncfs)
386 CALL(sys_sendmmsg) 386 CALL(sys_sendmmsg)
387/* 375 */ CALL(sys_setns) 387/* 375 */ CALL(sys_setns)
388 CALL(sys_process_vm_readv)
389 CALL(sys_process_vm_writev)
388#ifndef syscalls_counted 390#ifndef syscalls_counted
389.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls 391.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
390#define syscalls_counted 392#define syscalls_counted
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bd49a6a2a17d..3a456c6c7005 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -496,7 +496,7 @@ ENDPROC(__und_usr)
496 .popsection 496 .popsection
497 .pushsection __ex_table,"a" 497 .pushsection __ex_table,"a"
498 .long 1b, 4b 498 .long 1b, 4b
499#if __LINUX_ARM_ARCH__ >= 7 499#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
500 .long 2b, 4b 500 .long 2b, 4b
501 .long 3b, 4b 501 .long 3b, 4b
502#endif 502#endif
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 566c54c2a1fe..08c82fd844a8 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -360,7 +360,7 @@ __secondary_data:
360 * r13 = *virtual* address to jump to upon completion 360 * r13 = *virtual* address to jump to upon completion
361 */ 361 */
362__enable_mmu: 362__enable_mmu:
363#ifdef CONFIG_ALIGNMENT_TRAP 363#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
364 orr r0, r0, #CR_A 364 orr r0, r0, #CR_A
365#else 365#else
366 bic r0, r0, #CR_A 366 bic r0, r0, #CR_A
diff --git a/arch/arm/kernel/kprobes-arm.c b/arch/arm/kernel/kprobes-arm.c
index 9fe8910308af..8a30c89da70e 100644
--- a/arch/arm/kernel/kprobes-arm.c
+++ b/arch/arm/kernel/kprobes-arm.c
@@ -519,10 +519,12 @@ static const union decode_item arm_cccc_0000_____1001_table[] = {
519static const union decode_item arm_cccc_0001_____1001_table[] = { 519static const union decode_item arm_cccc_0001_____1001_table[] = {
520 /* Synchronization primitives */ 520 /* Synchronization primitives */
521 521
522#if __LINUX_ARM_ARCH__ < 6
523 /* Deprecated on ARMv6 and may be UNDEFINED on v7 */
522 /* SMP/SWPB cccc 0001 0x00 xxxx xxxx xxxx 1001 xxxx */ 524 /* SMP/SWPB cccc 0001 0x00 xxxx xxxx xxxx 1001 xxxx */
523 DECODE_EMULATEX (0x0fb000f0, 0x01000090, emulate_rd12rn16rm0_rwflags_nopc, 525 DECODE_EMULATEX (0x0fb000f0, 0x01000090, emulate_rd12rn16rm0_rwflags_nopc,
524 REGS(NOPC, NOPC, 0, 0, NOPC)), 526 REGS(NOPC, NOPC, 0, 0, NOPC)),
525 527#endif
526 /* LDREX/STREX{,D,B,H} cccc 0001 1xxx xxxx xxxx xxxx 1001 xxxx */ 528 /* LDREX/STREX{,D,B,H} cccc 0001 1xxx xxxx xxxx xxxx 1001 xxxx */
527 /* And unallocated instructions... */ 529 /* And unallocated instructions... */
528 DECODE_END 530 DECODE_END
diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
index fc82de8bdcce..ba32b393b3f0 100644
--- a/arch/arm/kernel/kprobes-test-arm.c
+++ b/arch/arm/kernel/kprobes-test-arm.c
@@ -427,18 +427,25 @@ void kprobe_arm_test_cases(void)
427 427
428 TEST_GROUP("Synchronization primitives") 428 TEST_GROUP("Synchronization primitives")
429 429
430 /* 430#if __LINUX_ARM_ARCH__ < 6
431 * Use hard coded constants for SWP instructions to avoid warnings 431 TEST_RP("swp lr, r",7,VAL2,", [r",8,0,"]")
432 * about deprecated instructions. 432 TEST_R( "swpvs r0, r",1,VAL1,", [sp]")
433 */ 433 TEST_RP("swp sp, r",14,VAL2,", [r",12,13*4,"]")
434 TEST_RP( ".word 0xe108e097 @ swp lr, r",7,VAL2,", [r",8,0,"]") 434#else
435 TEST_R( ".word 0x610d0091 @ swpvs r0, r",1,VAL1,", [sp]") 435 TEST_UNSUPPORTED(".word 0xe108e097 @ swp lr, r7, [r8]")
436 TEST_RP( ".word 0xe10cd09e @ swp sp, r",14,VAL2,", [r",12,13*4,"]") 436 TEST_UNSUPPORTED(".word 0x610d0091 @ swpvs r0, r1, [sp]")
437 TEST_UNSUPPORTED(".word 0xe10cd09e @ swp sp, r14 [r12]")
438#endif
437 TEST_UNSUPPORTED(".word 0xe102f091 @ swp pc, r1, [r2]") 439 TEST_UNSUPPORTED(".word 0xe102f091 @ swp pc, r1, [r2]")
438 TEST_UNSUPPORTED(".word 0xe102009f @ swp r0, pc, [r2]") 440 TEST_UNSUPPORTED(".word 0xe102009f @ swp r0, pc, [r2]")
439 TEST_UNSUPPORTED(".word 0xe10f0091 @ swp r0, r1, [pc]") 441 TEST_UNSUPPORTED(".word 0xe10f0091 @ swp r0, r1, [pc]")
440 TEST_RP( ".word 0xe148e097 @ swpb lr, r",7,VAL2,", [r",8,0,"]") 442#if __LINUX_ARM_ARCH__ < 6
441 TEST_R( ".word 0x614d0091 @ swpvsb r0, r",1,VAL1,", [sp]") 443 TEST_RP("swpb lr, r",7,VAL2,", [r",8,0,"]")
444 TEST_R( "swpvsb r0, r",1,VAL1,", [sp]")
445#else
446 TEST_UNSUPPORTED(".word 0xe148e097 @ swpb lr, r7, [r8]")
447 TEST_UNSUPPORTED(".word 0x614d0091 @ swpvsb r0, r1, [sp]")
448#endif
442 TEST_UNSUPPORTED(".word 0xe142f091 @ swpb pc, r1, [r2]") 449 TEST_UNSUPPORTED(".word 0xe142f091 @ swpb pc, r1, [r2]")
443 450
444 TEST_UNSUPPORTED(".word 0xe1100090") /* Unallocated space */ 451 TEST_UNSUPPORTED(".word 0xe1100090") /* Unallocated space */
@@ -550,7 +557,7 @@ void kprobe_arm_test_cases(void)
550 TEST_RPR( "strccd r",8, VAL2,", [r",13,0, ", r",12,48,"]") 557 TEST_RPR( "strccd r",8, VAL2,", [r",13,0, ", r",12,48,"]")
551 TEST_RPR( "strd r",4, VAL1,", [r",2, 24,", r",3, 48,"]!") 558 TEST_RPR( "strd r",4, VAL1,", [r",2, 24,", r",3, 48,"]!")
552 TEST_RPR( "strcsd r",12,VAL2,", [r",11,48,", -r",10,24,"]!") 559 TEST_RPR( "strcsd r",12,VAL2,", [r",11,48,", -r",10,24,"]!")
553 TEST_RPR( "strd r",2, VAL1,", [r",3, 24,"], r",4,48,"") 560 TEST_RPR( "strd r",2, VAL1,", [r",5, 24,"], r",4,48,"")
554 TEST_RPR( "strd r",10,VAL2,", [r",9, 48,"], -r",7,24,"") 561 TEST_RPR( "strd r",10,VAL2,", [r",9, 48,"], -r",7,24,"")
555 TEST_UNSUPPORTED(".word 0xe1afc0fa @ strd r12, [pc, r10]!") 562 TEST_UNSUPPORTED(".word 0xe1afc0fa @ strd r12, [pc, r10]!")
556 563
diff --git a/arch/arm/kernel/kprobes-test-thumb.c b/arch/arm/kernel/kprobes-test-thumb.c
index 5e726c31c45a..5d8b85792222 100644
--- a/arch/arm/kernel/kprobes-test-thumb.c
+++ b/arch/arm/kernel/kprobes-test-thumb.c
@@ -222,8 +222,8 @@ void kprobe_thumb16_test_cases(void)
222DONT_TEST_IN_ITBLOCK( 222DONT_TEST_IN_ITBLOCK(
223 TEST_BF_R( "cbnz r",0,0, ", 2f") 223 TEST_BF_R( "cbnz r",0,0, ", 2f")
224 TEST_BF_R( "cbz r",2,-1,", 2f") 224 TEST_BF_R( "cbz r",2,-1,", 2f")
225 TEST_BF_RX( "cbnz r",4,1, ", 2f",0x20) 225 TEST_BF_RX( "cbnz r",4,1, ", 2f", SPACE_0x20)
226 TEST_BF_RX( "cbz r",7,0, ", 2f",0x40) 226 TEST_BF_RX( "cbz r",7,0, ", 2f", SPACE_0x40)
227) 227)
228 TEST_R("sxth r0, r",7, HH1,"") 228 TEST_R("sxth r0, r",7, HH1,"")
229 TEST_R("sxth r7, r",0, HH2,"") 229 TEST_R("sxth r7, r",0, HH2,"")
@@ -246,7 +246,7 @@ DONT_TEST_IN_ITBLOCK(
246 TESTCASE_START(code) \ 246 TESTCASE_START(code) \
247 TEST_ARG_PTR(13, offset) \ 247 TEST_ARG_PTR(13, offset) \
248 TEST_ARG_END("") \ 248 TEST_ARG_END("") \
249 TEST_BRANCH_F(code,0) \ 249 TEST_BRANCH_F(code) \
250 TESTCASE_END 250 TESTCASE_END
251 251
252 TEST("push {r0}") 252 TEST("push {r0}")
@@ -319,8 +319,8 @@ CONDITION_INSTRUCTIONS(8,
319 319
320 TEST_BF( "b 2f") 320 TEST_BF( "b 2f")
321 TEST_BB( "b 2b") 321 TEST_BB( "b 2b")
322 TEST_BF_X("b 2f", 0x400) 322 TEST_BF_X("b 2f", SPACE_0x400)
323 TEST_BB_X("b 2b", 0x400) 323 TEST_BB_X("b 2b", SPACE_0x400)
324 324
325 TEST_GROUP("Testing instructions in IT blocks") 325 TEST_GROUP("Testing instructions in IT blocks")
326 326
@@ -746,7 +746,7 @@ CONDITION_INSTRUCTIONS(22,
746 TEST_BB("bne.w 2b") 746 TEST_BB("bne.w 2b")
747 TEST_BF("bgt.w 2f") 747 TEST_BF("bgt.w 2f")
748 TEST_BB("blt.w 2b") 748 TEST_BB("blt.w 2b")
749 TEST_BF_X("bpl.w 2f",0x1000) 749 TEST_BF_X("bpl.w 2f", SPACE_0x1000)
750) 750)
751 751
752 TEST_UNSUPPORTED("msr cpsr, r0") 752 TEST_UNSUPPORTED("msr cpsr, r0")
@@ -786,11 +786,11 @@ CONDITION_INSTRUCTIONS(22,
786 786
787 TEST_BF( "b.w 2f") 787 TEST_BF( "b.w 2f")
788 TEST_BB( "b.w 2b") 788 TEST_BB( "b.w 2b")
789 TEST_BF_X("b.w 2f", 0x1000) 789 TEST_BF_X("b.w 2f", SPACE_0x1000)
790 790
791 TEST_BF( "bl.w 2f") 791 TEST_BF( "bl.w 2f")
792 TEST_BB( "bl.w 2b") 792 TEST_BB( "bl.w 2b")
793 TEST_BB_X("bl.w 2b", 0x1000) 793 TEST_BB_X("bl.w 2b", SPACE_0x1000)
794 794
795 TEST_X( "blx __dummy_arm_subroutine", 795 TEST_X( "blx __dummy_arm_subroutine",
796 ".arm \n\t" 796 ".arm \n\t"
diff --git a/arch/arm/kernel/kprobes-test.h b/arch/arm/kernel/kprobes-test.h
index 0dc5d77b9356..e28a869b1ae4 100644
--- a/arch/arm/kernel/kprobes-test.h
+++ b/arch/arm/kernel/kprobes-test.h
@@ -149,23 +149,31 @@ struct test_arg_end {
149 "1: "instruction" \n\t" \ 149 "1: "instruction" \n\t" \
150 " nop \n\t" 150 " nop \n\t"
151 151
152#define TEST_BRANCH_F(instruction, xtra_dist) \ 152#define TEST_BRANCH_F(instruction) \
153 TEST_INSTRUCTION(instruction) \ 153 TEST_INSTRUCTION(instruction) \
154 ".if "#xtra_dist" \n\t" \
155 " b 99f \n\t" \ 154 " b 99f \n\t" \
156 ".space "#xtra_dist" \n\t" \ 155 "2: nop \n\t"
157 ".endif \n\t" \ 156
157#define TEST_BRANCH_B(instruction) \
158 " b 50f \n\t" \
159 " b 99f \n\t" \
160 "2: nop \n\t" \
161 " b 99f \n\t" \
162 TEST_INSTRUCTION(instruction)
163
164#define TEST_BRANCH_FX(instruction, codex) \
165 TEST_INSTRUCTION(instruction) \
166 " b 99f \n\t" \
167 codex" \n\t" \
158 " b 99f \n\t" \ 168 " b 99f \n\t" \
159 "2: nop \n\t" 169 "2: nop \n\t"
160 170
161#define TEST_BRANCH_B(instruction, xtra_dist) \ 171#define TEST_BRANCH_BX(instruction, codex) \
162 " b 50f \n\t" \ 172 " b 50f \n\t" \
163 " b 99f \n\t" \ 173 " b 99f \n\t" \
164 "2: nop \n\t" \ 174 "2: nop \n\t" \
165 " b 99f \n\t" \ 175 " b 99f \n\t" \
166 ".if "#xtra_dist" \n\t" \ 176 codex" \n\t" \
167 ".space "#xtra_dist" \n\t" \
168 ".endif \n\t" \
169 TEST_INSTRUCTION(instruction) 177 TEST_INSTRUCTION(instruction)
170 178
171#define TESTCASE_END \ 179#define TESTCASE_END \
@@ -301,47 +309,60 @@ struct test_arg_end {
301 TESTCASE_START(code1 #reg1 code2) \ 309 TESTCASE_START(code1 #reg1 code2) \
302 TEST_ARG_PTR(reg1, val1) \ 310 TEST_ARG_PTR(reg1, val1) \
303 TEST_ARG_END("") \ 311 TEST_ARG_END("") \
304 TEST_BRANCH_F(code1 #reg1 code2, 0) \ 312 TEST_BRANCH_F(code1 #reg1 code2) \
305 TESTCASE_END 313 TESTCASE_END
306 314
307#define TEST_BF_X(code, xtra_dist) \ 315#define TEST_BF(code) \
308 TESTCASE_START(code) \ 316 TESTCASE_START(code) \
309 TEST_ARG_END("") \ 317 TEST_ARG_END("") \
310 TEST_BRANCH_F(code, xtra_dist) \ 318 TEST_BRANCH_F(code) \
311 TESTCASE_END 319 TESTCASE_END
312 320
313#define TEST_BB_X(code, xtra_dist) \ 321#define TEST_BB(code) \
314 TESTCASE_START(code) \ 322 TESTCASE_START(code) \
315 TEST_ARG_END("") \ 323 TEST_ARG_END("") \
316 TEST_BRANCH_B(code, xtra_dist) \ 324 TEST_BRANCH_B(code) \
317 TESTCASE_END 325 TESTCASE_END
318 326
319#define TEST_BF_RX(code1, reg, val, code2, xtra_dist) \ 327#define TEST_BF_R(code1, reg, val, code2) \
320 TESTCASE_START(code1 #reg code2) \ 328 TESTCASE_START(code1 #reg code2) \
321 TEST_ARG_REG(reg, val) \ 329 TEST_ARG_REG(reg, val) \
322 TEST_ARG_END("") \ 330 TEST_ARG_END("") \
323 TEST_BRANCH_F(code1 #reg code2, xtra_dist) \ 331 TEST_BRANCH_F(code1 #reg code2) \
324 TESTCASE_END 332 TESTCASE_END
325 333
326#define TEST_BB_RX(code1, reg, val, code2, xtra_dist) \ 334#define TEST_BB_R(code1, reg, val, code2) \
327 TESTCASE_START(code1 #reg code2) \ 335 TESTCASE_START(code1 #reg code2) \
328 TEST_ARG_REG(reg, val) \ 336 TEST_ARG_REG(reg, val) \
329 TEST_ARG_END("") \ 337 TEST_ARG_END("") \
330 TEST_BRANCH_B(code1 #reg code2, xtra_dist) \ 338 TEST_BRANCH_B(code1 #reg code2) \
331 TESTCASE_END 339 TESTCASE_END
332 340
333#define TEST_BF(code) TEST_BF_X(code, 0)
334#define TEST_BB(code) TEST_BB_X(code, 0)
335
336#define TEST_BF_R(code1, reg, val, code2) TEST_BF_RX(code1, reg, val, code2, 0)
337#define TEST_BB_R(code1, reg, val, code2) TEST_BB_RX(code1, reg, val, code2, 0)
338
339#define TEST_BF_RR(code1, reg1, val1, code2, reg2, val2, code3) \ 341#define TEST_BF_RR(code1, reg1, val1, code2, reg2, val2, code3) \
340 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \ 342 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
341 TEST_ARG_REG(reg1, val1) \ 343 TEST_ARG_REG(reg1, val1) \
342 TEST_ARG_REG(reg2, val2) \ 344 TEST_ARG_REG(reg2, val2) \
343 TEST_ARG_END("") \ 345 TEST_ARG_END("") \
344 TEST_BRANCH_F(code1 #reg1 code2 #reg2 code3, 0) \ 346 TEST_BRANCH_F(code1 #reg1 code2 #reg2 code3) \
347 TESTCASE_END
348
349#define TEST_BF_X(code, codex) \
350 TESTCASE_START(code) \
351 TEST_ARG_END("") \
352 TEST_BRANCH_FX(code, codex) \
353 TESTCASE_END
354
355#define TEST_BB_X(code, codex) \
356 TESTCASE_START(code) \
357 TEST_ARG_END("") \
358 TEST_BRANCH_BX(code, codex) \
359 TESTCASE_END
360
361#define TEST_BF_RX(code1, reg, val, code2, codex) \
362 TESTCASE_START(code1 #reg code2) \
363 TEST_ARG_REG(reg, val) \
364 TEST_ARG_END("") \
365 TEST_BRANCH_FX(code1 #reg code2, codex) \
345 TESTCASE_END 366 TESTCASE_END
346 367
347#define TEST_X(code, codex) \ 368#define TEST_X(code, codex) \
@@ -372,6 +393,25 @@ struct test_arg_end {
372 TESTCASE_END 393 TESTCASE_END
373 394
374 395
396/*
397 * Macros for defining space directives spread over multiple lines.
398 * These are required so the compiler guesses better the length of inline asm
399 * code and will spill the literal pool early enough to avoid generating PC
400 * relative loads with out of range offsets.
401 */
402#define TWICE(x) x x
403#define SPACE_0x8 TWICE(".space 4\n\t")
404#define SPACE_0x10 TWICE(SPACE_0x8)
405#define SPACE_0x20 TWICE(SPACE_0x10)
406#define SPACE_0x40 TWICE(SPACE_0x20)
407#define SPACE_0x80 TWICE(SPACE_0x40)
408#define SPACE_0x100 TWICE(SPACE_0x80)
409#define SPACE_0x200 TWICE(SPACE_0x100)
410#define SPACE_0x400 TWICE(SPACE_0x200)
411#define SPACE_0x800 TWICE(SPACE_0x400)
412#define SPACE_0x1000 TWICE(SPACE_0x800)
413
414
375/* Various values used in test cases... */ 415/* Various values used in test cases... */
376#define N(val) (val ^ 0xffffffff) 416#define N(val) (val ^ 0xffffffff)
377#define VAL1 0x12345678 417#define VAL1 0x12345678
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index cc40b965d42a..29620b632ed9 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -32,24 +32,6 @@ static atomic_t waiting_for_crash_ipi;
32 32
33int machine_kexec_prepare(struct kimage *image) 33int machine_kexec_prepare(struct kimage *image)
34{ 34{
35 unsigned long page_list;
36 void *reboot_code_buffer;
37 page_list = image->head & PAGE_MASK;
38
39 reboot_code_buffer = page_address(image->control_code_page);
40
41 /* Prepare parameters for reboot_code_buffer*/
42 kexec_start_address = image->start;
43 kexec_indirection_page = page_list;
44 kexec_mach_type = machine_arch_type;
45 kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET;
46
47 /* copy our kernel relocation code to the control code page */
48 memcpy(reboot_code_buffer,
49 relocate_new_kernel, relocate_new_kernel_size);
50
51 flush_icache_range((unsigned long) reboot_code_buffer,
52 (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
53 return 0; 35 return 0;
54} 36}
55 37
@@ -100,14 +82,31 @@ void (*kexec_reinit)(void);
100 82
101void machine_kexec(struct kimage *image) 83void machine_kexec(struct kimage *image)
102{ 84{
85 unsigned long page_list;
103 unsigned long reboot_code_buffer_phys; 86 unsigned long reboot_code_buffer_phys;
104 void *reboot_code_buffer; 87 void *reboot_code_buffer;
105 88
89
90 page_list = image->head & PAGE_MASK;
91
106 /* we need both effective and real address here */ 92 /* we need both effective and real address here */
107 reboot_code_buffer_phys = 93 reboot_code_buffer_phys =
108 page_to_pfn(image->control_code_page) << PAGE_SHIFT; 94 page_to_pfn(image->control_code_page) << PAGE_SHIFT;
109 reboot_code_buffer = page_address(image->control_code_page); 95 reboot_code_buffer = page_address(image->control_code_page);
110 96
97 /* Prepare parameters for reboot_code_buffer*/
98 kexec_start_address = image->start;
99 kexec_indirection_page = page_list;
100 kexec_mach_type = machine_arch_type;
101 kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET;
102
103 /* copy our kernel relocation code to the control code page */
104 memcpy(reboot_code_buffer,
105 relocate_new_kernel, relocate_new_kernel_size);
106
107
108 flush_icache_range((unsigned long) reboot_code_buffer,
109 (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
111 printk(KERN_INFO "Bye!\n"); 110 printk(KERN_INFO "Bye!\n");
112 111
113 if (kexec_reinit) 112 if (kexec_reinit)
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 24e2347be6b1..172101ac97de 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -59,8 +59,7 @@ armpmu_get_pmu_id(void)
59} 59}
60EXPORT_SYMBOL_GPL(armpmu_get_pmu_id); 60EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
61 61
62int 62int perf_num_counters(void)
63armpmu_get_max_events(void)
64{ 63{
65 int max_events = 0; 64 int max_events = 0;
66 65
@@ -69,12 +68,6 @@ armpmu_get_max_events(void)
69 68
70 return max_events; 69 return max_events;
71} 70}
72EXPORT_SYMBOL_GPL(armpmu_get_max_events);
73
74int perf_num_counters(void)
75{
76 return armpmu_get_max_events();
77}
78EXPORT_SYMBOL_GPL(perf_num_counters); 71EXPORT_SYMBOL_GPL(perf_num_counters);
79 72
80#define HW_OP_UNSUPPORTED 0xFFFF 73#define HW_OP_UNSUPPORTED 0xFFFF
@@ -343,8 +336,14 @@ validate_group(struct perf_event *event)
343{ 336{
344 struct perf_event *sibling, *leader = event->group_leader; 337 struct perf_event *sibling, *leader = event->group_leader;
345 struct pmu_hw_events fake_pmu; 338 struct pmu_hw_events fake_pmu;
339 DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
346 340
347 memset(&fake_pmu, 0, sizeof(fake_pmu)); 341 /*
342 * Initialise the fake PMU. We only need to populate the
343 * used_mask for the purposes of validation.
344 */
345 memset(fake_used_mask, 0, sizeof(fake_used_mask));
346 fake_pmu.used_mask = fake_used_mask;
348 347
349 if (!validate_event(&fake_pmu, leader)) 348 if (!validate_event(&fake_pmu, leader))
350 return -ENOSPC; 349 return -ENOSPC;
@@ -374,6 +373,8 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
374{ 373{
375 int i, irq, irqs; 374 int i, irq, irqs;
376 struct platform_device *pmu_device = armpmu->plat_device; 375 struct platform_device *pmu_device = armpmu->plat_device;
376 struct arm_pmu_platdata *plat =
377 dev_get_platdata(&pmu_device->dev);
377 378
378 irqs = min(pmu_device->num_resources, num_possible_cpus()); 379 irqs = min(pmu_device->num_resources, num_possible_cpus());
379 380
@@ -381,8 +382,11 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
381 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs)) 382 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
382 continue; 383 continue;
383 irq = platform_get_irq(pmu_device, i); 384 irq = platform_get_irq(pmu_device, i);
384 if (irq >= 0) 385 if (irq >= 0) {
386 if (plat && plat->disable_irq)
387 plat->disable_irq(irq);
385 free_irq(irq, armpmu); 388 free_irq(irq, armpmu);
389 }
386 } 390 }
387 391
388 release_pmu(armpmu->type); 392 release_pmu(armpmu->type);
@@ -396,6 +400,9 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
396 int i, err, irq, irqs; 400 int i, err, irq, irqs;
397 struct platform_device *pmu_device = armpmu->plat_device; 401 struct platform_device *pmu_device = armpmu->plat_device;
398 402
403 if (!pmu_device)
404 return -ENODEV;
405
399 err = reserve_pmu(armpmu->type); 406 err = reserve_pmu(armpmu->type);
400 if (err) { 407 if (err) {
401 pr_warning("unable to reserve pmu\n"); 408 pr_warning("unable to reserve pmu\n");
@@ -439,7 +446,8 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
439 irq); 446 irq);
440 armpmu_release_hardware(armpmu); 447 armpmu_release_hardware(armpmu);
441 return err; 448 return err;
442 } 449 } else if (plat && plat->enable_irq)
450 plat->enable_irq(irq);
443 451
444 cpumask_set_cpu(i, &armpmu->active_irqs); 452 cpumask_set_cpu(i, &armpmu->active_irqs);
445 } 453 }
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index e63d8115c01b..533be9930ec2 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -65,13 +65,15 @@ enum armv6_counters {
65 * accesses/misses in hardware. 65 * accesses/misses in hardware.
66 */ 66 */
67static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = { 67static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
68 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES, 68 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES,
69 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC, 69 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC,
70 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, 70 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
71 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, 71 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
72 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC, 72 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
73 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT, 73 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT,
74 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, 74 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
75 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6_PERFCTR_IBUF_STALL,
76 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6_PERFCTR_LSU_FULL_STALL,
75}; 77};
76 78
77static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 79static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -218,13 +220,15 @@ enum armv6mpcore_perf_types {
218 * accesses/misses in hardware. 220 * accesses/misses in hardware.
219 */ 221 */
220static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = { 222static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
221 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES, 223 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
222 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC, 224 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
223 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, 225 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
224 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, 226 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
225 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC, 227 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
226 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT, 228 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
227 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, 229 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
230 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6MPCORE_PERFCTR_IBUF_STALL,
231 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6MPCORE_PERFCTR_LSU_FULL_STALL,
228}; 232};
229 233
230static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 234static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 1ef6d0034b85..460bbbb6b885 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -28,165 +28,87 @@ static struct arm_pmu armv7pmu;
28 * they are not available. 28 * they are not available.
29 */ 29 */
30enum armv7_perf_types { 30enum armv7_perf_types {
31 ARMV7_PERFCTR_PMNC_SW_INCR = 0x00, 31 ARMV7_PERFCTR_PMNC_SW_INCR = 0x00,
32 ARMV7_PERFCTR_IFETCH_MISS = 0x01, 32 ARMV7_PERFCTR_L1_ICACHE_REFILL = 0x01,
33 ARMV7_PERFCTR_ITLB_MISS = 0x02, 33 ARMV7_PERFCTR_ITLB_REFILL = 0x02,
34 ARMV7_PERFCTR_DCACHE_REFILL = 0x03, /* L1 */ 34 ARMV7_PERFCTR_L1_DCACHE_REFILL = 0x03,
35 ARMV7_PERFCTR_DCACHE_ACCESS = 0x04, /* L1 */ 35 ARMV7_PERFCTR_L1_DCACHE_ACCESS = 0x04,
36 ARMV7_PERFCTR_DTLB_REFILL = 0x05, 36 ARMV7_PERFCTR_DTLB_REFILL = 0x05,
37 ARMV7_PERFCTR_DREAD = 0x06, 37 ARMV7_PERFCTR_MEM_READ = 0x06,
38 ARMV7_PERFCTR_DWRITE = 0x07, 38 ARMV7_PERFCTR_MEM_WRITE = 0x07,
39 ARMV7_PERFCTR_INSTR_EXECUTED = 0x08, 39 ARMV7_PERFCTR_INSTR_EXECUTED = 0x08,
40 ARMV7_PERFCTR_EXC_TAKEN = 0x09, 40 ARMV7_PERFCTR_EXC_TAKEN = 0x09,
41 ARMV7_PERFCTR_EXC_EXECUTED = 0x0A, 41 ARMV7_PERFCTR_EXC_EXECUTED = 0x0A,
42 ARMV7_PERFCTR_CID_WRITE = 0x0B, 42 ARMV7_PERFCTR_CID_WRITE = 0x0B,
43 /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS. 43
44 /*
45 * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
44 * It counts: 46 * It counts:
45 * - all branch instructions, 47 * - all (taken) branch instructions,
46 * - instructions that explicitly write the PC, 48 * - instructions that explicitly write the PC,
47 * - exception generating instructions. 49 * - exception generating instructions.
48 */ 50 */
49 ARMV7_PERFCTR_PC_WRITE = 0x0C, 51 ARMV7_PERFCTR_PC_WRITE = 0x0C,
50 ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D, 52 ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D,
51 ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E, 53 ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E,
52 ARMV7_PERFCTR_UNALIGNED_ACCESS = 0x0F, 54 ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS = 0x0F,
55 ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
56 ARMV7_PERFCTR_CLOCK_CYCLES = 0x11,
57 ARMV7_PERFCTR_PC_BRANCH_PRED = 0x12,
53 58
54 /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */ 59 /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
55 ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10, 60 ARMV7_PERFCTR_MEM_ACCESS = 0x13,
56 ARMV7_PERFCTR_CLOCK_CYCLES = 0x11, 61 ARMV7_PERFCTR_L1_ICACHE_ACCESS = 0x14,
57 ARMV7_PERFCTR_PC_BRANCH_PRED = 0x12, 62 ARMV7_PERFCTR_L1_DCACHE_WB = 0x15,
58 ARMV7_PERFCTR_MEM_ACCESS = 0x13, 63 ARMV7_PERFCTR_L2_CACHE_ACCESS = 0x16,
59 ARMV7_PERFCTR_L1_ICACHE_ACCESS = 0x14, 64 ARMV7_PERFCTR_L2_CACHE_REFILL = 0x17,
60 ARMV7_PERFCTR_L1_DCACHE_WB = 0x15, 65 ARMV7_PERFCTR_L2_CACHE_WB = 0x18,
61 ARMV7_PERFCTR_L2_DCACHE_ACCESS = 0x16, 66 ARMV7_PERFCTR_BUS_ACCESS = 0x19,
62 ARMV7_PERFCTR_L2_DCACHE_REFILL = 0x17, 67 ARMV7_PERFCTR_MEM_ERROR = 0x1A,
63 ARMV7_PERFCTR_L2_DCACHE_WB = 0x18, 68 ARMV7_PERFCTR_INSTR_SPEC = 0x1B,
64 ARMV7_PERFCTR_BUS_ACCESS = 0x19, 69 ARMV7_PERFCTR_TTBR_WRITE = 0x1C,
65 ARMV7_PERFCTR_MEMORY_ERROR = 0x1A, 70 ARMV7_PERFCTR_BUS_CYCLES = 0x1D,
66 ARMV7_PERFCTR_INSTR_SPEC = 0x1B, 71
67 ARMV7_PERFCTR_TTBR_WRITE = 0x1C, 72 ARMV7_PERFCTR_CPU_CYCLES = 0xFF
68 ARMV7_PERFCTR_BUS_CYCLES = 0x1D,
69
70 ARMV7_PERFCTR_CPU_CYCLES = 0xFF
71}; 73};
72 74
73/* ARMv7 Cortex-A8 specific event types */ 75/* ARMv7 Cortex-A8 specific event types */
74enum armv7_a8_perf_types { 76enum armv7_a8_perf_types {
75 ARMV7_PERFCTR_WRITE_BUFFER_FULL = 0x40, 77 ARMV7_A8_PERFCTR_L2_CACHE_ACCESS = 0x43,
76 ARMV7_PERFCTR_L2_STORE_MERGED = 0x41, 78 ARMV7_A8_PERFCTR_L2_CACHE_REFILL = 0x44,
77 ARMV7_PERFCTR_L2_STORE_BUFF = 0x42, 79 ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS = 0x50,
78 ARMV7_PERFCTR_L2_ACCESS = 0x43, 80 ARMV7_A8_PERFCTR_STALL_ISIDE = 0x56,
79 ARMV7_PERFCTR_L2_CACH_MISS = 0x44,
80 ARMV7_PERFCTR_AXI_READ_CYCLES = 0x45,
81 ARMV7_PERFCTR_AXI_WRITE_CYCLES = 0x46,
82 ARMV7_PERFCTR_MEMORY_REPLAY = 0x47,
83 ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY = 0x48,
84 ARMV7_PERFCTR_L1_DATA_MISS = 0x49,
85 ARMV7_PERFCTR_L1_INST_MISS = 0x4A,
86 ARMV7_PERFCTR_L1_DATA_COLORING = 0x4B,
87 ARMV7_PERFCTR_L1_NEON_DATA = 0x4C,
88 ARMV7_PERFCTR_L1_NEON_CACH_DATA = 0x4D,
89 ARMV7_PERFCTR_L2_NEON = 0x4E,
90 ARMV7_PERFCTR_L2_NEON_HIT = 0x4F,
91 ARMV7_PERFCTR_L1_INST = 0x50,
92 ARMV7_PERFCTR_PC_RETURN_MIS_PRED = 0x51,
93 ARMV7_PERFCTR_PC_BRANCH_FAILED = 0x52,
94 ARMV7_PERFCTR_PC_BRANCH_TAKEN = 0x53,
95 ARMV7_PERFCTR_PC_BRANCH_EXECUTED = 0x54,
96 ARMV7_PERFCTR_OP_EXECUTED = 0x55,
97 ARMV7_PERFCTR_CYCLES_INST_STALL = 0x56,
98 ARMV7_PERFCTR_CYCLES_INST = 0x57,
99 ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL = 0x58,
100 ARMV7_PERFCTR_CYCLES_NEON_INST_STALL = 0x59,
101 ARMV7_PERFCTR_NEON_CYCLES = 0x5A,
102
103 ARMV7_PERFCTR_PMU0_EVENTS = 0x70,
104 ARMV7_PERFCTR_PMU1_EVENTS = 0x71,
105 ARMV7_PERFCTR_PMU_EVENTS = 0x72,
106}; 81};
107 82
108/* ARMv7 Cortex-A9 specific event types */ 83/* ARMv7 Cortex-A9 specific event types */
109enum armv7_a9_perf_types { 84enum armv7_a9_perf_types {
110 ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC = 0x40, 85 ARMV7_A9_PERFCTR_INSTR_CORE_RENAME = 0x68,
111 ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC = 0x41, 86 ARMV7_A9_PERFCTR_STALL_ICACHE = 0x60,
112 ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC = 0x42, 87 ARMV7_A9_PERFCTR_STALL_DISPATCH = 0x66,
113
114 ARMV7_PERFCTR_COHERENT_LINE_MISS = 0x50,
115 ARMV7_PERFCTR_COHERENT_LINE_HIT = 0x51,
116
117 ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES = 0x60,
118 ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES = 0x61,
119 ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
120 ARMV7_PERFCTR_STREX_EXECUTED_PASSED = 0x63,
121 ARMV7_PERFCTR_STREX_EXECUTED_FAILED = 0x64,
122 ARMV7_PERFCTR_DATA_EVICTION = 0x65,
123 ARMV7_PERFCTR_ISSUE_STAGE_NO_INST = 0x66,
124 ARMV7_PERFCTR_ISSUE_STAGE_EMPTY = 0x67,
125 ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE = 0x68,
126
127 ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
128
129 ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST = 0x70,
130 ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
131 ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST = 0x72,
132 ARMV7_PERFCTR_FP_EXECUTED_INST = 0x73,
133 ARMV7_PERFCTR_NEON_EXECUTED_INST = 0x74,
134
135 ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
136 ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES = 0x81,
137 ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES = 0x82,
138 ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES = 0x83,
139 ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES = 0x84,
140 ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES = 0x85,
141 ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES = 0x86,
142
143 ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES = 0x8A,
144 ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
145
146 ARMV7_PERFCTR_ISB_INST = 0x90,
147 ARMV7_PERFCTR_DSB_INST = 0x91,
148 ARMV7_PERFCTR_DMB_INST = 0x92,
149 ARMV7_PERFCTR_EXT_INTERRUPTS = 0x93,
150
151 ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED = 0xA0,
152 ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED = 0xA1,
153 ARMV7_PERFCTR_PLE_FIFO_FLUSH = 0xA2,
154 ARMV7_PERFCTR_PLE_RQST_COMPLETED = 0xA3,
155 ARMV7_PERFCTR_PLE_FIFO_OVERFLOW = 0xA4,
156 ARMV7_PERFCTR_PLE_RQST_PROG = 0xA5
157}; 88};
158 89
159/* ARMv7 Cortex-A5 specific event types */ 90/* ARMv7 Cortex-A5 specific event types */
160enum armv7_a5_perf_types { 91enum armv7_a5_perf_types {
161 ARMV7_PERFCTR_IRQ_TAKEN = 0x86, 92 ARMV7_A5_PERFCTR_PREFETCH_LINEFILL = 0xc2,
162 ARMV7_PERFCTR_FIQ_TAKEN = 0x87, 93 ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP = 0xc3,
163
164 ARMV7_PERFCTR_EXT_MEM_RQST = 0xc0,
165 ARMV7_PERFCTR_NC_EXT_MEM_RQST = 0xc1,
166 ARMV7_PERFCTR_PREFETCH_LINEFILL = 0xc2,
167 ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP = 0xc3,
168 ARMV7_PERFCTR_ENTER_READ_ALLOC = 0xc4,
169 ARMV7_PERFCTR_READ_ALLOC = 0xc5,
170
171 ARMV7_PERFCTR_STALL_SB_FULL = 0xc9,
172}; 94};
173 95
174/* ARMv7 Cortex-A15 specific event types */ 96/* ARMv7 Cortex-A15 specific event types */
175enum armv7_a15_perf_types { 97enum armv7_a15_perf_types {
176 ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS = 0x40, 98 ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ = 0x40,
177 ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS = 0x41, 99 ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE = 0x41,
178 ARMV7_PERFCTR_L1_DCACHE_READ_REFILL = 0x42, 100 ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ = 0x42,
179 ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL = 0x43, 101 ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE = 0x43,
180 102
181 ARMV7_PERFCTR_L1_DTLB_READ_REFILL = 0x4C, 103 ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ = 0x4C,
182 ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL = 0x4D, 104 ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE = 0x4D,
183 105
184 ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS = 0x50, 106 ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ = 0x50,
185 ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS = 0x51, 107 ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE = 0x51,
186 ARMV7_PERFCTR_L2_DCACHE_READ_REFILL = 0x52, 108 ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ = 0x52,
187 ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL = 0x53, 109 ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE = 0x53,
188 110
189 ARMV7_PERFCTR_SPEC_PC_WRITE = 0x76, 111 ARMV7_A15_PERFCTR_PC_WRITE_SPEC = 0x76,
190}; 112};
191 113
192/* 114/*
@@ -197,13 +119,15 @@ enum armv7_a15_perf_types {
197 * accesses/misses in hardware. 119 * accesses/misses in hardware.
198 */ 120 */
199static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = { 121static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
200 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 122 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
201 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 123 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
202 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, 124 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
203 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, 125 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
204 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 126 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
205 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 127 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
206 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 128 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
129 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE,
130 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
207}; 131};
208 132
209static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 133static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -217,12 +141,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
217 * combined. 141 * combined.
218 */ 142 */
219 [C(OP_READ)] = { 143 [C(OP_READ)] = {
220 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, 144 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
221 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, 145 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
222 }, 146 },
223 [C(OP_WRITE)] = { 147 [C(OP_WRITE)] = {
224 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, 148 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
225 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, 149 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
226 }, 150 },
227 [C(OP_PREFETCH)] = { 151 [C(OP_PREFETCH)] = {
228 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 152 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -231,12 +155,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
231 }, 155 },
232 [C(L1I)] = { 156 [C(L1I)] = {
233 [C(OP_READ)] = { 157 [C(OP_READ)] = {
234 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST, 158 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
235 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS, 159 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
236 }, 160 },
237 [C(OP_WRITE)] = { 161 [C(OP_WRITE)] = {
238 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST, 162 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
239 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS, 163 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
240 }, 164 },
241 [C(OP_PREFETCH)] = { 165 [C(OP_PREFETCH)] = {
242 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 166 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -245,12 +169,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
245 }, 169 },
246 [C(LL)] = { 170 [C(LL)] = {
247 [C(OP_READ)] = { 171 [C(OP_READ)] = {
248 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS, 172 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
249 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS, 173 [C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
250 }, 174 },
251 [C(OP_WRITE)] = { 175 [C(OP_WRITE)] = {
252 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS, 176 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
253 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS, 177 [C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
254 }, 178 },
255 [C(OP_PREFETCH)] = { 179 [C(OP_PREFETCH)] = {
256 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 180 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -274,11 +198,11 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
274 [C(ITLB)] = { 198 [C(ITLB)] = {
275 [C(OP_READ)] = { 199 [C(OP_READ)] = {
276 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 200 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
277 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 201 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
278 }, 202 },
279 [C(OP_WRITE)] = { 203 [C(OP_WRITE)] = {
280 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 204 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
281 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 205 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
282 }, 206 },
283 [C(OP_PREFETCH)] = { 207 [C(OP_PREFETCH)] = {
284 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 208 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -287,14 +211,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
287 }, 211 },
288 [C(BPU)] = { 212 [C(BPU)] = {
289 [C(OP_READ)] = { 213 [C(OP_READ)] = {
290 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, 214 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
291 [C(RESULT_MISS)] 215 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
292 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
293 }, 216 },
294 [C(OP_WRITE)] = { 217 [C(OP_WRITE)] = {
295 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, 218 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
296 [C(RESULT_MISS)] 219 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
297 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
298 }, 220 },
299 [C(OP_PREFETCH)] = { 221 [C(OP_PREFETCH)] = {
300 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 222 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -321,14 +243,15 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
321 * Cortex-A9 HW events mapping 243 * Cortex-A9 HW events mapping
322 */ 244 */
323static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = { 245static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
324 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 246 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
325 [PERF_COUNT_HW_INSTRUCTIONS] = 247 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME,
326 ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE, 248 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
327 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_DCACHE_ACCESS, 249 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
328 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_DCACHE_REFILL, 250 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
329 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 251 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
330 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 252 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
331 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 253 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE,
254 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV7_A9_PERFCTR_STALL_DISPATCH,
332}; 255};
333 256
334static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 257static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -342,12 +265,12 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
342 * combined. 265 * combined.
343 */ 266 */
344 [C(OP_READ)] = { 267 [C(OP_READ)] = {
345 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, 268 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
346 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, 269 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
347 }, 270 },
348 [C(OP_WRITE)] = { 271 [C(OP_WRITE)] = {
349 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, 272 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
350 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, 273 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
351 }, 274 },
352 [C(OP_PREFETCH)] = { 275 [C(OP_PREFETCH)] = {
353 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 276 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -357,11 +280,11 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
357 [C(L1I)] = { 280 [C(L1I)] = {
358 [C(OP_READ)] = { 281 [C(OP_READ)] = {
359 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 282 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
360 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, 283 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
361 }, 284 },
362 [C(OP_WRITE)] = { 285 [C(OP_WRITE)] = {
363 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 286 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
364 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, 287 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
365 }, 288 },
366 [C(OP_PREFETCH)] = { 289 [C(OP_PREFETCH)] = {
367 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 290 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -399,11 +322,11 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
399 [C(ITLB)] = { 322 [C(ITLB)] = {
400 [C(OP_READ)] = { 323 [C(OP_READ)] = {
401 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 324 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
402 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 325 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
403 }, 326 },
404 [C(OP_WRITE)] = { 327 [C(OP_WRITE)] = {
405 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 328 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
406 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 329 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
407 }, 330 },
408 [C(OP_PREFETCH)] = { 331 [C(OP_PREFETCH)] = {
409 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 332 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -412,14 +335,12 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
412 }, 335 },
413 [C(BPU)] = { 336 [C(BPU)] = {
414 [C(OP_READ)] = { 337 [C(OP_READ)] = {
415 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, 338 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
416 [C(RESULT_MISS)] 339 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
417 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
418 }, 340 },
419 [C(OP_WRITE)] = { 341 [C(OP_WRITE)] = {
420 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, 342 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
421 [C(RESULT_MISS)] 343 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
422 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
423 }, 344 },
424 [C(OP_PREFETCH)] = { 345 [C(OP_PREFETCH)] = {
425 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 346 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -446,13 +367,15 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
446 * Cortex-A5 HW events mapping 367 * Cortex-A5 HW events mapping
447 */ 368 */
448static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = { 369static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {
449 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 370 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
450 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 371 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
451 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, 372 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
452 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, 373 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
453 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 374 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
454 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 375 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
455 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, 376 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
377 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
378 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
456}; 379};
457 380
458static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 381static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -460,42 +383,34 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
460 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 383 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
461 [C(L1D)] = { 384 [C(L1D)] = {
462 [C(OP_READ)] = { 385 [C(OP_READ)] = {
463 [C(RESULT_ACCESS)] 386 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
464 = ARMV7_PERFCTR_DCACHE_ACCESS, 387 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
465 [C(RESULT_MISS)]
466 = ARMV7_PERFCTR_DCACHE_REFILL,
467 }, 388 },
468 [C(OP_WRITE)] = { 389 [C(OP_WRITE)] = {
469 [C(RESULT_ACCESS)] 390 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
470 = ARMV7_PERFCTR_DCACHE_ACCESS, 391 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
471 [C(RESULT_MISS)]
472 = ARMV7_PERFCTR_DCACHE_REFILL,
473 }, 392 },
474 [C(OP_PREFETCH)] = { 393 [C(OP_PREFETCH)] = {
475 [C(RESULT_ACCESS)] 394 [C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
476 = ARMV7_PERFCTR_PREFETCH_LINEFILL, 395 [C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
477 [C(RESULT_MISS)]
478 = ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
479 }, 396 },
480 }, 397 },
481 [C(L1I)] = { 398 [C(L1I)] = {
482 [C(OP_READ)] = { 399 [C(OP_READ)] = {
483 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 400 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
484 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, 401 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
485 }, 402 },
486 [C(OP_WRITE)] = { 403 [C(OP_WRITE)] = {
487 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 404 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
488 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, 405 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
489 }, 406 },
490 /* 407 /*
491 * The prefetch counters don't differentiate between the I 408 * The prefetch counters don't differentiate between the I
492 * side and the D side. 409 * side and the D side.
493 */ 410 */
494 [C(OP_PREFETCH)] = { 411 [C(OP_PREFETCH)] = {
495 [C(RESULT_ACCESS)] 412 [C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
496 = ARMV7_PERFCTR_PREFETCH_LINEFILL, 413 [C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
497 [C(RESULT_MISS)]
498 = ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
499 }, 414 },
500 }, 415 },
501 [C(LL)] = { 416 [C(LL)] = {
@@ -529,11 +444,11 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
529 [C(ITLB)] = { 444 [C(ITLB)] = {
530 [C(OP_READ)] = { 445 [C(OP_READ)] = {
531 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 446 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
532 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 447 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
533 }, 448 },
534 [C(OP_WRITE)] = { 449 [C(OP_WRITE)] = {
535 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 450 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
536 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 451 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
537 }, 452 },
538 [C(OP_PREFETCH)] = { 453 [C(OP_PREFETCH)] = {
539 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 454 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -543,13 +458,11 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
543 [C(BPU)] = { 458 [C(BPU)] = {
544 [C(OP_READ)] = { 459 [C(OP_READ)] = {
545 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 460 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
546 [C(RESULT_MISS)] 461 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
547 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
548 }, 462 },
549 [C(OP_WRITE)] = { 463 [C(OP_WRITE)] = {
550 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 464 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
551 [C(RESULT_MISS)] 465 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
552 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
553 }, 466 },
554 [C(OP_PREFETCH)] = { 467 [C(OP_PREFETCH)] = {
555 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 468 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -562,13 +475,15 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
562 * Cortex-A15 HW events mapping 475 * Cortex-A15 HW events mapping
563 */ 476 */
564static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = { 477static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {
565 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 478 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
566 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 479 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
567 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, 480 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
568 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, 481 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
569 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_SPEC_PC_WRITE, 482 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC,
570 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 483 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
571 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, 484 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES,
485 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
486 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
572}; 487};
573 488
574static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 489static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -576,16 +491,12 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
576 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 491 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
577 [C(L1D)] = { 492 [C(L1D)] = {
578 [C(OP_READ)] = { 493 [C(OP_READ)] = {
579 [C(RESULT_ACCESS)] 494 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ,
580 = ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS, 495 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ,
581 [C(RESULT_MISS)]
582 = ARMV7_PERFCTR_L1_DCACHE_READ_REFILL,
583 }, 496 },
584 [C(OP_WRITE)] = { 497 [C(OP_WRITE)] = {
585 [C(RESULT_ACCESS)] 498 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE,
586 = ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS, 499 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE,
587 [C(RESULT_MISS)]
588 = ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL,
589 }, 500 },
590 [C(OP_PREFETCH)] = { 501 [C(OP_PREFETCH)] = {
591 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 502 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -601,11 +512,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
601 */ 512 */
602 [C(OP_READ)] = { 513 [C(OP_READ)] = {
603 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 514 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
604 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, 515 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
605 }, 516 },
606 [C(OP_WRITE)] = { 517 [C(OP_WRITE)] = {
607 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 518 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
608 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, 519 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
609 }, 520 },
610 [C(OP_PREFETCH)] = { 521 [C(OP_PREFETCH)] = {
611 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 522 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -614,16 +525,12 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
614 }, 525 },
615 [C(LL)] = { 526 [C(LL)] = {
616 [C(OP_READ)] = { 527 [C(OP_READ)] = {
617 [C(RESULT_ACCESS)] 528 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,
618 = ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS, 529 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,
619 [C(RESULT_MISS)]
620 = ARMV7_PERFCTR_L2_DCACHE_READ_REFILL,
621 }, 530 },
622 [C(OP_WRITE)] = { 531 [C(OP_WRITE)] = {
623 [C(RESULT_ACCESS)] 532 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,
624 = ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS, 533 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,
625 [C(RESULT_MISS)]
626 = ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL,
627 }, 534 },
628 [C(OP_PREFETCH)] = { 535 [C(OP_PREFETCH)] = {
629 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 536 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -633,13 +540,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
633 [C(DTLB)] = { 540 [C(DTLB)] = {
634 [C(OP_READ)] = { 541 [C(OP_READ)] = {
635 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 542 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
636 [C(RESULT_MISS)] 543 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,
637 = ARMV7_PERFCTR_L1_DTLB_READ_REFILL,
638 }, 544 },
639 [C(OP_WRITE)] = { 545 [C(OP_WRITE)] = {
640 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 546 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
641 [C(RESULT_MISS)] 547 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,
642 = ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL,
643 }, 548 },
644 [C(OP_PREFETCH)] = { 549 [C(OP_PREFETCH)] = {
645 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 550 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -649,11 +554,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
649 [C(ITLB)] = { 554 [C(ITLB)] = {
650 [C(OP_READ)] = { 555 [C(OP_READ)] = {
651 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 556 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
652 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 557 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
653 }, 558 },
654 [C(OP_WRITE)] = { 559 [C(OP_WRITE)] = {
655 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 560 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
656 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 561 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
657 }, 562 },
658 [C(OP_PREFETCH)] = { 563 [C(OP_PREFETCH)] = {
659 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 564 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -663,13 +568,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
663 [C(BPU)] = { 568 [C(BPU)] = {
664 [C(OP_READ)] = { 569 [C(OP_READ)] = {
665 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 570 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
666 [C(RESULT_MISS)] 571 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
667 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
668 }, 572 },
669 [C(OP_WRITE)] = { 573 [C(OP_WRITE)] = {
670 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 574 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
671 [C(RESULT_MISS)] 575 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
672 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
673 }, 576 },
674 [C(OP_PREFETCH)] = { 577 [C(OP_PREFETCH)] = {
675 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 578 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index e0cca10a8411..3b99d8269829 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -48,13 +48,15 @@ enum xscale_counters {
48}; 48};
49 49
50static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = { 50static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
51 [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT, 51 [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT,
52 [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION, 52 [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION,
53 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, 53 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
54 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, 54 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
55 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH, 55 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
56 [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS, 56 [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS,
57 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, 57 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
58 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XSCALE_PERFCTR_ICACHE_NO_DELIVER,
59 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
58}; 60};
59 61
60static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 62static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
index 2c3407ee8576..2334bf8a650a 100644
--- a/arch/arm/kernel/pmu.c
+++ b/arch/arm/kernel/pmu.c
@@ -33,3 +33,4 @@ release_pmu(enum arm_pmu_type type)
33{ 33{
34 clear_bit_unlock(type, pmu_lock); 34 clear_bit_unlock(type, pmu_lock);
35} 35}
36EXPORT_SYMBOL_GPL(release_pmu);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 1e8b3e2de7a3..eeb3e16c6046 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -191,6 +191,9 @@ void cpu_idle(void)
191#endif 191#endif
192 192
193 local_irq_disable(); 193 local_irq_disable();
194#ifdef CONFIG_PL310_ERRATA_769419
195 wmb();
196#endif
194 if (hlt_counter) { 197 if (hlt_counter) {
195 local_irq_enable(); 198 local_irq_enable();
196 cpu_relax(); 199 cpu_relax();
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index a753880e984b..6c2b0db5d1e9 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -461,8 +461,10 @@ static void __init setup_processor(void)
461 cpu_name, read_cpuid_id(), read_cpuid_id() & 15, 461 cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
462 proc_arch[cpu_architecture()], cr_alignment); 462 proc_arch[cpu_architecture()], cr_alignment);
463 463
464 sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS); 464 snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
465 sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS); 465 list->arch_name, ENDIANNESS);
466 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
467 list->elf_name, ENDIANNESS);
466 elf_hwcap = list->elf_hwcap; 468 elf_hwcap = list->elf_hwcap;
467#ifndef CONFIG_ARM_THUMB 469#ifndef CONFIG_ARM_THUMB
468 elf_hwcap &= ~HWCAP_THUMB; 470 elf_hwcap &= ~HWCAP_THUMB;
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index 1040c00405d0..8200deaa14f6 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -43,7 +43,7 @@
43 43
44struct cputopo_arm cpu_topology[NR_CPUS]; 44struct cputopo_arm cpu_topology[NR_CPUS];
45 45
46const struct cpumask *cpu_coregroup_mask(unsigned int cpu) 46const struct cpumask *cpu_coregroup_mask(int cpu)
47{ 47{
48 return &cpu_topology[cpu].core_sibling; 48 return &cpu_topology[cpu].core_sibling;
49} 49}
diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
index 10d868a5a481..d6408d1ee543 100644
--- a/arch/arm/lib/bitops.h
+++ b/arch/arm/lib/bitops.h
@@ -1,5 +1,9 @@
1#include <asm/unwind.h>
2
1#if __LINUX_ARM_ARCH__ >= 6 3#if __LINUX_ARM_ARCH__ >= 6
2 .macro bitop, instr 4 .macro bitop, name, instr
5ENTRY( \name )
6UNWIND( .fnstart )
3 ands ip, r1, #3 7 ands ip, r1, #3
4 strneb r1, [ip] @ assert word-aligned 8 strneb r1, [ip] @ assert word-aligned
5 mov r2, #1 9 mov r2, #1
@@ -13,9 +17,13 @@
13 cmp r0, #0 17 cmp r0, #0
14 bne 1b 18 bne 1b
15 bx lr 19 bx lr
20UNWIND( .fnend )
21ENDPROC(\name )
16 .endm 22 .endm
17 23
18 .macro testop, instr, store 24 .macro testop, name, instr, store
25ENTRY( \name )
26UNWIND( .fnstart )
19 ands ip, r1, #3 27 ands ip, r1, #3
20 strneb r1, [ip] @ assert word-aligned 28 strneb r1, [ip] @ assert word-aligned
21 mov r2, #1 29 mov r2, #1
@@ -34,9 +42,13 @@
34 cmp r0, #0 42 cmp r0, #0
35 movne r0, #1 43 movne r0, #1
362: bx lr 442: bx lr
45UNWIND( .fnend )
46ENDPROC(\name )
37 .endm 47 .endm
38#else 48#else
39 .macro bitop, instr 49 .macro bitop, name, instr
50ENTRY( \name )
51UNWIND( .fnstart )
40 ands ip, r1, #3 52 ands ip, r1, #3
41 strneb r1, [ip] @ assert word-aligned 53 strneb r1, [ip] @ assert word-aligned
42 and r2, r0, #31 54 and r2, r0, #31
@@ -49,6 +61,8 @@
49 str r2, [r1, r0, lsl #2] 61 str r2, [r1, r0, lsl #2]
50 restore_irqs ip 62 restore_irqs ip
51 mov pc, lr 63 mov pc, lr
64UNWIND( .fnend )
65ENDPROC(\name )
52 .endm 66 .endm
53 67
54/** 68/**
@@ -59,7 +73,9 @@
59 * Note: we can trivially conditionalise the store instruction 73 * Note: we can trivially conditionalise the store instruction
60 * to avoid dirtying the data cache. 74 * to avoid dirtying the data cache.
61 */ 75 */
62 .macro testop, instr, store 76 .macro testop, name, instr, store
77ENTRY( \name )
78UNWIND( .fnstart )
63 ands ip, r1, #3 79 ands ip, r1, #3
64 strneb r1, [ip] @ assert word-aligned 80 strneb r1, [ip] @ assert word-aligned
65 and r3, r0, #31 81 and r3, r0, #31
@@ -73,5 +89,7 @@
73 moveq r0, #0 89 moveq r0, #0
74 restore_irqs ip 90 restore_irqs ip
75 mov pc, lr 91 mov pc, lr
92UNWIND( .fnend )
93ENDPROC(\name )
76 .endm 94 .endm
77#endif 95#endif
diff --git a/arch/arm/lib/changebit.S b/arch/arm/lib/changebit.S
index 68ed5b62e839..f4027862172f 100644
--- a/arch/arm/lib/changebit.S
+++ b/arch/arm/lib/changebit.S
@@ -12,6 +12,4 @@
12#include "bitops.h" 12#include "bitops.h"
13 .text 13 .text
14 14
15ENTRY(_change_bit) 15bitop _change_bit, eor
16 bitop eor
17ENDPROC(_change_bit)
diff --git a/arch/arm/lib/clearbit.S b/arch/arm/lib/clearbit.S
index 4c04c3b51eeb..f6b75fb64d30 100644
--- a/arch/arm/lib/clearbit.S
+++ b/arch/arm/lib/clearbit.S
@@ -12,6 +12,4 @@
12#include "bitops.h" 12#include "bitops.h"
13 .text 13 .text
14 14
15ENTRY(_clear_bit) 15bitop _clear_bit, bic
16 bitop bic
17ENDPROC(_clear_bit)
diff --git a/arch/arm/lib/setbit.S b/arch/arm/lib/setbit.S
index bbee5c66a23e..618fedae4b37 100644
--- a/arch/arm/lib/setbit.S
+++ b/arch/arm/lib/setbit.S
@@ -12,6 +12,4 @@
12#include "bitops.h" 12#include "bitops.h"
13 .text 13 .text
14 14
15ENTRY(_set_bit) 15bitop _set_bit, orr
16 bitop orr
17ENDPROC(_set_bit)
diff --git a/arch/arm/lib/testchangebit.S b/arch/arm/lib/testchangebit.S
index 15a4d431f229..4becdc3a59cb 100644
--- a/arch/arm/lib/testchangebit.S
+++ b/arch/arm/lib/testchangebit.S
@@ -12,6 +12,4 @@
12#include "bitops.h" 12#include "bitops.h"
13 .text 13 .text
14 14
15ENTRY(_test_and_change_bit) 15testop _test_and_change_bit, eor, str
16 testop eor, str
17ENDPROC(_test_and_change_bit)
diff --git a/arch/arm/lib/testclearbit.S b/arch/arm/lib/testclearbit.S
index 521b66b5b95d..918841dcce7a 100644
--- a/arch/arm/lib/testclearbit.S
+++ b/arch/arm/lib/testclearbit.S
@@ -12,6 +12,4 @@
12#include "bitops.h" 12#include "bitops.h"
13 .text 13 .text
14 14
15ENTRY(_test_and_clear_bit) 15testop _test_and_clear_bit, bicne, strne
16 testop bicne, strne
17ENDPROC(_test_and_clear_bit)
diff --git a/arch/arm/lib/testsetbit.S b/arch/arm/lib/testsetbit.S
index 1c98cc2185bb..8d1b2fe9e487 100644
--- a/arch/arm/lib/testsetbit.S
+++ b/arch/arm/lib/testsetbit.S
@@ -12,6 +12,4 @@
12#include "bitops.h" 12#include "bitops.h"
13 .text 13 .text
14 14
15ENTRY(_test_and_set_bit) 15testop _test_and_set_bit, orreq, streq
16 testop orreq, streq
17ENDPROC(_test_and_set_bit)
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 43eadbcc29ed..430da120a297 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -235,7 +235,7 @@ void __init bcmring_init_timer(void)
235 */ 235 */
236 bcmring_clocksource_init(); 236 bcmring_clocksource_init();
237 237
238 sp804_clockevents_register(TIMER0_VA_BASE, IRQ_TIMER0, "timer0"); 238 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
239} 239}
240 240
241struct sys_timer bcmring_timer = { 241struct sys_timer bcmring_timer = {
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
index b52b8de91bde..f4d4d6d174d0 100644
--- a/arch/arm/mach-bcmring/dma.c
+++ b/arch/arm/mach-bcmring/dma.c
@@ -36,6 +36,7 @@
36#include <linux/mm.h> 36#include <linux/mm.h>
37#include <linux/pfn.h> 37#include <linux/pfn.h>
38#include <linux/atomic.h> 38#include <linux/atomic.h>
39#include <linux/sched.h>
39#include <mach/dma.h> 40#include <mach/dma.h>
40 41
41/* I don't quite understand why dc4 fails when this is set to 1 and DMA is enabled */ 42/* I don't quite understand why dc4 fails when this is set to 1 and DMA is enabled */
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 35f6502144ae..4ebb382c5979 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -12,6 +12,8 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/cpuidle.h> 13#include <linux/cpuidle.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/export.h>
16#include <linux/time.h>
15 17
16#include <asm/proc-fns.h> 18#include <asm/proc-fns.h>
17 19
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 89bdf0039f7b..7266dd510f1a 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -22,6 +22,7 @@
22#include <linux/of_irq.h> 22#include <linux/of_irq.h>
23#include <linux/of_platform.h> 23#include <linux/of_platform.h>
24#include <linux/of_address.h> 24#include <linux/of_address.h>
25#include <linux/smp.h>
25 26
26#include <asm/cacheflush.h> 27#include <asm/cacheflush.h>
27#include <asm/unified.h> 28#include <asm/unified.h>
@@ -72,6 +73,9 @@ static void __init highbank_map_io(void)
72 73
73void highbank_set_cpu_jump(int cpu, void *jump_addr) 74void highbank_set_cpu_jump(int cpu, void *jump_addr)
74{ 75{
76#ifdef CONFIG_SMP
77 cpu = cpu_logical_map(cpu);
78#endif
75 writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu)); 79 writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu));
76 __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16); 80 __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
77 outer_clean_range(HB_JUMP_TABLE_PHYS(cpu), 81 outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 5f7f9c2a34ae..c44aa974e79c 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -10,11 +10,6 @@ config HAVE_IMX_MMDC
10config HAVE_IMX_SRC 10config HAVE_IMX_SRC
11 bool 11 bool
12 12
13#
14# ARCH_MX31 and ARCH_MX35 are left for compatibility
15# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
16# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
17# more sensible) names are used: SOC_IMX31 and SOC_IMX35
18config ARCH_MX1 13config ARCH_MX1
19 bool 14 bool
20 15
@@ -27,12 +22,6 @@ config ARCH_MX25
27config MACH_MX27 22config MACH_MX27
28 bool 23 bool
29 24
30config ARCH_MX31
31 bool
32
33config ARCH_MX35
34 bool
35
36config SOC_IMX1 25config SOC_IMX1
37 bool 26 bool
38 select ARCH_MX1 27 select ARCH_MX1
@@ -72,7 +61,6 @@ config SOC_IMX31
72 select CPU_V6 61 select CPU_V6
73 select IMX_HAVE_PLATFORM_MXC_RNGA 62 select IMX_HAVE_PLATFORM_MXC_RNGA
74 select ARCH_MXC_AUDMUX_V2 63 select ARCH_MXC_AUDMUX_V2
75 select ARCH_MX31
76 select MXC_AVIC 64 select MXC_AVIC
77 select SMP_ON_UP if SMP 65 select SMP_ON_UP if SMP
78 66
@@ -82,7 +70,6 @@ config SOC_IMX35
82 select ARCH_MXC_IOMUX_V3 70 select ARCH_MXC_IOMUX_V3
83 select ARCH_MXC_AUDMUX_V2 71 select ARCH_MXC_AUDMUX_V2
84 select HAVE_EPIT 72 select HAVE_EPIT
85 select ARCH_MX35
86 select MXC_AVIC 73 select MXC_AVIC
87 select SMP_ON_UP if SMP 74 select SMP_ON_UP if SMP
88 75
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
index 613a1b993bff..039a7abb165a 100644
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -1953,14 +1953,17 @@ static struct map_desc imx6q_clock_desc[] = {
1953 imx_map_entry(MX6Q, ANATOP, MT_DEVICE), 1953 imx_map_entry(MX6Q, ANATOP, MT_DEVICE),
1954}; 1954};
1955 1955
1956void __init imx6q_clock_map_io(void)
1957{
1958 iotable_init(imx6q_clock_desc, ARRAY_SIZE(imx6q_clock_desc));
1959}
1960
1956int __init mx6q_clocks_init(void) 1961int __init mx6q_clocks_init(void)
1957{ 1962{
1958 struct device_node *np; 1963 struct device_node *np;
1959 void __iomem *base; 1964 void __iomem *base;
1960 int i, irq; 1965 int i, irq;
1961 1966
1962 iotable_init(imx6q_clock_desc, ARRAY_SIZE(imx6q_clock_desc));
1963
1964 /* retrieve the freqency of fixed clocks from device tree */ 1967 /* retrieve the freqency of fixed clocks from device tree */
1965 for_each_compatible_node(np, NULL, "fixed-clock") { 1968 for_each_compatible_node(np, NULL, "fixed-clock") {
1966 u32 rate; 1969 u32 rate;
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 8bf5fa349484..9cd860a27af5 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -34,6 +34,7 @@ static void __init imx6q_map_io(void)
34{ 34{
35 imx_lluart_map_io(); 35 imx_lluart_map_io();
36 imx_scu_map_io(); 36 imx_scu_map_io();
37 imx6q_clock_map_io();
37} 38}
38 39
39static void __init imx6q_gpio_add_irq_domain(struct device_node *np, 40static void __init imx6q_gpio_add_irq_domain(struct device_node *np,
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 9f0e82ec3398..31807d2a8b7b 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -33,29 +33,32 @@
33static void imx3_idle(void) 33static void imx3_idle(void)
34{ 34{
35 unsigned long reg = 0; 35 unsigned long reg = 0;
36 __asm__ __volatile__( 36
37 /* disable I and D cache */ 37 if (!need_resched())
38 "mrc p15, 0, %0, c1, c0, 0\n" 38 __asm__ __volatile__(
39 "bic %0, %0, #0x00001000\n" 39 /* disable I and D cache */
40 "bic %0, %0, #0x00000004\n" 40 "mrc p15, 0, %0, c1, c0, 0\n"
41 "mcr p15, 0, %0, c1, c0, 0\n" 41 "bic %0, %0, #0x00001000\n"
42 /* invalidate I cache */ 42 "bic %0, %0, #0x00000004\n"
43 "mov %0, #0\n" 43 "mcr p15, 0, %0, c1, c0, 0\n"
44 "mcr p15, 0, %0, c7, c5, 0\n" 44 /* invalidate I cache */
45 /* clear and invalidate D cache */ 45 "mov %0, #0\n"
46 "mov %0, #0\n" 46 "mcr p15, 0, %0, c7, c5, 0\n"
47 "mcr p15, 0, %0, c7, c14, 0\n" 47 /* clear and invalidate D cache */
48 /* WFI */ 48 "mov %0, #0\n"
49 "mov %0, #0\n" 49 "mcr p15, 0, %0, c7, c14, 0\n"
50 "mcr p15, 0, %0, c7, c0, 4\n" 50 /* WFI */
51 "nop\n" "nop\n" "nop\n" "nop\n" 51 "mov %0, #0\n"
52 "nop\n" "nop\n" "nop\n" 52 "mcr p15, 0, %0, c7, c0, 4\n"
53 /* enable I and D cache */ 53 "nop\n" "nop\n" "nop\n" "nop\n"
54 "mrc p15, 0, %0, c1, c0, 0\n" 54 "nop\n" "nop\n" "nop\n"
55 "orr %0, %0, #0x00001000\n" 55 /* enable I and D cache */
56 "orr %0, %0, #0x00000004\n" 56 "mrc p15, 0, %0, c1, c0, 0\n"
57 "mcr p15, 0, %0, c1, c0, 0\n" 57 "orr %0, %0, #0x00001000\n"
58 : "=r" (reg)); 58 "orr %0, %0, #0x00000004\n"
59 "mcr p15, 0, %0, c1, c0, 0\n"
60 : "=r" (reg));
61 local_irq_enable();
59} 62}
60 63
61static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size, 64static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
@@ -108,6 +111,7 @@ void imx3_init_l2x0(void)
108 l2x0_init(l2x0_base, 0x00030024, 0x00000000); 111 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
109} 112}
110 113
114#ifdef CONFIG_SOC_IMX31
111static struct map_desc mx31_io_desc[] __initdata = { 115static struct map_desc mx31_io_desc[] __initdata = {
112 imx_map_entry(MX31, X_MEMC, MT_DEVICE), 116 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
113 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), 117 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
@@ -126,33 +130,11 @@ void __init mx31_map_io(void)
126 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); 130 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
127} 131}
128 132
129static struct map_desc mx35_io_desc[] __initdata = {
130 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
131 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
132 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
133 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
134 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
135};
136
137void __init mx35_map_io(void)
138{
139 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
140}
141
142void __init imx31_init_early(void) 133void __init imx31_init_early(void)
143{ 134{
144 mxc_set_cpu_type(MXC_CPU_MX31); 135 mxc_set_cpu_type(MXC_CPU_MX31);
145 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); 136 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
146 imx_idle = imx3_idle; 137 pm_idle = imx3_idle;
147 imx_ioremap = imx3_ioremap;
148}
149
150void __init imx35_init_early(void)
151{
152 mxc_set_cpu_type(MXC_CPU_MX35);
153 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
154 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
155 imx_idle = imx3_idle;
156 imx_ioremap = imx3_ioremap; 138 imx_ioremap = imx3_ioremap;
157} 139}
158 140
@@ -161,11 +143,6 @@ void __init mx31_init_irq(void)
161 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); 143 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
162} 144}
163 145
164void __init mx35_init_irq(void)
165{
166 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
167}
168
169static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { 146static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
170 .per_2_per_addr = 1677, 147 .per_2_per_addr = 1677,
171}; 148};
@@ -199,6 +176,35 @@ void __init imx31_soc_init(void)
199 176
200 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); 177 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
201} 178}
179#endif /* ifdef CONFIG_SOC_IMX31 */
180
181#ifdef CONFIG_SOC_IMX35
182static struct map_desc mx35_io_desc[] __initdata = {
183 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
184 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
185 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
186 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
187 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
188};
189
190void __init mx35_map_io(void)
191{
192 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
193}
194
195void __init imx35_init_early(void)
196{
197 mxc_set_cpu_type(MXC_CPU_MX35);
198 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
199 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
200 pm_idle = imx3_idle;
201 imx_ioremap = imx3_ioremap;
202}
203
204void __init mx35_init_irq(void)
205{
206 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
207}
202 208
203static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { 209static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
204 .ap_2_ap_addr = 642, 210 .ap_2_ap_addr = 642,
@@ -254,3 +260,4 @@ void __init imx35_soc_init(void)
254 260
255 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); 261 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
256} 262}
263#endif /* ifdef CONFIG_SOC_IMX35 */
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 36cacbd0dcc2..a8e33681b732 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -14,6 +14,7 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/of.h> 15#include <linux/of.h>
16#include <linux/of_address.h> 16#include <linux/of_address.h>
17#include <linux/smp.h>
17#include <asm/unified.h> 18#include <asm/unified.h>
18 19
19#define SRC_SCR 0x000 20#define SRC_SCR 0x000
@@ -23,10 +24,15 @@
23 24
24static void __iomem *src_base; 25static void __iomem *src_base;
25 26
27#ifndef CONFIG_SMP
28#define cpu_logical_map(cpu) 0
29#endif
30
26void imx_enable_cpu(int cpu, bool enable) 31void imx_enable_cpu(int cpu, bool enable)
27{ 32{
28 u32 mask, val; 33 u32 mask, val;
29 34
35 cpu = cpu_logical_map(cpu);
30 mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); 36 mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
31 val = readl_relaxed(src_base + SRC_SCR); 37 val = readl_relaxed(src_base + SRC_SCR);
32 val = enable ? val | mask : val & ~mask; 38 val = enable ? val | mask : val & ~mask;
@@ -35,6 +41,7 @@ void imx_enable_cpu(int cpu, bool enable)
35 41
36void imx_set_cpu_jump(int cpu, void *jump_addr) 42void imx_set_cpu_jump(int cpu, void *jump_addr)
37{ 43{
44 cpu = cpu_logical_map(cpu);
38 writel_relaxed(BSYM(virt_to_phys(jump_addr)), 45 writel_relaxed(BSYM(virt_to_phys(jump_addr)),
39 src_base + SRC_GPR1 + cpu * 8); 46 src_base + SRC_GPR1 + cpu * 8);
40} 47}
diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
index 69156568bc41..4665767a4f79 100644
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -182,7 +182,7 @@ static void __init gplugd_init(void)
182 182
183 /* on-chip devices */ 183 /* on-chip devices */
184 pxa168_add_uart(3); 184 pxa168_add_uart(3);
185 pxa168_add_ssp(0); 185 pxa168_add_ssp(1);
186 pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info)); 186 pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info));
187 187
188 pxa168_add_eth(&gplugd_eth_platform_data); 188 pxa168_add_eth(&gplugd_eth_platform_data);
diff --git a/arch/arm/mach-mmp/include/mach/gpio-pxa.h b/arch/arm/mach-mmp/include/mach/gpio-pxa.h
index d14eeaf16322..99b4ce1b6562 100644
--- a/arch/arm/mach-mmp/include/mach/gpio-pxa.h
+++ b/arch/arm/mach-mmp/include/mach/gpio-pxa.h
@@ -7,7 +7,7 @@
7#define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000) 7#define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000)
8 8
9#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) 9#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
10#define GPIO_REG(x) (GPIO_REGS_VIRT + (x)) 10#define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
11 11
12#define NR_BUILTIN_GPIO IRQ_GPIO_NUM 12#define NR_BUILTIN_GPIO IRQ_GPIO_NUM
13 13
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 5c5328257dca..5e2e7a843860 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -16,7 +16,7 @@
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/module.h> 17#include <linux/module.h>
18#include <mach/hardware.h> 18#include <mach/hardware.h>
19#include <asm/io.h> 19#include <linux/io.h>
20 20
21static int mx5_cpu_rev = -1; 21static int mx5_cpu_rev = -1;
22 22
@@ -67,7 +67,8 @@ static int __init mx51_neon_fixup(void)
67 if (!cpu_is_mx51()) 67 if (!cpu_is_mx51())
68 return 0; 68 return 0;
69 69
70 if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) { 70 if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
71 (elf_hwcap & HWCAP_NEON)) {
71 elf_hwcap &= ~HWCAP_NEON; 72 elf_hwcap &= ~HWCAP_NEON;
72 pr_info("Turning off NEON support, detected broken NEON implementation\n"); 73 pr_info("Turning off NEON support, detected broken NEON implementation\n");
73 } 74 }
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index 26eacc9d0d90..df4a508f240a 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -23,7 +23,9 @@
23 23
24static void imx5_idle(void) 24static void imx5_idle(void)
25{ 25{
26 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); 26 if (!need_resched())
27 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
28 local_irq_enable();
27} 29}
28 30
29/* 31/*
@@ -89,7 +91,7 @@ void __init imx51_init_early(void)
89 mxc_set_cpu_type(MXC_CPU_MX51); 91 mxc_set_cpu_type(MXC_CPU_MX51);
90 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); 92 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
91 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); 93 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
92 imx_idle = imx5_idle; 94 pm_idle = imx5_idle;
93} 95}
94 96
95void __init imx53_init_early(void) 97void __init imx53_init_early(void)
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 229ae3494216..da6e4aad177c 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -404,7 +404,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \
404 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \ 404 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
405 reg &= ~BM_CLKCTRL_##dr##_DIV; \ 405 reg &= ~BM_CLKCTRL_##dr##_DIV; \
406 reg |= div << BP_CLKCTRL_##dr##_DIV; \ 406 reg |= div << BP_CLKCTRL_##dr##_DIV; \
407 if (reg | (1 << clk->enable_shift)) { \ 407 if (reg & (1 << clk->enable_shift)) { \
408 pr_err("%s: clock is gated\n", __func__); \ 408 pr_err("%s: clock is gated\n", __func__); \
409 return -EINVAL; \ 409 return -EINVAL; \
410 } \ 410 } \
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index e0a028161dde..73f287d6429b 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -171,14 +171,6 @@ config MACH_OMAP_GENERIC
171comment "OMAP CPU Speed" 171comment "OMAP CPU Speed"
172 depends on ARCH_OMAP1 172 depends on ARCH_OMAP1
173 173
174config OMAP_CLOCKS_SET_BY_BOOTLOADER
175 bool "OMAP clocks set by bootloader"
176 depends on ARCH_OMAP1
177 help
178 Enable this option to prevent the kernel from overriding the clock
179 frequencies programmed by bootloader for MPU, DSP, MMUs, TC,
180 internal LCD controller and MPU peripherals.
181
182config OMAP_ARM_216MHZ 174config OMAP_ARM_216MHZ
183 bool "OMAP ARM 216 MHz CPU (1710 only)" 175 bool "OMAP ARM 216 MHz CPU (1710 only)"
184 depends on ARCH_OMAP1 && ARCH_OMAP16XX 176 depends on ARCH_OMAP1 && ARCH_OMAP16XX
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 1b374009b1a3..af7911963c0d 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -302,8 +302,6 @@ static void __init ams_delta_init(void)
302 omap_cfg_reg(J19_1610_CAM_D6); 302 omap_cfg_reg(J19_1610_CAM_D6);
303 omap_cfg_reg(J18_1610_CAM_D7); 303 omap_cfg_reg(J18_1610_CAM_D7);
304 304
305 iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc));
306
307 omap_board_config = ams_delta_config; 305 omap_board_config = ams_delta_config;
308 omap_board_config_size = ARRAY_SIZE(ams_delta_config); 306 omap_board_config_size = ARRAY_SIZE(ams_delta_config);
309 omap_serial_init(); 307 omap_serial_init();
@@ -373,10 +371,16 @@ static int __init ams_delta_modem_init(void)
373} 371}
374arch_initcall(ams_delta_modem_init); 372arch_initcall(ams_delta_modem_init);
375 373
374static void __init ams_delta_map_io(void)
375{
376 omap15xx_map_io();
377 iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc));
378}
379
376MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)") 380MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
377 /* Maintainer: Jonathan McDowell <noodles@earth.li> */ 381 /* Maintainer: Jonathan McDowell <noodles@earth.li> */
378 .atag_offset = 0x100, 382 .atag_offset = 0x100,
379 .map_io = omap15xx_map_io, 383 .map_io = ams_delta_map_io,
380 .init_early = omap1_init_early, 384 .init_early = omap1_init_early,
381 .reserve = omap_reserve, 385 .reserve = omap_reserve,
382 .init_irq = omap1_init_irq, 386 .init_irq = omap1_init_irq,
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index eaf09efb91ca..16b1423b454a 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -17,7 +17,8 @@
17 17
18#include <plat/clock.h> 18#include <plat/clock.h>
19 19
20extern int __init omap1_clk_init(void); 20int omap1_clk_init(void);
21void omap1_clk_late_init(void);
21extern int omap1_clk_enable(struct clk *clk); 22extern int omap1_clk_enable(struct clk *clk);
22extern void omap1_clk_disable(struct clk *clk); 23extern void omap1_clk_disable(struct clk *clk);
23extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate); 24extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 92400b9eb69f..1297bb58869c 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -767,6 +767,15 @@ static struct clk_functions omap1_clk_functions = {
767 .clk_disable_unused = omap1_clk_disable_unused, 767 .clk_disable_unused = omap1_clk_disable_unused,
768}; 768};
769 769
770static void __init omap1_show_rates(void)
771{
772 pr_notice("Clocking rate (xtal/DPLL1/MPU): "
773 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
774 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
775 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
776 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
777}
778
770int __init omap1_clk_init(void) 779int __init omap1_clk_init(void)
771{ 780{
772 struct omap_clk *c; 781 struct omap_clk *c;
@@ -835,9 +844,12 @@ int __init omap1_clk_init(void)
835 /* We want to be in syncronous scalable mode */ 844 /* We want to be in syncronous scalable mode */
836 omap_writew(0x1000, ARM_SYSST); 845 omap_writew(0x1000, ARM_SYSST);
837 846
838#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER 847
839 /* Use values set by bootloader. Determine PLL rate and recalculate 848 /*
840 * dependent clocks as if kernel had changed PLL or divisors. 849 * Initially use the values set by bootloader. Determine PLL rate and
850 * recalculate dependent clocks as if kernel had changed PLL or
851 * divisors. See also omap1_clk_late_init() that can reprogram dpll1
852 * after the SRAM is initialized.
841 */ 853 */
842 { 854 {
843 unsigned pll_ctl_val = omap_readw(DPLL_CTL); 855 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
@@ -862,25 +874,10 @@ int __init omap1_clk_init(void)
862 } 874 }
863 } 875 }
864 } 876 }
865#else
866 /* Find the highest supported frequency and enable it */
867 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
868 printk(KERN_ERR "System frequencies not set. Check your config.\n");
869 /* Guess sane values (60MHz) */
870 omap_writew(0x2290, DPLL_CTL);
871 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
872 ck_dpll1.rate = 60000000;
873 }
874#endif
875 propagate_rate(&ck_dpll1); 877 propagate_rate(&ck_dpll1);
876 /* Cache rates for clocks connected to ck_ref (not dpll1) */ 878 /* Cache rates for clocks connected to ck_ref (not dpll1) */
877 propagate_rate(&ck_ref); 879 propagate_rate(&ck_ref);
878 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " 880 omap1_show_rates();
879 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
880 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
881 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
882 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
883
884 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { 881 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
885 /* Select slicer output as OMAP input clock */ 882 /* Select slicer output as OMAP input clock */
886 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, 883 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
@@ -925,3 +922,21 @@ int __init omap1_clk_init(void)
925 922
926 return 0; 923 return 0;
927} 924}
925
926#define OMAP1_DPLL1_SANE_VALUE 60000000
927
928void __init omap1_clk_late_init(void)
929{
930 if (ck_dpll1.rate >= OMAP1_DPLL1_SANE_VALUE)
931 return;
932
933 /* Find the highest supported frequency and enable it */
934 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
935 pr_err("System frequencies not set, using default. Check your config.\n");
936 omap_writew(0x2290, DPLL_CTL);
937 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
938 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
939 }
940 propagate_rate(&ck_dpll1);
941 omap1_show_rates();
942}
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 9d47ca7f80fa..1d76a63c0983 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -30,6 +30,8 @@
30#include <plat/omap7xx.h> 30#include <plat/omap7xx.h>
31#include <plat/mcbsp.h> 31#include <plat/mcbsp.h>
32 32
33#include "clock.h"
34
33/*-------------------------------------------------------------------------*/ 35/*-------------------------------------------------------------------------*/
34 36
35#if defined(CONFIG_RTC_DRV_OMAP) || defined(CONFIG_RTC_DRV_OMAP_MODULE) 37#if defined(CONFIG_RTC_DRV_OMAP) || defined(CONFIG_RTC_DRV_OMAP_MODULE)
@@ -293,6 +295,7 @@ static int __init omap1_init_devices(void)
293 return -ENODEV; 295 return -ENODEV;
294 296
295 omap_sram_init(); 297 omap_sram_init();
298 omap1_clk_late_init();
296 299
297 /* please keep these calls, and their implementations above, 300 /* please keep these calls, and their implementations above,
298 * in alphabetical order so they're easier to sort through. 301 * in alphabetical order so they're easier to sort through.
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 22f7c97a2728..b6625130831d 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -336,6 +336,7 @@ config MACH_OMAP4_PANDA
336config OMAP3_EMU 336config OMAP3_EMU
337 bool "OMAP3 debugging peripherals" 337 bool "OMAP3 debugging peripherals"
338 depends on ARCH_OMAP3 338 depends on ARCH_OMAP3
339 select ARM_AMBA
339 select OC_ETM 340 select OC_ETM
340 help 341 help
341 Say Y here to enable debugging hardware of omap3 342 Say Y here to enable debugging hardware of omap3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 69ab1c069134..b009f17dee56 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
4 4
5# Common support 5# Common support
6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \ 6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
7 common.o gpio.o dma.o wd_timer.o 7 common.o gpio.o dma.o wd_timer.o display.o
8 8
9omap-2-3-common = irq.o sdrc.o 9omap-2-3-common = irq.o sdrc.o
10hwmod-common = omap_hwmod.o \ 10hwmod-common = omap_hwmod.o \
@@ -264,7 +264,4 @@ smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
264obj-y += $(smsc911x-m) $(smsc911x-y) 264obj-y += $(smsc911x-m) $(smsc911x-y)
265obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o 265obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
266 266
267disp-$(CONFIG_OMAP2_DSS) := display.o
268obj-y += $(disp-m) $(disp-y)
269
270obj-y += common-board-devices.o twl-common.o 267obj-y += common-board-devices.o twl-common.o
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 876f64779735..e20332f4abdc 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -24,6 +24,7 @@
24 24
25#include <linux/sched.h> 25#include <linux/sched.h>
26#include <linux/cpuidle.h> 26#include <linux/cpuidle.h>
27#include <linux/export.h>
27 28
28#include <plat/prcm.h> 29#include <plat/prcm.h>
29#include <plat/irqs.h> 30#include <plat/irqs.h>
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index adb2756e242f..dce9905d64bb 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -27,8 +27,35 @@
27#include <plat/omap_hwmod.h> 27#include <plat/omap_hwmod.h>
28#include <plat/omap_device.h> 28#include <plat/omap_device.h>
29#include <plat/omap-pm.h> 29#include <plat/omap-pm.h>
30#include <plat/common.h>
30 31
31#include "control.h" 32#include "control.h"
33#include "display.h"
34
35#define DISPC_CONTROL 0x0040
36#define DISPC_CONTROL2 0x0238
37#define DISPC_IRQSTATUS 0x0018
38
39#define DSS_SYSCONFIG 0x10
40#define DSS_SYSSTATUS 0x14
41#define DSS_CONTROL 0x40
42#define DSS_SDI_CONTROL 0x44
43#define DSS_PLL_CONTROL 0x48
44
45#define LCD_EN_MASK (0x1 << 0)
46#define DIGIT_EN_MASK (0x1 << 1)
47
48#define FRAMEDONE_IRQ_SHIFT 0
49#define EVSYNC_EVEN_IRQ_SHIFT 2
50#define EVSYNC_ODD_IRQ_SHIFT 3
51#define FRAMEDONE2_IRQ_SHIFT 22
52#define FRAMEDONETV_IRQ_SHIFT 24
53
54/*
55 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
56 * reset before deciding that something has gone wrong
57 */
58#define FRAMEDONE_IRQ_TIMEOUT 100
32 59
33static struct platform_device omap_display_device = { 60static struct platform_device omap_display_device = {
34 .name = "omapdss", 61 .name = "omapdss",
@@ -172,3 +199,135 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
172 199
173 return r; 200 return r;
174} 201}
202
203static void dispc_disable_outputs(void)
204{
205 u32 v, irq_mask = 0;
206 bool lcd_en, digit_en, lcd2_en = false;
207 int i;
208 struct omap_dss_dispc_dev_attr *da;
209 struct omap_hwmod *oh;
210
211 oh = omap_hwmod_lookup("dss_dispc");
212 if (!oh) {
213 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
214 return;
215 }
216
217 if (!oh->dev_attr) {
218 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
219 return;
220 }
221
222 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
223
224 /* store value of LCDENABLE and DIGITENABLE bits */
225 v = omap_hwmod_read(oh, DISPC_CONTROL);
226 lcd_en = v & LCD_EN_MASK;
227 digit_en = v & DIGIT_EN_MASK;
228
229 /* store value of LCDENABLE for LCD2 */
230 if (da->manager_count > 2) {
231 v = omap_hwmod_read(oh, DISPC_CONTROL2);
232 lcd2_en = v & LCD_EN_MASK;
233 }
234
235 if (!(lcd_en | digit_en | lcd2_en))
236 return; /* no managers currently enabled */
237
238 /*
239 * If any manager was enabled, we need to disable it before
240 * DSS clocks are disabled or DISPC module is reset
241 */
242 if (lcd_en)
243 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
244
245 if (digit_en) {
246 if (da->has_framedonetv_irq) {
247 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
248 } else {
249 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
250 1 << EVSYNC_ODD_IRQ_SHIFT;
251 }
252 }
253
254 if (lcd2_en)
255 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
256
257 /*
258 * clear any previous FRAMEDONE, FRAMEDONETV,
259 * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
260 */
261 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
262
263 /* disable LCD and TV managers */
264 v = omap_hwmod_read(oh, DISPC_CONTROL);
265 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
266 omap_hwmod_write(v, oh, DISPC_CONTROL);
267
268 /* disable LCD2 manager */
269 if (da->manager_count > 2) {
270 v = omap_hwmod_read(oh, DISPC_CONTROL2);
271 v &= ~LCD_EN_MASK;
272 omap_hwmod_write(v, oh, DISPC_CONTROL2);
273 }
274
275 i = 0;
276 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
277 irq_mask) {
278 i++;
279 if (i > FRAMEDONE_IRQ_TIMEOUT) {
280 pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
281 break;
282 }
283 mdelay(1);
284 }
285}
286
287#define MAX_MODULE_SOFTRESET_WAIT 10000
288int omap_dss_reset(struct omap_hwmod *oh)
289{
290 struct omap_hwmod_opt_clk *oc;
291 int c = 0;
292 int i, r;
293
294 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
295 pr_err("dss_core: hwmod data doesn't contain reset data\n");
296 return -EINVAL;
297 }
298
299 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
300 if (oc->_clk)
301 clk_enable(oc->_clk);
302
303 dispc_disable_outputs();
304
305 /* clear SDI registers */
306 if (cpu_is_omap3430()) {
307 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
308 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
309 }
310
311 /*
312 * clear DSS_CONTROL register to switch DSS clock sources to
313 * PRCM clock, if any
314 */
315 omap_hwmod_write(0x0, oh, DSS_CONTROL);
316
317 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
318 & SYSS_RESETDONE_MASK),
319 MAX_MODULE_SOFTRESET_WAIT, c);
320
321 if (c == MAX_MODULE_SOFTRESET_WAIT)
322 pr_warning("dss_core: waiting for reset to finish failed\n");
323 else
324 pr_debug("dss_core: softreset done\n");
325
326 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
327 if (oc->_clk)
328 clk_disable(oc->_clk);
329
330 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
331
332 return r;
333}
diff --git a/arch/arm/mach-omap2/display.h b/arch/arm/mach-omap2/display.h
new file mode 100644
index 000000000000..b871b017b352
--- /dev/null
+++ b/arch/arm/mach-omap2/display.h
@@ -0,0 +1,29 @@
1/*
2 * display.h - OMAP2+ integration-specific DSS header
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifndef __ARCH_ARM_MACH_OMAP2_DISPLAY_H
20#define __ARCH_ARM_MACH_OMAP2_DISPLAY_H
21
22#include <linux/kernel.h>
23
24struct omap_dss_dispc_dev_attr {
25 u8 manager_count;
26 bool has_framedonetv_irq;
27};
28
29#endif
diff --git a/arch/arm/mach-omap2/io.h b/arch/arm/mach-omap2/io.h
deleted file mode 100644
index e69de29bb2d1..000000000000
--- a/arch/arm/mach-omap2/io.h
+++ /dev/null
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 00fcd2c311ea..529142aff766 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -749,7 +749,7 @@ static int _count_mpu_irqs(struct omap_hwmod *oh)
749 ohii = &oh->mpu_irqs[i++]; 749 ohii = &oh->mpu_irqs[i++];
750 } while (ohii->irq != -1); 750 } while (ohii->irq != -1);
751 751
752 return i; 752 return i-1;
753} 753}
754 754
755/** 755/**
@@ -772,7 +772,7 @@ static int _count_sdma_reqs(struct omap_hwmod *oh)
772 ohdi = &oh->sdma_reqs[i++]; 772 ohdi = &oh->sdma_reqs[i++];
773 } while (ohdi->dma_req != -1); 773 } while (ohdi->dma_req != -1);
774 774
775 return i; 775 return i-1;
776} 776}
777 777
778/** 778/**
@@ -795,7 +795,7 @@ static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
795 mem = &os->addr[i++]; 795 mem = &os->addr[i++];
796 } while (mem->pa_start != mem->pa_end); 796 } while (mem->pa_start != mem->pa_end);
797 797
798 return i; 798 return i-1;
799} 799}
800 800
801/** 801/**
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 6d7206213525..a5409ce3f323 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -875,6 +875,10 @@ static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
875}; 875};
876 876
877static struct omap_hwmod_opt_clk dss_opt_clks[] = { 877static struct omap_hwmod_opt_clk dss_opt_clks[] = {
878 /*
879 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
880 * driver does not use these clocks.
881 */
878 { .role = "tv_clk", .clk = "dss_54m_fck" }, 882 { .role = "tv_clk", .clk = "dss_54m_fck" },
879 { .role = "sys_clk", .clk = "dss2_fck" }, 883 { .role = "sys_clk", .clk = "dss2_fck" },
880}; 884};
@@ -899,7 +903,7 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
899 .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), 903 .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
900 .masters = omap2420_dss_masters, 904 .masters = omap2420_dss_masters,
901 .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), 905 .masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
902 .flags = HWMOD_NO_IDLEST, 906 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
903}; 907};
904 908
905/* l4_core -> dss_dispc */ 909/* l4_core -> dss_dispc */
@@ -939,6 +943,7 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
939 .slaves = omap2420_dss_dispc_slaves, 943 .slaves = omap2420_dss_dispc_slaves,
940 .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), 944 .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
941 .flags = HWMOD_NO_IDLEST, 945 .flags = HWMOD_NO_IDLEST,
946 .dev_attr = &omap2_3_dss_dispc_dev_attr
942}; 947};
943 948
944/* l4_core -> dss_rfbi */ 949/* l4_core -> dss_rfbi */
@@ -961,6 +966,10 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
961 &omap2420_l4_core__dss_rfbi, 966 &omap2420_l4_core__dss_rfbi,
962}; 967};
963 968
969static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
970 { .role = "ick", .clk = "dss_ick" },
971};
972
964static struct omap_hwmod omap2420_dss_rfbi_hwmod = { 973static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
965 .name = "dss_rfbi", 974 .name = "dss_rfbi",
966 .class = &omap2_rfbi_hwmod_class, 975 .class = &omap2_rfbi_hwmod_class,
@@ -972,6 +981,8 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
972 .module_offs = CORE_MOD, 981 .module_offs = CORE_MOD,
973 }, 982 },
974 }, 983 },
984 .opt_clks = dss_rfbi_opt_clks,
985 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
975 .slaves = omap2420_dss_rfbi_slaves, 986 .slaves = omap2420_dss_rfbi_slaves,
976 .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), 987 .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
977 .flags = HWMOD_NO_IDLEST, 988 .flags = HWMOD_NO_IDLEST,
@@ -981,7 +992,7 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
981static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { 992static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
982 .master = &omap2420_l4_core_hwmod, 993 .master = &omap2420_l4_core_hwmod,
983 .slave = &omap2420_dss_venc_hwmod, 994 .slave = &omap2420_dss_venc_hwmod,
984 .clk = "dss_54m_fck", 995 .clk = "dss_ick",
985 .addr = omap2_dss_venc_addrs, 996 .addr = omap2_dss_venc_addrs,
986 .fw = { 997 .fw = {
987 .omap2 = { 998 .omap2 = {
@@ -1001,7 +1012,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1001static struct omap_hwmod omap2420_dss_venc_hwmod = { 1012static struct omap_hwmod omap2420_dss_venc_hwmod = {
1002 .name = "dss_venc", 1013 .name = "dss_venc",
1003 .class = &omap2_venc_hwmod_class, 1014 .class = &omap2_venc_hwmod_class,
1004 .main_clk = "dss1_fck", 1015 .main_clk = "dss_54m_fck",
1005 .prcm = { 1016 .prcm = {
1006 .omap2 = { 1017 .omap2 = {
1007 .prcm_reg_id = 1, 1018 .prcm_reg_id = 1,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index a2580d01c3ff..c4f56cb60d7d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -942,6 +942,10 @@ static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
942}; 942};
943 943
944static struct omap_hwmod_opt_clk dss_opt_clks[] = { 944static struct omap_hwmod_opt_clk dss_opt_clks[] = {
945 /*
946 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
947 * driver does not use these clocks.
948 */
945 { .role = "tv_clk", .clk = "dss_54m_fck" }, 949 { .role = "tv_clk", .clk = "dss_54m_fck" },
946 { .role = "sys_clk", .clk = "dss2_fck" }, 950 { .role = "sys_clk", .clk = "dss2_fck" },
947}; 951};
@@ -966,7 +970,7 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
966 .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), 970 .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
967 .masters = omap2430_dss_masters, 971 .masters = omap2430_dss_masters,
968 .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), 972 .masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
969 .flags = HWMOD_NO_IDLEST, 973 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
970}; 974};
971 975
972/* l4_core -> dss_dispc */ 976/* l4_core -> dss_dispc */
@@ -1000,6 +1004,7 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1000 .slaves = omap2430_dss_dispc_slaves, 1004 .slaves = omap2430_dss_dispc_slaves,
1001 .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), 1005 .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1002 .flags = HWMOD_NO_IDLEST, 1006 .flags = HWMOD_NO_IDLEST,
1007 .dev_attr = &omap2_3_dss_dispc_dev_attr
1003}; 1008};
1004 1009
1005/* l4_core -> dss_rfbi */ 1010/* l4_core -> dss_rfbi */
@@ -1016,6 +1021,10 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1016 &omap2430_l4_core__dss_rfbi, 1021 &omap2430_l4_core__dss_rfbi,
1017}; 1022};
1018 1023
1024static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1025 { .role = "ick", .clk = "dss_ick" },
1026};
1027
1019static struct omap_hwmod omap2430_dss_rfbi_hwmod = { 1028static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1020 .name = "dss_rfbi", 1029 .name = "dss_rfbi",
1021 .class = &omap2_rfbi_hwmod_class, 1030 .class = &omap2_rfbi_hwmod_class,
@@ -1027,6 +1036,8 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1027 .module_offs = CORE_MOD, 1036 .module_offs = CORE_MOD,
1028 }, 1037 },
1029 }, 1038 },
1039 .opt_clks = dss_rfbi_opt_clks,
1040 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1030 .slaves = omap2430_dss_rfbi_slaves, 1041 .slaves = omap2430_dss_rfbi_slaves,
1031 .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), 1042 .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1032 .flags = HWMOD_NO_IDLEST, 1043 .flags = HWMOD_NO_IDLEST,
@@ -1036,7 +1047,7 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1036static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { 1047static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1037 .master = &omap2430_l4_core_hwmod, 1048 .master = &omap2430_l4_core_hwmod,
1038 .slave = &omap2430_dss_venc_hwmod, 1049 .slave = &omap2430_dss_venc_hwmod,
1039 .clk = "dss_54m_fck", 1050 .clk = "dss_ick",
1040 .addr = omap2_dss_venc_addrs, 1051 .addr = omap2_dss_venc_addrs,
1041 .flags = OCPIF_SWSUP_IDLE, 1052 .flags = OCPIF_SWSUP_IDLE,
1042 .user = OCP_USER_MPU | OCP_USER_SDMA, 1053 .user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1050,7 +1061,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1050static struct omap_hwmod omap2430_dss_venc_hwmod = { 1061static struct omap_hwmod omap2430_dss_venc_hwmod = {
1051 .name = "dss_venc", 1062 .name = "dss_venc",
1052 .class = &omap2_venc_hwmod_class, 1063 .class = &omap2_venc_hwmod_class,
1053 .main_clk = "dss1_fck", 1064 .main_clk = "dss_54m_fck",
1054 .prcm = { 1065 .prcm = {
1055 .omap2 = { 1066 .omap2 = {
1056 .prcm_reg_id = 1, 1067 .prcm_reg_id = 1,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index c451729d289a..c11273da5dcc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -11,6 +11,7 @@
11#include <plat/omap_hwmod.h> 11#include <plat/omap_hwmod.h>
12#include <plat/serial.h> 12#include <plat/serial.h>
13#include <plat/dma.h> 13#include <plat/dma.h>
14#include <plat/common.h>
14 15
15#include <mach/irqs.h> 16#include <mach/irqs.h>
16 17
@@ -43,13 +44,15 @@ static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
43 .rev_offs = 0x0000, 44 .rev_offs = 0x0000,
44 .sysc_offs = 0x0010, 45 .sysc_offs = 0x0010,
45 .syss_offs = 0x0014, 46 .syss_offs = 0x0014,
46 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 47 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
48 SYSS_HAS_RESET_STATUS),
47 .sysc_fields = &omap_hwmod_sysc_type1, 49 .sysc_fields = &omap_hwmod_sysc_type1,
48}; 50};
49 51
50struct omap_hwmod_class omap2_dss_hwmod_class = { 52struct omap_hwmod_class omap2_dss_hwmod_class = {
51 .name = "dss", 53 .name = "dss",
52 .sysc = &omap2_dss_sysc, 54 .sysc = &omap2_dss_sysc,
55 .reset = omap_dss_reset,
53}; 56};
54 57
55/* 58/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index bc9035ec87fc..7f8915ad5099 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1369,9 +1369,14 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1369}; 1369};
1370 1370
1371static struct omap_hwmod_opt_clk dss_opt_clks[] = { 1371static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1372 { .role = "tv_clk", .clk = "dss_tv_fck" }, 1372 /*
1373 { .role = "video_clk", .clk = "dss_96m_fck" }, 1373 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1374 * driver does not use these clocks.
1375 */
1374 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 1376 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1377 { .role = "tv_clk", .clk = "dss_tv_fck" },
1378 /* required only on OMAP3430 */
1379 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1375}; 1380};
1376 1381
1377static struct omap_hwmod omap3430es1_dss_core_hwmod = { 1382static struct omap_hwmod omap3430es1_dss_core_hwmod = {
@@ -1394,11 +1399,12 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1394 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), 1399 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1395 .masters = omap3xxx_dss_masters, 1400 .masters = omap3xxx_dss_masters,
1396 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), 1401 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1397 .flags = HWMOD_NO_IDLEST, 1402 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1398}; 1403};
1399 1404
1400static struct omap_hwmod omap3xxx_dss_core_hwmod = { 1405static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1401 .name = "dss_core", 1406 .name = "dss_core",
1407 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1402 .class = &omap2_dss_hwmod_class, 1408 .class = &omap2_dss_hwmod_class,
1403 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 1409 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1404 .sdma_reqs = omap3xxx_dss_sdma_chs, 1410 .sdma_reqs = omap3xxx_dss_sdma_chs,
@@ -1456,6 +1462,7 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1456 .slaves = omap3xxx_dss_dispc_slaves, 1462 .slaves = omap3xxx_dss_dispc_slaves,
1457 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), 1463 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1458 .flags = HWMOD_NO_IDLEST, 1464 .flags = HWMOD_NO_IDLEST,
1465 .dev_attr = &omap2_3_dss_dispc_dev_attr
1459}; 1466};
1460 1467
1461/* 1468/*
@@ -1486,6 +1493,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1486static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { 1493static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1487 .master = &omap3xxx_l4_core_hwmod, 1494 .master = &omap3xxx_l4_core_hwmod,
1488 .slave = &omap3xxx_dss_dsi1_hwmod, 1495 .slave = &omap3xxx_dss_dsi1_hwmod,
1496 .clk = "dss_ick",
1489 .addr = omap3xxx_dss_dsi1_addrs, 1497 .addr = omap3xxx_dss_dsi1_addrs,
1490 .fw = { 1498 .fw = {
1491 .omap2 = { 1499 .omap2 = {
@@ -1502,6 +1510,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1502 &omap3xxx_l4_core__dss_dsi1, 1510 &omap3xxx_l4_core__dss_dsi1,
1503}; 1511};
1504 1512
1513static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1514 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1515};
1516
1505static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { 1517static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1506 .name = "dss_dsi1", 1518 .name = "dss_dsi1",
1507 .class = &omap3xxx_dsi_hwmod_class, 1519 .class = &omap3xxx_dsi_hwmod_class,
@@ -1514,6 +1526,8 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1514 .module_offs = OMAP3430_DSS_MOD, 1526 .module_offs = OMAP3430_DSS_MOD,
1515 }, 1527 },
1516 }, 1528 },
1529 .opt_clks = dss_dsi1_opt_clks,
1530 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1517 .slaves = omap3xxx_dss_dsi1_slaves, 1531 .slaves = omap3xxx_dss_dsi1_slaves,
1518 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), 1532 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1519 .flags = HWMOD_NO_IDLEST, 1533 .flags = HWMOD_NO_IDLEST,
@@ -1540,6 +1554,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1540 &omap3xxx_l4_core__dss_rfbi, 1554 &omap3xxx_l4_core__dss_rfbi,
1541}; 1555};
1542 1556
1557static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1558 { .role = "ick", .clk = "dss_ick" },
1559};
1560
1543static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { 1561static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1544 .name = "dss_rfbi", 1562 .name = "dss_rfbi",
1545 .class = &omap2_rfbi_hwmod_class, 1563 .class = &omap2_rfbi_hwmod_class,
@@ -1551,6 +1569,8 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1551 .module_offs = OMAP3430_DSS_MOD, 1569 .module_offs = OMAP3430_DSS_MOD,
1552 }, 1570 },
1553 }, 1571 },
1572 .opt_clks = dss_rfbi_opt_clks,
1573 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1554 .slaves = omap3xxx_dss_rfbi_slaves, 1574 .slaves = omap3xxx_dss_rfbi_slaves,
1555 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), 1575 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1556 .flags = HWMOD_NO_IDLEST, 1576 .flags = HWMOD_NO_IDLEST,
@@ -1560,7 +1580,7 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1560static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { 1580static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1561 .master = &omap3xxx_l4_core_hwmod, 1581 .master = &omap3xxx_l4_core_hwmod,
1562 .slave = &omap3xxx_dss_venc_hwmod, 1582 .slave = &omap3xxx_dss_venc_hwmod,
1563 .clk = "dss_tv_fck", 1583 .clk = "dss_ick",
1564 .addr = omap2_dss_venc_addrs, 1584 .addr = omap2_dss_venc_addrs,
1565 .fw = { 1585 .fw = {
1566 .omap2 = { 1586 .omap2 = {
@@ -1578,10 +1598,15 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1578 &omap3xxx_l4_core__dss_venc, 1598 &omap3xxx_l4_core__dss_venc,
1579}; 1599};
1580 1600
1601static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1602 /* required only on OMAP3430 */
1603 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1604};
1605
1581static struct omap_hwmod omap3xxx_dss_venc_hwmod = { 1606static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1582 .name = "dss_venc", 1607 .name = "dss_venc",
1583 .class = &omap2_venc_hwmod_class, 1608 .class = &omap2_venc_hwmod_class,
1584 .main_clk = "dss1_alwon_fck", 1609 .main_clk = "dss_tv_fck",
1585 .prcm = { 1610 .prcm = {
1586 .omap2 = { 1611 .omap2 = {
1587 .prcm_reg_id = 1, 1612 .prcm_reg_id = 1,
@@ -1589,6 +1614,8 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1589 .module_offs = OMAP3430_DSS_MOD, 1614 .module_offs = OMAP3430_DSS_MOD,
1590 }, 1615 },
1591 }, 1616 },
1617 .opt_clks = dss_venc_opt_clks,
1618 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
1592 .slaves = omap3xxx_dss_venc_slaves, 1619 .slaves = omap3xxx_dss_venc_slaves,
1593 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), 1620 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1594 .flags = HWMOD_NO_IDLEST, 1621 .flags = HWMOD_NO_IDLEST,
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7695e5d43316..daaf165af696 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -30,6 +30,7 @@
30#include <plat/mmc.h> 30#include <plat/mmc.h>
31#include <plat/i2c.h> 31#include <plat/i2c.h>
32#include <plat/dmtimer.h> 32#include <plat/dmtimer.h>
33#include <plat/common.h>
33 34
34#include "omap_hwmod_common_data.h" 35#include "omap_hwmod_common_data.h"
35 36
@@ -1187,6 +1188,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1187static struct omap_hwmod_class omap44xx_dss_hwmod_class = { 1188static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1188 .name = "dss", 1189 .name = "dss",
1189 .sysc = &omap44xx_dss_sysc, 1190 .sysc = &omap44xx_dss_sysc,
1191 .reset = omap_dss_reset,
1190}; 1192};
1191 1193
1192/* dss */ 1194/* dss */
@@ -1240,12 +1242,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1240static struct omap_hwmod_opt_clk dss_opt_clks[] = { 1242static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1241 { .role = "sys_clk", .clk = "dss_sys_clk" }, 1243 { .role = "sys_clk", .clk = "dss_sys_clk" },
1242 { .role = "tv_clk", .clk = "dss_tv_clk" }, 1244 { .role = "tv_clk", .clk = "dss_tv_clk" },
1243 { .role = "dss_clk", .clk = "dss_dss_clk" }, 1245 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1244 { .role = "video_clk", .clk = "dss_48mhz_clk" },
1245}; 1246};
1246 1247
1247static struct omap_hwmod omap44xx_dss_hwmod = { 1248static struct omap_hwmod omap44xx_dss_hwmod = {
1248 .name = "dss_core", 1249 .name = "dss_core",
1250 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1249 .class = &omap44xx_dss_hwmod_class, 1251 .class = &omap44xx_dss_hwmod_class,
1250 .clkdm_name = "l3_dss_clkdm", 1252 .clkdm_name = "l3_dss_clkdm",
1251 .main_clk = "dss_dss_clk", 1253 .main_clk = "dss_dss_clk",
@@ -1325,6 +1327,11 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1325 { } 1327 { }
1326}; 1328};
1327 1329
1330static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1331 .manager_count = 3,
1332 .has_framedonetv_irq = 1
1333};
1334
1328/* l4_per -> dss_dispc */ 1335/* l4_per -> dss_dispc */
1329static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { 1336static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1330 .master = &omap44xx_l4_per_hwmod, 1337 .master = &omap44xx_l4_per_hwmod,
@@ -1340,12 +1347,6 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1340 &omap44xx_l4_per__dss_dispc, 1347 &omap44xx_l4_per__dss_dispc,
1341}; 1348};
1342 1349
1343static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1344 { .role = "sys_clk", .clk = "dss_sys_clk" },
1345 { .role = "tv_clk", .clk = "dss_tv_clk" },
1346 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1347};
1348
1349static struct omap_hwmod omap44xx_dss_dispc_hwmod = { 1350static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1350 .name = "dss_dispc", 1351 .name = "dss_dispc",
1351 .class = &omap44xx_dispc_hwmod_class, 1352 .class = &omap44xx_dispc_hwmod_class,
@@ -1359,10 +1360,9 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1359 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1360 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1360 }, 1361 },
1361 }, 1362 },
1362 .opt_clks = dss_dispc_opt_clks,
1363 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
1364 .slaves = omap44xx_dss_dispc_slaves, 1363 .slaves = omap44xx_dss_dispc_slaves,
1365 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), 1364 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1365 .dev_attr = &omap44xx_dss_dispc_dev_attr
1366}; 1366};
1367 1367
1368/* 1368/*
@@ -1624,7 +1624,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1624 .clkdm_name = "l3_dss_clkdm", 1624 .clkdm_name = "l3_dss_clkdm",
1625 .mpu_irqs = omap44xx_dss_hdmi_irqs, 1625 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1626 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, 1626 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1627 .main_clk = "dss_dss_clk", 1627 .main_clk = "dss_48mhz_clk",
1628 .prcm = { 1628 .prcm = {
1629 .omap4 = { 1629 .omap4 = {
1630 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1630 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -1785,7 +1785,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1785 .name = "dss_venc", 1785 .name = "dss_venc",
1786 .class = &omap44xx_venc_hwmod_class, 1786 .class = &omap44xx_venc_hwmod_class,
1787 .clkdm_name = "l3_dss_clkdm", 1787 .clkdm_name = "l3_dss_clkdm",
1788 .main_clk = "dss_dss_clk", 1788 .main_clk = "dss_tv_clk",
1789 .prcm = { 1789 .prcm = {
1790 .omap4 = { 1790 .omap4 = {
1791 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1791 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
index de832ebc93a9..51e5418899fb 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -49,3 +49,7 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
49 .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT, 49 .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
50}; 50};
51 51
52struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
53 .manager_count = 2,
54 .has_framedonetv_irq = 0
55};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 39a7c37f4587..ad5d8f04c0b8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -16,6 +16,8 @@
16 16
17#include <plat/omap_hwmod.h> 17#include <plat/omap_hwmod.h>
18 18
19#include "display.h"
20
19/* Common address space across OMAP2xxx */ 21/* Common address space across OMAP2xxx */
20extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[]; 22extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
21extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[]; 23extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
@@ -111,4 +113,6 @@ extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
111extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class; 113extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
112extern struct omap_hwmod_class omap2xxx_mcspi_class; 114extern struct omap_hwmod_class omap2xxx_mcspi_class;
113 115
116extern struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr;
117
114#endif 118#endif
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
index 6a66aa5e2a5b..d15225ff5c49 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.c
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -237,7 +237,7 @@ static int __devexit omap4_l3_remove(struct platform_device *pdev)
237static const struct of_device_id l3_noc_match[] = { 237static const struct of_device_id l3_noc_match[] = {
238 {.compatible = "ti,omap4-l3-noc", }, 238 {.compatible = "ti,omap4-l3-noc", },
239 {}, 239 {},
240} 240};
241MODULE_DEVICE_TABLE(of, l3_noc_match); 241MODULE_DEVICE_TABLE(of, l3_noc_match);
242#else 242#else
243#define l3_noc_match NULL 243#define l3_noc_match NULL
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index e7bee5ca407c..1881fe915149 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -24,6 +24,7 @@
24#include "powerdomain.h" 24#include "powerdomain.h"
25#include "clockdomain.h" 25#include "clockdomain.h"
26#include "pm.h" 26#include "pm.h"
27#include "twl-common.h"
27 28
28static struct omap_device_pm_latency *pm_lats; 29static struct omap_device_pm_latency *pm_lats;
29 30
@@ -226,11 +227,8 @@ postcore_initcall(omap2_common_pm_init);
226 227
227static int __init omap2_common_pm_late_init(void) 228static int __init omap2_common_pm_late_init(void)
228{ 229{
229 /* Init the OMAP TWL parameters */
230 omap3_twl_init();
231 omap4_twl_init();
232
233 /* Init the voltage layer */ 230 /* Init the voltage layer */
231 omap_pmic_late_init();
234 omap_voltage_late_init(); 232 omap_voltage_late_init();
235 233
236 /* Initialize the voltages */ 234 /* Initialize the voltages */
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 919d827ed707..9dd93453e563 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -139,7 +139,7 @@ static irqreturn_t sr_interrupt(int irq, void *data)
139 sr_write_reg(sr_info, ERRCONFIG_V1, status); 139 sr_write_reg(sr_info, ERRCONFIG_V1, status);
140 } else if (sr_info->ip_type == SR_TYPE_V2) { 140 } else if (sr_info->ip_type == SR_TYPE_V2) {
141 /* Read the status bits */ 141 /* Read the status bits */
142 sr_read_reg(sr_info, IRQSTATUS); 142 status = sr_read_reg(sr_info, IRQSTATUS);
143 143
144 /* Clear them by writing back */ 144 /* Clear them by writing back */
145 sr_write_reg(sr_info, IRQSTATUS, status); 145 sr_write_reg(sr_info, IRQSTATUS, status);
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 522435772168..10b20c652e5d 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -30,6 +30,7 @@
30#include <plat/usb.h> 30#include <plat/usb.h>
31 31
32#include "twl-common.h" 32#include "twl-common.h"
33#include "pm.h"
33 34
34static struct i2c_board_info __initdata pmic_i2c_board_info = { 35static struct i2c_board_info __initdata pmic_i2c_board_info = {
35 .addr = 0x48, 36 .addr = 0x48,
@@ -48,6 +49,16 @@ void __init omap_pmic_init(int bus, u32 clkrate,
48 omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1); 49 omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
49} 50}
50 51
52void __init omap_pmic_late_init(void)
53{
54 /* Init the OMAP TWL parameters (if PMIC has been registerd) */
55 if (!pmic_i2c_board_info.irq)
56 return;
57
58 omap3_twl_init();
59 omap4_twl_init();
60}
61
51#if defined(CONFIG_ARCH_OMAP3) 62#if defined(CONFIG_ARCH_OMAP3)
52static struct twl4030_usb_data omap3_usb_pdata = { 63static struct twl4030_usb_data omap3_usb_pdata = {
53 .usb_mode = T2_USB_MODE_ULPI, 64 .usb_mode = T2_USB_MODE_ULPI,
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index 5e83a5bd37fb..275dde8cb27a 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -1,6 +1,8 @@
1#ifndef __OMAP_PMIC_COMMON__ 1#ifndef __OMAP_PMIC_COMMON__
2#define __OMAP_PMIC_COMMON__ 2#define __OMAP_PMIC_COMMON__
3 3
4#include <plat/irqs.h>
5
4#define TWL_COMMON_PDATA_USB (1 << 0) 6#define TWL_COMMON_PDATA_USB (1 << 0)
5#define TWL_COMMON_PDATA_BCI (1 << 1) 7#define TWL_COMMON_PDATA_BCI (1 << 1)
6#define TWL_COMMON_PDATA_MADC (1 << 2) 8#define TWL_COMMON_PDATA_MADC (1 << 2)
@@ -30,6 +32,7 @@ struct twl4030_platform_data;
30 32
31void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq, 33void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
32 struct twl4030_platform_data *pmic_data); 34 struct twl4030_platform_data *pmic_data);
35void omap_pmic_late_init(void);
33 36
34static inline void omap2_pmic_init(const char *pmic_type, 37static inline void omap2_pmic_init(const char *pmic_type,
35 struct twl4030_platform_data *pmic_data) 38 struct twl4030_platform_data *pmic_data)
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index fc0b8544e174..4b81f59a4cba 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -307,7 +307,7 @@ static inline void balloon3_mmc_init(void) {}
307/****************************************************************************** 307/******************************************************************************
308 * USB Gadget 308 * USB Gadget
309 ******************************************************************************/ 309 ******************************************************************************/
310#if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE) 310#if defined(CONFIG_USB_PXA27X)||defined(CONFIG_USB_PXA27X_MODULE)
311static void balloon3_udc_command(int cmd) 311static void balloon3_udc_command(int cmd)
312{ 312{
313 if (cmd == PXA2XX_UDC_CMD_CONNECT) 313 if (cmd == PXA2XX_UDC_CMD_CONNECT)
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index 692e1ffc5586..d23b92b80488 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -146,7 +146,7 @@ static void __init colibri_pxa320_init_eth(void)
146static inline void __init colibri_pxa320_init_eth(void) {} 146static inline void __init colibri_pxa320_init_eth(void) {}
147#endif /* CONFIG_AX88796 */ 147#endif /* CONFIG_AX88796 */
148 148
149#if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE) 149#if defined(CONFIG_USB_PXA27X)||defined(CONFIG_USB_PXA27X_MODULE)
150static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = { 150static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = {
151 .gpio_vbus = mfp_to_gpio(MFP_PIN_GPIO96), 151 .gpio_vbus = mfp_to_gpio(MFP_PIN_GPIO96),
152 .gpio_pullup = -1, 152 .gpio_pullup = -1,
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index 9c8208ca0415..ffdd70dad327 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -106,7 +106,7 @@ static void __init gumstix_mmc_init(void)
106} 106}
107#endif 107#endif
108 108
109#ifdef CONFIG_USB_GADGET_PXA25X 109#ifdef CONFIG_USB_PXA25X
110static struct gpio_vbus_mach_info gumstix_udc_info = { 110static struct gpio_vbus_mach_info gumstix_udc_info = {
111 .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn, 111 .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn,
112 .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx, 112 .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx,
diff --git a/arch/arm/mach-pxa/include/mach/palm27x.h b/arch/arm/mach-pxa/include/mach/palm27x.h
index f80bbe246afe..d4eac3d6ffb5 100644
--- a/arch/arm/mach-pxa/include/mach/palm27x.h
+++ b/arch/arm/mach-pxa/include/mach/palm27x.h
@@ -37,8 +37,8 @@ extern void __init palm27x_lcd_init(int power,
37#define palm27x_lcd_init(power, mode) do {} while (0) 37#define palm27x_lcd_init(power, mode) do {} while (0)
38#endif 38#endif
39 39
40#if defined(CONFIG_USB_GADGET_PXA27X) || \ 40#if defined(CONFIG_USB_PXA27X) || \
41 defined(CONFIG_USB_GADGET_PXA27X_MODULE) 41 defined(CONFIG_USB_PXA27X_MODULE)
42extern void __init palm27x_udc_init(int vbus, int pullup, 42extern void __init palm27x_udc_init(int vbus, int pullup,
43 int vbus_inverted); 43 int vbus_inverted);
44#else 44#else
diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c
index 325c245c0a0d..fbc10d7b95d1 100644
--- a/arch/arm/mach-pxa/palm27x.c
+++ b/arch/arm/mach-pxa/palm27x.c
@@ -164,8 +164,8 @@ void __init palm27x_lcd_init(int power, struct pxafb_mode_info *mode)
164/****************************************************************************** 164/******************************************************************************
165 * USB Gadget 165 * USB Gadget
166 ******************************************************************************/ 166 ******************************************************************************/
167#if defined(CONFIG_USB_GADGET_PXA27X) || \ 167#if defined(CONFIG_USB_PXA27X) || \
168 defined(CONFIG_USB_GADGET_PXA27X_MODULE) 168 defined(CONFIG_USB_PXA27X_MODULE)
169static struct gpio_vbus_mach_info palm27x_udc_info = { 169static struct gpio_vbus_mach_info palm27x_udc_info = {
170 .gpio_vbus_inverted = 1, 170 .gpio_vbus_inverted = 1,
171}; 171};
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index 6ec7caefb37c..2c24c67fd92b 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -338,7 +338,7 @@ static inline void palmtc_mkp_init(void) {}
338/****************************************************************************** 338/******************************************************************************
339 * UDC 339 * UDC
340 ******************************************************************************/ 340 ******************************************************************************/
341#if defined(CONFIG_USB_GADGET_PXA25X)||defined(CONFIG_USB_GADGET_PXA25X_MODULE) 341#if defined(CONFIG_USB_PXA25X)||defined(CONFIG_USB_PXA25X_MODULE)
342static struct gpio_vbus_mach_info palmtc_udc_info = { 342static struct gpio_vbus_mach_info palmtc_udc_info = {
343 .gpio_vbus = GPIO_NR_PALMTC_USB_DETECT_N, 343 .gpio_vbus = GPIO_NR_PALMTC_USB_DETECT_N,
344 .gpio_vbus_inverted = 1, 344 .gpio_vbus_inverted = 1,
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index a7539a6ed1ff..ca0c6615028c 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -343,7 +343,7 @@ static inline void vpac270_uhc_init(void) {}
343/****************************************************************************** 343/******************************************************************************
344 * USB Gadget 344 * USB Gadget
345 ******************************************************************************/ 345 ******************************************************************************/
346#if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE) 346#if defined(CONFIG_USB_PXA27X)||defined(CONFIG_USB_PXA27X_MODULE)
347static struct gpio_vbus_mach_info vpac270_gpio_vbus_info = { 347static struct gpio_vbus_mach_info vpac270_gpio_vbus_info = {
348 .gpio_vbus = GPIO41_VPAC270_UDC_DETECT, 348 .gpio_vbus = GPIO41_VPAC270_UDC_DETECT,
349 .gpio_pullup = -1, 349 .gpio_pullup = -1,
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 66668565ee75..f208154b1382 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -8,7 +8,7 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#include <linux/module.h> 11#include <linux/export.h>
12#include <linux/interrupt.h> 12#include <linux/interrupt.h>
13#include <linux/i2c.h> 13#include <linux/i2c.h>
14 14
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index 0a5b22942fd3..34bbcbfb1706 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -20,6 +20,7 @@
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/irq.h> 21#include <linux/irq.h>
22#include <linux/bitrev.h> 22#include <linux/bitrev.h>
23#include <linux/console.h>
23#include <asm/system.h> 24#include <asm/system.h>
24#include <asm/io.h> 25#include <asm/io.h>
25#include <asm/tlbflush.h> 26#include <asm/tlbflush.h>
@@ -106,9 +107,8 @@ static int pd_power_down(struct generic_pm_domain *genpd)
106 return 0; 107 return 0;
107} 108}
108 109
109static int pd_power_up(struct generic_pm_domain *genpd) 110static int __pd_power_up(struct sh7372_pm_domain *sh7372_pd, bool do_resume)
110{ 111{
111 struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
112 unsigned int mask = 1 << sh7372_pd->bit_shift; 112 unsigned int mask = 1 << sh7372_pd->bit_shift;
113 unsigned int retry_count; 113 unsigned int retry_count;
114 int ret = 0; 114 int ret = 0;
@@ -123,13 +123,13 @@ static int pd_power_up(struct generic_pm_domain *genpd)
123 123
124 for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) { 124 for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
125 if (!(__raw_readl(SWUCR) & mask)) 125 if (!(__raw_readl(SWUCR) & mask))
126 goto out; 126 break;
127 if (retry_count > PSTR_RETRIES) 127 if (retry_count > PSTR_RETRIES)
128 udelay(PSTR_DELAY_US); 128 udelay(PSTR_DELAY_US);
129 else 129 else
130 cpu_relax(); 130 cpu_relax();
131 } 131 }
132 if (__raw_readl(SWUCR) & mask) 132 if (!retry_count)
133 ret = -EIO; 133 ret = -EIO;
134 134
135 if (!sh7372_pd->no_debug) 135 if (!sh7372_pd->no_debug)
@@ -137,12 +137,17 @@ static int pd_power_up(struct generic_pm_domain *genpd)
137 mask, __raw_readl(PSTR)); 137 mask, __raw_readl(PSTR));
138 138
139 out: 139 out:
140 if (ret == 0 && sh7372_pd->resume) 140 if (ret == 0 && sh7372_pd->resume && do_resume)
141 sh7372_pd->resume(); 141 sh7372_pd->resume();
142 142
143 return ret; 143 return ret;
144} 144}
145 145
146static int pd_power_up(struct generic_pm_domain *genpd)
147{
148 return __pd_power_up(to_sh7372_pd(genpd), true);
149}
150
146static void sh7372_a4r_suspend(void) 151static void sh7372_a4r_suspend(void)
147{ 152{
148 sh7372_intcs_suspend(); 153 sh7372_intcs_suspend();
@@ -174,7 +179,7 @@ void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
174 genpd->active_wakeup = pd_active_wakeup; 179 genpd->active_wakeup = pd_active_wakeup;
175 genpd->power_off = pd_power_down; 180 genpd->power_off = pd_power_down;
176 genpd->power_on = pd_power_up; 181 genpd->power_on = pd_power_up;
177 genpd->power_on(&sh7372_pd->genpd); 182 __pd_power_up(sh7372_pd, false);
178} 183}
179 184
180void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd, 185void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
@@ -227,11 +232,23 @@ struct sh7372_pm_domain sh7372_a3sp = {
227 .no_debug = true, 232 .no_debug = true,
228}; 233};
229 234
235static void sh7372_a3sp_init(void)
236{
237 /* serial consoles make use of SCIF hardware located in A3SP,
238 * keep such power domain on if "no_console_suspend" is set.
239 */
240 sh7372_a3sp.stay_on = !console_suspend_enabled;
241}
242
230struct sh7372_pm_domain sh7372_a3sg = { 243struct sh7372_pm_domain sh7372_a3sg = {
231 .bit_shift = 13, 244 .bit_shift = 13,
232}; 245};
233 246
234#endif /* CONFIG_PM */ 247#else /* !CONFIG_PM */
248
249static inline void sh7372_a3sp_init(void) {}
250
251#endif /* !CONFIG_PM */
235 252
236#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) 253#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
237static int sh7372_do_idle_core_standby(unsigned long unused) 254static int sh7372_do_idle_core_standby(unsigned long unused)
@@ -465,6 +482,8 @@ void __init sh7372_pm_init(void)
465 /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */ 482 /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
466 __raw_writel(0, PDNSEL); 483 __raw_writel(0, PDNSEL);
467 484
485 sh7372_a3sp_init();
486
468 sh7372_suspend_init(); 487 sh7372_suspend_init();
469 sh7372_cpuidle_init(); 488 sh7372_cpuidle_init();
470} 489}
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index 7a1fa6adb7c3..5b0c38abacc1 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -422,7 +422,7 @@ struct platform_device nuc900_device_kpi = {
422 422
423/* LCD controller*/ 423/* LCD controller*/
424 424
425static struct nuc900fb_display __initdata nuc900_lcd_info[] = { 425static struct nuc900fb_display nuc900_lcd_info[] = {
426 /* Giantplus Technology GPM1040A0 320x240 Color TFT LCD */ 426 /* Giantplus Technology GPM1040A0 320x240 Color TFT LCD */
427 [0] = { 427 [0] = {
428 .type = LCM_DCCS_VA_SRC_RGB565, 428 .type = LCM_DCCS_VA_SRC_RGB565,
@@ -445,7 +445,7 @@ static struct nuc900fb_display __initdata nuc900_lcd_info[] = {
445 }, 445 },
446}; 446};
447 447
448static struct nuc900fb_mach_info nuc900_fb_info __initdata = { 448static struct nuc900fb_mach_info nuc900_fb_info = {
449#if defined(CONFIG_GPM1040A0_320X240) 449#if defined(CONFIG_GPM1040A0_320X240)
450 .displays = &nuc900_lcd_info[0], 450 .displays = &nuc900_lcd_info[0],
451#else 451#else
diff --git a/arch/arm/mach-w90x900/include/mach/mfp.h b/arch/arm/mach-w90x900/include/mach/mfp.h
index 94c0e71617c6..23ef1f573abd 100644
--- a/arch/arm/mach-w90x900/include/mach/mfp.h
+++ b/arch/arm/mach-w90x900/include/mach/mfp.h
@@ -19,6 +19,7 @@
19extern void mfp_set_groupf(struct device *dev); 19extern void mfp_set_groupf(struct device *dev);
20extern void mfp_set_groupc(struct device *dev); 20extern void mfp_set_groupc(struct device *dev);
21extern void mfp_set_groupi(struct device *dev); 21extern void mfp_set_groupi(struct device *dev);
22extern void mfp_set_groupg(struct device *dev); 22extern void mfp_set_groupg(struct device *dev, const char *subname);
23extern void mfp_set_groupd(struct device *dev, const char *subname);
23 24
24#endif /* __ASM_ARCH_MFP_H */ 25#endif /* __ASM_ARCH_MFP_H */
diff --git a/arch/arm/mach-w90x900/include/mach/nuc900_spi.h b/arch/arm/mach-w90x900/include/mach/nuc900_spi.h
index bd94819e314f..2c4e0c128501 100644
--- a/arch/arm/mach-w90x900/include/mach/nuc900_spi.h
+++ b/arch/arm/mach-w90x900/include/mach/nuc900_spi.h
@@ -14,7 +14,7 @@
14#ifndef __ASM_ARCH_SPI_H 14#ifndef __ASM_ARCH_SPI_H
15#define __ASM_ARCH_SPI_H 15#define __ASM_ARCH_SPI_H
16 16
17extern void mfp_set_groupg(struct device *dev); 17extern void mfp_set_groupg(struct device *dev, const char *subname);
18 18
19struct nuc900_spi_info { 19struct nuc900_spi_info {
20 unsigned int num_cs; 20 unsigned int num_cs;
diff --git a/arch/arm/mach-w90x900/mfp.c b/arch/arm/mach-w90x900/mfp.c
index fb7fb627b1a5..9dd74612bb87 100644
--- a/arch/arm/mach-w90x900/mfp.c
+++ b/arch/arm/mach-w90x900/mfp.c
@@ -26,10 +26,8 @@
26#define REG_MFSEL (W90X900_VA_GCR + 0xC) 26#define REG_MFSEL (W90X900_VA_GCR + 0xC)
27 27
28#define GPSELF (0x01 << 1) 28#define GPSELF (0x01 << 1)
29
30#define GPSELC (0x03 << 2) 29#define GPSELC (0x03 << 2)
31#define ENKPI (0x02 << 2) 30#define GPSELD (0x0f << 4)
32#define ENNAND (0x01 << 2)
33 31
34#define GPSELEI0 (0x01 << 26) 32#define GPSELEI0 (0x01 << 26)
35#define GPSELEI1 (0x01 << 27) 33#define GPSELEI1 (0x01 << 27)
@@ -37,11 +35,16 @@
37#define GPIOG0TO1 (0x03 << 14) 35#define GPIOG0TO1 (0x03 << 14)
38#define GPIOG2TO3 (0x03 << 16) 36#define GPIOG2TO3 (0x03 << 16)
39#define GPIOG22TO23 (0x03 << 22) 37#define GPIOG22TO23 (0x03 << 22)
38#define GPIOG18TO20 (0x07 << 18)
40 39
41#define ENSPI (0x0a << 14) 40#define ENSPI (0x0a << 14)
42#define ENI2C0 (0x01 << 14) 41#define ENI2C0 (0x01 << 14)
43#define ENI2C1 (0x01 << 16) 42#define ENI2C1 (0x01 << 16)
44#define ENAC97 (0x02 << 22) 43#define ENAC97 (0x02 << 22)
44#define ENSD1 (0x02 << 18)
45#define ENSD0 (0x0a << 4)
46#define ENKPI (0x02 << 2)
47#define ENNAND (0x01 << 2)
45 48
46static DEFINE_MUTEX(mfp_mutex); 49static DEFINE_MUTEX(mfp_mutex);
47 50
@@ -127,16 +130,19 @@ void mfp_set_groupi(struct device *dev)
127} 130}
128EXPORT_SYMBOL(mfp_set_groupi); 131EXPORT_SYMBOL(mfp_set_groupi);
129 132
130void mfp_set_groupg(struct device *dev) 133void mfp_set_groupg(struct device *dev, const char *subname)
131{ 134{
132 unsigned long mfpen; 135 unsigned long mfpen;
133 const char *dev_id; 136 const char *dev_id;
134 137
135 BUG_ON(!dev); 138 BUG_ON((!dev) && (!subname));
136 139
137 mutex_lock(&mfp_mutex); 140 mutex_lock(&mfp_mutex);
138 141
139 dev_id = dev_name(dev); 142 if (subname != NULL)
143 dev_id = subname;
144 else
145 dev_id = dev_name(dev);
140 146
141 mfpen = __raw_readl(REG_MFSEL); 147 mfpen = __raw_readl(REG_MFSEL);
142 148
@@ -152,6 +158,9 @@ void mfp_set_groupg(struct device *dev)
152 } else if (strcmp(dev_id, "nuc900-audio") == 0) { 158 } else if (strcmp(dev_id, "nuc900-audio") == 0) {
153 mfpen &= ~(GPIOG22TO23); 159 mfpen &= ~(GPIOG22TO23);
154 mfpen |= ENAC97;/*enable AC97*/ 160 mfpen |= ENAC97;/*enable AC97*/
161 } else if (strcmp(dev_id, "nuc900-mmc-port1") == 0) {
162 mfpen &= ~(GPIOG18TO20);
163 mfpen |= (ENSD1 | 0x01);/*enable sd1*/
155 } else { 164 } else {
156 mfpen &= ~(GPIOG0TO1 | GPIOG2TO3);/*GPIOG[3:0]*/ 165 mfpen &= ~(GPIOG0TO1 | GPIOG2TO3);/*GPIOG[3:0]*/
157 } 166 }
@@ -162,3 +171,30 @@ void mfp_set_groupg(struct device *dev)
162} 171}
163EXPORT_SYMBOL(mfp_set_groupg); 172EXPORT_SYMBOL(mfp_set_groupg);
164 173
174void mfp_set_groupd(struct device *dev, const char *subname)
175{
176 unsigned long mfpen;
177 const char *dev_id;
178
179 BUG_ON((!dev) && (!subname));
180
181 mutex_lock(&mfp_mutex);
182
183 if (subname != NULL)
184 dev_id = subname;
185 else
186 dev_id = dev_name(dev);
187
188 mfpen = __raw_readl(REG_MFSEL);
189
190 if (strcmp(dev_id, "nuc900-mmc-port0") == 0) {
191 mfpen &= ~GPSELD;/*enable sd0*/
192 mfpen |= ENSD0;
193 } else
194 mfpen &= (~GPSELD);
195
196 __raw_writel(mfpen, REG_MFSEL);
197
198 mutex_unlock(&mfp_mutex);
199}
200EXPORT_SYMBOL(mfp_set_groupd);
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 8ac9e9f84790..b1e192ba8c24 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -61,7 +61,7 @@ static inline void cache_sync(void)
61{ 61{
62 void __iomem *base = l2x0_base; 62 void __iomem *base = l2x0_base;
63 63
64#ifdef CONFIG_ARM_ERRATA_753970 64#ifdef CONFIG_PL310_ERRATA_753970
65 /* write to an unmmapped register */ 65 /* write to an unmmapped register */
66 writel_relaxed(0, base + L2X0_DUMMY_REG); 66 writel_relaxed(0, base + L2X0_DUMMY_REG);
67#else 67#else
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index e4e7f6cba1ab..1aa664a1999f 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -168,7 +168,7 @@ static int __init consistent_init(void)
168 pte_t *pte; 168 pte_t *pte;
169 int i = 0; 169 int i = 0;
170 unsigned long base = consistent_base; 170 unsigned long base = consistent_base;
171 unsigned long num_ptes = (CONSISTENT_END - base) >> PGDIR_SHIFT; 171 unsigned long num_ptes = (CONSISTENT_END - base) >> PMD_SHIFT;
172 172
173 consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL); 173 consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL);
174 if (!consistent_pte) { 174 if (!consistent_pte) {
@@ -332,6 +332,15 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
332 struct page *page; 332 struct page *page;
333 void *addr; 333 void *addr;
334 334
335 /*
336 * Following is a work-around (a.k.a. hack) to prevent pages
337 * with __GFP_COMP being passed to split_page() which cannot
338 * handle them. The real problem is that this flag probably
339 * should be 0 on ARM as it is not supported on this
340 * platform; see CONFIG_HUGETLBFS.
341 */
342 gfp &= ~(__GFP_COMP);
343
335 *handle = ~0; 344 *handle = ~0;
336 size = PAGE_ALIGN(size); 345 size = PAGE_ALIGN(size);
337 346
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index 74be05f3e03a..44b628e4d6ea 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -9,8 +9,7 @@
9#include <linux/io.h> 9#include <linux/io.h>
10#include <linux/personality.h> 10#include <linux/personality.h>
11#include <linux/random.h> 11#include <linux/random.h>
12#include <asm/cputype.h> 12#include <asm/cachetype.h>
13#include <asm/system.h>
14 13
15#define COLOUR_ALIGN(addr,pgoff) \ 14#define COLOUR_ALIGN(addr,pgoff) \
16 ((((addr)+SHMLBA-1)&~(SHMLBA-1)) + \ 15 ((((addr)+SHMLBA-1)&~(SHMLBA-1)) + \
@@ -32,25 +31,15 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
32 struct mm_struct *mm = current->mm; 31 struct mm_struct *mm = current->mm;
33 struct vm_area_struct *vma; 32 struct vm_area_struct *vma;
34 unsigned long start_addr; 33 unsigned long start_addr;
35#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) 34 int do_align = 0;
36 unsigned int cache_type; 35 int aliasing = cache_is_vipt_aliasing();
37 int do_align = 0, aliasing = 0;
38 36
39 /* 37 /*
40 * We only need to do colour alignment if either the I or D 38 * We only need to do colour alignment if either the I or D
41 * caches alias. This is indicated by bits 9 and 21 of the 39 * caches alias.
42 * cache type register.
43 */ 40 */
44 cache_type = read_cpuid_cachetype(); 41 if (aliasing)
45 if (cache_type != read_cpuid_id()) { 42 do_align = filp || (flags & MAP_SHARED);
46 aliasing = (cache_type | cache_type >> 12) & (1 << 11);
47 if (aliasing)
48 do_align = filp || flags & MAP_SHARED;
49 }
50#else
51#define do_align 0
52#define aliasing 0
53#endif
54 43
55 /* 44 /*
56 * We enforce the MAP_FIXED case. 45 * We enforce the MAP_FIXED case.
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 14b4703e6e46..6698cae942f7 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -85,7 +85,6 @@ enum mxc_cpu_pwr_mode {
85}; 85};
86 86
87extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); 87extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
88extern void (*imx_idle)(void);
89extern void imx_print_silicon_rev(const char *cpu, int srev); 88extern void imx_print_silicon_rev(const char *cpu, int srev);
90 89
91void avic_handle_irq(struct pt_regs *); 90void avic_handle_irq(struct pt_regs *);
@@ -132,4 +131,5 @@ extern void imx53_qsb_common_init(void);
132extern void imx53_smd_common_init(void); 131extern void imx53_smd_common_init(void);
133extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); 132extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
134extern void imx6q_pm_init(void); 133extern void imx6q_pm_init(void);
134extern void imx6q_clock_map_io(void);
135#endif 135#endif
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 00a78193c681..a4d36d601d55 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -50,20 +50,6 @@
50#define IMX_CHIP_REVISION_3_3 0x33 50#define IMX_CHIP_REVISION_3_3 0x33
51#define IMX_CHIP_REVISION_UNKNOWN 0xff 51#define IMX_CHIP_REVISION_UNKNOWN 0xff
52 52
53#define IMX_CHIP_REVISION_1_0_STRING "1.0"
54#define IMX_CHIP_REVISION_1_1_STRING "1.1"
55#define IMX_CHIP_REVISION_1_2_STRING "1.2"
56#define IMX_CHIP_REVISION_1_3_STRING "1.3"
57#define IMX_CHIP_REVISION_2_0_STRING "2.0"
58#define IMX_CHIP_REVISION_2_1_STRING "2.1"
59#define IMX_CHIP_REVISION_2_2_STRING "2.2"
60#define IMX_CHIP_REVISION_2_3_STRING "2.3"
61#define IMX_CHIP_REVISION_3_0_STRING "3.0"
62#define IMX_CHIP_REVISION_3_1_STRING "3.1"
63#define IMX_CHIP_REVISION_3_2_STRING "3.2"
64#define IMX_CHIP_REVISION_3_3_STRING "3.3"
65#define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown"
66
67#ifndef __ASSEMBLY__ 53#ifndef __ASSEMBLY__
68extern unsigned int __mxc_cpu_type; 54extern unsigned int __mxc_cpu_type;
69#endif 55#endif
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index cf88b3593fba..b9895d250167 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -17,14 +17,9 @@
17#ifndef __ASM_ARCH_MXC_SYSTEM_H__ 17#ifndef __ASM_ARCH_MXC_SYSTEM_H__
18#define __ASM_ARCH_MXC_SYSTEM_H__ 18#define __ASM_ARCH_MXC_SYSTEM_H__
19 19
20extern void (*imx_idle)(void);
21
22static inline void arch_idle(void) 20static inline void arch_idle(void)
23{ 21{
24 if (imx_idle != NULL) 22 cpu_do_idle();
25 (imx_idle)();
26 else
27 cpu_do_idle();
28} 23}
29 24
30void arch_reset(char mode, const char *cmd); 25void arch_reset(char mode, const char *cmd);
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index b1cfc6a49715..7e5c76ea4466 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -21,6 +21,7 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/err.h> 22#include <linux/err.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/module.h>
24 25
25#include <mach/hardware.h> 26#include <mach/hardware.h>
26#include <mach/common.h> 27#include <mach/common.h>
@@ -28,8 +29,8 @@
28#include <asm/system.h> 29#include <asm/system.h>
29#include <asm/mach-types.h> 30#include <asm/mach-types.h>
30 31
31void (*imx_idle)(void) = NULL;
32void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL; 32void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
33EXPORT_SYMBOL_GPL(imx_ioremap);
33 34
34static void __iomem *wdog_base; 35static void __iomem *wdog_base;
35 36
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 197ca03c3f7d..eb73ab40e955 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -165,8 +165,8 @@ struct dpll_data {
165 u8 auto_recal_bit; 165 u8 auto_recal_bit;
166 u8 recal_en_bit; 166 u8 recal_en_bit;
167 u8 recal_st_bit; 167 u8 recal_st_bit;
168 u8 flags;
169# endif 168# endif
169 u8 flags;
170}; 170};
171 171
172#endif 172#endif
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 346098fb9219..257f9770b2da 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -28,11 +28,14 @@
28#define __ARCH_ARM_MACH_OMAP_COMMON_H 28#define __ARCH_ARM_MACH_OMAP_COMMON_H
29 29
30#include <plat/i2c.h> 30#include <plat/i2c.h>
31#include <plat/omap_hwmod.h>
31 32
32extern int __init omap_init_clocksource_32k(void); 33extern int __init omap_init_clocksource_32k(void);
33extern unsigned long long notrace omap_32k_sched_clock(void); 34extern unsigned long long notrace omap_32k_sched_clock(void);
34 35
35extern void omap_reserve(void); 36extern void omap_reserve(void);
37extern int omap_dss_reset(struct omap_hwmod *);
38
36void omap_sram_init(void); 39void omap_sram_init(void);
37 40
38#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ 41#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c b/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
index a9276667c2fb..c7adad0e8de0 100644
--- a/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
+++ b/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
@@ -12,7 +12,7 @@
12*/ 12*/
13 13
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/module.h> 15#include <linux/export.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/ioport.h> 17#include <linux/ioport.h>
18#include <linux/cpufreq.h> 18#include <linux/cpufreq.h>
diff --git a/arch/arm/plat-s5p/sysmmu.c b/arch/arm/plat-s5p/sysmmu.c
index e1cbc728c775..c8bec9c7655d 100644
--- a/arch/arm/plat-s5p/sysmmu.c
+++ b/arch/arm/plat-s5p/sysmmu.c
@@ -11,6 +11,7 @@
11#include <linux/io.h> 11#include <linux/io.h>
12#include <linux/interrupt.h> 12#include <linux/interrupt.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/export.h>
14 15
15#include <asm/pgtable.h> 16#include <asm/pgtable.h>
16 17
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index d48245bb02b3..df8155b9d4d1 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -24,6 +24,8 @@
24#ifndef __PLAT_GPIO_CFG_H 24#ifndef __PLAT_GPIO_CFG_H
25#define __PLAT_GPIO_CFG_H __FILE__ 25#define __PLAT_GPIO_CFG_H __FILE__
26 26
27#include<linux/types.h>
28
27typedef unsigned int __bitwise__ samsung_gpio_pull_t; 29typedef unsigned int __bitwise__ samsung_gpio_pull_t;
28typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; 30typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
29 31
diff --git a/arch/arm/plat-samsung/pd.c b/arch/arm/plat-samsung/pd.c
index efe1d564473e..312b510d86b7 100644
--- a/arch/arm/plat-samsung/pd.c
+++ b/arch/arm/plat-samsung/pd.c
@@ -11,7 +11,7 @@
11*/ 11*/
12 12
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/module.h> 14#include <linux/export.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/pm_runtime.h> 17#include <linux/pm_runtime.h>
diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c
index dc1185dcf80d..c559d8438c70 100644
--- a/arch/arm/plat-samsung/pwm.c
+++ b/arch/arm/plat-samsung/pwm.c
@@ -11,7 +11,7 @@
11 * the Free Software Foundation; either version 2 of the License. 11 * the Free Software Foundation; either version 2 of the License.
12*/ 12*/
13 13
14#include <linux/module.h> 14#include <linux/export.h>
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/slab.h> 17#include <linux/slab.h>
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 5bdeef969847..ccbe16f47227 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -1123,5 +1123,6 @@ blissc MACH_BLISSC BLISSC 3491
1123thales_adc MACH_THALES_ADC THALES_ADC 3492 1123thales_adc MACH_THALES_ADC THALES_ADC 3492
1124ubisys_p9d_evp MACH_UBISYS_P9D_EVP UBISYS_P9D_EVP 3493 1124ubisys_p9d_evp MACH_UBISYS_P9D_EVP UBISYS_P9D_EVP 3493
1125atdgp318 MACH_ATDGP318 ATDGP318 3494 1125atdgp318 MACH_ATDGP318 ATDGP318 3494
1126m28evk MACH_M28EVK M28EVK 3613
1126smdk4212 MACH_SMDK4212 SMDK4212 3638 1127smdk4212 MACH_SMDK4212 SMDK4212 3638
1127smdk4412 MACH_SMDK4412 SMDK4412 3765 1128smdk4412 MACH_SMDK4412 SMDK4412 3765
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 19:43:58 -0500