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authorKumar Gala <galak@codeaurora.org>2014-03-07 11:56:59 -0500
committerKumar Gala <galak@codeaurora.org>2014-08-21 12:43:34 -0400
commit68de308b1c02f3b11705406b07e84790eb1a37e9 (patch)
tree2fa3b02b15381c50d086ed61114f3e87e10c5396 /arch/arm
parent14ff1c43881aa8f43d0ec0fa264dc9ed995f801b (diff)
ARM: qcom: Add initial IPQ8064 SoC and AP148 device trees
Add basic IPQ8064 SoC include device tree and support for basic booting on the AP148 Reference board with support for UART, I2C, and SPI. Signed-off-by: Kumar Gala <galak@codeaurora.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064-ap148.dts85
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi1
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064.dtsi250
-rw-r--r--arch/arm/mach-qcom/board.c2
5 files changed, 339 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b8c5cd3ddeb9..a097a042bdb3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -342,6 +342,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
342 qcom-apq8064-ifc6410.dtb \ 342 qcom-apq8064-ifc6410.dtb \
343 qcom-apq8074-dragonboard.dtb \ 343 qcom-apq8074-dragonboard.dtb \
344 qcom-apq8084-mtp.dtb \ 344 qcom-apq8084-mtp.dtb \
345 qcom-ipq8064-ap148.dtb \
345 qcom-msm8660-surf.dtb \ 346 qcom-msm8660-surf.dtb \
346 qcom-msm8960-cdp.dtb 347 qcom-msm8960-cdp.dtb
347dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 348dtb-$(CONFIG_ARCH_ROCKCHIP) += \
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
new file mode 100644
index 000000000000..95e64955fb8e
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -0,0 +1,85 @@
1#include "qcom-ipq8064-v1.0.dtsi"
2
3/ {
4 model = "Qualcomm IPQ8064/AP148";
5 compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
6
7 reserved-memory {
8 #address-cells = <1>;
9 #size-cells = <1>;
10 ranges;
11 rsvd@41200000 {
12 reg = <0x41200000 0x300000>;
13 no-map;
14 };
15 };
16
17 soc {
18 pinmux@800000 {
19 i2c4_pins: i2c4_pinmux {
20 pins = "gpio12", "gpio13";
21 function = "gsbi4";
22 bias-disable;
23 };
24
25 spi_pins: spi_pins {
26 mux {
27 pins = "gpio18", "gpio19", "gpio21";
28 function = "gsbi5";
29 drive-strength = <10>;
30 bias-none;
31 };
32 };
33 };
34
35 gsbi@16300000 {
36 qcom,mode = <GSBI_PROT_I2C_UART>;
37 status = "ok";
38 serial@16340000 {
39 status = "ok";
40 };
41
42 i2c4: i2c@16380000 {
43 status = "ok";
44
45 clock-frequency = <200000>;
46
47 pinctrl-0 = <&i2c4_pins>;
48 pinctrl-names = "default";
49 };
50 };
51
52 gsbi5: gsbi@1a200000 {
53 qcom,mode = <GSBI_PROT_SPI>;
54 status = "ok";
55
56 spi4: spi@1a280000 {
57 status = "ok";
58 spi-max-frequency = <50000000>;
59
60 pinctrl-0 = <&spi_pins>;
61 pinctrl-names = "default";
62
63 cs-gpios = <&qcom_pinmux 20 0>;
64
65 flash: m25p80@0 {
66 compatible = "s25fl256s1";
67 #address-cells = <1>;
68 #size-cells = <1>;
69 spi-max-frequency = <50000000>;
70 reg = <0>;
71
72 partition@0 {
73 label = "rootfs";
74 reg = <0x0 0x1000000>;
75 };
76
77 partition@1 {
78 label = "scratch";
79 reg = <0x1000000 0x1000000>;
80 };
81 };
82 };
83 };
84 };
85};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
new file mode 100644
index 000000000000..7093b075e408
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
@@ -0,0 +1 @@
#include "qcom-ipq8064.dtsi"
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
new file mode 100644
index 000000000000..244f857f0e6f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -0,0 +1,250 @@
1/dts-v1/;
2
3#include "skeleton.dtsi"
4#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5#include <dt-bindings/soc/qcom,gsbi.h>
6
7/ {
8 model = "Qualcomm IPQ8064";
9 compatible = "qcom,ipq8064";
10 interrupt-parent = <&intc>;
11
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 cpu@0 {
17 compatible = "qcom,krait";
18 enable-method = "qcom,kpss-acc-v1";
19 device_type = "cpu";
20 reg = <0>;
21 next-level-cache = <&L2>;
22 qcom,acc = <&acc0>;
23 qcom,saw = <&saw0>;
24 };
25
26 cpu@1 {
27 compatible = "qcom,krait";
28 enable-method = "qcom,kpss-acc-v1";
29 device_type = "cpu";
30 reg = <1>;
31 next-level-cache = <&L2>;
32 qcom,acc = <&acc1>;
33 qcom,saw = <&saw1>;
34 };
35
36 L2: l2-cache {
37 compatible = "cache";
38 cache-level = <2>;
39 };
40 };
41
42 cpu-pmu {
43 compatible = "qcom,krait-pmu";
44 interrupts = <1 10 0x304>;
45 };
46
47 reserved-memory {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 ranges;
51
52 nss@40000000 {
53 reg = <0x40000000 0x1000000>;
54 no-map;
55 };
56
57 smem@41000000 {
58 reg = <0x41000000 0x200000>;
59 no-map;
60 };
61 };
62
63 soc: soc {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 ranges;
67 compatible = "simple-bus";
68
69 qcom_pinmux: pinmux@800000 {
70 compatible = "qcom,ipq8064-pinctrl";
71 reg = <0x800000 0x4000>;
72
73 gpio-controller;
74 #gpio-cells = <2>;
75 interrupt-controller;
76 #interrupt-cells = <2>;
77 interrupts = <0 32 0x4>;
78 };
79
80 intc: interrupt-controller@2000000 {
81 compatible = "qcom,msm-qgic2";
82 interrupt-controller;
83 #interrupt-cells = <3>;
84 reg = <0x02000000 0x1000>,
85 <0x02002000 0x1000>;
86 };
87
88 timer@200a000 {
89 compatible = "qcom,kpss-timer", "qcom,msm-timer";
90 interrupts = <1 1 0x301>,
91 <1 2 0x301>,
92 <1 3 0x301>;
93 reg = <0x0200a000 0x100>;
94 clock-frequency = <25000000>,
95 <32768>;
96 cpu-offset = <0x80000>;
97 };
98
99 acc0: clock-controller@2088000 {
100 compatible = "qcom,kpss-acc-v1";
101 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
102 };
103
104 acc1: clock-controller@2098000 {
105 compatible = "qcom,kpss-acc-v1";
106 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
107 };
108
109 saw0: regulator@2089000 {
110 compatible = "qcom,saw2";
111 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
112 regulator;
113 };
114
115 saw1: regulator@2099000 {
116 compatible = "qcom,saw2";
117 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
118 regulator;
119 };
120
121 gsbi2: gsbi@12480000 {
122 compatible = "qcom,gsbi-v1.0.0";
123 reg = <0x12480000 0x100>;
124 clocks = <&gcc GSBI2_H_CLK>;
125 clock-names = "iface";
126 #address-cells = <1>;
127 #size-cells = <1>;
128 ranges;
129 status = "disabled";
130
131 serial@12490000 {
132 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
133 reg = <0x12490000 0x1000>,
134 <0x12480000 0x1000>;
135 interrupts = <0 195 0x0>;
136 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
137 clock-names = "core", "iface";
138 status = "disabled";
139 };
140
141 i2c@124a0000 {
142 compatible = "qcom,i2c-qup-v1.1.1";
143 reg = <0x124a0000 0x1000>;
144 interrupts = <0 196 0>;
145
146 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
147 clock-names = "core", "iface";
148 status = "disabled";
149
150 #address-cells = <1>;
151 #size-cells = <0>;
152 };
153
154 };
155
156 gsbi4: gsbi@16300000 {
157 compatible = "qcom,gsbi-v1.0.0";
158 reg = <0x16300000 0x100>;
159 clocks = <&gcc GSBI4_H_CLK>;
160 clock-names = "iface";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges;
164 status = "disabled";
165
166 serial@16340000 {
167 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
168 reg = <0x16340000 0x1000>,
169 <0x16300000 0x1000>;
170 interrupts = <0 152 0x0>;
171 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
172 clock-names = "core", "iface";
173 status = "disabled";
174 };
175
176 i2c@16380000 {
177 compatible = "qcom,i2c-qup-v1.1.1";
178 reg = <0x16380000 0x1000>;
179 interrupts = <0 153 0>;
180
181 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
182 clock-names = "core", "iface";
183 status = "disabled";
184
185 #address-cells = <1>;
186 #size-cells = <0>;
187 };
188 };
189
190 gsbi5: gsbi@1a200000 {
191 compatible = "qcom,gsbi-v1.0.0";
192 reg = <0x1a200000 0x100>;
193 clocks = <&gcc GSBI5_H_CLK>;
194 clock-names = "iface";
195 #address-cells = <1>;
196 #size-cells = <1>;
197 ranges;
198 status = "disabled";
199
200 serial@1a240000 {
201 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
202 reg = <0x1a240000 0x1000>,
203 <0x1a200000 0x1000>;
204 interrupts = <0 154 0x0>;
205 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
206 clock-names = "core", "iface";
207 status = "disabled";
208 };
209
210 i2c@1a280000 {
211 compatible = "qcom,i2c-qup-v1.1.1";
212 reg = <0x1a280000 0x1000>;
213 interrupts = <0 155 0>;
214
215 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
216 clock-names = "core", "iface";
217 status = "disabled";
218
219 #address-cells = <1>;
220 #size-cells = <0>;
221 };
222
223 spi@1a280000 {
224 compatible = "qcom,spi-qup-v1.1.1";
225 reg = <0x1a280000 0x1000>;
226 interrupts = <0 155 0>;
227
228 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
229 clock-names = "core", "iface";
230 status = "disabled";
231
232 #address-cells = <1>;
233 #size-cells = <0>;
234 };
235 };
236
237 qcom,ssbi@500000 {
238 compatible = "qcom,ssbi";
239 reg = <0x00500000 0x1000>;
240 qcom,controller-type = "pmic-arbiter";
241 };
242
243 gcc: clock-controller@900000 {
244 compatible = "qcom,gcc-ipq8064";
245 reg = <0x00900000 0x4000>;
246 #clock-cells = <1>;
247 #reset-cells = <1>;
248 };
249 };
250};
diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
index c437a9941726..6d8bbf7d39d8 100644
--- a/arch/arm/mach-qcom/board.c
+++ b/arch/arm/mach-qcom/board.c
@@ -18,6 +18,8 @@ static const char * const qcom_dt_match[] __initconst = {
18 "qcom,apq8064", 18 "qcom,apq8064",
19 "qcom,apq8074-dragonboard", 19 "qcom,apq8074-dragonboard",
20 "qcom,apq8084", 20 "qcom,apq8084",
21 "qcom,ipq8062",
22 "qcom,ipq8064",
21 "qcom,msm8660-surf", 23 "qcom,msm8660-surf",
22 "qcom,msm8960-cdp", 24 "qcom,msm8960-cdp",
23 NULL 25 NULL
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 08:24:35 -0400