diff options
| author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-08-03 10:15:29 -0400 |
|---|---|---|
| committer | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-09-27 09:46:20 -0400 |
| commit | 68b5e858dde8dcb0413b7c1d699c1056ecc0934d (patch) | |
| tree | 9c32690770575b3a083ab2d5d4da7c65981be436 /arch/arm | |
| parent | 5a2db4e3865868c3bf230435fb312524c0e10bd4 (diff) | |
ARM: mx51: fix naming of spi related defines
The names used now match the processor's reference manual. Also remove
MXC from the interrupt defines to match the other imx platforms.
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Jason Wang <jason77.wang@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx51.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 92b39f7256e9..d0fda396adf2 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h | |||
| @@ -67,7 +67,7 @@ | |||
| 67 | #define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) | 67 | #define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) |
| 68 | #define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000) | 68 | #define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000) |
| 69 | #define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000) | 69 | #define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000) |
| 70 | #define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000) | 70 | #define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000) |
| 71 | #define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000) | 71 | #define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000) |
| 72 | #define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000) | 72 | #define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000) |
| 73 | #define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000) | 73 | #define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000) |
| @@ -121,12 +121,12 @@ | |||
| 121 | #define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000) | 121 | #define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000) |
| 122 | #define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000) | 122 | #define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000) |
| 123 | #define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000) | 123 | #define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000) |
| 124 | #define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000) | 124 | #define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000) |
| 125 | #define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000) | 125 | #define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000) |
| 126 | #define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000) | 126 | #define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000) |
| 127 | #define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000) | 127 | #define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000) |
| 128 | #define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000) | 128 | #define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000) |
| 129 | #define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000) | 129 | #define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000) |
| 130 | #define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000) | 130 | #define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000) |
| 131 | #define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000) | 131 | #define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000) |
| 132 | #define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000) | 132 | #define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000) |
| @@ -346,9 +346,9 @@ | |||
| 346 | #define MX51_MXC_INT_UART3 33 | 346 | #define MX51_MXC_INT_UART3 33 |
| 347 | #define MX51_MXC_INT_RESV34 34 | 347 | #define MX51_MXC_INT_RESV34 34 |
| 348 | #define MX51_MXC_INT_RESV35 35 | 348 | #define MX51_MXC_INT_RESV35 35 |
| 349 | #define MX51_MXC_INT_CSPI1 36 | 349 | #define MX51_INT_ECSPI1 36 |
| 350 | #define MX51_MXC_INT_CSPI2 37 | 350 | #define MX51_INT_ECSPI2 37 |
| 351 | #define MX51_MXC_INT_CSPI 38 | 351 | #define MX51_INT_CSPI 38 |
| 352 | #define MX51_MXC_INT_GPT 39 | 352 | #define MX51_MXC_INT_GPT 39 |
| 353 | #define MX51_MXC_INT_EPIT1 40 | 353 | #define MX51_MXC_INT_EPIT1 40 |
| 354 | #define MX51_MXC_INT_EPIT2 41 | 354 | #define MX51_MXC_INT_EPIT2 41 |