diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-12-29 07:39:50 -0500 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-01-15 18:28:50 -0500 |
commit | 4adf2b4bd303e73dfc13c3428383a8dba129fdb5 (patch) | |
tree | ad4d71e3fa9165efc33f1296e9760aa53fbf3e3b /arch/arm | |
parent | 1e42fa04afb0dae65292683a5dcad85572ab7553 (diff) |
ARM: fix footbridge clockevent device
commit 4ff859fe1dc0da0f87bbdfff78f527898878fa4a upstream.
The clockevents code was being told that the footbridge clock event
device ticks at 16x the rate which it actually does. This leads to
timekeeping problems since it allows the clocksource to wrap before
the kernel notices. Fix this by using the correct clock.
Fixes: 4e8d76373c9fd ("ARM: footbridge: convert to clockevents/clocksource")
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-footbridge/dc21285-timer.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index 9ee78f7b4990..782f6c71fa0a 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c | |||
@@ -96,11 +96,12 @@ static struct irqaction footbridge_timer_irq = { | |||
96 | void __init footbridge_timer_init(void) | 96 | void __init footbridge_timer_init(void) |
97 | { | 97 | { |
98 | struct clock_event_device *ce = &ckevt_dc21285; | 98 | struct clock_event_device *ce = &ckevt_dc21285; |
99 | unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16); | ||
99 | 100 | ||
100 | clocksource_register_hz(&cksrc_dc21285, (mem_fclk_21285 + 8) / 16); | 101 | clocksource_register_hz(&cksrc_dc21285, rate); |
101 | 102 | ||
102 | setup_irq(ce->irq, &footbridge_timer_irq); | 103 | setup_irq(ce->irq, &footbridge_timer_irq); |
103 | 104 | ||
104 | ce->cpumask = cpumask_of(smp_processor_id()); | 105 | ce->cpumask = cpumask_of(smp_processor_id()); |
105 | clockevents_config_and_register(ce, mem_fclk_21285, 0x4, 0xffffff); | 106 | clockevents_config_and_register(ce, rate, 0x4, 0xffffff); |
106 | } | 107 | } |