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authorBen Dooks <ben-linux@fluff.org>2010-01-26 02:13:35 -0500
committerBen Dooks <ben-linux@fluff.org>2010-02-01 12:55:26 -0500
commit491547d43bc2393de914b5ad18b6f5219107f918 (patch)
tree105eb1aa178d7dd21890cefdd3965af6113a0881 /arch/arm
parent5cbcccb370355d4cd8534796bf32ac8bb04627cc (diff)
ARM: S3C2442: Merge s3c2442.c and clock.c
Merge s3c2442.c and clock.c as the s3c242.c does not contain much and the clock parts are always built for s3c2442 anyway. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-s3c2442/Makefile1
-rw-r--r--arch/arm/mach-s3c2442/clock.c153
-rw-r--r--arch/arm/mach-s3c2442/s3c2442.c153
3 files changed, 142 insertions, 165 deletions
diff --git a/arch/arm/mach-s3c2442/Makefile b/arch/arm/mach-s3c2442/Makefile
index 2a909c6c5798..7e31ccdc83de 100644
--- a/arch/arm/mach-s3c2442/Makefile
+++ b/arch/arm/mach-s3c2442/Makefile
@@ -10,7 +10,6 @@ obj-n :=
10obj- := 10obj- :=
11 11
12obj-$(CONFIG_CPU_S3C2442) += s3c2442.o 12obj-$(CONFIG_CPU_S3C2442) += s3c2442.o
13obj-$(CONFIG_CPU_S3C2442) += clock.o
14 13
15# Machine support 14# Machine support
16 15
diff --git a/arch/arm/mach-s3c2442/clock.c b/arch/arm/mach-s3c2442/clock.c
deleted file mode 100644
index d9b692a12480..000000000000
--- a/arch/arm/mach-s3c2442/clock.c
+++ /dev/null
@@ -1,153 +0,0 @@
1/* linux/arch/arm/mach-s3c2442/clock.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2442 Clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/sysdev.h>
32#include <linux/interrupt.h>
33#include <linux/ioport.h>
34#include <linux/mutex.h>
35#include <linux/clk.h>
36#include <linux/io.h>
37
38#include <mach/hardware.h>
39#include <asm/atomic.h>
40#include <asm/irq.h>
41
42#include <mach/regs-clock.h>
43
44#include <plat/clock.h>
45#include <plat/cpu.h>
46
47/* S3C2442 extended clock support */
48
49static unsigned long s3c2442_camif_upll_round(struct clk *clk,
50 unsigned long rate)
51{
52 unsigned long parent_rate = clk_get_rate(clk->parent);
53 int div;
54
55 if (rate > parent_rate)
56 return parent_rate;
57
58 div = parent_rate / rate;
59
60 if (div == 3)
61 return parent_rate / 3;
62
63 /* note, we remove the +/- 1 calculations for the divisor */
64
65 div /= 2;
66
67 if (div < 1)
68 div = 1;
69 else if (div > 16)
70 div = 16;
71
72 return parent_rate / (div * 2);
73}
74
75static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
76{
77 unsigned long parent_rate = clk_get_rate(clk->parent);
78 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
79
80 rate = s3c2442_camif_upll_round(clk, rate);
81
82 camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
83
84 if (rate == parent_rate) {
85 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
86 } else if ((parent_rate / rate) == 3) {
87 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
88 camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
89 } else {
90 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
91 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
92 camdivn |= (((parent_rate / rate) / 2) - 1);
93 }
94
95 __raw_writel(camdivn, S3C2440_CAMDIVN);
96
97 return 0;
98}
99
100/* Extra S3C2442 clocks */
101
102static struct clk s3c2442_clk_cam = {
103 .name = "camif",
104 .id = -1,
105 .enable = s3c2410_clkcon_enable,
106 .ctrlbit = S3C2440_CLKCON_CAMERA,
107};
108
109static struct clk s3c2442_clk_cam_upll = {
110 .name = "camif-upll",
111 .id = -1,
112 .ops = &(struct clk_ops) {
113 .set_rate = s3c2442_camif_upll_setrate,
114 .round_rate = s3c2442_camif_upll_round,
115 },
116};
117
118static int s3c2442_clk_add(struct sys_device *sysdev)
119{
120 struct clk *clock_upll;
121 struct clk *clock_h;
122 struct clk *clock_p;
123
124 clock_p = clk_get(NULL, "pclk");
125 clock_h = clk_get(NULL, "hclk");
126 clock_upll = clk_get(NULL, "upll");
127
128 if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
129 printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
130 return -EINVAL;
131 }
132
133 s3c2442_clk_cam.parent = clock_h;
134 s3c2442_clk_cam_upll.parent = clock_upll;
135
136 s3c24xx_register_clock(&s3c2442_clk_cam);
137 s3c24xx_register_clock(&s3c2442_clk_cam_upll);
138
139 clk_disable(&s3c2442_clk_cam);
140
141 return 0;
142}
143
144static struct sysdev_driver s3c2442_clk_driver = {
145 .add = s3c2442_clk_add,
146};
147
148static __init int s3c2442_clk_init(void)
149{
150 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
151}
152
153arch_initcall(s3c2442_clk_init);
diff --git a/arch/arm/mach-s3c2442/s3c2442.c b/arch/arm/mach-s3c2442/s3c2442.c
index 4663bdc7fff6..188ad1e57dc0 100644
--- a/arch/arm/mach-s3c2442/s3c2442.c
+++ b/arch/arm/mach-s3c2442/s3c2442.c
@@ -1,27 +1,158 @@
1/* linux/arch/arm/mach-s3c2442/s3c2442.c 1/* linux/arch/arm/mach-s3c2442/s3c2442.c
2 * 2 *
3 * Copyright (c) 2006 Simtec Electronics 3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
5 * 6 *
6 * Samsung S3C2442 Mobile CPU support 7 * S3C2442 core and lock support
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License as published by
10 * published by the Free Software Foundation. 11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
11*/ 22*/
12 23
24#include <linux/init.h>
25#include <linux/module.h>
13#include <linux/kernel.h> 26#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h> 27#include <linux/list.h>
17#include <linux/timer.h> 28#include <linux/errno.h>
18#include <linux/init.h> 29#include <linux/err.h>
19#include <linux/serial_core.h> 30#include <linux/device.h>
20#include <linux/sysdev.h> 31#include <linux/sysdev.h>
32#include <linux/interrupt.h>
33#include <linux/ioport.h>
34#include <linux/mutex.h>
35#include <linux/clk.h>
36#include <linux/io.h>
21 37
22#include <plat/s3c2442.h> 38#include <mach/hardware.h>
39#include <asm/atomic.h>
40#include <asm/irq.h>
41
42#include <mach/regs-clock.h>
43
44#include <plat/clock.h>
23#include <plat/cpu.h> 45#include <plat/cpu.h>
24 46
47/* S3C2442 extended clock support */
48
49static unsigned long s3c2442_camif_upll_round(struct clk *clk,
50 unsigned long rate)
51{
52 unsigned long parent_rate = clk_get_rate(clk->parent);
53 int div;
54
55 if (rate > parent_rate)
56 return parent_rate;
57
58 div = parent_rate / rate;
59
60 if (div == 3)
61 return parent_rate / 3;
62
63 /* note, we remove the +/- 1 calculations for the divisor */
64
65 div /= 2;
66
67 if (div < 1)
68 div = 1;
69 else if (div > 16)
70 div = 16;
71
72 return parent_rate / (div * 2);
73}
74
75static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
76{
77 unsigned long parent_rate = clk_get_rate(clk->parent);
78 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
79
80 rate = s3c2442_camif_upll_round(clk, rate);
81
82 camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
83
84 if (rate == parent_rate) {
85 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
86 } else if ((parent_rate / rate) == 3) {
87 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
88 camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
89 } else {
90 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
91 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
92 camdivn |= (((parent_rate / rate) / 2) - 1);
93 }
94
95 __raw_writel(camdivn, S3C2440_CAMDIVN);
96
97 return 0;
98}
99
100/* Extra S3C2442 clocks */
101
102static struct clk s3c2442_clk_cam = {
103 .name = "camif",
104 .id = -1,
105 .enable = s3c2410_clkcon_enable,
106 .ctrlbit = S3C2440_CLKCON_CAMERA,
107};
108
109static struct clk s3c2442_clk_cam_upll = {
110 .name = "camif-upll",
111 .id = -1,
112 .ops = &(struct clk_ops) {
113 .set_rate = s3c2442_camif_upll_setrate,
114 .round_rate = s3c2442_camif_upll_round,
115 },
116};
117
118static int s3c2442_clk_add(struct sys_device *sysdev)
119{
120 struct clk *clock_upll;
121 struct clk *clock_h;
122 struct clk *clock_p;
123
124 clock_p = clk_get(NULL, "pclk");
125 clock_h = clk_get(NULL, "hclk");
126 clock_upll = clk_get(NULL, "upll");
127
128 if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
129 printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
130 return -EINVAL;
131 }
132
133 s3c2442_clk_cam.parent = clock_h;
134 s3c2442_clk_cam_upll.parent = clock_upll;
135
136 s3c24xx_register_clock(&s3c2442_clk_cam);
137 s3c24xx_register_clock(&s3c2442_clk_cam_upll);
138
139 clk_disable(&s3c2442_clk_cam);
140
141 return 0;
142}
143
144static struct sysdev_driver s3c2442_clk_driver = {
145 .add = s3c2442_clk_add,
146};
147
148static __init int s3c2442_clk_init(void)
149{
150 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
151}
152
153arch_initcall(s3c2442_clk_init);
154
155
25static struct sys_device s3c2442_sysdev = { 156static struct sys_device s3c2442_sysdev = {
26 .cls = &s3c2442_sysclass, 157 .cls = &s3c2442_sysclass,
27}; 158};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 13:31:45 -0500