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authorMaxime Ripard <maxime.ripard@free-electrons.com>2014-02-01 10:46:16 -0500
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-02-07 16:30:02 -0500
commit2f41898704d3cff796ea0adaea272808707d758e (patch)
tree2710c9920795784ebec60546d3b07b92430d41b3 /arch/arm
parent38dbfb59d1175ef458d006556061adeaa8751b72 (diff)
ARM: sun7i: dt: Fix interrupt trigger types
The Allwinner A20 uses the ARM GIC as its internal interrupts controller. The GIC can work on several interrupt triggers, and the A20 was actually setting it up to use a rising edge as a trigger, while it was actually a level high trigger, leading to some interrupts that would be completely ignored if the edge was missed. Fix this for the remaining DT nodes that slipped through. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: stable@vger.kernel.org
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 119f066f0d98..2374f5aa92e8 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -454,7 +454,7 @@
454 rtc: rtc@01c20d00 { 454 rtc: rtc@01c20d00 {
455 compatible = "allwinner,sun7i-a20-rtc"; 455 compatible = "allwinner,sun7i-a20-rtc";
456 reg = <0x01c20d00 0x20>; 456 reg = <0x01c20d00 0x20>;
457 interrupts = <0 24 1>; 457 interrupts = <0 24 4>;
458 }; 458 };
459 459
460 sid: eeprom@01c23800 { 460 sid: eeprom@01c23800 {
@@ -596,10 +596,10 @@
596 hstimer@01c60000 { 596 hstimer@01c60000 {
597 compatible = "allwinner,sun7i-a20-hstimer"; 597 compatible = "allwinner,sun7i-a20-hstimer";
598 reg = <0x01c60000 0x1000>; 598 reg = <0x01c60000 0x1000>;
599 interrupts = <0 81 1>, 599 interrupts = <0 81 4>,
600 <0 82 1>, 600 <0 82 4>,
601 <0 83 1>, 601 <0 83 4>,
602 <0 84 1>; 602 <0 84 4>;
603 clocks = <&ahb_gates 28>; 603 clocks = <&ahb_gates 28>;
604 }; 604 };
605 605