diff options
author | Daniel Walker <dwalker@codeaurora.org> | 2010-05-04 14:29:54 -0400 |
---|---|---|
committer | Daniel Walker <dwalker@codeaurora.org> | 2010-05-13 19:08:46 -0400 |
commit | 2f2a74e637b7ea4a52a7aea82f2a1835749d3a35 (patch) | |
tree | 94a6f39638a5779aed9ff7313a1e39166dc01f22 /arch/arm | |
parent | 90e37c57bab2876c50fe479d26e228c9aa871556 (diff) |
msm: dma: add 7x30 security domain abstraction
The MSM SOC's DMA controller contains several security domains.
On the MSM7x00, only security domain 3 is accessible to our CPU.
The 7x30, however, uses security domain 2. Fix up the register
definition macros to select this appropriately, based on
configured target.
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Gregory Bean <gbean@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-msm/include/mach/dma.h | 32 |
1 files changed, 17 insertions, 15 deletions
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h index 5ab5bdffab07..04c51cc04f31 100644 --- a/arch/arm/mach-msm/include/mach/dma.h +++ b/arch/arm/mach-msm/include/mach/dma.h | |||
@@ -41,40 +41,42 @@ int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr); | |||
41 | #define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2)) | 41 | #define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2)) |
42 | #define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2)) | 42 | #define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2)) |
43 | 43 | ||
44 | /* only security domain 3 is available to the ARM11 | 44 | #if defined(CONFIG_ARCH_MSM7X30) |
45 | * SD0 -> mARM trusted, SD1 -> mARM nontrusted, SD2 -> aDSP, SD3 -> aARM | 45 | #define DMOV_SD_AARM DMOV_SD2 |
46 | */ | 46 | #else |
47 | #define DMOV_SD_AARM DMOV_SD3 | ||
48 | #endif | ||
47 | 49 | ||
48 | #define DMOV_CMD_PTR(ch) DMOV_SD3(0x000, ch) | 50 | #define DMOV_CMD_PTR(ch) DMOV_SD_AARM(0x000, ch) |
49 | #define DMOV_CMD_LIST (0 << 29) /* does not work */ | 51 | #define DMOV_CMD_LIST (0 << 29) /* does not work */ |
50 | #define DMOV_CMD_PTR_LIST (1 << 29) /* works */ | 52 | #define DMOV_CMD_PTR_LIST (1 << 29) /* works */ |
51 | #define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */ | 53 | #define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */ |
52 | #define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */ | 54 | #define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */ |
53 | #define DMOV_CMD_ADDR(addr) ((addr) >> 3) | 55 | #define DMOV_CMD_ADDR(addr) ((addr) >> 3) |
54 | 56 | ||
55 | #define DMOV_RSLT(ch) DMOV_SD3(0x040, ch) | 57 | #define DMOV_RSLT(ch) DMOV_SD_AARM(0x040, ch) |
56 | #define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */ | 58 | #define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */ |
57 | #define DMOV_RSLT_ERROR (1 << 3) | 59 | #define DMOV_RSLT_ERROR (1 << 3) |
58 | #define DMOV_RSLT_FLUSH (1 << 2) | 60 | #define DMOV_RSLT_FLUSH (1 << 2) |
59 | #define DMOV_RSLT_DONE (1 << 1) /* top pointer done */ | 61 | #define DMOV_RSLT_DONE (1 << 1) /* top pointer done */ |
60 | #define DMOV_RSLT_USER (1 << 0) /* command with FR force result */ | 62 | #define DMOV_RSLT_USER (1 << 0) /* command with FR force result */ |
61 | 63 | ||
62 | #define DMOV_FLUSH0(ch) DMOV_SD3(0x080, ch) | 64 | #define DMOV_FLUSH0(ch) DMOV_SD_AARM(0x080, ch) |
63 | #define DMOV_FLUSH1(ch) DMOV_SD3(0x0C0, ch) | 65 | #define DMOV_FLUSH1(ch) DMOV_SD_AARM(0x0C0, ch) |
64 | #define DMOV_FLUSH2(ch) DMOV_SD3(0x100, ch) | 66 | #define DMOV_FLUSH2(ch) DMOV_SD_AARM(0x100, ch) |
65 | #define DMOV_FLUSH3(ch) DMOV_SD3(0x140, ch) | 67 | #define DMOV_FLUSH3(ch) DMOV_SD_AARM(0x140, ch) |
66 | #define DMOV_FLUSH4(ch) DMOV_SD3(0x180, ch) | 68 | #define DMOV_FLUSH4(ch) DMOV_SD_AARM(0x180, ch) |
67 | #define DMOV_FLUSH5(ch) DMOV_SD3(0x1C0, ch) | 69 | #define DMOV_FLUSH5(ch) DMOV_SD_AARM(0x1C0, ch) |
68 | 70 | ||
69 | #define DMOV_STATUS(ch) DMOV_SD3(0x200, ch) | 71 | #define DMOV_STATUS(ch) DMOV_SD_AARM(0x200, ch) |
70 | #define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29)) | 72 | #define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29)) |
71 | #define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3) | 73 | #define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3) |
72 | #define DMOV_STATUS_RSLT_VALID (1 << 1) | 74 | #define DMOV_STATUS_RSLT_VALID (1 << 1) |
73 | #define DMOV_STATUS_CMD_PTR_RDY (1 << 0) | 75 | #define DMOV_STATUS_CMD_PTR_RDY (1 << 0) |
74 | 76 | ||
75 | #define DMOV_ISR DMOV_SD3(0x380, 0) | 77 | #define DMOV_ISR DMOV_SD_AARM(0x380, 0) |
76 | 78 | ||
77 | #define DMOV_CONFIG(ch) DMOV_SD3(0x300, ch) | 79 | #define DMOV_CONFIG(ch) DMOV_SD_AARM(0x300, ch) |
78 | #define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2) | 80 | #define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2) |
79 | #define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1) | 81 | #define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1) |
80 | #define DMOV_CONFIG_IRQ_EN (1 << 0) | 82 | #define DMOV_CONFIG_IRQ_EN (1 << 0) |