aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
authorOlof Johansson <olof@lixom.net>2011-12-13 22:35:03 -0500
committerOlof Johansson <olof@lixom.net>2011-12-13 22:35:03 -0500
commit2da994e687f7991cc76e3270c423bf6500b9424a (patch)
tree437d685035c2a39395f14c233831422ed636c016 /arch/arm
parent00e929808a1cb410f45a620c0fc79d8d0a2506b1 (diff)
parentdb33f4de9952af112b0d4f2436ce931ae632aba0 (diff)
Merge branch 'orion/devel' into next/devel
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/kernel/perf_event.c6
-rw-r--r--arch/arm/mach-at91/at91rm9200_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9260.c6
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c2
-rw-r--r--arch/arm/mach-at91/include/mach/system_rev.h2
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm365-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c6
-rw-r--r--arch/arm/mach-davinci/dm646x.c1
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h5
-rw-r--r--arch/arm/mach-davinci/psc.c18
-rw-r--r--arch/arm/mach-dove/addr-map.c121
-rw-r--r--arch/arm/mach-dove/common.c16
-rw-r--r--arch/arm/mach-dove/common.h1
-rw-r--r--arch/arm/mach-dove/pcie.c4
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c9
-rw-r--r--arch/arm/mach-kirkwood/addr-map.c137
-rw-r--r--arch/arm/mach-kirkwood/common.c19
-rw-r--r--arch/arm/mach-kirkwood/common.h1
-rw-r--r--arch/arm/mach-kirkwood/include/mach/kirkwood.h1
-rw-r--r--arch/arm/mach-kirkwood/mpp.c1
-rw-r--r--arch/arm/mach-kirkwood/mpp.h1
-rw-r--r--arch/arm/mach-kirkwood/pcie.c4
-rw-r--r--arch/arm/mach-msm/devices-iommu.c1
-rw-r--r--arch/arm/mach-mv78xx0/addr-map.c102
-rw-r--r--arch/arm/mach-mv78xx0/common.c22
-rw-r--r--arch/arm/mach-mv78xx0/common.h1
-rw-r--r--arch/arm/mach-mv78xx0/mpp.c1
-rw-r--r--arch/arm/mach-mv78xx0/pcie.c4
-rw-r--r--arch/arm/mach-mx5/imx51-dt.c12
-rw-r--r--arch/arm/mach-mx5/imx53-dt.c12
-rw-r--r--arch/arm/mach-mxs/include/mach/mx28.h4
-rw-r--r--arch/arm/mach-mxs/include/mach/mxs.h1
-rw-r--r--arch/arm/mach-mxs/mach-m28evk.c2
-rw-r--r--arch/arm/mach-mxs/mach-stmp378x_devb.c2
-rw-r--r--arch/arm/mach-mxs/module-tx28.c4
-rw-r--r--arch/arm/mach-orion5x/addr-map.c146
-rw-r--r--arch/arm/mach-orion5x/common.c23
-rw-r--r--arch/arm/mach-orion5x/common.h3
-rw-r--r--arch/arm/mach-orion5x/include/mach/orion5x.h2
-rw-r--r--arch/arm/mach-orion5x/mpp.c1
-rw-r--r--arch/arm/mach-orion5x/pci.c5
-rw-r--r--arch/arm/mach-prima2/pm.c1
-rw-r--r--arch/arm/mach-prima2/prima2.c1
-rw-r--r--arch/arm/mach-s3c64xx/dev-spi.c1
-rw-r--r--arch/arm/mach-s3c64xx/s3c6400.c2
-rw-r--r--arch/arm/mach-s3c64xx/setup-fb-24bpp.c2
-rw-r--r--arch/arm/mach-sa1100/Makefile.boot4
-rw-r--r--arch/arm/plat-orion/Makefile2
-rw-r--r--arch/arm/plat-orion/addr-map.c174
-rw-r--r--arch/arm/plat-orion/common.c43
-rw-r--r--arch/arm/plat-orion/include/plat/addr-map.h53
-rw-r--r--arch/arm/plat-orion/include/plat/audio.h3
-rw-r--r--arch/arm/plat-orion/include/plat/common.h17
-rw-r--r--arch/arm/plat-orion/include/plat/ehci-orion.h1
-rw-r--r--arch/arm/plat-orion/include/plat/mv_xor.h6
-rw-r--r--arch/arm/plat-orion/include/plat/mvsdio.h1
-rw-r--r--arch/arm/plat-orion/include/plat/pcie.h3
-rw-r--r--arch/arm/plat-orion/pcie.c6
61 files changed, 502 insertions, 537 deletions
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index c475379199b1..8e9c98edc068 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -353,15 +353,15 @@ validate_group(struct perf_event *event)
353 fake_pmu.used_mask = fake_used_mask; 353 fake_pmu.used_mask = fake_used_mask;
354 354
355 if (!validate_event(&fake_pmu, leader)) 355 if (!validate_event(&fake_pmu, leader))
356 return -ENOSPC; 356 return -EINVAL;
357 357
358 list_for_each_entry(sibling, &leader->sibling_list, group_entry) { 358 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
359 if (!validate_event(&fake_pmu, sibling)) 359 if (!validate_event(&fake_pmu, sibling))
360 return -ENOSPC; 360 return -EINVAL;
361 } 361 }
362 362
363 if (!validate_event(&fake_pmu, event)) 363 if (!validate_event(&fake_pmu, event))
364 return -ENOSPC; 364 return -EINVAL;
365 365
366 return 0; 366 return 0;
367} 367}
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 66591fa53e05..ad930688358c 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -83,7 +83,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
83 * USB Device (Gadget) 83 * USB Device (Gadget)
84 * -------------------------------------------------------------------- */ 84 * -------------------------------------------------------------------- */
85 85
86#ifdef CONFIG_USB_GADGET_AT91 86#ifdef CONFIG_USB_AT91
87static struct at91_udc_data udc_data; 87static struct at91_udc_data udc_data;
88 88
89static struct resource udc_resources[] = { 89static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index b84a9f642f59..0d20677fbef0 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -195,9 +195,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
195 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), 195 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
196 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), 196 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
197 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), 197 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
198 CLKDEV_CON_DEV_ID("t3_clk", "atmel_tcb.1", &tc3_clk), 198 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
199 CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk), 199 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
200 CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk), 200 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
201 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk), 201 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
202 /* more usart lookup table for DT entries */ 202 /* more usart lookup table for DT entries */
203 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), 203 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 25e3464fb07f..629fa9774972 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -84,7 +84,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
84 * USB Device (Gadget) 84 * USB Device (Gadget)
85 * -------------------------------------------------------------------- */ 85 * -------------------------------------------------------------------- */
86 86
87#ifdef CONFIG_USB_GADGET_AT91 87#ifdef CONFIG_USB_AT91
88static struct at91_udc_data udc_data; 88static struct at91_udc_data udc_data;
89 89
90static struct resource udc_resources[] = { 90static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index ae78f4d03b73..a178b58b0b9c 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -87,7 +87,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
87 * USB Device (Gadget) 87 * USB Device (Gadget)
88 * -------------------------------------------------------------------- */ 88 * -------------------------------------------------------------------- */
89 89
90#ifdef CONFIG_USB_GADGET_AT91 90#ifdef CONFIG_USB_AT91
91static struct at91_udc_data udc_data; 91static struct at91_udc_data udc_data;
92 92
93static struct resource udc_resources[] = { 93static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index ad017eb1f8df..d5fbac9ff4fa 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -92,7 +92,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
92 * USB Device (Gadget) 92 * USB Device (Gadget)
93 * -------------------------------------------------------------------- */ 93 * -------------------------------------------------------------------- */
94 94
95#ifdef CONFIG_USB_GADGET_AT91 95#ifdef CONFIG_USB_AT91
96static struct at91_udc_data udc_data; 96static struct at91_udc_data udc_data;
97 97
98static struct resource udc_resources[] = { 98static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-at91/include/mach/system_rev.h b/arch/arm/mach-at91/include/mach/system_rev.h
index 8f4866045b41..ec164a4124c9 100644
--- a/arch/arm/mach-at91/include/mach/system_rev.h
+++ b/arch/arm/mach-at91/include/mach/system_rev.h
@@ -19,7 +19,7 @@
19#define BOARD_HAVE_NAND_16BIT (1 << 31) 19#define BOARD_HAVE_NAND_16BIT (1 << 31)
20static inline int board_have_nand_16bit(void) 20static inline int board_have_nand_16bit(void)
21{ 21{
22 return system_rev & BOARD_HAVE_NAND_16BIT; 22 return (system_rev & BOARD_HAVE_NAND_16BIT) ? 1 : 0;
23} 23}
24 24
25#endif /* __ARCH_SYSTEM_REV_H__ */ 25#endif /* __ARCH_SYSTEM_REV_H__ */
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 1d7d24995226..6659a90dbcad 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -753,7 +753,7 @@ static struct snd_platform_data da850_evm_snd_data = {
753 .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), 753 .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction),
754 .tdm_slots = 2, 754 .tdm_slots = 2,
755 .serial_dir = da850_iis_serializer_direction, 755 .serial_dir = da850_iis_serializer_direction,
756 .asp_chan_q = EVENTQ_1, 756 .asp_chan_q = EVENTQ_0,
757 .version = MCASP_VERSION_2, 757 .version = MCASP_VERSION_2,
758 .txnumevt = 1, 758 .txnumevt = 1,
759 .rxnumevt = 1, 759 .rxnumevt = 1,
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 1918ae711428..46e1f4173b97 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -107,7 +107,7 @@ static struct mtd_partition davinci_nand_partitions[] = {
107 /* UBL (a few copies) plus U-Boot */ 107 /* UBL (a few copies) plus U-Boot */
108 .name = "bootloader", 108 .name = "bootloader",
109 .offset = 0, 109 .offset = 0,
110 .size = 28 * NAND_BLOCK_SIZE, 110 .size = 30 * NAND_BLOCK_SIZE,
111 .mask_flags = MTD_WRITEABLE, /* force read-only */ 111 .mask_flags = MTD_WRITEABLE, /* force read-only */
112 }, { 112 }, {
113 /* U-Boot environment */ 113 /* U-Boot environment */
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index e574d7f837a8..635bf7740157 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -564,7 +564,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
564 int val; 564 int val;
565 u32 value; 565 u32 value;
566 566
567 if (!vpif_vsclkdis_reg || !cpld_client) 567 if (!vpif_vidclkctl_reg || !cpld_client)
568 return -ENXIO; 568 return -ENXIO;
569 569
570 val = i2c_smbus_read_byte(cpld_client); 570 val = i2c_smbus_read_byte(cpld_client);
@@ -572,7 +572,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
572 return val; 572 return val;
573 573
574 spin_lock_irqsave(&vpif_reg_lock, flags); 574 spin_lock_irqsave(&vpif_reg_lock, flags);
575 value = __raw_readl(vpif_vsclkdis_reg); 575 value = __raw_readl(vpif_vidclkctl_reg);
576 if (mux_mode) { 576 if (mux_mode) {
577 val &= VPIF_INPUT_TWO_CHANNEL; 577 val &= VPIF_INPUT_TWO_CHANNEL;
578 value |= VIDCH1CLK; 578 value |= VIDCH1CLK;
@@ -580,7 +580,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
580 val |= VPIF_INPUT_ONE_CHANNEL; 580 val |= VPIF_INPUT_ONE_CHANNEL;
581 value &= ~VIDCH1CLK; 581 value &= ~VIDCH1CLK;
582 } 582 }
583 __raw_writel(value, vpif_vsclkdis_reg); 583 __raw_writel(value, vpif_vidclkctl_reg);
584 spin_unlock_irqrestore(&vpif_reg_lock, flags); 584 spin_unlock_irqrestore(&vpif_reg_lock, flags);
585 585
586 err = i2c_smbus_write_byte(cpld_client, val); 586 err = i2c_smbus_write_byte(cpld_client, val);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 0b68ed534f8e..af27c130595f 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -161,7 +161,6 @@ static struct clk dsp_clk = {
161 .name = "dsp", 161 .name = "dsp",
162 .parent = &pll1_sysclk1, 162 .parent = &pll1_sysclk1,
163 .lpsc = DM646X_LPSC_C64X_CPU, 163 .lpsc = DM646X_LPSC_C64X_CPU,
164 .flags = PSC_DSP,
165 .usecount = 1, /* REVISIT how to disable? */ 164 .usecount = 1, /* REVISIT how to disable? */
166}; 165};
167 166
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index fa59c097223d..8bc3fc256171 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -233,7 +233,7 @@
233#define PTCMD 0x120 233#define PTCMD 0x120
234#define PTSTAT 0x128 234#define PTSTAT 0x128
235#define PDSTAT 0x200 235#define PDSTAT 0x200
236#define PDCTL1 0x304 236#define PDCTL 0x300
237#define MDSTAT 0x800 237#define MDSTAT 0x800
238#define MDCTL 0xA00 238#define MDCTL 0xA00
239 239
@@ -244,7 +244,10 @@
244#define PSC_STATE_ENABLE 3 244#define PSC_STATE_ENABLE 3
245 245
246#define MDSTAT_STATE_MASK 0x3f 246#define MDSTAT_STATE_MASK 0x3f
247#define PDSTAT_STATE_MASK 0x1f
247#define MDCTL_FORCE BIT(31) 248#define MDCTL_FORCE BIT(31)
249#define PDCTL_NEXT BIT(1)
250#define PDCTL_EPCGOOD BIT(8)
248 251
249#ifndef __ASSEMBLER__ 252#ifndef __ASSEMBLER__
250 253
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 1fb6bdff38c1..d7e210f4b55c 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -52,7 +52,7 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
52void davinci_psc_config(unsigned int domain, unsigned int ctlr, 52void davinci_psc_config(unsigned int domain, unsigned int ctlr,
53 unsigned int id, bool enable, u32 flags) 53 unsigned int id, bool enable, u32 flags)
54{ 54{
55 u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl; 55 u32 epcpr, ptcmd, ptstat, pdstat, pdctl, mdstat, mdctl;
56 void __iomem *psc_base; 56 void __iomem *psc_base;
57 struct davinci_soc_info *soc_info = &davinci_soc_info; 57 struct davinci_soc_info *soc_info = &davinci_soc_info;
58 u32 next_state = PSC_STATE_ENABLE; 58 u32 next_state = PSC_STATE_ENABLE;
@@ -79,11 +79,11 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
79 mdctl |= MDCTL_FORCE; 79 mdctl |= MDCTL_FORCE;
80 __raw_writel(mdctl, psc_base + MDCTL + 4 * id); 80 __raw_writel(mdctl, psc_base + MDCTL + 4 * id);
81 81
82 pdstat = __raw_readl(psc_base + PDSTAT); 82 pdstat = __raw_readl(psc_base + PDSTAT + 4 * domain);
83 if ((pdstat & 0x00000001) == 0) { 83 if ((pdstat & PDSTAT_STATE_MASK) == 0) {
84 pdctl1 = __raw_readl(psc_base + PDCTL1); 84 pdctl = __raw_readl(psc_base + PDCTL + 4 * domain);
85 pdctl1 |= 0x1; 85 pdctl |= PDCTL_NEXT;
86 __raw_writel(pdctl1, psc_base + PDCTL1); 86 __raw_writel(pdctl, psc_base + PDCTL + 4 * domain);
87 87
88 ptcmd = 1 << domain; 88 ptcmd = 1 << domain;
89 __raw_writel(ptcmd, psc_base + PTCMD); 89 __raw_writel(ptcmd, psc_base + PTCMD);
@@ -92,9 +92,9 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
92 epcpr = __raw_readl(psc_base + EPCPR); 92 epcpr = __raw_readl(psc_base + EPCPR);
93 } while ((((epcpr >> domain) & 1) == 0)); 93 } while ((((epcpr >> domain) & 1) == 0));
94 94
95 pdctl1 = __raw_readl(psc_base + PDCTL1); 95 pdctl = __raw_readl(psc_base + PDCTL + 4 * domain);
96 pdctl1 |= 0x100; 96 pdctl |= PDCTL_EPCGOOD;
97 __raw_writel(pdctl1, psc_base + PDCTL1); 97 __raw_writel(pdctl, psc_base + PDCTL + 4 * domain);
98 } else { 98 } else {
99 ptcmd = 1 << domain; 99 ptcmd = 1 << domain;
100 __raw_writel(ptcmd, psc_base + PTCMD); 100 __raw_writel(ptcmd, psc_base + PTCMD);
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
index 00be4fc26dd7..98b8c83b09ab 100644
--- a/arch/arm/mach-dove/addr-map.c
+++ b/arch/arm/mach-dove/addr-map.c
@@ -14,6 +14,7 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
16#include <asm/setup.h> 16#include <asm/setup.h>
17#include <plat/addr-map.h>
17#include "common.h" 18#include "common.h"
18 19
19/* 20/*
@@ -34,98 +35,72 @@
34#define ATTR_PCIE_MEM 0xe8 35#define ATTR_PCIE_MEM 0xe8
35#define ATTR_SCRATCHPAD 0x0 36#define ATTR_SCRATCHPAD 0x0
36 37
37/*
38 * CPU Address Decode Windows registers
39 */
40#define WIN_CTRL(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0)
41#define WIN_BASE(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4)
42#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8)
43#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc)
44
45struct mbus_dram_target_info dove_mbus_dram_info;
46
47static inline void __iomem *ddr_map_sc(int i) 38static inline void __iomem *ddr_map_sc(int i)
48{ 39{
49 return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); 40 return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
50} 41}
51 42
52static int cpu_win_can_remap(int win) 43/*
53{ 44 * Description of the windows needed by the platform code
54 if (win < 4) 45 */
55 return 1; 46static struct __initdata orion_addr_map_cfg addr_map_cfg = {
56 47 .num_wins = 8,
57 return 0; 48 .remappable_wins = 4,
58} 49 .bridge_virt_base = BRIDGE_VIRT_BASE,
59 50};
60static void __init setup_cpu_win(int win, u32 base, u32 size,
61 u8 target, u8 attr, int remap)
62{
63 u32 ctrl;
64
65 base &= 0xffff0000;
66 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
67
68 writel(base, WIN_BASE(win));
69 writel(ctrl, WIN_CTRL(win));
70 if (cpu_win_can_remap(win)) {
71 if (remap < 0)
72 remap = base;
73 writel(remap & 0xffff0000, WIN_REMAP_LO(win));
74 writel(0, WIN_REMAP_HI(win));
75 }
76}
77
78void __init dove_setup_cpu_mbus(void)
79{
80 int i;
81 int cs;
82 51
52static const struct __initdata orion_addr_map_info addr_map_info[] = {
83 /* 53 /*
84 * First, disable and clear windows. 54 * Windows for PCIe IO+MEM space.
85 */ 55 */
86 for (i = 0; i < 8; i++) { 56 { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
87 writel(0, WIN_BASE(i)); 57 TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE
88 writel(0, WIN_CTRL(i)); 58 },
89 if (cpu_win_can_remap(i)) { 59 { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
90 writel(0, WIN_REMAP_LO(i)); 60 TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE
91 writel(0, WIN_REMAP_HI(i)); 61 },
92 } 62 { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
93 } 63 TARGET_PCIE0, ATTR_PCIE_MEM, -1
94 64 },
65 { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
66 TARGET_PCIE1, ATTR_PCIE_MEM, -1
67 },
95 /* 68 /*
96 * Setup windows for PCIe IO+MEM space. 69 * Window for CESA engine.
97 */ 70 */
98 setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, 71 { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
99 TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE); 72 TARGET_CESA, ATTR_CESA, -1
100 setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, 73 },
101 TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE);
102 setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
103 TARGET_PCIE0, ATTR_PCIE_MEM, -1);
104 setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
105 TARGET_PCIE1, ATTR_PCIE_MEM, -1);
106
107 /* 74 /*
108 * Setup window for CESA engine. 75 * Window to the BootROM for Standby and Sleep Resume
109 */ 76 */
110 setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, 77 { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
111 TARGET_CESA, ATTR_CESA, -1); 78 TARGET_BOOTROM, ATTR_BOOTROM, -1
112 79 },
113 /* 80 /*
114 * Setup the Window to the BootROM for Standby and Sleep Resume 81 * Window to the PMU Scratch Pad space
115 */ 82 */
116 setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, 83 { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
117 TARGET_BOOTROM, ATTR_BOOTROM, -1); 84 TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1
85 },
86 /* End marker */
87 { -1, 0, 0, 0, 0, 0 }
88};
89
90void __init dove_setup_cpu_mbus(void)
91{
92 int i;
93 int cs;
118 94
119 /* 95 /*
120 * Setup the Window to the PMU Scratch Pad space 96 * Disable, clear and configure windows.
121 */ 97 */
122 setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, 98 orion_config_wins(&addr_map_cfg, addr_map_info);
123 TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1);
124 99
125 /* 100 /*
126 * Setup MBUS dram target info. 101 * Setup MBUS dram target info.
127 */ 102 */
128 dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 103 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
129 104
130 for (i = 0, cs = 0; i < 2; i++) { 105 for (i = 0, cs = 0; i < 2; i++) {
131 u32 map = readl(ddr_map_sc(i)); 106 u32 map = readl(ddr_map_sc(i));
@@ -136,7 +111,7 @@ void __init dove_setup_cpu_mbus(void)
136 if (map & 1) { 111 if (map & 1) {
137 struct mbus_dram_window *w; 112 struct mbus_dram_window *w;
138 113
139 w = &dove_mbus_dram_info.cs[cs++]; 114 w = &orion_mbus_dram_info.cs[cs++];
140 w->cs_index = i; 115 w->cs_index = i;
141 w->mbus_attr = 0; /* CS address decoding done inside */ 116 w->mbus_attr = 0; /* CS address decoding done inside */
142 /* the DDR controller, no need to */ 117 /* the DDR controller, no need to */
@@ -145,5 +120,5 @@ void __init dove_setup_cpu_mbus(void)
145 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); 120 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
146 } 121 }
147 } 122 }
148 dove_mbus_dram_info.num_cs = cs; 123 orion_mbus_dram_info.num_cs = cs;
149} 124}
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index a9e0dae86a26..29ff0d076f0a 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -14,7 +14,6 @@
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/pci.h> 15#include <linux/pci.h>
16#include <linux/clk.h> 16#include <linux/clk.h>
17#include <linux/mbus.h>
18#include <linux/ata_platform.h> 17#include <linux/ata_platform.h>
19#include <linux/gpio.h> 18#include <linux/gpio.h>
20#include <asm/page.h> 19#include <asm/page.h>
@@ -30,6 +29,7 @@
30#include <linux/irq.h> 29#include <linux/irq.h>
31#include <plat/time.h> 30#include <plat/time.h>
32#include <plat/common.h> 31#include <plat/common.h>
32#include <plat/addr-map.h>
33#include "common.h" 33#include "common.h"
34 34
35static int get_tclk(void); 35static int get_tclk(void);
@@ -71,8 +71,7 @@ void __init dove_map_io(void)
71 ****************************************************************************/ 71 ****************************************************************************/
72void __init dove_ehci0_init(void) 72void __init dove_ehci0_init(void)
73{ 73{
74 orion_ehci_init(&dove_mbus_dram_info, 74 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
75 DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
76} 75}
77 76
78/***************************************************************************** 77/*****************************************************************************
@@ -80,8 +79,7 @@ void __init dove_ehci0_init(void)
80 ****************************************************************************/ 79 ****************************************************************************/
81void __init dove_ehci1_init(void) 80void __init dove_ehci1_init(void)
82{ 81{
83 orion_ehci_1_init(&dove_mbus_dram_info, 82 orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
84 DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
85} 83}
86 84
87/***************************************************************************** 85/*****************************************************************************
@@ -89,7 +87,7 @@ void __init dove_ehci1_init(void)
89 ****************************************************************************/ 87 ****************************************************************************/
90void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 88void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
91{ 89{
92 orion_ge00_init(eth_data, &dove_mbus_dram_info, 90 orion_ge00_init(eth_data,
93 DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM, 91 DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
94 0, get_tclk()); 92 0, get_tclk());
95} 93}
@@ -107,8 +105,7 @@ void __init dove_rtc_init(void)
107 ****************************************************************************/ 105 ****************************************************************************/
108void __init dove_sata_init(struct mv_sata_platform_data *sata_data) 106void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
109{ 107{
110 orion_sata_init(sata_data, &dove_mbus_dram_info, 108 orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
111 DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
112 109
113} 110}
114 111
@@ -198,8 +195,7 @@ struct sys_timer dove_timer = {
198 ****************************************************************************/ 195 ****************************************************************************/
199void __init dove_xor0_init(void) 196void __init dove_xor0_init(void)
200{ 197{
201 orion_xor0_init(&dove_mbus_dram_info, 198 orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
202 DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
203 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); 199 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
204} 200}
205 201
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index 6a2046e44706..7322371d3908 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -15,7 +15,6 @@ struct mv643xx_eth_platform_data;
15struct mv_sata_platform_data; 15struct mv_sata_platform_data;
16 16
17extern struct sys_timer dove_timer; 17extern struct sys_timer dove_timer;
18extern struct mbus_dram_target_info dove_mbus_dram_info;
19 18
20/* 19/*
21 * Basic Dove init functions used early by machine-setup. 20 * Basic Dove init functions used early by machine-setup.
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index aa2b3a09a51d..6c11a4df7178 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -10,7 +10,6 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/mbus.h>
14#include <video/vga.h> 13#include <video/vga.h>
15#include <asm/mach/pci.h> 14#include <asm/mach/pci.h>
16#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
@@ -19,6 +18,7 @@
19#include <plat/pcie.h> 18#include <plat/pcie.h>
20#include <mach/irqs.h> 19#include <mach/irqs.h>
21#include <mach/bridge-regs.h> 20#include <mach/bridge-regs.h>
21#include <plat/addr-map.h>
22#include "common.h" 22#include "common.h"
23 23
24struct pcie_port { 24struct pcie_port {
@@ -50,7 +50,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
50 */ 50 */
51 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 51 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
52 52
53 orion_pcie_setup(pp->base, &dove_mbus_dram_info); 53 orion_pcie_setup(pp->base);
54 54
55 /* 55 /*
56 * IORESOURCE_IO 56 * IORESOURCE_IO
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 9cd860a27af5..8deb012189b5 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -37,14 +37,15 @@ static void __init imx6q_map_io(void)
37 imx6q_clock_map_io(); 37 imx6q_clock_map_io();
38} 38}
39 39
40static void __init imx6q_gpio_add_irq_domain(struct device_node *np, 40static int __init imx6q_gpio_add_irq_domain(struct device_node *np,
41 struct device_node *interrupt_parent) 41 struct device_node *interrupt_parent)
42{ 42{
43 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS - 43 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
44 32 * 7; /* imx6q gets 7 gpio ports */
45 44
45 gpio_irq_base -= 32;
46 irq_domain_add_simple(np, gpio_irq_base); 46 irq_domain_add_simple(np, gpio_irq_base);
47 gpio_irq_base += 32; 47
48 return 0;
48} 49}
49 50
50static const struct of_device_id imx6q_irq_match[] __initconst = { 51static const struct of_device_id imx6q_irq_match[] __initconst = {
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 8d03bcef5182..e9a7180863d9 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -13,12 +13,12 @@
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <mach/hardware.h> 15#include <mach/hardware.h>
16#include <plat/addr-map.h>
16#include "common.h" 17#include "common.h"
17 18
18/* 19/*
19 * Generic Address Decode Windows bit settings 20 * Generic Address Decode Windows bit settings
20 */ 21 */
21#define TARGET_DDR 0
22#define TARGET_DEV_BUS 1 22#define TARGET_DEV_BUS 1
23#define TARGET_SRAM 3 23#define TARGET_SRAM 3
24#define TARGET_PCIE 4 24#define TARGET_PCIE 4
@@ -36,118 +36,55 @@
36#define ATTR_SRAM 0x01 36#define ATTR_SRAM 0x01
37 37
38/* 38/*
39 * Helpers to get DDR bank info 39 * Description of the windows needed by the platform code
40 */ 40 */
41#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) 41static struct __initdata orion_addr_map_cfg addr_map_cfg = {
42#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) 42 .num_wins = 8,
43 43 .remappable_wins = 4,
44/* 44 .bridge_virt_base = BRIDGE_VIRT_BASE,
45 * CPU Address Decode Windows registers 45};
46 */
47#define WIN_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
48#define WIN_CTRL_OFF 0x0000
49#define WIN_BASE_OFF 0x0004
50#define WIN_REMAP_LO_OFF 0x0008
51#define WIN_REMAP_HI_OFF 0x000c
52
53
54struct mbus_dram_target_info kirkwood_mbus_dram_info;
55
56static int __init cpu_win_can_remap(int win)
57{
58 if (win < 4)
59 return 1;
60
61 return 0;
62}
63
64static void __init setup_cpu_win(int win, u32 base, u32 size,
65 u8 target, u8 attr, int remap)
66{
67 void __iomem *addr = (void __iomem *)WIN_OFF(win);
68 u32 ctrl;
69
70 base &= 0xffff0000;
71 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
72
73 writel(base, addr + WIN_BASE_OFF);
74 writel(ctrl, addr + WIN_CTRL_OFF);
75 if (cpu_win_can_remap(win)) {
76 if (remap < 0)
77 remap = base;
78
79 writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
80 writel(0, addr + WIN_REMAP_HI_OFF);
81 }
82}
83
84void __init kirkwood_setup_cpu_mbus(void)
85{
86 void __iomem *addr;
87 int i;
88 int cs;
89 46
47static const struct __initdata orion_addr_map_info addr_map_info[] = {
90 /* 48 /*
91 * First, disable and clear windows. 49 * Windows for PCIe IO+MEM space.
92 */ 50 */
93 for (i = 0; i < 8; i++) { 51 { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
94 addr = (void __iomem *)WIN_OFF(i); 52 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE
95 53 },
96 writel(0, addr + WIN_BASE_OFF); 54 { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
97 writel(0, addr + WIN_CTRL_OFF); 55 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE
98 if (cpu_win_can_remap(i)) { 56 },
99 writel(0, addr + WIN_REMAP_LO_OFF); 57 { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
100 writel(0, addr + WIN_REMAP_HI_OFF); 58 TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE
101 } 59 },
102 } 60 { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
103 61 TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE
62 },
104 /* 63 /*
105 * Setup windows for PCIe IO+MEM space. 64 * Window for NAND controller.
106 */ 65 */
107 setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, 66 { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
108 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); 67 TARGET_DEV_BUS, ATTR_DEV_NAND, -1
109 setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, 68 },
110 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
111 setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
112 TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
113 setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
114 TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
115
116 /* 69 /*
117 * Setup window for NAND controller. 70 * Window for SRAM.
118 */ 71 */
119 setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, 72 { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
120 TARGET_DEV_BUS, ATTR_DEV_NAND, -1); 73 TARGET_SRAM, ATTR_SRAM, -1
74 },
75 /* End marker */
76 { -1, 0, 0, 0, 0, 0 }
77};
121 78
79void __init kirkwood_setup_cpu_mbus(void)
80{
122 /* 81 /*
123 * Setup window for SRAM. 82 * Disable, clear and configure windows.
124 */ 83 */
125 setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, 84 orion_config_wins(&addr_map_cfg, addr_map_info);
126 TARGET_SRAM, ATTR_SRAM, -1);
127 85
128 /* 86 /*
129 * Setup MBUS dram target info. 87 * Setup MBUS dram target info.
130 */ 88 */
131 kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 89 orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
132
133 addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
134
135 for (i = 0, cs = 0; i < 4; i++) {
136 u32 base = readl(addr + DDR_BASE_CS_OFF(i));
137 u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
138
139 /*
140 * Chip select enabled?
141 */
142 if (size & 1) {
143 struct mbus_dram_window *w;
144
145 w = &kirkwood_mbus_dram_info.cs[cs++];
146 w->cs_index = i;
147 w->mbus_attr = 0xf & ~(1 << i);
148 w->base = base & 0xffff0000;
149 w->size = (size | 0x0000ffff) + 1;
150 }
151 }
152 kirkwood_mbus_dram_info.num_cs = cs;
153} 90}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index f3248cfbe51d..10566d4052d2 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -12,7 +12,6 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/serial_8250.h> 14#include <linux/serial_8250.h>
15#include <linux/mbus.h>
16#include <linux/ata_platform.h> 15#include <linux/ata_platform.h>
17#include <linux/mtd/nand.h> 16#include <linux/mtd/nand.h>
18#include <linux/dma-mapping.h> 17#include <linux/dma-mapping.h>
@@ -30,6 +29,7 @@
30#include <plat/orion_nand.h> 29#include <plat/orion_nand.h>
31#include <plat/common.h> 30#include <plat/common.h>
32#include <plat/time.h> 31#include <plat/time.h>
32#include <plat/addr-map.h>
33#include "common.h" 33#include "common.h"
34 34
35/***************************************************************************** 35/*****************************************************************************
@@ -73,8 +73,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
73void __init kirkwood_ehci_init(void) 73void __init kirkwood_ehci_init(void)
74{ 74{
75 kirkwood_clk_ctrl |= CGC_USB0; 75 kirkwood_clk_ctrl |= CGC_USB0;
76 orion_ehci_init(&kirkwood_mbus_dram_info, 76 orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
77 USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
78} 77}
79 78
80 79
@@ -85,7 +84,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
85{ 84{
86 kirkwood_clk_ctrl |= CGC_GE0; 85 kirkwood_clk_ctrl |= CGC_GE0;
87 86
88 orion_ge00_init(eth_data, &kirkwood_mbus_dram_info, 87 orion_ge00_init(eth_data,
89 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, 88 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
90 IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk); 89 IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
91} 90}
@@ -99,7 +98,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
99 98
100 kirkwood_clk_ctrl |= CGC_GE1; 99 kirkwood_clk_ctrl |= CGC_GE1;
101 100
102 orion_ge01_init(eth_data, &kirkwood_mbus_dram_info, 101 orion_ge01_init(eth_data,
103 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, 102 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
104 IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk); 103 IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
105} 104}
@@ -178,8 +177,7 @@ void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
178 if (sata_data->n_ports > 1) 177 if (sata_data->n_ports > 1)
179 kirkwood_clk_ctrl |= CGC_SATA1; 178 kirkwood_clk_ctrl |= CGC_SATA1;
180 179
181 orion_sata_init(sata_data, &kirkwood_mbus_dram_info, 180 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
182 SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
183} 181}
184 182
185 183
@@ -221,7 +219,6 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
221 mvsdio_data->clock = 100000000; 219 mvsdio_data->clock = 100000000;
222 else 220 else
223 mvsdio_data->clock = 200000000; 221 mvsdio_data->clock = 200000000;
224 mvsdio_data->dram = &kirkwood_mbus_dram_info;
225 kirkwood_clk_ctrl |= CGC_SDIO; 222 kirkwood_clk_ctrl |= CGC_SDIO;
226 kirkwood_sdio.dev.platform_data = mvsdio_data; 223 kirkwood_sdio.dev.platform_data = mvsdio_data;
227 platform_device_register(&kirkwood_sdio); 224 platform_device_register(&kirkwood_sdio);
@@ -285,8 +282,7 @@ static void __init kirkwood_xor0_init(void)
285{ 282{
286 kirkwood_clk_ctrl |= CGC_XOR0; 283 kirkwood_clk_ctrl |= CGC_XOR0;
287 284
288 orion_xor0_init(&kirkwood_mbus_dram_info, 285 orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
289 XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
290 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01); 286 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
291} 287}
292 288
@@ -364,7 +360,6 @@ static struct resource kirkwood_i2s_resources[] = {
364}; 360};
365 361
366static struct kirkwood_asoc_platform_data kirkwood_i2s_data = { 362static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
367 .dram = &kirkwood_mbus_dram_info,
368 .burst = 128, 363 .burst = 128,
369}; 364};
370 365
@@ -430,6 +425,8 @@ static char * __init kirkwood_id(void)
430 } else if (dev == MV88F6282_DEV_ID) { 425 } else if (dev == MV88F6282_DEV_ID) {
431 if (rev == MV88F6282_REV_A0) 426 if (rev == MV88F6282_REV_A0)
432 return "MV88F6282-Rev-A0"; 427 return "MV88F6282-Rev-A0";
428 else if (rev == MV88F6282_REV_A1)
429 return "MV88F6282-Rev-A1";
433 else 430 else
434 return "MV88F6282-Rev-Unsupported"; 431 return "MV88F6282-Rev-Unsupported";
435 } else { 432 } else {
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index b9b0f0968a36..4756b945106b 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -30,7 +30,6 @@ void kirkwood_init(void);
30void kirkwood_init_early(void); 30void kirkwood_init_early(void);
31void kirkwood_init_irq(void); 31void kirkwood_init_irq(void);
32 32
33extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
34void kirkwood_setup_cpu_mbus(void); 33void kirkwood_setup_cpu_mbus(void);
35 34
36void kirkwood_enable_pcie(void); 35void kirkwood_enable_pcie(void);
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 010bdeb4ac5f..fede3d503efa 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -135,4 +135,5 @@
135 135
136#define MV88F6282_DEV_ID 0x6282 136#define MV88F6282_DEV_ID 0x6282
137#define MV88F6282_REV_A0 0 137#define MV88F6282_REV_A0 0
138#define MV88F6282_REV_A1 1
138#endif 139#endif
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index cc431fa22ccb..0c6ad63f10c7 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -10,7 +10,6 @@
10#include <linux/gpio.h> 10#include <linux/gpio.h>
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h> 13#include <linux/io.h>
15#include <mach/hardware.h> 14#include <mach/hardware.h>
16#include <plat/mpp.h> 15#include <plat/mpp.h>
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index ac787957e2d9..e8fda45c0736 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -102,6 +102,7 @@
102#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 102#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 )
103 103
104#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 104#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 )
105#define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 )
105#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) 106#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 )
106#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 107#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 )
107#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 108#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 )
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 74b992d810ea..fb451bfe478b 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -11,12 +11,12 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/slab.h> 13#include <linux/slab.h>
14#include <linux/mbus.h>
15#include <video/vga.h> 14#include <video/vga.h>
16#include <asm/irq.h> 15#include <asm/irq.h>
17#include <asm/mach/pci.h> 16#include <asm/mach/pci.h>
18#include <plat/pcie.h> 17#include <plat/pcie.h>
19#include <mach/bridge-regs.h> 18#include <mach/bridge-regs.h>
19#include <plat/addr-map.h>
20#include "common.h" 20#include "common.h"
21 21
22void kirkwood_enable_pcie(void) 22void kirkwood_enable_pcie(void)
@@ -208,7 +208,7 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
208 */ 208 */
209 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 209 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
210 210
211 orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info); 211 orion_pcie_setup(pp->base);
212 212
213 return 1; 213 return 1;
214} 214}
diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c
index 24030d0da6e3..0fb7a17df398 100644
--- a/arch/arm/mach-msm/devices-iommu.c
+++ b/arch/arm/mach-msm/devices-iommu.c
@@ -18,6 +18,7 @@
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/bootmem.h> 20#include <linux/bootmem.h>
21#include <linux/module.h>
21#include <mach/irqs.h> 22#include <mach/irqs.h>
22#include <mach/iommu.h> 23#include <mach/iommu.h>
23 24
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 311d5b0e9bc7..62b53d710efd 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -12,12 +12,12 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <plat/addr-map.h>
15#include "common.h" 16#include "common.h"
16 17
17/* 18/*
18 * Generic Address Decode Windows bit settings 19 * Generic Address Decode Windows bit settings
19 */ 20 */
20#define TARGET_DDR 0
21#define TARGET_DEV_BUS 1 21#define TARGET_DEV_BUS 1
22#define TARGET_PCIE0 4 22#define TARGET_PCIE0 4
23#define TARGET_PCIE1 8 23#define TARGET_PCIE1 8
@@ -32,23 +32,10 @@
32#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l))) 32#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l)))
33 33
34/* 34/*
35 * Helpers to get DDR bank info
36 */
37#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
38#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
39
40/*
41 * CPU Address Decode Windows registers 35 * CPU Address Decode Windows registers
42 */ 36 */
43#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) 37#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
44#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) 38#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
45#define WIN_CTRL_OFF 0x0000
46#define WIN_BASE_OFF 0x0004
47#define WIN_REMAP_LO_OFF 0x0008
48#define WIN_REMAP_HI_OFF 0x000c
49
50
51struct mbus_dram_target_info mv78xx0_mbus_dram_info;
52 39
53static void __init __iomem *win_cfg_base(int win) 40static void __init __iomem *win_cfg_base(int win)
54{ 41{
@@ -63,94 +50,43 @@ static void __init __iomem *win_cfg_base(int win)
63 return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); 50 return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
64} 51}
65 52
66static int __init cpu_win_can_remap(int win) 53/*
67{ 54 * Description of the windows needed by the platform code
68 if (win < 8) 55 */
69 return 1; 56static struct __initdata orion_addr_map_cfg addr_map_cfg = {
70 57 .num_wins = 14,
71 return 0; 58 .remappable_wins = 8,
72} 59 .win_cfg_base = win_cfg_base,
73 60};
74static void __init setup_cpu_win(int win, u32 base, u32 size,
75 u8 target, u8 attr, int remap)
76{
77 void __iomem *addr = win_cfg_base(win);
78 u32 ctrl;
79
80 base &= 0xffff0000;
81 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
82
83 writel(base, addr + WIN_BASE_OFF);
84 writel(ctrl, addr + WIN_CTRL_OFF);
85 if (cpu_win_can_remap(win)) {
86 if (remap < 0)
87 remap = base;
88
89 writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
90 writel(0, addr + WIN_REMAP_HI_OFF);
91 }
92}
93 61
94void __init mv78xx0_setup_cpu_mbus(void) 62void __init mv78xx0_setup_cpu_mbus(void)
95{ 63{
96 void __iomem *addr;
97 int i;
98 int cs;
99
100 /* 64 /*
101 * First, disable and clear windows. 65 * Disable, clear and configure windows.
102 */ 66 */
103 for (i = 0; i < 14; i++) { 67 orion_config_wins(&addr_map_cfg, NULL);
104 addr = win_cfg_base(i);
105
106 writel(0, addr + WIN_BASE_OFF);
107 writel(0, addr + WIN_CTRL_OFF);
108 if (cpu_win_can_remap(i)) {
109 writel(0, addr + WIN_REMAP_LO_OFF);
110 writel(0, addr + WIN_REMAP_HI_OFF);
111 }
112 }
113 68
114 /* 69 /*
115 * Setup MBUS dram target info. 70 * Setup MBUS dram target info.
116 */ 71 */
117 mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
118
119 if (mv78xx0_core_index() == 0) 72 if (mv78xx0_core_index() == 0)
120 addr = (void __iomem *)DDR_WINDOW_CPU0_BASE; 73 orion_setup_cpu_mbus_target(&addr_map_cfg,
74 DDR_WINDOW_CPU0_BASE);
121 else 75 else
122 addr = (void __iomem *)DDR_WINDOW_CPU1_BASE; 76 orion_setup_cpu_mbus_target(&addr_map_cfg,
123 77 DDR_WINDOW_CPU1_BASE);
124 for (i = 0, cs = 0; i < 4; i++) {
125 u32 base = readl(addr + DDR_BASE_CS_OFF(i));
126 u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
127
128 /*
129 * Chip select enabled?
130 */
131 if (size & 1) {
132 struct mbus_dram_window *w;
133
134 w = &mv78xx0_mbus_dram_info.cs[cs++];
135 w->cs_index = i;
136 w->mbus_attr = 0xf & ~(1 << i);
137 w->base = base & 0xffff0000;
138 w->size = (size | 0x0000ffff) + 1;
139 }
140 }
141 mv78xx0_mbus_dram_info.num_cs = cs;
142} 78}
143 79
144void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, 80void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
145 int maj, int min) 81 int maj, int min)
146{ 82{
147 setup_cpu_win(window, base, size, TARGET_PCIE(maj), 83 orion_setup_cpu_win(&addr_map_cfg, window, base, size,
148 ATTR_PCIE_IO(min), -1); 84 TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1);
149} 85}
150 86
151void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, 87void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
152 int maj, int min) 88 int maj, int min)
153{ 89{
154 setup_cpu_win(window, base, size, TARGET_PCIE(maj), 90 orion_setup_cpu_win(&addr_map_cfg, window, base, size,
155 ATTR_PCIE_MEM(min), -1); 91 TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);
156} 92}
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 23d3980ef59d..534ce204e8b9 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -12,7 +12,6 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/serial_8250.h> 14#include <linux/serial_8250.h>
15#include <linux/mbus.h>
16#include <linux/ata_platform.h> 15#include <linux/ata_platform.h>
17#include <linux/ethtool.h> 16#include <linux/ethtool.h>
18#include <asm/mach/map.h> 17#include <asm/mach/map.h>
@@ -23,6 +22,7 @@
23#include <plat/orion_nand.h> 22#include <plat/orion_nand.h>
24#include <plat/time.h> 23#include <plat/time.h>
25#include <plat/common.h> 24#include <plat/common.h>
25#include <plat/addr-map.h>
26#include "common.h" 26#include "common.h"
27 27
28static int get_tclk(void); 28static int get_tclk(void);
@@ -169,8 +169,7 @@ void __init mv78xx0_map_io(void)
169 ****************************************************************************/ 169 ****************************************************************************/
170void __init mv78xx0_ehci0_init(void) 170void __init mv78xx0_ehci0_init(void)
171{ 171{
172 orion_ehci_init(&mv78xx0_mbus_dram_info, 172 orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
173 USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
174} 173}
175 174
176 175
@@ -179,8 +178,7 @@ void __init mv78xx0_ehci0_init(void)
179 ****************************************************************************/ 178 ****************************************************************************/
180void __init mv78xx0_ehci1_init(void) 179void __init mv78xx0_ehci1_init(void)
181{ 180{
182 orion_ehci_1_init(&mv78xx0_mbus_dram_info, 181 orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
183 USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
184} 182}
185 183
186 184
@@ -189,8 +187,7 @@ void __init mv78xx0_ehci1_init(void)
189 ****************************************************************************/ 187 ****************************************************************************/
190void __init mv78xx0_ehci2_init(void) 188void __init mv78xx0_ehci2_init(void)
191{ 189{
192 orion_ehci_2_init(&mv78xx0_mbus_dram_info, 190 orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
193 USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
194} 191}
195 192
196 193
@@ -199,7 +196,7 @@ void __init mv78xx0_ehci2_init(void)
199 ****************************************************************************/ 196 ****************************************************************************/
200void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) 197void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
201{ 198{
202 orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info, 199 orion_ge00_init(eth_data,
203 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, 200 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
204 IRQ_MV78XX0_GE_ERR, get_tclk()); 201 IRQ_MV78XX0_GE_ERR, get_tclk());
205} 202}
@@ -210,7 +207,7 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
210 ****************************************************************************/ 207 ****************************************************************************/
211void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) 208void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
212{ 209{
213 orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info, 210 orion_ge01_init(eth_data,
214 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, 211 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
215 NO_IRQ, get_tclk()); 212 NO_IRQ, get_tclk());
216} 213}
@@ -234,7 +231,7 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
234 eth_data->duplex = DUPLEX_FULL; 231 eth_data->duplex = DUPLEX_FULL;
235 } 232 }
236 233
237 orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info, 234 orion_ge10_init(eth_data,
238 GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, 235 GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
239 NO_IRQ, get_tclk()); 236 NO_IRQ, get_tclk());
240} 237}
@@ -258,7 +255,7 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
258 eth_data->duplex = DUPLEX_FULL; 255 eth_data->duplex = DUPLEX_FULL;
259 } 256 }
260 257
261 orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info, 258 orion_ge11_init(eth_data,
262 GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, 259 GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
263 NO_IRQ, get_tclk()); 260 NO_IRQ, get_tclk());
264} 261}
@@ -277,8 +274,7 @@ void __init mv78xx0_i2c_init(void)
277 ****************************************************************************/ 274 ****************************************************************************/
278void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) 275void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
279{ 276{
280 orion_sata_init(sata_data, &mv78xx0_mbus_dram_info, 277 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
281 SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
282} 278}
283 279
284 280
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 632e63d65e7a..f2ca59c75c6f 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -23,7 +23,6 @@ void mv78xx0_init(void);
23void mv78xx0_init_early(void); 23void mv78xx0_init_early(void);
24void mv78xx0_init_irq(void); 24void mv78xx0_init_irq(void);
25 25
26extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
27void mv78xx0_setup_cpu_mbus(void); 26void mv78xx0_setup_cpu_mbus(void);
28void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, 27void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
29 int maj, int min); 28 int maj, int min);
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index cf4e494d44bf..df50342179e2 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -10,7 +10,6 @@
10#include <linux/gpio.h> 10#include <linux/gpio.h>
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h> 13#include <linux/io.h>
15#include <plat/mpp.h> 14#include <plat/mpp.h>
16#include <mach/hardware.h> 15#include <mach/hardware.h>
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index c51af1cac300..12fcb108b0e1 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -10,11 +10,11 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/mbus.h>
14#include <video/vga.h> 13#include <video/vga.h>
15#include <asm/irq.h> 14#include <asm/irq.h>
16#include <asm/mach/pci.h> 15#include <asm/mach/pci.h>
17#include <plat/pcie.h> 16#include <plat/pcie.h>
17#include <plat/addr-map.h>
18#include "common.h" 18#include "common.h"
19 19
20struct pcie_port { 20struct pcie_port {
@@ -153,7 +153,7 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
153 * Generic PCIe unit setup. 153 * Generic PCIe unit setup.
154 */ 154 */
155 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 155 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
156 orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info); 156 orion_pcie_setup(pp->base);
157 157
158 sys->resource[0] = &pp->res[0]; 158 sys->resource[0] = &pp->res[0];
159 sys->resource[1] = &pp->res[1]; 159 sys->resource[1] = &pp->res[1];
diff --git a/arch/arm/mach-mx5/imx51-dt.c b/arch/arm/mach-mx5/imx51-dt.c
index ccc61585659b..596edd967dbf 100644
--- a/arch/arm/mach-mx5/imx51-dt.c
+++ b/arch/arm/mach-mx5/imx51-dt.c
@@ -44,20 +44,22 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
44 { /* sentinel */ } 44 { /* sentinel */ }
45}; 45};
46 46
47static void __init imx51_tzic_add_irq_domain(struct device_node *np, 47static int __init imx51_tzic_add_irq_domain(struct device_node *np,
48 struct device_node *interrupt_parent) 48 struct device_node *interrupt_parent)
49{ 49{
50 irq_domain_add_simple(np, 0); 50 irq_domain_add_simple(np, 0);
51 return 0;
51} 52}
52 53
53static void __init imx51_gpio_add_irq_domain(struct device_node *np, 54static int __init imx51_gpio_add_irq_domain(struct device_node *np,
54 struct device_node *interrupt_parent) 55 struct device_node *interrupt_parent)
55{ 56{
56 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS - 57 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
57 32 * 4; /* imx51 gets 4 gpio ports */
58 58
59 gpio_irq_base -= 32;
59 irq_domain_add_simple(np, gpio_irq_base); 60 irq_domain_add_simple(np, gpio_irq_base);
60 gpio_irq_base += 32; 61
62 return 0;
61} 63}
62 64
63static const struct of_device_id imx51_irq_match[] __initconst = { 65static const struct of_device_id imx51_irq_match[] __initconst = {
diff --git a/arch/arm/mach-mx5/imx53-dt.c b/arch/arm/mach-mx5/imx53-dt.c
index ccaa0b81b768..85bfd5ff21b0 100644
--- a/arch/arm/mach-mx5/imx53-dt.c
+++ b/arch/arm/mach-mx5/imx53-dt.c
@@ -48,20 +48,22 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
48 { /* sentinel */ } 48 { /* sentinel */ }
49}; 49};
50 50
51static void __init imx53_tzic_add_irq_domain(struct device_node *np, 51static int __init imx53_tzic_add_irq_domain(struct device_node *np,
52 struct device_node *interrupt_parent) 52 struct device_node *interrupt_parent)
53{ 53{
54 irq_domain_add_simple(np, 0); 54 irq_domain_add_simple(np, 0);
55 return 0;
55} 56}
56 57
57static void __init imx53_gpio_add_irq_domain(struct device_node *np, 58static int __init imx53_gpio_add_irq_domain(struct device_node *np,
58 struct device_node *interrupt_parent) 59 struct device_node *interrupt_parent)
59{ 60{
60 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS - 61 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
61 32 * 7; /* imx53 gets 7 gpio ports */
62 62
63 gpio_irq_base -= 32;
63 irq_domain_add_simple(np, gpio_irq_base); 64 irq_domain_add_simple(np, gpio_irq_base);
64 gpio_irq_base += 32; 65
66 return 0;
65} 67}
66 68
67static const struct of_device_id imx53_irq_match[] __initconst = { 69static const struct of_device_id imx53_irq_match[] __initconst = {
diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h
index 75d86118b76a..30c7990f3c01 100644
--- a/arch/arm/mach-mxs/include/mach/mx28.h
+++ b/arch/arm/mach-mxs/include/mach/mx28.h
@@ -104,8 +104,8 @@
104#define MX28_INT_CAN1 9 104#define MX28_INT_CAN1 9
105#define MX28_INT_LRADC_TOUCH 10 105#define MX28_INT_LRADC_TOUCH 10
106#define MX28_INT_HSADC 13 106#define MX28_INT_HSADC 13
107#define MX28_INT_IRADC_THRESH0 14 107#define MX28_INT_LRADC_THRESH0 14
108#define MX28_INT_IRADC_THRESH1 15 108#define MX28_INT_LRADC_THRESH1 15
109#define MX28_INT_LRADC_CH0 16 109#define MX28_INT_LRADC_CH0 16
110#define MX28_INT_LRADC_CH1 17 110#define MX28_INT_LRADC_CH1 17
111#define MX28_INT_LRADC_CH2 18 111#define MX28_INT_LRADC_CH2 18
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
index 0d2d2b470998..bde5f6634747 100644
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -30,6 +30,7 @@
30 */ 30 */
31#define cpu_is_mx23() ( \ 31#define cpu_is_mx23() ( \
32 machine_is_mx23evk() || \ 32 machine_is_mx23evk() || \
33 machine_is_stmp378x() || \
33 0) 34 0)
34#define cpu_is_mx28() ( \ 35#define cpu_is_mx28() ( \
35 machine_is_mx28evk() || \ 36 machine_is_mx28evk() || \
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
index 3b1681e4f49a..6b00577b7025 100644
--- a/arch/arm/mach-mxs/mach-m28evk.c
+++ b/arch/arm/mach-mxs/mach-m28evk.c
@@ -361,6 +361,6 @@ static struct sys_timer m28evk_timer = {
361MACHINE_START(M28EVK, "DENX M28 EVK") 361MACHINE_START(M28EVK, "DENX M28 EVK")
362 .map_io = mx28_map_io, 362 .map_io = mx28_map_io,
363 .init_irq = mx28_init_irq, 363 .init_irq = mx28_init_irq,
364 .init_machine = m28evk_init,
365 .timer = &m28evk_timer, 364 .timer = &m28evk_timer,
365 .init_machine = m28evk_init,
366MACHINE_END 366MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
index 177e53123a02..6834dea38c04 100644
--- a/arch/arm/mach-mxs/mach-stmp378x_devb.c
+++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c
@@ -115,6 +115,6 @@ static struct sys_timer stmp378x_dvb_timer = {
115MACHINE_START(STMP378X, "STMP378X") 115MACHINE_START(STMP378X, "STMP378X")
116 .map_io = mx23_map_io, 116 .map_io = mx23_map_io,
117 .init_irq = mx23_init_irq, 117 .init_irq = mx23_init_irq,
118 .init_machine = stmp378x_dvb_init,
119 .timer = &stmp378x_dvb_timer, 118 .timer = &stmp378x_dvb_timer,
119 .init_machine = stmp378x_dvb_init,
120MACHINE_END 120MACHINE_END
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c
index 0fcff47009cf..9a7b08b2a925 100644
--- a/arch/arm/mach-mxs/module-tx28.c
+++ b/arch/arm/mach-mxs/module-tx28.c
@@ -66,11 +66,11 @@ static const iomux_cfg_t tx28_fec1_pads[] __initconst = {
66 MX28_PAD_ENET0_CRS__ENET1_RX_EN, 66 MX28_PAD_ENET0_CRS__ENET1_RX_EN,
67}; 67};
68 68
69static struct fec_platform_data tx28_fec0_data = { 69static const struct fec_platform_data tx28_fec0_data __initconst = {
70 .phy = PHY_INTERFACE_MODE_RMII, 70 .phy = PHY_INTERFACE_MODE_RMII,
71}; 71};
72 72
73static struct fec_platform_data tx28_fec1_data = { 73static const struct fec_platform_data tx28_fec1_data __initconst = {
74 .phy = PHY_INTERFACE_MODE_RMII, 74 .phy = PHY_INTERFACE_MODE_RMII,
75}; 75};
76 76
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 5ceafdccc456..3638e5c12b7e 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -14,8 +14,8 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/mbus.h> 15#include <linux/mbus.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/errno.h>
18#include <mach/hardware.h> 17#include <mach/hardware.h>
18#include <plat/addr-map.h>
19#include "common.h" 19#include "common.h"
20 20
21/* 21/*
@@ -41,7 +41,6 @@
41/* 41/*
42 * Generic Address Decode Windows bit settings 42 * Generic Address Decode Windows bit settings
43 */ 43 */
44#define TARGET_DDR 0
45#define TARGET_DEV_BUS 1 44#define TARGET_DEV_BUS 1
46#define TARGET_PCI 3 45#define TARGET_PCI 3
47#define TARGET_PCIE 4 46#define TARGET_PCIE 4
@@ -57,27 +56,10 @@
57#define ATTR_DEV_BOOT 0xf 56#define ATTR_DEV_BOOT 0xf
58#define ATTR_SRAM 0x0 57#define ATTR_SRAM 0x0
59 58
60/*
61 * Helpers to get DDR bank info
62 */
63#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x))
64#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3))
65#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3))
66
67/*
68 * CPU Address Decode Windows registers
69 */
70#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x))
71#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
72#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
73#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
74#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
75
76
77struct mbus_dram_target_info orion5x_mbus_dram_info;
78static int __initdata win_alloc_count; 59static int __initdata win_alloc_count;
79 60
80static int __init orion5x_cpu_win_can_remap(int win) 61static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
62 const int win)
81{ 63{
82 u32 dev, rev; 64 u32 dev, rev;
83 65
@@ -91,116 +73,82 @@ static int __init orion5x_cpu_win_can_remap(int win)
91 return 0; 73 return 0;
92} 74}
93 75
94static int __init setup_cpu_win(int win, u32 base, u32 size, 76/*
95 u8 target, u8 attr, int remap) 77 * Description of the windows needed by the platform code
96{ 78 */
97 if (win >= 8) { 79static struct __initdata orion_addr_map_cfg addr_map_cfg = {
98 printk(KERN_ERR "setup_cpu_win: trying to allocate " 80 .num_wins = 8,
99 "window %d\n", win); 81 .cpu_win_can_remap = cpu_win_can_remap,
100 return -ENOSPC; 82 .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
101 } 83};
102
103 writel(base & 0xffff0000, CPU_WIN_BASE(win));
104 writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1,
105 CPU_WIN_CTRL(win));
106
107 if (orion5x_cpu_win_can_remap(win)) {
108 if (remap < 0)
109 remap = base;
110
111 writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
112 writel(0, CPU_WIN_REMAP_HI(win));
113 }
114 return 0;
115}
116
117void __init orion5x_setup_cpu_mbus_bridge(void)
118{
119 int i;
120 int cs;
121 84
85static const struct __initdata orion_addr_map_info addr_map_info[] = {
122 /* 86 /*
123 * First, disable and clear windows. 87 * Setup windows for PCI+PCIe IO+MEM space.
124 */ 88 */
125 for (i = 0; i < 8; i++) { 89 { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
126 writel(0, CPU_WIN_BASE(i)); 90 TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE
127 writel(0, CPU_WIN_CTRL(i)); 91 },
128 if (orion5x_cpu_win_can_remap(i)) { 92 { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
129 writel(0, CPU_WIN_REMAP_LO(i)); 93 TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE
130 writel(0, CPU_WIN_REMAP_HI(i)); 94 },
131 } 95 { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
132 } 96 TARGET_PCIE, ATTR_PCIE_MEM, -1
97 },
98 { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
99 TARGET_PCI, ATTR_PCI_MEM, -1
100 },
101 /* End marker */
102 { -1, 0, 0, 0, 0, 0 }
103};
133 104
105void __init orion5x_setup_cpu_mbus_bridge(void)
106{
134 /* 107 /*
135 * Setup windows for PCI+PCIe IO+MEM space. 108 * Disable, clear and configure windows.
136 */ 109 */
137 setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE, 110 orion_config_wins(&addr_map_cfg, addr_map_info);
138 TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE);
139 setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
140 TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE);
141 setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
142 TARGET_PCIE, ATTR_PCIE_MEM, -1);
143 setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
144 TARGET_PCI, ATTR_PCI_MEM, -1);
145 win_alloc_count = 4; 111 win_alloc_count = 4;
146 112
147 /* 113 /*
148 * Setup MBUS dram target info. 114 * Setup MBUS dram target info.
149 */ 115 */
150 orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 116 orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
151
152 for (i = 0, cs = 0; i < 4; i++) {
153 u32 base = readl(DDR_BASE_CS(i));
154 u32 size = readl(DDR_SIZE_CS(i));
155
156 /*
157 * Chip select enabled?
158 */
159 if (size & 1) {
160 struct mbus_dram_window *w;
161
162 w = &orion5x_mbus_dram_info.cs[cs++];
163 w->cs_index = i;
164 w->mbus_attr = 0xf & ~(1 << i);
165 w->base = base & 0xffff0000;
166 w->size = (size | 0x0000ffff) + 1;
167 }
168 }
169 orion5x_mbus_dram_info.num_cs = cs;
170} 117}
171 118
172void __init orion5x_setup_dev_boot_win(u32 base, u32 size) 119void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
173{ 120{
174 setup_cpu_win(win_alloc_count++, base, size, 121 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
175 TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); 122 TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
176} 123}
177 124
178void __init orion5x_setup_dev0_win(u32 base, u32 size) 125void __init orion5x_setup_dev0_win(u32 base, u32 size)
179{ 126{
180 setup_cpu_win(win_alloc_count++, base, size, 127 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
181 TARGET_DEV_BUS, ATTR_DEV_CS0, -1); 128 TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
182} 129}
183 130
184void __init orion5x_setup_dev1_win(u32 base, u32 size) 131void __init orion5x_setup_dev1_win(u32 base, u32 size)
185{ 132{
186 setup_cpu_win(win_alloc_count++, base, size, 133 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
187 TARGET_DEV_BUS, ATTR_DEV_CS1, -1); 134 TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
188} 135}
189 136
190void __init orion5x_setup_dev2_win(u32 base, u32 size) 137void __init orion5x_setup_dev2_win(u32 base, u32 size)
191{ 138{
192 setup_cpu_win(win_alloc_count++, base, size, 139 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
193 TARGET_DEV_BUS, ATTR_DEV_CS2, -1); 140 TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
194} 141}
195 142
196void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) 143void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
197{ 144{
198 setup_cpu_win(win_alloc_count++, base, size, 145 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
199 TARGET_PCIE, ATTR_PCIE_WA, -1); 146 TARGET_PCIE, ATTR_PCIE_WA, -1);
200} 147}
201 148
202int __init orion5x_setup_sram_win(void) 149void __init orion5x_setup_sram_win(void)
203{ 150{
204 return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE, 151 orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++,
205 ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); 152 ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE,
153 TARGET_SRAM, ATTR_SRAM, -1);
206} 154}
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 22ace0bf2f92..79ef693d2c03 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -15,7 +15,6 @@
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h> 16#include <linux/dma-mapping.h>
17#include <linux/serial_8250.h> 17#include <linux/serial_8250.h>
18#include <linux/mbus.h>
19#include <linux/mv643xx_i2c.h> 18#include <linux/mv643xx_i2c.h>
20#include <linux/ata_platform.h> 19#include <linux/ata_platform.h>
21#include <net/dsa.h> 20#include <net/dsa.h>
@@ -31,6 +30,7 @@
31#include <plat/orion_nand.h> 30#include <plat/orion_nand.h>
32#include <plat/time.h> 31#include <plat/time.h>
33#include <plat/common.h> 32#include <plat/common.h>
33#include <plat/addr-map.h>
34#include "common.h" 34#include "common.h"
35 35
36/***************************************************************************** 36/*****************************************************************************
@@ -71,8 +71,7 @@ void __init orion5x_map_io(void)
71 ****************************************************************************/ 71 ****************************************************************************/
72void __init orion5x_ehci0_init(void) 72void __init orion5x_ehci0_init(void)
73{ 73{
74 orion_ehci_init(&orion5x_mbus_dram_info, 74 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
75 ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
76} 75}
77 76
78 77
@@ -81,8 +80,7 @@ void __init orion5x_ehci0_init(void)
81 ****************************************************************************/ 80 ****************************************************************************/
82void __init orion5x_ehci1_init(void) 81void __init orion5x_ehci1_init(void)
83{ 82{
84 orion_ehci_1_init(&orion5x_mbus_dram_info, 83 orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
85 ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
86} 84}
87 85
88 86
@@ -91,7 +89,7 @@ void __init orion5x_ehci1_init(void)
91 ****************************************************************************/ 89 ****************************************************************************/
92void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) 90void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
93{ 91{
94 orion_ge00_init(eth_data, &orion5x_mbus_dram_info, 92 orion_ge00_init(eth_data,
95 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, 93 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
96 IRQ_ORION5X_ETH_ERR, orion5x_tclk); 94 IRQ_ORION5X_ETH_ERR, orion5x_tclk);
97} 95}
@@ -121,8 +119,7 @@ void __init orion5x_i2c_init(void)
121 ****************************************************************************/ 119 ****************************************************************************/
122void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) 120void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
123{ 121{
124 orion_sata_init(sata_data, &orion5x_mbus_dram_info, 122 orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
125 ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
126} 123}
127 124
128 125
@@ -158,8 +155,7 @@ void __init orion5x_uart1_init(void)
158 ****************************************************************************/ 155 ****************************************************************************/
159void __init orion5x_xor_init(void) 156void __init orion5x_xor_init(void)
160{ 157{
161 orion_xor0_init(&orion5x_mbus_dram_info, 158 orion_xor0_init(ORION5X_XOR_PHYS_BASE,
162 ORION5X_XOR_PHYS_BASE,
163 ORION5X_XOR_PHYS_BASE + 0x200, 159 ORION5X_XOR_PHYS_BASE + 0x200,
164 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); 160 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
165} 161}
@@ -169,12 +165,7 @@ void __init orion5x_xor_init(void)
169 ****************************************************************************/ 165 ****************************************************************************/
170static void __init orion5x_crypto_init(void) 166static void __init orion5x_crypto_init(void)
171{ 167{
172 int ret; 168 orion5x_setup_sram_win();
173
174 ret = orion5x_setup_sram_win();
175 if (ret)
176 return;
177
178 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, 169 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
179 SZ_8K, IRQ_ORION5X_CESA); 170 SZ_8K, IRQ_ORION5X_CESA);
180} 171}
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 909489f4d23e..889d80c7a151 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -20,14 +20,13 @@ extern struct sys_timer orion5x_timer;
20 * functions to map its interfaces and by the machine-setup to map its on- 20 * functions to map its interfaces and by the machine-setup to map its on-
21 * board devices. Details in /mach-orion/addr-map.c 21 * board devices. Details in /mach-orion/addr-map.c
22 */ 22 */
23extern struct mbus_dram_target_info orion5x_mbus_dram_info;
24void orion5x_setup_cpu_mbus_bridge(void); 23void orion5x_setup_cpu_mbus_bridge(void);
25void orion5x_setup_dev_boot_win(u32 base, u32 size); 24void orion5x_setup_dev_boot_win(u32 base, u32 size);
26void orion5x_setup_dev0_win(u32 base, u32 size); 25void orion5x_setup_dev0_win(u32 base, u32 size);
27void orion5x_setup_dev1_win(u32 base, u32 size); 26void orion5x_setup_dev1_win(u32 base, u32 size);
28void orion5x_setup_dev2_win(u32 base, u32 size); 27void orion5x_setup_dev2_win(u32 base, u32 size);
29void orion5x_setup_pcie_wa_win(u32 base, u32 size); 28void orion5x_setup_pcie_wa_win(u32 base, u32 size);
30int orion5x_setup_sram_win(void); 29void orion5x_setup_sram_win(void);
31 30
32void orion5x_ehci0_init(void); 31void orion5x_ehci0_init(void);
33void orion5x_ehci1_init(void); 32void orion5x_ehci1_init(void);
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 0a28bbc76891..2745f5d95b3f 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -69,7 +69,7 @@
69 ******************************************************************************/ 69 ******************************************************************************/
70 70
71#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) 71#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000)
72 72#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE | 0x1500)
73#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) 73#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
74#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) 74#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
75#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) 75#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index b6ddd7a5db6a..5b70026f478c 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -10,7 +10,6 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h> 13#include <linux/io.h>
15#include <mach/hardware.h> 14#include <mach/hardware.h>
16#include <plat/mpp.h> 15#include <plat/mpp.h>
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index bc4a920e26ee..a494c470e3e4 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -18,6 +18,7 @@
18#include <asm/irq.h> 18#include <asm/irq.h>
19#include <asm/mach/pci.h> 19#include <asm/mach/pci.h>
20#include <plat/pcie.h> 20#include <plat/pcie.h>
21#include <plat/addr-map.h>
21#include "common.h" 22#include "common.h"
22 23
23/***************************************************************************** 24/*****************************************************************************
@@ -145,7 +146,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
145 /* 146 /*
146 * Generic PCIe unit setup. 147 * Generic PCIe unit setup.
147 */ 148 */
148 orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); 149 orion_pcie_setup(PCIE_BASE);
149 150
150 /* 151 /*
151 * Check whether to apply Orion-1/Orion-NAS PCIe config 152 * Check whether to apply Orion-1/Orion-NAS PCIe config
@@ -477,7 +478,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
477 /* 478 /*
478 * Point PCI unit MBUS decode windows to DRAM space. 479 * Point PCI unit MBUS decode windows to DRAM space.
479 */ 480 */
480 orion5x_setup_pci_wins(&orion5x_mbus_dram_info); 481 orion5x_setup_pci_wins(&orion_mbus_dram_info);
481 482
482 /* 483 /*
483 * Master + Slave enable 484 * Master + Slave enable
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index cb53160f6c5d..26ebb57719df 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -9,6 +9,7 @@
9#include <linux/kernel.h> 9#include <linux/kernel.h>
10#include <linux/suspend.h> 10#include <linux/suspend.h>
11#include <linux/slab.h> 11#include <linux/slab.h>
12#include <linux/module.h>
12#include <linux/of.h> 13#include <linux/of.h>
13#include <linux/of_address.h> 14#include <linux/of_address.h>
14#include <linux/of_device.h> 15#include <linux/of_device.h>
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c
index ef555c041962..a12b689a8702 100644
--- a/arch/arm/mach-prima2/prima2.c
+++ b/arch/arm/mach-prima2/prima2.c
@@ -8,6 +8,7 @@
8 8
9#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <asm/sizes.h>
11#include <asm/mach-types.h> 12#include <asm/mach-types.h>
12#include <asm/mach/arch.h> 13#include <asm/mach/arch.h>
13#include <linux/of.h> 14#include <linux/of.h>
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
index 5e6b42089eb4..3341fd118723 100644
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ b/arch/arm/mach-s3c64xx/dev-spi.c
@@ -10,6 +10,7 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/string.h> 12#include <linux/string.h>
13#include <linux/export.h>
13#include <linux/platform_device.h> 14#include <linux/platform_device.h>
14#include <linux/dma-mapping.h> 15#include <linux/dma-mapping.h>
15#include <linux/gpio.h> 16#include <linux/gpio.h>
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 7a3bc32df425..51c00f2453c6 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -70,7 +70,7 @@ void __init s3c6400_init_irq(void)
70 s3c64xx_init_irq(~0 & ~(0xf << 5), ~0); 70 s3c64xx_init_irq(~0 & ~(0xf << 5), ~0);
71} 71}
72 72
73struct sysdev_class s3c6400_sysclass = { 73static struct sysdev_class s3c6400_sysclass = {
74 .name = "s3c6400-core", 74 .name = "s3c6400-core",
75}; 75};
76 76
diff --git a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
index 83d2afb79e9f..2cf80026c58d 100644
--- a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
+++ b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
@@ -20,7 +20,7 @@
20#include <plat/fb.h> 20#include <plat/fb.h>
21#include <plat/gpio-cfg.h> 21#include <plat/gpio-cfg.h>
22 22
23extern void s3c64xx_fb_gpio_setup_24bpp(void) 23void s3c64xx_fb_gpio_setup_24bpp(void)
24{ 24{
25 s3c_gpio_cfgrange_nopull(S3C64XX_GPI(0), 16, S3C_GPIO_SFN(2)); 25 s3c_gpio_cfgrange_nopull(S3C64XX_GPI(0), 16, S3C_GPIO_SFN(2));
26 s3c_gpio_cfgrange_nopull(S3C64XX_GPJ(0), 12, S3C_GPIO_SFN(2)); 26 s3c_gpio_cfgrange_nopull(S3C64XX_GPJ(0), 12, S3C_GPIO_SFN(2));
diff --git a/arch/arm/mach-sa1100/Makefile.boot b/arch/arm/mach-sa1100/Makefile.boot
index 5a616f6e5612..f7951aa04562 100644
--- a/arch/arm/mach-sa1100/Makefile.boot
+++ b/arch/arm/mach-sa1100/Makefile.boot
@@ -1,5 +1,5 @@
1ifeq ($(CONFIG_ARCH_SA1100),y) 1ifeq ($(CONFIG_SA1111),y)
2 zreladdr-$(CONFIG_SA1111) += 0xc0208000 2 zreladdr-y += 0xc0208000
3else 3else
4 zreladdr-y += 0xc0008000 4 zreladdr-y += 0xc0008000
5endif 5endif
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index 95a5fc53b6db..c20ce0f5ce33 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := irq.o pcie.o time.o common.o mpp.o 5obj-y := irq.o pcie.o time.o common.o mpp.o addr-map.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
new file mode 100644
index 000000000000..367ca89ac403
--- /dev/null
+++ b/arch/arm/plat-orion/addr-map.c
@@ -0,0 +1,174 @@
1/*
2 * arch/arm/plat-orion/addr-map.c
3 *
4 * Address map functions for Marvell Orion based SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/mbus.h>
15#include <linux/io.h>
16#include <plat/addr-map.h>
17
18struct mbus_dram_target_info orion_mbus_dram_info;
19
20const struct mbus_dram_target_info *mv_mbus_dram_info(void)
21{
22 return &orion_mbus_dram_info;
23}
24EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
25
26/*
27 * DDR target is the same on all Orion platforms.
28 */
29#define TARGET_DDR 0
30
31/*
32 * Helpers to get DDR bank info
33 */
34#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
35#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
36
37/*
38 * CPU Address Decode Windows registers
39 */
40#define WIN_CTRL_OFF 0x0000
41#define WIN_BASE_OFF 0x0004
42#define WIN_REMAP_LO_OFF 0x0008
43#define WIN_REMAP_HI_OFF 0x000c
44
45/*
46 * Default implementation
47 */
48static void __init __iomem *
49orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
50{
51 return (void __iomem *)(cfg->bridge_virt_base + (win << 4));
52}
53
54/*
55 * Default implementation
56 */
57static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
58 const int win)
59{
60 if (win < cfg->remappable_wins)
61 return 1;
62
63 return 0;
64}
65
66void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
67 const int win, const u32 base,
68 const u32 size, const u8 target,
69 const u8 attr, const int remap)
70{
71 void __iomem *addr = cfg->win_cfg_base(cfg, win);
72 u32 ctrl, base_high, remap_addr;
73
74 if (win >= cfg->num_wins) {
75 printk(KERN_ERR "setup_cpu_win: trying to allocate window "
76 "%d when only %d allowed\n", win, cfg->num_wins);
77 }
78
79 base_high = base & 0xffff0000;
80 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
81
82 writel(base_high, addr + WIN_BASE_OFF);
83 writel(ctrl, addr + WIN_CTRL_OFF);
84 if (cfg->cpu_win_can_remap(cfg, win)) {
85 if (remap < 0)
86 remap_addr = base;
87 else
88 remap_addr = remap;
89 writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF);
90 writel(0, addr + WIN_REMAP_HI_OFF);
91 }
92}
93
94/*
95 * Configure a number of windows.
96 */
97static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg,
98 const struct orion_addr_map_info *info)
99{
100 while (info->win != -1) {
101 orion_setup_cpu_win(cfg, info->win, info->base, info->size,
102 info->target, info->attr, info->remap);
103 info++;
104 }
105}
106
107static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg)
108{
109 void __iomem *addr;
110 int i;
111
112 for (i = 0; i < cfg->num_wins; i++) {
113 addr = cfg->win_cfg_base(cfg, i);
114
115 writel(0, addr + WIN_BASE_OFF);
116 writel(0, addr + WIN_CTRL_OFF);
117 if (cfg->cpu_win_can_remap(cfg, i)) {
118 writel(0, addr + WIN_REMAP_LO_OFF);
119 writel(0, addr + WIN_REMAP_HI_OFF);
120 }
121 }
122}
123
124/*
125 * Disable, clear and configure windows.
126 */
127void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
128 const struct orion_addr_map_info *info)
129{
130 if (!cfg->cpu_win_can_remap)
131 cfg->cpu_win_can_remap = orion_cpu_win_can_remap;
132
133 if (!cfg->win_cfg_base)
134 cfg->win_cfg_base = orion_win_cfg_base;
135
136 orion_disable_wins(cfg);
137
138 if (info)
139 orion_setup_cpu_wins(cfg, info);
140}
141
142/*
143 * Setup MBUS dram target info.
144 */
145void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
146 const u32 ddr_window_cpu_base)
147{
148 void __iomem *addr;
149 int i;
150 int cs;
151
152 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
153
154 addr = (void __iomem *)ddr_window_cpu_base;
155
156 for (i = 0, cs = 0; i < 4; i++) {
157 u32 base = readl(addr + DDR_BASE_CS_OFF(i));
158 u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
159
160 /*
161 * Chip select enabled?
162 */
163 if (size & 1) {
164 struct mbus_dram_window *w;
165
166 w = &orion_mbus_dram_info.cs[cs++];
167 w->cs_index = i;
168 w->mbus_attr = 0xf & ~(1 << i);
169 w->base = base & 0xffff0000;
170 w->size = (size | 0x0000ffff) + 1;
171 }
172 }
173 orion_mbus_dram_info.num_cs = cs;
174}
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 9e5451b3c8e3..e5a2fde29b19 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -13,7 +13,6 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
15#include <linux/serial_8250.h> 15#include <linux/serial_8250.h>
16#include <linux/mbus.h>
17#include <linux/ata_platform.h> 16#include <linux/ata_platform.h>
18#include <linux/mv643xx_eth.h> 17#include <linux/mv643xx_eth.h>
19#include <linux/mv643xx_i2c.h> 18#include <linux/mv643xx_i2c.h>
@@ -203,13 +202,12 @@ void __init orion_rtc_init(unsigned long mapbase,
203 ****************************************************************************/ 202 ****************************************************************************/
204static __init void ge_complete( 203static __init void ge_complete(
205 struct mv643xx_eth_shared_platform_data *orion_ge_shared_data, 204 struct mv643xx_eth_shared_platform_data *orion_ge_shared_data,
206 struct mbus_dram_target_info *mbus_dram_info, int tclk, 205 int tclk,
207 struct resource *orion_ge_resource, unsigned long irq, 206 struct resource *orion_ge_resource, unsigned long irq,
208 struct platform_device *orion_ge_shared, 207 struct platform_device *orion_ge_shared,
209 struct mv643xx_eth_platform_data *eth_data, 208 struct mv643xx_eth_platform_data *eth_data,
210 struct platform_device *orion_ge) 209 struct platform_device *orion_ge)
211{ 210{
212 orion_ge_shared_data->dram = mbus_dram_info;
213 orion_ge_shared_data->t_clk = tclk; 211 orion_ge_shared_data->t_clk = tclk;
214 orion_ge_resource->start = irq; 212 orion_ge_resource->start = irq;
215 orion_ge_resource->end = irq; 213 orion_ge_resource->end = irq;
@@ -259,7 +257,6 @@ static struct platform_device orion_ge00 = {
259}; 257};
260 258
261void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, 259void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
262 struct mbus_dram_target_info *mbus_dram_info,
263 unsigned long mapbase, 260 unsigned long mapbase,
264 unsigned long irq, 261 unsigned long irq,
265 unsigned long irq_err, 262 unsigned long irq_err,
@@ -267,7 +264,7 @@ void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
267{ 264{
268 fill_resources(&orion_ge00_shared, orion_ge00_shared_resources, 265 fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
269 mapbase + 0x2000, SZ_16K - 1, irq_err); 266 mapbase + 0x2000, SZ_16K - 1, irq_err);
270 ge_complete(&orion_ge00_shared_data, mbus_dram_info, tclk, 267 ge_complete(&orion_ge00_shared_data, tclk,
271 orion_ge00_resources, irq, &orion_ge00_shared, 268 orion_ge00_resources, irq, &orion_ge00_shared,
272 eth_data, &orion_ge00); 269 eth_data, &orion_ge00);
273} 270}
@@ -313,7 +310,6 @@ static struct platform_device orion_ge01 = {
313}; 310};
314 311
315void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, 312void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
316 struct mbus_dram_target_info *mbus_dram_info,
317 unsigned long mapbase, 313 unsigned long mapbase,
318 unsigned long irq, 314 unsigned long irq,
319 unsigned long irq_err, 315 unsigned long irq_err,
@@ -321,7 +317,7 @@ void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
321{ 317{
322 fill_resources(&orion_ge01_shared, orion_ge01_shared_resources, 318 fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
323 mapbase + 0x2000, SZ_16K - 1, irq_err); 319 mapbase + 0x2000, SZ_16K - 1, irq_err);
324 ge_complete(&orion_ge01_shared_data, mbus_dram_info, tclk, 320 ge_complete(&orion_ge01_shared_data, tclk,
325 orion_ge01_resources, irq, &orion_ge01_shared, 321 orion_ge01_resources, irq, &orion_ge01_shared,
326 eth_data, &orion_ge01); 322 eth_data, &orion_ge01);
327} 323}
@@ -367,7 +363,6 @@ static struct platform_device orion_ge10 = {
367}; 363};
368 364
369void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, 365void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
370 struct mbus_dram_target_info *mbus_dram_info,
371 unsigned long mapbase, 366 unsigned long mapbase,
372 unsigned long irq, 367 unsigned long irq,
373 unsigned long irq_err, 368 unsigned long irq_err,
@@ -375,7 +370,7 @@ void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
375{ 370{
376 fill_resources(&orion_ge10_shared, orion_ge10_shared_resources, 371 fill_resources(&orion_ge10_shared, orion_ge10_shared_resources,
377 mapbase + 0x2000, SZ_16K - 1, irq_err); 372 mapbase + 0x2000, SZ_16K - 1, irq_err);
378 ge_complete(&orion_ge10_shared_data, mbus_dram_info, tclk, 373 ge_complete(&orion_ge10_shared_data, tclk,
379 orion_ge10_resources, irq, &orion_ge10_shared, 374 orion_ge10_resources, irq, &orion_ge10_shared,
380 eth_data, &orion_ge10); 375 eth_data, &orion_ge10);
381} 376}
@@ -421,7 +416,6 @@ static struct platform_device orion_ge11 = {
421}; 416};
422 417
423void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, 418void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
424 struct mbus_dram_target_info *mbus_dram_info,
425 unsigned long mapbase, 419 unsigned long mapbase,
426 unsigned long irq, 420 unsigned long irq,
427 unsigned long irq_err, 421 unsigned long irq_err,
@@ -429,7 +423,7 @@ void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
429{ 423{
430 fill_resources(&orion_ge11_shared, orion_ge11_shared_resources, 424 fill_resources(&orion_ge11_shared, orion_ge11_shared_resources,
431 mapbase + 0x2000, SZ_16K - 1, irq_err); 425 mapbase + 0x2000, SZ_16K - 1, irq_err);
432 ge_complete(&orion_ge11_shared_data, mbus_dram_info, tclk, 426 ge_complete(&orion_ge11_shared_data, tclk,
433 orion_ge11_resources, irq, &orion_ge11_shared, 427 orion_ge11_resources, irq, &orion_ge11_shared,
434 eth_data, &orion_ge11); 428 eth_data, &orion_ge11);
435} 429}
@@ -592,8 +586,6 @@ void __init orion_wdt_init(unsigned long tclk)
592/***************************************************************************** 586/*****************************************************************************
593 * XOR 587 * XOR
594 ****************************************************************************/ 588 ****************************************************************************/
595static struct mv_xor_platform_shared_data orion_xor_shared_data;
596
597static u64 orion_xor_dmamask = DMA_BIT_MASK(32); 589static u64 orion_xor_dmamask = DMA_BIT_MASK(32);
598 590
599void __init orion_xor_init_channels( 591void __init orion_xor_init_channels(
@@ -632,9 +624,6 @@ static struct resource orion_xor0_shared_resources[] = {
632static struct platform_device orion_xor0_shared = { 624static struct platform_device orion_xor0_shared = {
633 .name = MV_XOR_SHARED_NAME, 625 .name = MV_XOR_SHARED_NAME,
634 .id = 0, 626 .id = 0,
635 .dev = {
636 .platform_data = &orion_xor_shared_data,
637 },
638 .num_resources = ARRAY_SIZE(orion_xor0_shared_resources), 627 .num_resources = ARRAY_SIZE(orion_xor0_shared_resources),
639 .resource = orion_xor0_shared_resources, 628 .resource = orion_xor0_shared_resources,
640}; 629};
@@ -687,14 +676,11 @@ static struct platform_device orion_xor01_channel = {
687 }, 676 },
688}; 677};
689 678
690void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info, 679void __init orion_xor0_init(unsigned long mapbase_low,
691 unsigned long mapbase_low,
692 unsigned long mapbase_high, 680 unsigned long mapbase_high,
693 unsigned long irq_0, 681 unsigned long irq_0,
694 unsigned long irq_1) 682 unsigned long irq_1)
695{ 683{
696 orion_xor_shared_data.dram = mbus_dram_info;
697
698 orion_xor0_shared_resources[0].start = mapbase_low; 684 orion_xor0_shared_resources[0].start = mapbase_low;
699 orion_xor0_shared_resources[0].end = mapbase_low + 0xff; 685 orion_xor0_shared_resources[0].end = mapbase_low + 0xff;
700 orion_xor0_shared_resources[1].start = mapbase_high; 686 orion_xor0_shared_resources[1].start = mapbase_high;
@@ -727,9 +713,6 @@ static struct resource orion_xor1_shared_resources[] = {
727static struct platform_device orion_xor1_shared = { 713static struct platform_device orion_xor1_shared = {
728 .name = MV_XOR_SHARED_NAME, 714 .name = MV_XOR_SHARED_NAME,
729 .id = 1, 715 .id = 1,
730 .dev = {
731 .platform_data = &orion_xor_shared_data,
732 },
733 .num_resources = ARRAY_SIZE(orion_xor1_shared_resources), 716 .num_resources = ARRAY_SIZE(orion_xor1_shared_resources),
734 .resource = orion_xor1_shared_resources, 717 .resource = orion_xor1_shared_resources,
735}; 718};
@@ -828,11 +811,9 @@ static struct platform_device orion_ehci = {
828 }, 811 },
829}; 812};
830 813
831void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, 814void __init orion_ehci_init(unsigned long mapbase,
832 unsigned long mapbase,
833 unsigned long irq) 815 unsigned long irq)
834{ 816{
835 orion_ehci_data.dram = mbus_dram_info;
836 fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, 817 fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
837 irq); 818 irq);
838 819
@@ -854,11 +835,9 @@ static struct platform_device orion_ehci_1 = {
854 }, 835 },
855}; 836};
856 837
857void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, 838void __init orion_ehci_1_init(unsigned long mapbase,
858 unsigned long mapbase,
859 unsigned long irq) 839 unsigned long irq)
860{ 840{
861 orion_ehci_data.dram = mbus_dram_info;
862 fill_resources(&orion_ehci_1, orion_ehci_1_resources, 841 fill_resources(&orion_ehci_1, orion_ehci_1_resources,
863 mapbase, SZ_4K - 1, irq); 842 mapbase, SZ_4K - 1, irq);
864 843
@@ -880,11 +859,9 @@ static struct platform_device orion_ehci_2 = {
880 }, 859 },
881}; 860};
882 861
883void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, 862void __init orion_ehci_2_init(unsigned long mapbase,
884 unsigned long mapbase,
885 unsigned long irq) 863 unsigned long irq)
886{ 864{
887 orion_ehci_data.dram = mbus_dram_info;
888 fill_resources(&orion_ehci_2, orion_ehci_2_resources, 865 fill_resources(&orion_ehci_2, orion_ehci_2_resources,
889 mapbase, SZ_4K - 1, irq); 866 mapbase, SZ_4K - 1, irq);
890 867
@@ -911,11 +888,9 @@ static struct platform_device orion_sata = {
911}; 888};
912 889
913void __init orion_sata_init(struct mv_sata_platform_data *sata_data, 890void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
914 struct mbus_dram_target_info *mbus_dram_info,
915 unsigned long mapbase, 891 unsigned long mapbase,
916 unsigned long irq) 892 unsigned long irq)
917{ 893{
918 sata_data->dram = mbus_dram_info;
919 orion_sata.dev.platform_data = sata_data; 894 orion_sata.dev.platform_data = sata_data;
920 fill_resources(&orion_sata, orion_sata_resources, 895 fill_resources(&orion_sata, orion_sata_resources,
921 mapbase, 0x5000 - 1, irq); 896 mapbase, 0x5000 - 1, irq);
diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
new file mode 100644
index 000000000000..fd556f77562c
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -0,0 +1,53 @@
1/*
2 * arch/arm/plat-orion/include/plat/addr-map.h
3 *
4 * Marvell Orion SoC address map handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __PLAT_ADDR_MAP_H
12#define __PLAT_ADDR_MAP_H
13
14extern struct mbus_dram_target_info orion_mbus_dram_info;
15
16struct orion_addr_map_cfg {
17 const int num_wins; /* Total number of windows */
18 const int remappable_wins;
19 const u32 bridge_virt_base;
20
21 /* If NULL, the default cpu_win_can_remap will be used, using
22 the value in remappable_wins */
23 int (*cpu_win_can_remap) (const struct orion_addr_map_cfg *cfg,
24 const int win);
25 /* If NULL, the default win_cfg_base will be used, using the
26 value in bridge_virt_base */
27 void __iomem *(*win_cfg_base) (const struct orion_addr_map_cfg *cfg,
28 const int win);
29};
30
31/*
32 * Information needed to setup one address mapping.
33 */
34struct orion_addr_map_info {
35 const int win;
36 const u32 base;
37 const u32 size;
38 const u8 target;
39 const u8 attr;
40 const int remap;
41};
42
43void __init orion_config_wins(struct orion_addr_map_cfg *cfg,
44 const struct orion_addr_map_info *info);
45
46void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
47 const int win, const u32 base,
48 const u32 size, const u8 target,
49 const u8 attr, const int remap);
50
51void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
52 const u32 ddr_window_cpu_base);
53#endif
diff --git a/arch/arm/plat-orion/include/plat/audio.h b/arch/arm/plat-orion/include/plat/audio.h
index 9cf1f781329b..885f8abd927b 100644
--- a/arch/arm/plat-orion/include/plat/audio.h
+++ b/arch/arm/plat-orion/include/plat/audio.h
@@ -1,11 +1,8 @@
1#ifndef __PLAT_AUDIO_H 1#ifndef __PLAT_AUDIO_H
2#define __PLAT_AUDIO_H 2#define __PLAT_AUDIO_H
3 3
4#include <linux/mbus.h>
5
6struct kirkwood_asoc_platform_data { 4struct kirkwood_asoc_platform_data {
7 u32 tclk; 5 u32 tclk;
8 struct mbus_dram_target_info *dram;
9 int burst; 6 int burst;
10}; 7};
11#endif 8#endif
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index a63c357e2ab1..0fe08d77e835 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -37,28 +37,24 @@ void __init orion_rtc_init(unsigned long mapbase,
37 unsigned long irq); 37 unsigned long irq);
38 38
39void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, 39void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
40 struct mbus_dram_target_info *mbus_dram_info,
41 unsigned long mapbase, 40 unsigned long mapbase,
42 unsigned long irq, 41 unsigned long irq,
43 unsigned long irq_err, 42 unsigned long irq_err,
44 int tclk); 43 int tclk);
45 44
46void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, 45void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
47 struct mbus_dram_target_info *mbus_dram_info,
48 unsigned long mapbase, 46 unsigned long mapbase,
49 unsigned long irq, 47 unsigned long irq,
50 unsigned long irq_err, 48 unsigned long irq_err,
51 int tclk); 49 int tclk);
52 50
53void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, 51void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
54 struct mbus_dram_target_info *mbus_dram_info,
55 unsigned long mapbase, 52 unsigned long mapbase,
56 unsigned long irq, 53 unsigned long irq,
57 unsigned long irq_err, 54 unsigned long irq_err,
58 int tclk); 55 int tclk);
59 56
60void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, 57void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
61 struct mbus_dram_target_info *mbus_dram_info,
62 unsigned long mapbase, 58 unsigned long mapbase,
63 unsigned long irq, 59 unsigned long irq,
64 unsigned long irq_err, 60 unsigned long irq_err,
@@ -82,8 +78,7 @@ void __init orion_spi_1_init(unsigned long mapbase,
82 78
83void __init orion_wdt_init(unsigned long tclk); 79void __init orion_wdt_init(unsigned long tclk);
84 80
85void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info, 81void __init orion_xor0_init(unsigned long mapbase_low,
86 unsigned long mapbase_low,
87 unsigned long mapbase_high, 82 unsigned long mapbase_high,
88 unsigned long irq_0, 83 unsigned long irq_0,
89 unsigned long irq_1); 84 unsigned long irq_1);
@@ -93,20 +88,16 @@ void __init orion_xor1_init(unsigned long mapbase_low,
93 unsigned long irq_0, 88 unsigned long irq_0,
94 unsigned long irq_1); 89 unsigned long irq_1);
95 90
96void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info, 91void __init orion_ehci_init(unsigned long mapbase,
97 unsigned long mapbase,
98 unsigned long irq); 92 unsigned long irq);
99 93
100void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info, 94void __init orion_ehci_1_init(unsigned long mapbase,
101 unsigned long mapbase,
102 unsigned long irq); 95 unsigned long irq);
103 96
104void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info, 97void __init orion_ehci_2_init(unsigned long mapbase,
105 unsigned long mapbase,
106 unsigned long irq); 98 unsigned long irq);
107 99
108void __init orion_sata_init(struct mv_sata_platform_data *sata_data, 100void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
109 struct mbus_dram_target_info *mbus_dram_info,
110 unsigned long mapbase, 101 unsigned long mapbase,
111 unsigned long irq); 102 unsigned long irq);
112 103
diff --git a/arch/arm/plat-orion/include/plat/ehci-orion.h b/arch/arm/plat-orion/include/plat/ehci-orion.h
index 4ec668e77460..6fc78e430420 100644
--- a/arch/arm/plat-orion/include/plat/ehci-orion.h
+++ b/arch/arm/plat-orion/include/plat/ehci-orion.h
@@ -19,7 +19,6 @@ enum orion_ehci_phy_ver {
19}; 19};
20 20
21struct orion_ehci_data { 21struct orion_ehci_data {
22 struct mbus_dram_target_info *dram;
23 enum orion_ehci_phy_ver phy_version; 22 enum orion_ehci_phy_ver phy_version;
24}; 23};
25 24
diff --git a/arch/arm/plat-orion/include/plat/mv_xor.h b/arch/arm/plat-orion/include/plat/mv_xor.h
index bd5f3bdb4ae3..2ba1f7d76eef 100644
--- a/arch/arm/plat-orion/include/plat/mv_xor.h
+++ b/arch/arm/plat-orion/include/plat/mv_xor.h
@@ -13,12 +13,6 @@
13#define MV_XOR_SHARED_NAME "mv_xor_shared" 13#define MV_XOR_SHARED_NAME "mv_xor_shared"
14#define MV_XOR_NAME "mv_xor" 14#define MV_XOR_NAME "mv_xor"
15 15
16struct mbus_dram_target_info;
17
18struct mv_xor_platform_shared_data {
19 struct mbus_dram_target_info *dram;
20};
21
22struct mv_xor_platform_data { 16struct mv_xor_platform_data {
23 struct platform_device *shared; 17 struct platform_device *shared;
24 int hw_id; 18 int hw_id;
diff --git a/arch/arm/plat-orion/include/plat/mvsdio.h b/arch/arm/plat-orion/include/plat/mvsdio.h
index 14ca88676002..1190efedcb94 100644
--- a/arch/arm/plat-orion/include/plat/mvsdio.h
+++ b/arch/arm/plat-orion/include/plat/mvsdio.h
@@ -12,7 +12,6 @@
12#include <linux/mbus.h> 12#include <linux/mbus.h>
13 13
14struct mvsdio_platform_data { 14struct mvsdio_platform_data {
15 struct mbus_dram_target_info *dram;
16 unsigned int clock; 15 unsigned int clock;
17 int gpio_card_detect; 16 int gpio_card_detect;
18 int gpio_write_protect; 17 int gpio_write_protect;
diff --git a/arch/arm/plat-orion/include/plat/pcie.h b/arch/arm/plat-orion/include/plat/pcie.h
index cc99163e73fd..fe5b9e862747 100644
--- a/arch/arm/plat-orion/include/plat/pcie.h
+++ b/arch/arm/plat-orion/include/plat/pcie.h
@@ -20,8 +20,7 @@ int orion_pcie_x4_mode(void __iomem *base);
20int orion_pcie_get_local_bus_nr(void __iomem *base); 20int orion_pcie_get_local_bus_nr(void __iomem *base);
21void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); 21void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
22void orion_pcie_reset(void __iomem *base); 22void orion_pcie_reset(void __iomem *base);
23void orion_pcie_setup(void __iomem *base, 23void orion_pcie_setup(void __iomem *base);
24 struct mbus_dram_target_info *dram);
25int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, 24int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
26 u32 devfn, int where, int size, u32 *val); 25 u32 devfn, int where, int size, u32 *val);
27int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, 26int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index af2d733c50b5..86dbb5bdb172 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -13,6 +13,7 @@
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <asm/mach/pci.h> 14#include <asm/mach/pci.h>
15#include <plat/pcie.h> 15#include <plat/pcie.h>
16#include <plat/addr-map.h>
16#include <linux/delay.h> 17#include <linux/delay.h>
17 18
18/* 19/*
@@ -175,8 +176,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base,
175 writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); 176 writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1));
176} 177}
177 178
178void __init orion_pcie_setup(void __iomem *base, 179void __init orion_pcie_setup(void __iomem *base)
179 struct mbus_dram_target_info *dram)
180{ 180{
181 u16 cmd; 181 u16 cmd;
182 u32 mask; 182 u32 mask;
@@ -184,7 +184,7 @@ void __init orion_pcie_setup(void __iomem *base,
184 /* 184 /*
185 * Point PCIe unit MBUS decode windows to DRAM space. 185 * Point PCIe unit MBUS decode windows to DRAM space.
186 */ 186 */
187 orion_pcie_setup_wins(base, dram); 187 orion_pcie_setup_wins(base, &orion_mbus_dram_info);
188 188
189 /* 189 /*
190 * Master + slave enable. 190 * Master + slave enable.
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 21:22:22 -0400