diff options
author | Will Deacon <will.deacon@arm.com> | 2013-02-18 17:07:47 -0500 |
---|---|---|
committer | Will Deacon <will.deacon@arm.com> | 2013-08-12 07:25:44 -0400 |
commit | 2c813980c6113ac2c407fbed99f53242088c3038 (patch) | |
tree | bc68fc216c14179d10b2ddc5a86129550e4c9531 /arch/arm | |
parent | 587b9b6487acddf777301c867c24f31fdf4ada4a (diff) |
ARM: tlb: don't perform inner-shareable invalidation for local BP ops
Now that the ASID allocator doesn't require inner-shareable maintenance,
we can convert the local_bp_flush_all function to perform only
non-shareable flushing, in a similar manner to the TLB invalidation
routines.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/include/asm/tlbflush.h | 22 | ||||
-rw-r--r-- | arch/arm/kernel/smp_tlb.c | 2 |
2 files changed, 21 insertions, 3 deletions
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 9b725d2bcb6b..84718240340c 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h | |||
@@ -531,17 +531,35 @@ static inline void __flush_tlb_kernel_page(unsigned long kaddr) | |||
531 | * Branch predictor maintenance is paired with full TLB invalidation, so | 531 | * Branch predictor maintenance is paired with full TLB invalidation, so |
532 | * there is no need for any barriers here. | 532 | * there is no need for any barriers here. |
533 | */ | 533 | */ |
534 | static inline void __local_flush_bp_all(void) | ||
535 | { | ||
536 | const int zero = 0; | ||
537 | const unsigned int __tlb_flag = __cpu_tlb_flags; | ||
538 | |||
539 | if (tlb_flag(TLB_V6_BP)) | ||
540 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); | ||
541 | } | ||
542 | |||
534 | static inline void local_flush_bp_all(void) | 543 | static inline void local_flush_bp_all(void) |
535 | { | 544 | { |
536 | const int zero = 0; | 545 | const int zero = 0; |
537 | const unsigned int __tlb_flag = __cpu_tlb_flags; | 546 | const unsigned int __tlb_flag = __cpu_tlb_flags; |
538 | 547 | ||
548 | __local_flush_bp_all(); | ||
539 | if (tlb_flag(TLB_V7_UIS_BP)) | 549 | if (tlb_flag(TLB_V7_UIS_BP)) |
540 | asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero)); | ||
541 | else if (tlb_flag(TLB_V6_BP)) | ||
542 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); | 550 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); |
543 | } | 551 | } |
544 | 552 | ||
553 | static inline void __flush_bp_all(void) | ||
554 | { | ||
555 | const int zero = 0; | ||
556 | const unsigned int __tlb_flag = __cpu_tlb_flags; | ||
557 | |||
558 | __local_flush_bp_all(); | ||
559 | if (tlb_flag(TLB_V7_UIS_BP)) | ||
560 | asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero)); | ||
561 | } | ||
562 | |||
545 | #include <asm/cputype.h> | 563 | #include <asm/cputype.h> |
546 | #ifdef CONFIG_ARM_ERRATA_798181 | 564 | #ifdef CONFIG_ARM_ERRATA_798181 |
547 | static inline int erratum_a15_798181(void) | 565 | static inline int erratum_a15_798181(void) |
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c index 5883b8ae77c8..83ccca303df8 100644 --- a/arch/arm/kernel/smp_tlb.c +++ b/arch/arm/kernel/smp_tlb.c | |||
@@ -173,5 +173,5 @@ void flush_bp_all(void) | |||
173 | if (tlb_ops_need_broadcast()) | 173 | if (tlb_ops_need_broadcast()) |
174 | on_each_cpu(ipi_flush_bp_all, NULL, 1); | 174 | on_each_cpu(ipi_flush_bp_all, NULL, 1); |
175 | else | 175 | else |
176 | local_flush_bp_all(); | 176 | __flush_bp_all(); |
177 | } | 177 | } |