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authorArnd Bergmann <arnd@arndb.de>2011-10-20 09:30:55 -0400
committerArnd Bergmann <arnd@arndb.de>2011-10-20 09:30:55 -0400
commit29ea35969b92a4be122a58c4aceea8c5e2c388d9 (patch)
tree8285c0e98e7bb03868d390b58180e3cab876a8db /arch/arm
parent112d17d6f75b93e1dcaec2e2232a411148b3bf71 (diff)
parentb4cbb8a4e602ea77b0525d06eff89c6a6070dab3 (diff)
Merge branch 'imx/devel' into next/devel
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig14
-rw-r--r--arch/arm/boot/dts/tegra-harmony.dts12
-rw-r--r--arch/arm/boot/dts/tegra-seaboard.dts6
-rw-r--r--arch/arm/configs/mxs_defconfig1
-rw-r--r--arch/arm/include/asm/futex.h34
-rw-r--r--arch/arm/include/asm/unistd.h4
-rw-r--r--arch/arm/kernel/smp_scu.c10
-rw-r--r--arch/arm/kernel/vmlinux.lds.S15
-rw-r--r--arch/arm/mach-dove/common.c2
-rw-r--r--arch/arm/mach-exynos4/clock.c8
-rw-r--r--arch/arm/mach-exynos4/mct.c10
-rw-r--r--arch/arm/mach-exynos4/platsmp.c2
-rw-r--r--arch/arm/mach-exynos4/setup-keypad.c11
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c2
-rw-r--r--arch/arm/mach-integrator/pci_v3.c2
-rw-r--r--arch/arm/mach-mx5/board-mx53_ard.c1
-rw-r--r--arch/arm/mach-mx5/board-mx53_loco.c1
-rw-r--r--arch/arm/mach-mx5/board-mx53_smd.c16
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c19
-rw-r--r--arch/arm/mach-mx5/devices-imx53.h2
-rw-r--r--arch/arm/mach-mxs/Kconfig17
-rw-r--r--arch/arm/mach-mxs/Makefile1
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c16
-rw-r--r--arch/arm/mach-mxs/include/mach/mxs.h1
-rw-r--r--arch/arm/mach-mxs/include/mach/uncompress.h1
-rw-r--r--arch/arm/mach-mxs/mach-m28evk.c366
-rw-r--r--arch/arm/mach-s3c2443/clock.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6410.c39
-rw-r--r--arch/arm/mach-s5pv210/clock.c6
-rw-r--r--arch/arm/mm/cache-v7.S20
-rw-r--r--arch/arm/mm/dma-mapping.c2
-rw-r--r--arch/arm/plat-mxc/devices/Kconfig4
-rw-r--r--arch/arm/plat-mxc/devices/Makefile1
-rw-r--r--arch/arm/plat-mxc/devices/platform-ahci-imx.c156
-rw-r--r--arch/arm/plat-mxc/include/mach/devices-common.h10
-rw-r--r--arch/arm/plat-s5p/irq-gpioint.c9
-rw-r--r--arch/arm/plat-samsung/clock.c11
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h8
-rw-r--r--arch/arm/plat-samsung/include/plat/watchdog-reset.h10
39 files changed, 747 insertions, 105 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3c47745c7f7b..3bf38c84fd23 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1284,6 +1284,20 @@ config ARM_ERRATA_364296
1284 processor into full low interrupt latency mode. ARM11MPCore 1284 processor into full low interrupt latency mode. ARM11MPCore
1285 is not affected. 1285 is not affected.
1286 1286
1287config ARM_ERRATA_764369
1288 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1289 depends on CPU_V7 && SMP
1290 help
1291 This option enables the workaround for erratum 764369
1292 affecting Cortex-A9 MPCore with two or more processors (all
1293 current revisions). Under certain timing circumstances, a data
1294 cache line maintenance operation by MVA targeting an Inner
1295 Shareable memory region may fail to proceed up to either the
1296 Point of Coherency or to the Point of Unification of the
1297 system. This workaround adds a DSB instruction before the
1298 relevant cache maintenance functions and sets a specific bit
1299 in the diagnostic control register of the SCU.
1300
1287endmenu 1301endmenu
1288 1302
1289source "arch/arm/common/Kconfig" 1303source "arch/arm/common/Kconfig"
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 4c053340ce33..e5818668d091 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -57,14 +57,14 @@
57 }; 57 };
58 58
59 sdhci@c8000200 { 59 sdhci@c8000200 {
60 gpios = <&gpio 69 0>, /* cd, gpio PI5 */ 60 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
61 <&gpio 57 0>, /* wp, gpio PH1 */ 61 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
62 <&gpio 155 0>; /* power, gpio PT3 */ 62 power-gpios = <&gpio 155 0>; /* gpio PT3 */
63 }; 63 };
64 64
65 sdhci@c8000600 { 65 sdhci@c8000600 {
66 gpios = <&gpio 58 0>, /* cd, gpio PH2 */ 66 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
67 <&gpio 59 0>, /* wp, gpio PH3 */ 67 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
68 <&gpio 70 0>; /* power, gpio PI6 */ 68 power-gpios = <&gpio 70 0>; /* gpio PI6 */
69 }; 69 };
70}; 70};
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index 1940cae00748..64cedca6fc79 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -21,8 +21,8 @@
21 }; 21 };
22 22
23 sdhci@c8000400 { 23 sdhci@c8000400 {
24 gpios = <&gpio 69 0>, /* cd, gpio PI5 */ 24 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
25 <&gpio 57 0>, /* wp, gpio PH1 */ 25 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
26 <&gpio 70 0>; /* power, gpio PI6 */ 26 power-gpios = <&gpio 70 0>; /* gpio PI6 */
27 }; 27 };
28}; 28};
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index db2cb7d180dc..6ee781bf6bf1 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -26,6 +26,7 @@ CONFIG_MACH_MX23EVK=y
26CONFIG_MACH_MX28EVK=y 26CONFIG_MACH_MX28EVK=y
27CONFIG_MACH_STMP378X_DEVB=y 27CONFIG_MACH_STMP378X_DEVB=y
28CONFIG_MACH_TX28=y 28CONFIG_MACH_TX28=y
29CONFIG_MACH_M28EVK=y
29# CONFIG_ARM_THUMB is not set 30# CONFIG_ARM_THUMB is not set
30CONFIG_NO_HZ=y 31CONFIG_NO_HZ=y
31CONFIG_HIGH_RES_TIMERS=y 32CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 8c73900da9ed..253cc86318bf 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -25,17 +25,17 @@
25 25
26#ifdef CONFIG_SMP 26#ifdef CONFIG_SMP
27 27
28#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 28#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
29 smp_mb(); \ 29 smp_mb(); \
30 __asm__ __volatile__( \ 30 __asm__ __volatile__( \
31 "1: ldrex %1, [%2]\n" \ 31 "1: ldrex %1, [%3]\n" \
32 " " insn "\n" \ 32 " " insn "\n" \
33 "2: strex %1, %0, [%2]\n" \ 33 "2: strex %2, %0, [%3]\n" \
34 " teq %1, #0\n" \ 34 " teq %2, #0\n" \
35 " bne 1b\n" \ 35 " bne 1b\n" \
36 " mov %0, #0\n" \ 36 " mov %0, #0\n" \
37 __futex_atomic_ex_table("%4") \ 37 __futex_atomic_ex_table("%5") \
38 : "=&r" (ret), "=&r" (oldval) \ 38 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
39 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ 39 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
40 : "cc", "memory") 40 : "cc", "memory")
41 41
@@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
73#include <linux/preempt.h> 73#include <linux/preempt.h>
74#include <asm/domain.h> 74#include <asm/domain.h>
75 75
76#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 76#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
77 __asm__ __volatile__( \ 77 __asm__ __volatile__( \
78 "1: " T(ldr) " %1, [%2]\n" \ 78 "1: " T(ldr) " %1, [%3]\n" \
79 " " insn "\n" \ 79 " " insn "\n" \
80 "2: " T(str) " %0, [%2]\n" \ 80 "2: " T(str) " %0, [%3]\n" \
81 " mov %0, #0\n" \ 81 " mov %0, #0\n" \
82 __futex_atomic_ex_table("%4") \ 82 __futex_atomic_ex_table("%5") \
83 : "=&r" (ret), "=&r" (oldval) \ 83 : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
84 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ 84 : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
85 : "cc", "memory") 85 : "cc", "memory")
86 86
@@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
117 int cmp = (encoded_op >> 24) & 15; 117 int cmp = (encoded_op >> 24) & 15;
118 int oparg = (encoded_op << 8) >> 20; 118 int oparg = (encoded_op << 8) >> 20;
119 int cmparg = (encoded_op << 20) >> 20; 119 int cmparg = (encoded_op << 20) >> 20;
120 int oldval = 0, ret; 120 int oldval = 0, ret, tmp;
121 121
122 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) 122 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
123 oparg = 1 << oparg; 123 oparg = 1 << oparg;
@@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
129 129
130 switch (op) { 130 switch (op) {
131 case FUTEX_OP_SET: 131 case FUTEX_OP_SET:
132 __futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg); 132 __futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
133 break; 133 break;
134 case FUTEX_OP_ADD: 134 case FUTEX_OP_ADD:
135 __futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg); 135 __futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
136 break; 136 break;
137 case FUTEX_OP_OR: 137 case FUTEX_OP_OR:
138 __futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg); 138 __futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
139 break; 139 break;
140 case FUTEX_OP_ANDN: 140 case FUTEX_OP_ANDN:
141 __futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg); 141 __futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
142 break; 142 break;
143 case FUTEX_OP_XOR: 143 case FUTEX_OP_XOR:
144 __futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg); 144 __futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
145 break; 145 break;
146 default: 146 default:
147 ret = -ENOSYS; 147 ret = -ENOSYS;
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 2c04ed5efeb5..c60a2944f95b 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -478,8 +478,8 @@
478/* 478/*
479 * Unimplemented (or alternatively implemented) syscalls 479 * Unimplemented (or alternatively implemented) syscalls
480 */ 480 */
481#define __IGNORE_fadvise64_64 1 481#define __IGNORE_fadvise64_64
482#define __IGNORE_migrate_pages 1 482#define __IGNORE_migrate_pages
483 483
484#endif /* __KERNEL__ */ 484#endif /* __KERNEL__ */
485#endif /* __ASM_ARM_UNISTD_H */ 485#endif /* __ASM_ARM_UNISTD_H */
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 79ed5e7f204a..7fcddb75c877 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -13,6 +13,7 @@
13 13
14#include <asm/smp_scu.h> 14#include <asm/smp_scu.h>
15#include <asm/cacheflush.h> 15#include <asm/cacheflush.h>
16#include <asm/cputype.h>
16 17
17#define SCU_CTRL 0x00 18#define SCU_CTRL 0x00
18#define SCU_CONFIG 0x04 19#define SCU_CONFIG 0x04
@@ -37,6 +38,15 @@ void __init scu_enable(void __iomem *scu_base)
37{ 38{
38 u32 scu_ctrl; 39 u32 scu_ctrl;
39 40
41#ifdef CONFIG_ARM_ERRATA_764369
42 /* Cortex-A9 only */
43 if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
44 scu_ctrl = __raw_readl(scu_base + 0x30);
45 if (!(scu_ctrl & 1))
46 __raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
47 }
48#endif
49
40 scu_ctrl = __raw_readl(scu_base + SCU_CTRL); 50 scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
41 /* already enabled? */ 51 /* already enabled? */
42 if (scu_ctrl & 1) 52 if (scu_ctrl & 1)
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index bf977f8514f6..4e66f62b8d41 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -23,8 +23,10 @@
23 23
24#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK) 24#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
25#define ARM_EXIT_KEEP(x) x 25#define ARM_EXIT_KEEP(x) x
26#define ARM_EXIT_DISCARD(x)
26#else 27#else
27#define ARM_EXIT_KEEP(x) 28#define ARM_EXIT_KEEP(x)
29#define ARM_EXIT_DISCARD(x) x
28#endif 30#endif
29 31
30OUTPUT_ARCH(arm) 32OUTPUT_ARCH(arm)
@@ -39,6 +41,11 @@ jiffies = jiffies_64 + 4;
39SECTIONS 41SECTIONS
40{ 42{
41 /* 43 /*
44 * XXX: The linker does not define how output sections are
45 * assigned to input sections when there are multiple statements
46 * matching the same input section name. There is no documented
47 * order of matching.
48 *
42 * unwind exit sections must be discarded before the rest of the 49 * unwind exit sections must be discarded before the rest of the
43 * unwind sections get included. 50 * unwind sections get included.
44 */ 51 */
@@ -47,6 +54,9 @@ SECTIONS
47 *(.ARM.extab.exit.text) 54 *(.ARM.extab.exit.text)
48 ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text)) 55 ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
49 ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text)) 56 ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
57 ARM_EXIT_DISCARD(EXIT_TEXT)
58 ARM_EXIT_DISCARD(EXIT_DATA)
59 EXIT_CALL
50#ifndef CONFIG_HOTPLUG 60#ifndef CONFIG_HOTPLUG
51 *(.ARM.exidx.devexit.text) 61 *(.ARM.exidx.devexit.text)
52 *(.ARM.extab.devexit.text) 62 *(.ARM.extab.devexit.text)
@@ -58,6 +68,8 @@ SECTIONS
58#ifndef CONFIG_SMP_ON_UP 68#ifndef CONFIG_SMP_ON_UP
59 *(.alt.smp.init) 69 *(.alt.smp.init)
60#endif 70#endif
71 *(.discard)
72 *(.discard.*)
61 } 73 }
62 74
63#ifdef CONFIG_XIP_KERNEL 75#ifdef CONFIG_XIP_KERNEL
@@ -279,9 +291,6 @@ SECTIONS
279 291
280 STABS_DEBUG 292 STABS_DEBUG
281 .comment 0 : { *(.comment) } 293 .comment 0 : { *(.comment) }
282
283 /* Default discards */
284 DISCARDS
285} 294}
286 295
287/* 296/*
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 83dce859886d..a9e0dae86a26 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -158,7 +158,7 @@ void __init dove_spi0_init(void)
158 158
159void __init dove_spi1_init(void) 159void __init dove_spi1_init(void)
160{ 160{
161 orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk()); 161 orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk());
162} 162}
163 163
164/***************************************************************************** 164/*****************************************************************************
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 1561b036a9bf..86964d2e9e1b 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -899,8 +899,7 @@ static struct clksrc_clk clksrcs[] = {
899 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 }, 899 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
900 }, { 900 }, {
901 .clk = { 901 .clk = {
902 .name = "sclk_cam", 902 .name = "sclk_cam0",
903 .devname = "exynos4-fimc.0",
904 .enable = exynos4_clksrc_mask_cam_ctrl, 903 .enable = exynos4_clksrc_mask_cam_ctrl,
905 .ctrlbit = (1 << 16), 904 .ctrlbit = (1 << 16),
906 }, 905 },
@@ -909,8 +908,7 @@ static struct clksrc_clk clksrcs[] = {
909 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 }, 908 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
910 }, { 909 }, {
911 .clk = { 910 .clk = {
912 .name = "sclk_cam", 911 .name = "sclk_cam1",
913 .devname = "exynos4-fimc.1",
914 .enable = exynos4_clksrc_mask_cam_ctrl, 912 .enable = exynos4_clksrc_mask_cam_ctrl,
915 .ctrlbit = (1 << 20), 913 .ctrlbit = (1 << 20),
916 }, 914 },
@@ -1160,7 +1158,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
1160 1158
1161 vpllsrc = clk_get_rate(&clk_vpllsrc.clk); 1159 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1162 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), 1160 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1163 __raw_readl(S5P_VPLL_CON1), pll_4650); 1161 __raw_readl(S5P_VPLL_CON1), pll_4650c);
1164 1162
1165 clk_fout_apll.ops = &exynos4_fout_apll_ops; 1163 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1166 clk_fout_mpll.rate = mpll; 1164 clk_fout_mpll.rate = mpll;
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index 1ae059b7ad7b..ddd86864fb83 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -132,12 +132,18 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
132 return ((cycle_t)hi << 32) | lo; 132 return ((cycle_t)hi << 32) | lo;
133} 133}
134 134
135static void exynos4_frc_resume(struct clocksource *cs)
136{
137 exynos4_mct_frc_start(0, 0);
138}
139
135struct clocksource mct_frc = { 140struct clocksource mct_frc = {
136 .name = "mct-frc", 141 .name = "mct-frc",
137 .rating = 400, 142 .rating = 400,
138 .read = exynos4_frc_read, 143 .read = exynos4_frc_read,
139 .mask = CLOCKSOURCE_MASK(64), 144 .mask = CLOCKSOURCE_MASK(64),
140 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 145 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
146 .resume = exynos4_frc_resume,
141}; 147};
142 148
143static void __init exynos4_clocksource_init(void) 149static void __init exynos4_clocksource_init(void)
@@ -389,9 +395,11 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
389} 395}
390 396
391/* Setup the local clock events for a CPU */ 397/* Setup the local clock events for a CPU */
392void __cpuinit local_timer_setup(struct clock_event_device *evt) 398int __cpuinit local_timer_setup(struct clock_event_device *evt)
393{ 399{
394 exynos4_mct_tick_init(evt); 400 exynos4_mct_tick_init(evt);
401
402 return 0;
395} 403}
396 404
397int local_timer_ack(void) 405int local_timer_ack(void)
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index 7c2282c6ba81..df6ef1b2f98b 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -106,6 +106,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
106 */ 106 */
107 spin_lock(&boot_lock); 107 spin_lock(&boot_lock);
108 spin_unlock(&boot_lock); 108 spin_unlock(&boot_lock);
109
110 set_cpu_online(cpu, true);
109} 111}
110 112
111int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) 113int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
diff --git a/arch/arm/mach-exynos4/setup-keypad.c b/arch/arm/mach-exynos4/setup-keypad.c
index 1ee0ebff111f..7862bfb5933d 100644
--- a/arch/arm/mach-exynos4/setup-keypad.c
+++ b/arch/arm/mach-exynos4/setup-keypad.c
@@ -19,15 +19,16 @@ void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
19 19
20 if (rows > 8) { 20 if (rows > 8) {
21 /* Set all the necessary GPX2 pins: KP_ROW[0~7] */ 21 /* Set all the necessary GPX2 pins: KP_ROW[0~7] */
22 s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3)); 22 s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3),
23 S3C_GPIO_PULL_UP);
23 24
24 /* Set all the necessary GPX3 pins: KP_ROW[8~] */ 25 /* Set all the necessary GPX3 pins: KP_ROW[8~] */
25 s3c_gpio_cfgrange_nopull(EXYNOS4_GPX3(0), (rows - 8), 26 s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
26 S3C_GPIO_SFN(3)); 27 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
27 } else { 28 } else {
28 /* Set all the necessary GPX2 pins: KP_ROW[x] */ 29 /* Set all the necessary GPX2 pins: KP_ROW[x] */
29 s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), rows, 30 s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3),
30 S3C_GPIO_SFN(3)); 31 S3C_GPIO_PULL_UP);
31 } 32 }
32 33
33 /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */ 34 /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index fcf0ae95651f..8cdc730dcb3a 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -32,6 +32,7 @@
32#include <linux/interrupt.h> 32#include <linux/interrupt.h>
33#include <linux/io.h> 33#include <linux/io.h>
34#include <linux/mtd/physmap.h> 34#include <linux/mtd/physmap.h>
35#include <video/vga.h>
35 36
36#include <mach/hardware.h> 37#include <mach/hardware.h>
37#include <mach/platform.h> 38#include <mach/platform.h>
@@ -154,6 +155,7 @@ static struct map_desc ap_io_desc[] __initdata = {
154static void __init ap_map_io(void) 155static void __init ap_map_io(void)
155{ 156{
156 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); 157 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
158 vga_base = PCI_MEMORY_VADDR;
157} 159}
158 160
159#define INTEGRATOR_SC_VALID_INT 0x003fffff 161#define INTEGRATOR_SC_VALID_INT 0x003fffff
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index dd56bfb351e3..11b86e5b71c2 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -27,7 +27,6 @@
27#include <linux/spinlock.h> 27#include <linux/spinlock.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/io.h> 29#include <linux/io.h>
30#include <video/vga.h>
31 30
32#include <mach/hardware.h> 31#include <mach/hardware.h>
33#include <mach/platform.h> 32#include <mach/platform.h>
@@ -505,7 +504,6 @@ void __init pci_v3_preinit(void)
505 504
506 pcibios_min_io = 0x6000; 505 pcibios_min_io = 0x6000;
507 pcibios_min_mem = 0x00100000; 506 pcibios_min_mem = 0x00100000;
508 vga_base = PCI_MEMORY_VADDR;
509 507
510 /* 508 /*
511 * Hook in our fault handler for PCI errors 509 * Hook in our fault handler for PCI errors
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c
index cb4d753c6c95..614edcb0aa7e 100644
--- a/arch/arm/mach-mx5/board-mx53_ard.c
+++ b/arch/arm/mach-mx5/board-mx53_ard.c
@@ -234,6 +234,7 @@ static void __init mx53_ard_board_init(void)
234 imx53_add_imx_i2c(1, &mx53_ard_i2c2_data); 234 imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
235 imx53_add_imx_i2c(2, &mx53_ard_i2c3_data); 235 imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
236 imx_add_gpio_keys(&ard_button_data); 236 imx_add_gpio_keys(&ard_button_data);
237 imx53_add_ahci_imx();
237} 238}
238 239
239static void __init mx53_ard_timer_init(void) 240static void __init mx53_ard_timer_init(void)
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 7149416d1519..0af2766f8610 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -293,6 +293,7 @@ static void __init mx53_loco_board_init(void)
293 imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data); 293 imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
294 imx_add_gpio_keys(&loco_button_data); 294 imx_add_gpio_keys(&loco_button_data);
295 gpio_led_register_device(-1, &mx53loco_leds_data); 295 gpio_led_register_device(-1, &mx53loco_leds_data);
296 imx53_add_ahci_imx();
296} 297}
297 298
298static void __init mx53_loco_timer_init(void) 299static void __init mx53_loco_timer_init(void)
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
index e64fd2c088eb..d12fd3043ba6 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -35,6 +35,7 @@
35#include "devices-imx53.h" 35#include "devices-imx53.h"
36 36
37#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) 37#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
38#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3)
38 39
39static iomux_v3_cfg_t mx53_smd_pads[] = { 40static iomux_v3_cfg_t mx53_smd_pads[] = {
40 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, 41 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
@@ -111,6 +112,19 @@ static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
111 .bitrate = 100000, 112 .bitrate = 100000,
112}; 113};
113 114
115static inline void mx53_smd_ahci_pwr_on(void)
116{
117 int ret;
118
119 /* Enable SATA PWR */
120 ret = gpio_request_one(MX53_SMD_SATA_PWR_EN,
121 GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr");
122 if (ret) {
123 pr_err("failed to enable SATA_PWR_EN: %d\n", ret);
124 return;
125 }
126}
127
114static void __init mx53_smd_board_init(void) 128static void __init mx53_smd_board_init(void)
115{ 129{
116 imx53_soc_init(); 130 imx53_soc_init();
@@ -125,6 +139,8 @@ static void __init mx53_smd_board_init(void)
125 imx53_add_sdhci_esdhc_imx(0, NULL); 139 imx53_add_sdhci_esdhc_imx(0, NULL);
126 imx53_add_sdhci_esdhc_imx(1, NULL); 140 imx53_add_sdhci_esdhc_imx(1, NULL);
127 imx53_add_sdhci_esdhc_imx(2, NULL); 141 imx53_add_sdhci_esdhc_imx(2, NULL);
142 mx53_smd_ahci_pwr_on();
143 imx53_add_ahci_imx();
128} 144}
129 145
130static void __init mx53_smd_timer_init(void) 146static void __init mx53_smd_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 2b9bd1fabaf9..b94879e8679f 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1401,6 +1401,22 @@ static struct clk esdhc4_mx53_clk = {
1401 .secondary = &esdhc4_ipg_clk, 1401 .secondary = &esdhc4_ipg_clk,
1402}; 1402};
1403 1403
1404static struct clk sata_clk = {
1405 .parent = &ipg_clk,
1406 .enable = _clk_max_enable,
1407 .enable_reg = MXC_CCM_CCGR4,
1408 .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
1409 .disable = _clk_max_disable,
1410};
1411
1412static struct clk ahci_phy_clk = {
1413 .parent = &usb_phy1_clk,
1414};
1415
1416static struct clk ahci_dma_clk = {
1417 .parent = &ahb_clk,
1418};
1419
1404DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk); 1420DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
1405DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk); 1421DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
1406DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk); 1422DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
@@ -1513,6 +1529,9 @@ static struct clk_lookup mx53_lookups[] = {
1513 _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) 1529 _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
1514 _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk) 1530 _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
1515 _REGISTER_CLOCK("pata_imx", NULL, pata_clk) 1531 _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
1532 _REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk)
1533 _REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk)
1534 _REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk)
1516}; 1535};
1517 1536
1518static void clk_tree_init(void) 1537static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 7ca5d0c76f8b..6e1e5d1f8c3a 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -44,3 +44,5 @@ extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
44extern const struct imx_pata_imx_data imx53_pata_imx_data; 44extern const struct imx_pata_imx_data imx53_pata_imx_data;
45#define imx53_add_pata_imx() \ 45#define imx53_add_pata_imx() \
46 imx_add_pata_imx(&imx53_pata_imx_data) 46 imx_add_pata_imx(&imx53_pata_imx_data)
47
48extern struct platform_device *__init imx53_add_ahci_imx(void);
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index fdf104f083b7..cf00b3e3be85 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -70,8 +70,25 @@ config MODULE_TX28
70 select MXS_HAVE_PLATFORM_MXS_PWM 70 select MXS_HAVE_PLATFORM_MXS_PWM
71 select MXS_HAVE_PLATFORM_RTC_STMP3XXX 71 select MXS_HAVE_PLATFORM_RTC_STMP3XXX
72 72
73config MODULE_M28
74 bool
75 select SOC_IMX28
76 select LEDS_GPIO_REGISTER
77 select MXS_HAVE_AMBA_DUART
78 select MXS_HAVE_PLATFORM_AUART
79 select MXS_HAVE_PLATFORM_FEC
80 select MXS_HAVE_PLATFORM_FLEXCAN
81 select MXS_HAVE_PLATFORM_MXS_I2C
82 select MXS_HAVE_PLATFORM_MXS_MMC
83 select MXS_HAVE_PLATFORM_MXSFB
84 select MXS_OCOTP
85
73config MACH_TX28 86config MACH_TX28
74 bool "Ka-Ro TX28 module" 87 bool "Ka-Ro TX28 module"
75 select MODULE_TX28 88 select MODULE_TX28
76 89
90config MACH_M28EVK
91 bool "Support DENX M28EVK Platform"
92 select MODULE_M28
93
77endif 94endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index ea8dcb7742bc..8c93b24896bf 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
10obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o 10obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
11obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o 11obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
12obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o 12obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
13obj-$(CONFIG_MACH_M28EVK) += mach-m28evk.o
13obj-$(CONFIG_MODULE_TX28) += module-tx28.o 14obj-$(CONFIG_MODULE_TX28) += module-tx28.o
14obj-$(CONFIG_MACH_TX28) += mach-tx28.o 15obj-$(CONFIG_MACH_TX28) += mach-tx28.o
15 16
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 7954013bd32f..e2fb70c6a745 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -740,11 +740,17 @@ static int clk_misc_init(void)
740 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, 740 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
741 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); 741 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
742 742
743 /* Extra fec clock setting */ 743 /*
744 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); 744 * Extra fec clock setting
745 reg &= ~BM_CLKCTRL_ENET_SLEEP; 745 * The DENX M28 uses an external clock source
746 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; 746 * and the clock output must not be enabled
747 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); 747 */
748 if (!machine_is_m28evk()) {
749 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
750 reg &= ~BM_CLKCTRL_ENET_SLEEP;
751 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
752 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
753 }
748 754
749 /* 755 /*
750 * 480 MHz seems too high to be ssp clock source directly, 756 * 480 MHz seems too high to be ssp clock source directly,
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
index 5aa5f754c846..0d2d2b470998 100644
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -33,6 +33,7 @@
33 0) 33 0)
34#define cpu_is_mx28() ( \ 34#define cpu_is_mx28() ( \
35 machine_is_mx28evk() || \ 35 machine_is_mx28evk() || \
36 machine_is_m28evk() || \
36 machine_is_tx28() || \ 37 machine_is_tx28() || \
37 0) 38 0)
38 39
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index 7f8bf6539646..67776746f143 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -63,6 +63,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
63 mxs_duart_base = MX23_DUART_BASE_ADDR; 63 mxs_duart_base = MX23_DUART_BASE_ADDR;
64 break; 64 break;
65 case MACH_TYPE_MX28EVK: 65 case MACH_TYPE_MX28EVK:
66 case MACH_TYPE_M28EVK:
66 case MACH_TYPE_TX28: 67 case MACH_TYPE_TX28:
67 mxs_duart_base = MX28_DUART_BASE_ADDR; 68 mxs_duart_base = MX28_DUART_BASE_ADDR;
68 break; 69 break;
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
new file mode 100644
index 000000000000..3b1681e4f49a
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-m28evk.c
@@ -0,0 +1,366 @@
1/*
2 * Copyright (C) 2011
3 * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
4 *
5 * based on: mach-mx28_evk.c
6 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/delay.h>
20#include <linux/platform_device.h>
21#include <linux/gpio.h>
22#include <linux/leds.h>
23#include <linux/irq.h>
24#include <linux/clk.h>
25#include <linux/i2c.h>
26#include <linux/i2c/at24.h>
27
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30#include <asm/mach/time.h>
31
32#include <mach/common.h>
33#include <mach/iomux-mx28.h>
34
35#include "devices-mx28.h"
36
37#define M28EVK_GPIO_USERLED1 MXS_GPIO_NR(3, 16)
38#define M28EVK_GPIO_USERLED2 MXS_GPIO_NR(3, 17)
39
40#define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18)
41#define M28EVK_LCD_ENABLE MXS_GPIO_NR(3, 28)
42
43#define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12)
44#define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28)
45
46static const iomux_cfg_t m28evk_pads[] __initconst = {
47 /* duart */
48 MX28_PAD_AUART0_CTS__DUART_RX | MXS_PAD_CTRL,
49 MX28_PAD_AUART0_RTS__DUART_TX | MXS_PAD_CTRL,
50
51 /* auart0 */
52 MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
53 MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
54
55 /* auart3 */
56 MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
57 MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
58 MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
59 MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
60
61#define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
62 /* fec0 */
63 MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
64 MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
65 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
66 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
67 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
68 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
69 MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
70 MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
71 MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
72 /* fec1 */
73 MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
74 MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
75 MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
76 MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
77 MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
78 MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
79
80 /* flexcan0 */
81 MX28_PAD_GPMI_RDY2__CAN0_TX,
82 MX28_PAD_GPMI_RDY3__CAN0_RX,
83
84 /* flexcan1 */
85 MX28_PAD_GPMI_CE2N__CAN1_TX,
86 MX28_PAD_GPMI_CE3N__CAN1_RX,
87
88 /* I2C */
89 MX28_PAD_I2C0_SCL__I2C0_SCL,
90 MX28_PAD_I2C0_SDA__I2C0_SDA,
91
92 /* mxsfb (lcdif) */
93 MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
94 MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
95 MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
96 MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
97 MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
98 MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
99 MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
100 MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
101 MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
102 MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
103 MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
104 MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
105 MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
106 MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
107 MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
108 MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
109 MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
110 MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
111 MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
112 MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
113 MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
114 MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
115 MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
116 MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
117
118 MX28_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
119 MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
120
121 /* mmc0 */
122 MX28_PAD_SSP0_DATA0__SSP0_D0 |
123 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
124 MX28_PAD_SSP0_DATA1__SSP0_D1 |
125 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
126 MX28_PAD_SSP0_DATA2__SSP0_D2 |
127 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
128 MX28_PAD_SSP0_DATA3__SSP0_D3 |
129 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
130 MX28_PAD_SSP0_DATA4__SSP0_D4 |
131 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
132 MX28_PAD_SSP0_DATA5__SSP0_D5 |
133 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
134 MX28_PAD_SSP0_DATA6__SSP0_D6 |
135 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
136 MX28_PAD_SSP0_DATA7__SSP0_D7 |
137 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
138 MX28_PAD_SSP0_CMD__SSP0_CMD |
139 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
140 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
141 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
142 MX28_PAD_SSP0_SCK__SSP0_SCK |
143 (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
144
145 /* mmc1 */
146 MX28_PAD_GPMI_D00__SSP1_D0 |
147 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
148 MX28_PAD_GPMI_D01__SSP1_D1 |
149 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
150 MX28_PAD_GPMI_D02__SSP1_D2 |
151 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
152 MX28_PAD_GPMI_D03__SSP1_D3 |
153 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
154 MX28_PAD_GPMI_D04__SSP1_D4 |
155 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
156 MX28_PAD_GPMI_D05__SSP1_D5 |
157 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
158 MX28_PAD_GPMI_D06__SSP1_D6 |
159 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
160 MX28_PAD_GPMI_D07__SSP1_D7 |
161 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
162 MX28_PAD_GPMI_RDY1__SSP1_CMD |
163 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
164 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
165 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
166 MX28_PAD_GPMI_WRN__SSP1_SCK |
167 (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
168 /* write protect */
169 MX28_PAD_GPMI_RESETN__GPIO_0_28 |
170 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
171 /* slot power enable */
172 MX28_PAD_PWM4__GPIO_3_29 |
173 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
174
175 /* led */
176 MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
177 MX28_PAD_PWM1__GPIO_3_17 | MXS_PAD_CTRL,
178
179 /* nand */
180 MX28_PAD_GPMI_D00__GPMI_D0 |
181 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
182 MX28_PAD_GPMI_D01__GPMI_D1 |
183 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
184 MX28_PAD_GPMI_D02__GPMI_D2 |
185 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
186 MX28_PAD_GPMI_D03__GPMI_D3 |
187 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
188 MX28_PAD_GPMI_D04__GPMI_D4 |
189 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
190 MX28_PAD_GPMI_D05__GPMI_D5 |
191 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
192 MX28_PAD_GPMI_D06__GPMI_D6 |
193 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
194 MX28_PAD_GPMI_D07__GPMI_D7 |
195 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
196 MX28_PAD_GPMI_CE0N__GPMI_CE0N |
197 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
198 MX28_PAD_GPMI_RDY0__GPMI_READY0 |
199 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
200 MX28_PAD_GPMI_RDN__GPMI_RDN |
201 (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
202 MX28_PAD_GPMI_WRN__GPMI_WRN |
203 (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
204 MX28_PAD_GPMI_ALE__GPMI_ALE |
205 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
206 MX28_PAD_GPMI_CLE__GPMI_CLE |
207 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
208 MX28_PAD_GPMI_RESETN__GPMI_RESETN |
209 (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
210
211 /* Backlight */
212 MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL,
213};
214
215/* led */
216static const struct gpio_led m28evk_leds[] __initconst = {
217 {
218 .name = "user-led1",
219 .default_trigger = "heartbeat",
220 .gpio = M28EVK_GPIO_USERLED1,
221 },
222 {
223 .name = "user-led2",
224 .default_trigger = "heartbeat",
225 .gpio = M28EVK_GPIO_USERLED2,
226 },
227};
228
229static const struct gpio_led_platform_data m28evk_led_data __initconst = {
230 .leds = m28evk_leds,
231 .num_leds = ARRAY_SIZE(m28evk_leds),
232};
233
234static struct fec_platform_data mx28_fec_pdata[] __initdata = {
235 {
236 /* fec0 */
237 .phy = PHY_INTERFACE_MODE_RMII,
238 }, {
239 /* fec1 */
240 .phy = PHY_INTERFACE_MODE_RMII,
241 },
242};
243
244static int __init m28evk_fec_get_mac(void)
245{
246 int i;
247 u32 val;
248 const u32 *ocotp = mxs_get_ocotp();
249
250 if (!ocotp) {
251 pr_err("%s: timeout when reading fec mac from OCOTP\n",
252 __func__);
253 return -ETIMEDOUT;
254 }
255
256 /*
257 * OCOTP only stores the last 4 octets for each mac address,
258 * so hard-code DENX OUI (C0:E5:4E) here.
259 */
260 for (i = 0; i < 2; i++) {
261 val = ocotp[i * 4];
262 mx28_fec_pdata[i].mac[0] = 0xC0;
263 mx28_fec_pdata[i].mac[1] = 0xE5;
264 mx28_fec_pdata[i].mac[2] = 0x4E;
265 mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
266 mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
267 mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
268 }
269
270 return 0;
271}
272
273/* mxsfb (lcdif) */
274static struct fb_videomode m28evk_video_modes[] = {
275 {
276 .name = "Ampire AM-800480R2TMQW-T01H",
277 .refresh = 60,
278 .xres = 800,
279 .yres = 480,
280 .pixclock = 30066, /* picosecond (33.26 MHz) */
281 .left_margin = 0,
282 .right_margin = 256,
283 .upper_margin = 0,
284 .lower_margin = 45,
285 .hsync_len = 1,
286 .vsync_len = 1,
287 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
288 },
289};
290
291static const struct mxsfb_platform_data m28evk_mxsfb_pdata __initconst = {
292 .mode_list = m28evk_video_modes,
293 .mode_count = ARRAY_SIZE(m28evk_video_modes),
294 .default_bpp = 16,
295 .ld_intf_width = STMLCDIF_18BIT,
296};
297
298static struct at24_platform_data m28evk_eeprom = {
299 .byte_len = 16384,
300 .page_size = 32,
301 .flags = AT24_FLAG_ADDR16,
302};
303
304static struct i2c_board_info m28_stk5v3_i2c_boardinfo[] __initdata = {
305 {
306 I2C_BOARD_INFO("at24", 0x51), /* E0=1, E1=0, E2=0 */
307 .platform_data = &m28evk_eeprom,
308 },
309};
310
311static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
312 {
313 /* mmc0 */
314 .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT,
315 .flags = SLOTF_8_BIT_CAPABLE,
316 }, {
317 /* mmc1 */
318 .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT,
319 .flags = SLOTF_8_BIT_CAPABLE,
320 },
321};
322
323static void __init m28evk_init(void)
324{
325 mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
326
327 mx28_add_duart();
328 mx28_add_auart0();
329 mx28_add_auart3();
330
331 if (!m28evk_fec_get_mac()) {
332 mx28_add_fec(0, &mx28_fec_pdata[0]);
333 mx28_add_fec(1, &mx28_fec_pdata[1]);
334 }
335
336 mx28_add_flexcan(0, NULL);
337 mx28_add_flexcan(1, NULL);
338
339 mx28_add_mxsfb(&m28evk_mxsfb_pdata);
340
341 mx28_add_mxs_mmc(0, &m28evk_mmc_pdata[0]);
342 mx28_add_mxs_mmc(1, &m28evk_mmc_pdata[1]);
343
344 gpio_led_register_device(0, &m28evk_led_data);
345
346 /* I2C */
347 mx28_add_mxs_i2c(0);
348 i2c_register_board_info(0, m28_stk5v3_i2c_boardinfo,
349 ARRAY_SIZE(m28_stk5v3_i2c_boardinfo));
350}
351
352static void __init m28evk_timer_init(void)
353{
354 mx28_clocks_init();
355}
356
357static struct sys_timer m28evk_timer = {
358 .init = m28evk_timer_init,
359};
360
361MACHINE_START(M28EVK, "DENX M28 EVK")
362 .map_io = mx28_map_io,
363 .init_irq = mx28_init_irq,
364 .init_machine = m28evk_init,
365 .timer = &m28evk_timer,
366MACHINE_END
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index a1a7176675b9..38058af48972 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -128,7 +128,7 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
128 unsigned long clkcon0; 128 unsigned long clkcon0;
129 129
130 clkcon0 = __raw_readl(S3C2443_CLKDIV0); 130 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
131 clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK; 131 clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK;
132 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT; 132 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
133 __raw_writel(clkcon0, S3C2443_CLKDIV0); 133 __raw_writel(clkcon0, S3C2443_CLKDIV0);
134 } 134 }
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ecbea92bf83b..a9f3183e0290 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -262,45 +262,6 @@ static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
262 .cols = 8, 262 .cols = 8,
263}; 263};
264 264
265static int smdk6410_backlight_init(struct device *dev)
266{
267 int ret;
268
269 ret = gpio_request(S3C64XX_GPF(15), "Backlight");
270 if (ret) {
271 printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
272 return ret;
273 }
274
275 /* Configure GPIO pin with S3C64XX_GPF15_PWM_TOUT1 */
276 s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2));
277
278 return 0;
279}
280
281static void smdk6410_backlight_exit(struct device *dev)
282{
283 s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_OUTPUT);
284 gpio_free(S3C64XX_GPF(15));
285}
286
287static struct platform_pwm_backlight_data smdk6410_backlight_data = {
288 .pwm_id = 1,
289 .max_brightness = 255,
290 .dft_brightness = 255,
291 .pwm_period_ns = 78770,
292 .init = smdk6410_backlight_init,
293 .exit = smdk6410_backlight_exit,
294};
295
296static struct platform_device smdk6410_backlight_device = {
297 .name = "pwm-backlight",
298 .dev = {
299 .parent = &s3c_device_timer[1].dev,
300 .platform_data = &smdk6410_backlight_data,
301 },
302};
303
304static struct map_desc smdk6410_iodesc[] = {}; 265static struct map_desc smdk6410_iodesc[] = {};
305 266
306static struct platform_device *smdk6410_devices[] __initdata = { 267static struct platform_device *smdk6410_devices[] __initdata = {
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 52a8e607bcc2..f5f8fa89679c 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -815,8 +815,7 @@ static struct clksrc_clk clksrcs[] = {
815 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, 815 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
816 }, { 816 }, {
817 .clk = { 817 .clk = {
818 .name = "sclk_cam", 818 .name = "sclk_cam0",
819 .devname = "s5pv210-fimc.0",
820 .enable = s5pv210_clk_mask0_ctrl, 819 .enable = s5pv210_clk_mask0_ctrl,
821 .ctrlbit = (1 << 3), 820 .ctrlbit = (1 << 3),
822 }, 821 },
@@ -825,8 +824,7 @@ static struct clksrc_clk clksrcs[] = {
825 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 }, 824 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
826 }, { 825 }, {
827 .clk = { 826 .clk = {
828 .name = "sclk_cam", 827 .name = "sclk_cam1",
829 .devname = "s5pv210-fimc.1",
830 .enable = s5pv210_clk_mask0_ctrl, 828 .enable = s5pv210_clk_mask0_ctrl,
831 .ctrlbit = (1 << 4), 829 .ctrlbit = (1 << 4),
832 }, 830 },
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 3b24bfa3b828..07c4bc8ea0a4 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -174,6 +174,10 @@ ENTRY(v7_coherent_user_range)
174 dcache_line_size r2, r3 174 dcache_line_size r2, r3
175 sub r3, r2, #1 175 sub r3, r2, #1
176 bic r12, r0, r3 176 bic r12, r0, r3
177#ifdef CONFIG_ARM_ERRATA_764369
178 ALT_SMP(W(dsb))
179 ALT_UP(W(nop))
180#endif
1771: 1811:
178 USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification 182 USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
179 add r12, r12, r2 183 add r12, r12, r2
@@ -223,6 +227,10 @@ ENTRY(v7_flush_kern_dcache_area)
223 add r1, r0, r1 227 add r1, r0, r1
224 sub r3, r2, #1 228 sub r3, r2, #1
225 bic r0, r0, r3 229 bic r0, r0, r3
230#ifdef CONFIG_ARM_ERRATA_764369
231 ALT_SMP(W(dsb))
232 ALT_UP(W(nop))
233#endif
2261: 2341:
227 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 235 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
228 add r0, r0, r2 236 add r0, r0, r2
@@ -247,6 +255,10 @@ v7_dma_inv_range:
247 sub r3, r2, #1 255 sub r3, r2, #1
248 tst r0, r3 256 tst r0, r3
249 bic r0, r0, r3 257 bic r0, r0, r3
258#ifdef CONFIG_ARM_ERRATA_764369
259 ALT_SMP(W(dsb))
260 ALT_UP(W(nop))
261#endif
250 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 262 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
251 263
252 tst r1, r3 264 tst r1, r3
@@ -270,6 +282,10 @@ v7_dma_clean_range:
270 dcache_line_size r2, r3 282 dcache_line_size r2, r3
271 sub r3, r2, #1 283 sub r3, r2, #1
272 bic r0, r0, r3 284 bic r0, r0, r3
285#ifdef CONFIG_ARM_ERRATA_764369
286 ALT_SMP(W(dsb))
287 ALT_UP(W(nop))
288#endif
2731: 2891:
274 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line 290 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
275 add r0, r0, r2 291 add r0, r0, r2
@@ -288,6 +304,10 @@ ENTRY(v7_dma_flush_range)
288 dcache_line_size r2, r3 304 dcache_line_size r2, r3
289 sub r3, r2, #1 305 sub r3, r2, #1
290 bic r0, r0, r3 306 bic r0, r0, r3
307#ifdef CONFIG_ARM_ERRATA_764369
308 ALT_SMP(W(dsb))
309 ALT_UP(W(nop))
310#endif
2911: 3111:
292 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 312 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
293 add r0, r0, r2 313 add r0, r0, r2
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 0a0a1e7c20d2..c3ff82f92d9c 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -324,6 +324,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
324 324
325 if (addr) 325 if (addr)
326 *handle = pfn_to_dma(dev, page_to_pfn(page)); 326 *handle = pfn_to_dma(dev, page_to_pfn(page));
327 else
328 __dma_free_buffer(page, size);
327 329
328 return addr; 330 return addr;
329} 331}
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index b0f74f70b25c..cb3e3eef55c0 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -79,3 +79,7 @@ config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
79 79
80config IMX_HAVE_PLATFORM_SPI_IMX 80config IMX_HAVE_PLATFORM_SPI_IMX
81 bool 81 bool
82
83config IMX_HAVE_PLATFORM_AHCI
84 bool
85 default y if ARCH_MX53
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index a093b454541d..c11ac8472beb 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
26obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o 26obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
27obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o 27obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
28obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o 28obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
29obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) += platform-ahci-imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-ahci-imx.c b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
new file mode 100644
index 000000000000..d8a56aee521b
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
@@ -0,0 +1,156 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/io.h>
22#include <linux/clk.h>
23#include <linux/err.h>
24#include <linux/device.h>
25#include <linux/dma-mapping.h>
26#include <asm/sizes.h>
27#include <mach/hardware.h>
28#include <mach/devices-common.h>
29
30#define imx_ahci_imx_data_entry_single(soc, _devid) \
31 { \
32 .devid = _devid, \
33 .iobase = soc ## _SATA_BASE_ADDR, \
34 .irq = soc ## _INT_SATA, \
35 }
36
37#ifdef CONFIG_SOC_IMX53
38const struct imx_ahci_imx_data imx53_ahci_imx_data __initconst =
39 imx_ahci_imx_data_entry_single(MX53, "imx53-ahci");
40#endif
41
42enum {
43 HOST_CAP = 0x00,
44 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
45 HOST_PORTS_IMPL = 0x0c,
46 HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
47};
48
49static struct clk *sata_clk, *sata_ref_clk;
50
51/* AHCI module Initialization, if return 0, initialization is successful. */
52static int imx_sata_init(struct device *dev, void __iomem *addr)
53{
54 u32 tmpdata;
55 int ret = 0;
56 struct clk *clk;
57
58 sata_clk = clk_get(dev, "ahci");
59 if (IS_ERR(sata_clk)) {
60 dev_err(dev, "no sata clock.\n");
61 return PTR_ERR(sata_clk);
62 }
63 ret = clk_enable(sata_clk);
64 if (ret) {
65 dev_err(dev, "can't enable sata clock.\n");
66 goto put_sata_clk;
67 }
68
69 /* Get the AHCI SATA PHY CLK */
70 sata_ref_clk = clk_get(dev, "ahci_phy");
71 if (IS_ERR(sata_ref_clk)) {
72 dev_err(dev, "no sata ref clock.\n");
73 ret = PTR_ERR(sata_ref_clk);
74 goto release_sata_clk;
75 }
76 ret = clk_enable(sata_ref_clk);
77 if (ret) {
78 dev_err(dev, "can't enable sata ref clock.\n");
79 goto put_sata_ref_clk;
80 }
81
82 /* Get the AHB clock rate, and configure the TIMER1MS reg later */
83 clk = clk_get(dev, "ahci_dma");
84 if (IS_ERR(clk)) {
85 dev_err(dev, "no dma clock.\n");
86 ret = PTR_ERR(clk);
87 goto release_sata_ref_clk;
88 }
89 tmpdata = clk_get_rate(clk) / 1000;
90 clk_put(clk);
91
92 writel(tmpdata, addr + HOST_TIMER1MS);
93
94 tmpdata = readl(addr + HOST_CAP);
95 if (!(tmpdata & HOST_CAP_SSS)) {
96 tmpdata |= HOST_CAP_SSS;
97 writel(tmpdata, addr + HOST_CAP);
98 }
99
100 if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
101 writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
102 addr + HOST_PORTS_IMPL);
103
104 return 0;
105
106release_sata_ref_clk:
107 clk_disable(sata_ref_clk);
108put_sata_ref_clk:
109 clk_put(sata_ref_clk);
110release_sata_clk:
111 clk_disable(sata_clk);
112put_sata_clk:
113 clk_put(sata_clk);
114
115 return ret;
116}
117
118static void imx_sata_exit(struct device *dev)
119{
120 clk_disable(sata_ref_clk);
121 clk_put(sata_ref_clk);
122
123 clk_disable(sata_clk);
124 clk_put(sata_clk);
125
126}
127struct platform_device *__init imx_add_ahci_imx(
128 const struct imx_ahci_imx_data *data,
129 const struct ahci_platform_data *pdata)
130{
131 struct resource res[] = {
132 {
133 .start = data->iobase,
134 .end = data->iobase + SZ_4K - 1,
135 .flags = IORESOURCE_MEM,
136 }, {
137 .start = data->irq,
138 .end = data->irq,
139 .flags = IORESOURCE_IRQ,
140 },
141 };
142
143 return imx_add_platform_device_dmamask(data->devid, 0,
144 res, ARRAY_SIZE(res),
145 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
146}
147
148struct platform_device *__init imx53_add_ahci_imx(void)
149{
150 struct ahci_platform_data pdata = {
151 .init = imx_sata_init,
152 .exit = imx_sata_exit,
153 };
154
155 return imx_add_ahci_imx(&imx53_ahci_imx_data, &pdata);
156}
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 4cbad45edc15..117a381fe3d5 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -309,3 +309,13 @@ struct platform_device *__init imx_add_spi_imx(
309struct platform_device *imx_add_imx_dma(void); 309struct platform_device *imx_add_imx_dma(void);
310struct platform_device *imx_add_imx_sdma(char *name, 310struct platform_device *imx_add_imx_sdma(char *name,
311 resource_size_t iobase, int irq, struct sdma_platform_data *pdata); 311 resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
312
313#include <linux/ahci_platform.h>
314struct imx_ahci_imx_data {
315 const char *devid;
316 resource_size_t iobase;
317 resource_size_t irq;
318};
319struct platform_device *__init imx_add_ahci_imx(
320 const struct imx_ahci_imx_data *data,
321 const struct ahci_platform_data *pdata);
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index f71078ef6bb5..f88216d23991 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -114,17 +114,18 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
114{ 114{
115 static int used_gpioint_groups = 0; 115 static int used_gpioint_groups = 0;
116 int group = chip->group; 116 int group = chip->group;
117 struct s5p_gpioint_bank *bank = NULL; 117 struct s5p_gpioint_bank *b, *bank = NULL;
118 struct irq_chip_generic *gc; 118 struct irq_chip_generic *gc;
119 struct irq_chip_type *ct; 119 struct irq_chip_type *ct;
120 120
121 if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT) 121 if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
122 return -ENOMEM; 122 return -ENOMEM;
123 123
124 list_for_each_entry(bank, &banks, list) { 124 list_for_each_entry(b, &banks, list) {
125 if (group >= bank->start && 125 if (group >= b->start && group < b->start + b->nr_groups) {
126 group < bank->start + bank->nr_groups) 126 bank = b;
127 break; 127 break;
128 }
128 } 129 }
129 if (!bank) 130 if (!bank)
130 return -EINVAL; 131 return -EINVAL;
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 302c42670bd1..3b4451979d1b 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -64,6 +64,17 @@ static LIST_HEAD(clocks);
64 */ 64 */
65DEFINE_SPINLOCK(clocks_lock); 65DEFINE_SPINLOCK(clocks_lock);
66 66
67/* Global watchdog clock used by arch_wtd_reset() callback */
68struct clk *s3c2410_wdtclk;
69static int __init s3c_wdt_reset_init(void)
70{
71 s3c2410_wdtclk = clk_get(NULL, "watchdog");
72 if (IS_ERR(s3c2410_wdtclk))
73 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
74 return 0;
75}
76arch_initcall(s3c_wdt_reset_init);
77
67/* enable and disable calls for use with the clk struct */ 78/* enable and disable calls for use with the clk struct */
68 79
69static int clk_null_enable(struct clk *clk, int enable) 80static int clk_null_enable(struct clk *clk, int enable)
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 87d5b38a86fb..73c66d4d10fa 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -9,6 +9,9 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10*/ 10*/
11 11
12#ifndef __ASM_PLAT_CLOCK_H
13#define __ASM_PLAT_CLOCK_H __FILE__
14
12#include <linux/spinlock.h> 15#include <linux/spinlock.h>
13#include <linux/clkdev.h> 16#include <linux/clkdev.h>
14 17
@@ -121,3 +124,8 @@ extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
121 124
122extern void s3c_pwmclk_init(void); 125extern void s3c_pwmclk_init(void);
123 126
127/* Global watchdog clock used by arch_wtd_reset() callback */
128
129extern struct clk *s3c2410_wdtclk;
130
131#endif /* __ASM_PLAT_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
index 54b762acb5a0..40dbb2b0ae22 100644
--- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h
+++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
@@ -10,6 +10,7 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13#include <plat/clock.h>
13#include <plat/regs-watchdog.h> 14#include <plat/regs-watchdog.h>
14#include <mach/map.h> 15#include <mach/map.h>
15 16
@@ -19,17 +20,12 @@
19 20
20static inline void arch_wdt_reset(void) 21static inline void arch_wdt_reset(void)
21{ 22{
22 struct clk *wdtclk;
23
24 printk("arch_reset: attempting watchdog reset\n"); 23 printk("arch_reset: attempting watchdog reset\n");
25 24
26 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ 25 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
27 26
28 wdtclk = clk_get(NULL, "watchdog"); 27 if (s3c2410_wdtclk)
29 if (!IS_ERR(wdtclk)) { 28 clk_enable(s3c2410_wdtclk);
30 clk_enable(wdtclk);
31 } else
32 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
33 29
34 /* put initial values into count and data */ 30 /* put initial values into count and data */
35 __raw_writel(0x80, S3C2410_WTCNT); 31 __raw_writel(0x80, S3C2410_WTCNT);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 16:46:28 -0500