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authorHolger Schurig <hs4233@mail.mn-solutions.de>2009-01-26 10:34:53 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2009-03-13 05:33:53 -0400
commit260a1fd26c62af482a22c6b31cc7882b4ec980d2 (patch)
tree358b432297a42123ac3970999ac9e1add47d5dd2 /arch/arm
parent058b7a6f465bebd87c1f295afdd56cc6a33dffbd (diff)
arm/imx2x: split i.MX21/i.MX27 register definitions
* define new CONFIG_ARCH_MX21 (this one is currently mutually exclusive to CONFIG_ARCH_MX27, but this might change) * splits one header file. Memory definitions, interrupt sources, DMA channels are split into common part, i.MX27 specific and i.MX21 specific. * guard access to UART5/UART6, which don't exist on i.MX21 Signed-off-by: Holger Schurig <hs4233@mail.mn-solutions.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h81
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h197
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h200
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h4
5 files changed, 306 insertions, 180 deletions
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index a612d8bb73c8..11f5727ea445 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -27,6 +27,10 @@
27#endif 27#endif
28 28
29#ifdef CONFIG_ARCH_MX2 29#ifdef CONFIG_ARCH_MX2
30# include <mach/mx2x.h>
31# ifdef CONFIG_MACH_MX21
32# include <mach/mx21.h>
33# endif
30# ifdef CONFIG_MACH_MX27 34# ifdef CONFIG_MACH_MX27
31# include <mach/mx27.h> 35# include <mach/mx27.h>
32# endif 36# endif
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
new file mode 100644
index 000000000000..cfdbe051caf6
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -0,0 +1,81 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
5 *
6 * This contains i.MX21-specific hardware definitions. For those
7 * hardware pieces that are common between i.MX21 and i.MX27, have a
8 * look at mx2x.h.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25#ifndef __ASM_ARCH_MXC_MX21_H__
26#define __ASM_ARCH_MXC_MX21_H__
27
28#ifndef __ASM_ARCH_MXC_HARDWARE_H__
29#error "Do not include directly."
30#endif
31
32
33/* Memory regions and CS */
34#define SDRAM_BASE_ADDR 0xC0000000
35#define CSD1_BASE_ADDR 0xC4000000
36
37#define CS0_BASE_ADDR 0xC8000000
38#define CS1_BASE_ADDR 0xCC000000
39#define CS2_BASE_ADDR 0xD0000000
40#define CS3_BASE_ADDR 0xD1000000
41#define CS4_BASE_ADDR 0xD2000000
42#define CS5_BASE_ADDR 0xDD000000
43#define PCMCIA_MEM_BASE_ADDR 0xD4000000
44
45/* NAND, SDRAM, WEIM etc controllers */
46#define X_MEMC_BASE_ADDR 0xDF000000
47#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
48#define X_MEMC_SIZE SZ_256K
49
50#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
51#define EIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
52#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
53#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
54
55#define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */
56
57/* this is an i.MX21 CPU */
58#define cpu_is_mx21() (1)
59
60/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
61#define ARCH_NR_GPIOS (6*32 + 16)
62
63/* fixed interrupt numbers */
64#define MXC_INT_USBCTRL 58
65#define MXC_INT_USBCTRL 58
66#define MXC_INT_USBMNP 57
67#define MXC_INT_USBFUNC 56
68#define MXC_INT_USBHOST 55
69#define MXC_INT_USBDMA 54
70#define MXC_INT_USBWKUP 53
71#define MXC_INT_EMMADEC 50
72#define MXC_INT_EMMAENC 49
73#define MXC_INT_BMI 30
74#define MXC_INT_FIRI 9
75
76/* fixed DMA request numbers */
77#define DMA_REQ_BMI_RX 29
78#define DMA_REQ_BMI_TX 28
79#define DMA_REQ_FIRI_RX 4
80
81#endif /* __ASM_ARCH_MXC_MX21_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 9c609d3ba23e..5f6a8a7bb19c 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -2,6 +2,10 @@
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 * 4 *
5 * This contains i.MX27-specific hardware definitions. For those
6 * hardware pieces that are common between i.MX21 and i.MX27, have a
7 * look at mx2x.h.
8 *
5 * This program is free software; you can redistribute it and/or 9 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 10 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2 11 * as published by the Free Software Foundation; either version 2
@@ -27,35 +31,6 @@
27/* IRAM */ 31/* IRAM */
28#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ 32#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */
29 33
30/* Register offests */
31#define AIPI_BASE_ADDR 0x10000000
32#define AIPI_BASE_ADDR_VIRT 0xF4000000
33#define AIPI_SIZE SZ_1M
34
35#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000)
36#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000)
37#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000)
38#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000)
39#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000)
40#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000)
41#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000)
42#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000)
43#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000)
44#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000)
45#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000)
46#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000)
47#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000)
48#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000)
49#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000)
50#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000)
51#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000)
52#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000)
53#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000)
54#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000)
55#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000)
56#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000)
57
58#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000)
59#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000) 34#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000)
60#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000) 35#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000)
61#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000) 36#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000)
@@ -64,55 +39,24 @@
64#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000) 39#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000)
65#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000) 40#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000)
66#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000) 41#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000)
67
68#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000)
69#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000)
70#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000) 42#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000)
71#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000)
72/* for mx27*/
73#define OTG_BASE_ADDR USBOTG_BASE_ADDR 43#define OTG_BASE_ADDR USBOTG_BASE_ADDR
74#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) 44#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000)
75#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000)
76#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
77#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
78#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
79#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) 45#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000)
80
81#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000) 46#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000)
82#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000) 47#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000)
83#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000) 48#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000)
84#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000) 49#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000)
85#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000) 50#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000)
86 51
87#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000) 52/* ROM patch */
88#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000)
89
90/* ROMP and AVIC */
91#define ROMP_BASE_ADDR 0x10041000 53#define ROMP_BASE_ADDR 0x10041000
92 54
93#define AVIC_BASE_ADDR 0x10040000
94
95#define SAHB1_BASE_ADDR 0x80000000
96#define SAHB1_BASE_ADDR_VIRT 0xF4100000
97#define SAHB1_SIZE SZ_1M
98
99#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
100#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000) 55#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000)
101 56
102/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
103#define X_MEMC_BASE_ADDR 0xD8000000
104#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
105#define X_MEMC_SIZE SZ_1M
106
107#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR)
108#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
109#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
110#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
111#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
112
113/* Memory regions and CS */ 57/* Memory regions and CS */
114#define SDRAM_BASE_ADDR 0xA0000000 58#define SDRAM_BASE_ADDR 0xA0000000
115#define CSD1_BASE_ADDR 0xB0000000 59#define CSD1_BASE_ADDR 0xB0000000
116 60
117#define CS0_BASE_ADDR 0xC0000000 61#define CS0_BASE_ADDR 0xC0000000
118#define CS1_BASE_ADDR 0xC8000000 62#define CS1_BASE_ADDR 0xC8000000
@@ -122,44 +66,20 @@
122#define CS5_BASE_ADDR 0xD6000000 66#define CS5_BASE_ADDR 0xD6000000
123#define PCMCIA_MEM_BASE_ADDR 0xDC000000 67#define PCMCIA_MEM_BASE_ADDR 0xDC000000
124 68
125/* 69/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
126 * This macro defines the physical to virtual address mapping for all the 70#define X_MEMC_BASE_ADDR 0xD8000000
127 * peripheral modules. It is used by passing in the physical address as x 71#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
128 * and returning the virtual address. If the physical address is not mapped, 72#define X_MEMC_SIZE SZ_1M
129 * it returns 0xDEADBEEF
130 */
131#define IO_ADDRESS(x) \
132 (void __force __iomem *) \
133 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
134 AIPI_IO_ADDRESS(x) : \
135 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
136 SAHB1_IO_ADDRESS(x) : \
137 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
138 X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
139
140/* define the address mapping macros: in physical address order */
141#define AIPI_IO_ADDRESS(x) \
142 (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
143
144#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
145
146#define SAHB1_IO_ADDRESS(x) \
147 (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
148
149#define CS4_IO_ADDRESS(x) \
150 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
151
152#define X_MEMC_IO_ADDRESS(x) \
153 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
154 73
155#define PCMCIA_IO_ADDRESS(x) \ 74#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR)
156 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) 75#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
76#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
77#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
78#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
157 79
158/* fixed interrput numbers */ 80/* fixed interrupt numbers */
159#define MXC_INT_CCM 63 81#define MXC_INT_CCM 63
160#define MXC_INT_IIM 62 82#define MXC_INT_IIM 62
161#define MXC_INT_LCDC 61
162#define MXC_INT_SLCDC 60
163#define MXC_INT_SAHARA 59 83#define MXC_INT_SAHARA 59
164#define MXC_INT_SCC_SCM 58 84#define MXC_INT_SCC_SCM 58
165#define MXC_INT_SCC_SMN 57 85#define MXC_INT_SCC_SMN 57
@@ -167,54 +87,12 @@
167#define MXC_INT_USB2 55 87#define MXC_INT_USB2 55
168#define MXC_INT_USB1 54 88#define MXC_INT_USB1 54
169#define MXC_INT_VPU 53 89#define MXC_INT_VPU 53
170#define MXC_INT_EMMAPP 52
171#define MXC_INT_EMMAPRP 51
172#define MXC_INT_FEC 50 90#define MXC_INT_FEC 50
173#define MXC_INT_UART5 49 91#define MXC_INT_UART5 49
174#define MXC_INT_UART6 48 92#define MXC_INT_UART6 48
175#define MXC_INT_DMACH15 47
176#define MXC_INT_DMACH14 46
177#define MXC_INT_DMACH13 45
178#define MXC_INT_DMACH12 44
179#define MXC_INT_DMACH11 43
180#define MXC_INT_DMACH10 42
181#define MXC_INT_DMACH9 41
182#define MXC_INT_DMACH8 40
183#define MXC_INT_DMACH7 39
184#define MXC_INT_DMACH6 38
185#define MXC_INT_DMACH5 37
186#define MXC_INT_DMACH4 36
187#define MXC_INT_DMACH3 35
188#define MXC_INT_DMACH2 34
189#define MXC_INT_DMACH1 33
190#define MXC_INT_DMACH0 32
191#define MXC_INT_CSI 31
192#define MXC_INT_ATA 30 93#define MXC_INT_ATA 30
193#define MXC_INT_NANDFC 29
194#define MXC_INT_PCMCIA 28
195#define MXC_INT_WDOG 27
196#define MXC_INT_GPT1 26
197#define MXC_INT_GPT2 25
198#define MXC_INT_GPT3 24
199#define MXC_INT_GPT INT_GPT1
200#define MXC_INT_PWM 23
201#define MXC_INT_RTC 22
202#define MXC_INT_KPP 21
203#define MXC_INT_UART1 20
204#define MXC_INT_UART2 19
205#define MXC_INT_UART3 18
206#define MXC_INT_UART4 17
207#define MXC_INT_CSPI1 16
208#define MXC_INT_CSPI2 15
209#define MXC_INT_SSI1 14
210#define MXC_INT_SSI2 13
211#define MXC_INT_I2C 12
212#define MXC_INT_SDHC1 11
213#define MXC_INT_SDHC2 10
214#define MXC_INT_SDHC3 9 94#define MXC_INT_SDHC3 9
215#define MXC_INT_GPIO 8
216#define MXC_INT_SDHC 7 95#define MXC_INT_SDHC 7
217#define MXC_INT_CSPI3 6
218#define MXC_INT_RTIC 5 96#define MXC_INT_RTIC 5
219#define MXC_INT_GPT4 4 97#define MXC_INT_GPT4 4
220#define MXC_INT_GPT5 3 98#define MXC_INT_GPT5 3
@@ -228,36 +106,9 @@
228#define DMA_REQ_UART6_TX 34 106#define DMA_REQ_UART6_TX 34
229#define DMA_REQ_UART5_RX 33 107#define DMA_REQ_UART5_RX 33
230#define DMA_REQ_UART5_TX 32 108#define DMA_REQ_UART5_TX 32
231#define DMA_REQ_CSI_RX 31
232#define DMA_REQ_CSI_STAT 30
233#define DMA_REQ_ATA_RCV 29 109#define DMA_REQ_ATA_RCV 29
234#define DMA_REQ_ATA_TX 28 110#define DMA_REQ_ATA_TX 28
235#define DMA_REQ_UART1_TX 27
236#define DMA_REQ_UART1_RX 26
237#define DMA_REQ_UART2_TX 25
238#define DMA_REQ_UART2_RX 24
239#define DMA_REQ_UART3_TX 23
240#define DMA_REQ_UART3_RX 22
241#define DMA_REQ_UART4_TX 21
242#define DMA_REQ_UART4_RX 20
243#define DMA_REQ_CSPI1_TX 19
244#define DMA_REQ_CSPI1_RX 18
245#define DMA_REQ_CSPI2_TX 17
246#define DMA_REQ_CSPI2_RX 16
247#define DMA_REQ_SSI1_TX1 15
248#define DMA_REQ_SSI1_RX1 14
249#define DMA_REQ_SSI1_TX0 13
250#define DMA_REQ_SSI1_RX0 12
251#define DMA_REQ_SSI2_TX1 11
252#define DMA_REQ_SSI2_RX1 10
253#define DMA_REQ_SSI2_TX0 9
254#define DMA_REQ_SSI2_RX0 8
255#define DMA_REQ_SDHC1 7
256#define DMA_REQ_SDHC2 6
257#define DMA_REQ_MSHC 4 111#define DMA_REQ_MSHC 4
258#define DMA_REQ_EXT 3
259#define DMA_REQ_CSPI3_TX 2
260#define DMA_REQ_CSPI3_RX 1
261 112
262/* silicon revisions specific to i.MX27 */ 113/* silicon revisions specific to i.MX27 */
263#define CHIP_REV_1_0 0x00 114#define CHIP_REV_1_0 0x00
@@ -267,20 +118,6 @@
267extern int mx27_revision(void); 118extern int mx27_revision(void);
268#endif 119#endif
269 120
270/* gpio and gpio based interrupt handling */
271#define GPIO_DR 0x1C
272#define GPIO_GDIR 0x00
273#define GPIO_PSR 0x24
274#define GPIO_ICR1 0x28
275#define GPIO_ICR2 0x2C
276#define GPIO_IMR 0x30
277#define GPIO_ISR 0x34
278#define GPIO_INT_LOW_LEV 0x3
279#define GPIO_INT_HIGH_LEV 0x2
280#define GPIO_INT_RISE_EDGE 0x0
281#define GPIO_INT_FALL_EDGE 0x1
282#define GPIO_INT_NONE 0x4
283
284/* Mandatory defines used globally */ 121/* Mandatory defines used globally */
285 122
286/* this is an i.MX27 CPU */ 123/* this is an i.MX27 CPU */
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
new file mode 100644
index 000000000000..fc40d3ab8c5b
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -0,0 +1,200 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This contains hardware definitions that are common between i.MX21 and
6 * i.MX27.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#ifndef __ASM_ARCH_MXC_MX2x_H__
24#define __ASM_ARCH_MXC_MX2x_H__
25
26#ifndef __ASM_ARCH_MXC_HARDWARE_H__
27#error "Do not include directly."
28#endif
29
30/* The following addresses are common between i.MX21 and i.MX27 */
31
32/* Register offests */
33#define AIPI_BASE_ADDR 0x10000000
34#define AIPI_BASE_ADDR_VIRT 0xF4000000
35#define AIPI_SIZE SZ_1M
36
37#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000)
38#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000)
39#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000)
40#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000)
41#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000)
42#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000)
43#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000)
44#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000)
45#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000)
46#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000)
47#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000)
48#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000)
49#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000)
50#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000)
51#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000)
52#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000)
53#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000)
54#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000)
55#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000)
56#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000)
57#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000)
58#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000)
59#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000)
60#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000)
61#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000)
62#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000)
63#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000)
64#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
65#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
66#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
67#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000)
68#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000)
69
70#define AVIC_BASE_ADDR 0x10040000
71
72#define SAHB1_BASE_ADDR 0x80000000
73#define SAHB1_BASE_ADDR_VIRT 0xF4100000
74#define SAHB1_SIZE SZ_1M
75
76#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
77
78/*
79 * This macro defines the physical to virtual address mapping for all the
80 * peripheral modules. It is used by passing in the physical address as x
81 * and returning the virtual address. If the physical address is not mapped,
82 * it returns 0xDEADBEEF
83 */
84#define IO_ADDRESS(x) \
85 (void __force __iomem *) \
86 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
87 AIPI_IO_ADDRESS(x) : \
88 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
89 SAHB1_IO_ADDRESS(x) : \
90 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
91 X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
92
93/* define the address mapping macros: in physical address order */
94#define AIPI_IO_ADDRESS(x) \
95 (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
96
97#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
98
99#define SAHB1_IO_ADDRESS(x) \
100 (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
101
102#define CS4_IO_ADDRESS(x) \
103 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
104
105#define X_MEMC_IO_ADDRESS(x) \
106 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
107
108#define PCMCIA_IO_ADDRESS(x) \
109 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
110
111/* fixed interrupt numbers */
112#define MXC_INT_LCDC 61
113#define MXC_INT_SLCDC 60
114#define MXC_INT_EMMAPP 52
115#define MXC_INT_EMMAPRP 51
116#define MXC_INT_DMACH15 47
117#define MXC_INT_DMACH14 46
118#define MXC_INT_DMACH13 45
119#define MXC_INT_DMACH12 44
120#define MXC_INT_DMACH11 43
121#define MXC_INT_DMACH10 42
122#define MXC_INT_DMACH9 41
123#define MXC_INT_DMACH8 40
124#define MXC_INT_DMACH7 39
125#define MXC_INT_DMACH6 38
126#define MXC_INT_DMACH5 37
127#define MXC_INT_DMACH4 36
128#define MXC_INT_DMACH3 35
129#define MXC_INT_DMACH2 34
130#define MXC_INT_DMACH1 33
131#define MXC_INT_DMACH0 32
132#define MXC_INT_CSI 31
133#define MXC_INT_NANDFC 29
134#define MXC_INT_PCMCIA 28
135#define MXC_INT_WDOG 27
136#define MXC_INT_GPT1 26
137#define MXC_INT_GPT2 25
138#define MXC_INT_GPT3 24
139#define MXC_INT_GPT INT_GPT1
140#define MXC_INT_PWM 23
141#define MXC_INT_RTC 22
142#define MXC_INT_KPP 21
143#define MXC_INT_UART1 20
144#define MXC_INT_UART2 19
145#define MXC_INT_UART3 18
146#define MXC_INT_UART4 17
147#define MXC_INT_CSPI1 16
148#define MXC_INT_CSPI2 15
149#define MXC_INT_SSI1 14
150#define MXC_INT_SSI2 13
151#define MXC_INT_I2C 12
152#define MXC_INT_SDHC1 11
153#define MXC_INT_SDHC2 10
154#define MXC_INT_GPIO 8
155#define MXC_INT_CSPI3 6
156
157/* gpio and gpio based interrupt handling */
158#define GPIO_DR 0x1C
159#define GPIO_GDIR 0x00
160#define GPIO_PSR 0x24
161#define GPIO_ICR1 0x28
162#define GPIO_ICR2 0x2C
163#define GPIO_IMR 0x30
164#define GPIO_ISR 0x34
165#define GPIO_INT_LOW_LEV 0x3
166#define GPIO_INT_HIGH_LEV 0x2
167#define GPIO_INT_RISE_EDGE 0x0
168#define GPIO_INT_FALL_EDGE 0x1
169#define GPIO_INT_NONE 0x4
170
171/* fixed DMA request numbers */
172#define DMA_REQ_CSI_RX 31
173#define DMA_REQ_CSI_STAT 30
174#define DMA_REQ_UART1_TX 27
175#define DMA_REQ_UART1_RX 26
176#define DMA_REQ_UART2_TX 25
177#define DMA_REQ_UART2_RX 24
178#define DMA_REQ_UART3_TX 23
179#define DMA_REQ_UART3_RX 22
180#define DMA_REQ_UART4_TX 21
181#define DMA_REQ_UART4_RX 20
182#define DMA_REQ_CSPI1_TX 19
183#define DMA_REQ_CSPI1_RX 18
184#define DMA_REQ_CSPI2_TX 17
185#define DMA_REQ_CSPI2_RX 16
186#define DMA_REQ_SSI1_TX1 15
187#define DMA_REQ_SSI1_RX1 14
188#define DMA_REQ_SSI1_TX0 13
189#define DMA_REQ_SSI1_RX0 12
190#define DMA_REQ_SSI2_TX1 11
191#define DMA_REQ_SSI2_RX1 10
192#define DMA_REQ_SSI2_TX0 9
193#define DMA_REQ_SSI2_RX0 8
194#define DMA_REQ_SDHC1 7
195#define DMA_REQ_SDHC2 6
196#define DMA_REQ_EXT 3
197#define DMA_REQ_CSPI3_TX 2
198#define DMA_REQ_CSPI3_RX 1
199
200#endif /* __ASM_ARCH_MXC_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index bbd848e004d7..d6b0c472cd97 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -37,6 +37,10 @@
37# define cpu_is_mx27() (0) 37# define cpu_is_mx27() (0)
38#endif 38#endif
39 39
40#ifndef CONFIG_MACH_MX21
41# define cpu_is_mx21() (0)
42#endif
43
40#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) 44#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
41#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10) 45#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10)
42#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4) 46#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 20:27:32 -0500