diff options
| author | Daniel Mack <daniel@caiaq.de> | 2009-03-04 15:16:57 -0500 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2009-03-06 08:37:12 -0500 |
| commit | 20a41eac4fbaa22d051d0fbaeaf3315d2d8c4860 (patch) | |
| tree | 47dbc8522985fd6625ce4de4f76707feca6d4f75 /arch/arm | |
| parent | 89492be88616aa20b3a6c3eb512f83c0c7d0c8a3 (diff) | |
ASoC: Fix name of register bit in pxa-ssp
A bit in PXA's SSCR0 register was erroneously named ADC but its name is
in fact ACS (audio clock select).
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/regs-ssp.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h index 3c04cde2cf1f..cacdcae451e6 100644 --- a/arch/arm/mach-pxa/include/mach/regs-ssp.h +++ b/arch/arm/mach-pxa/include/mach/regs-ssp.h | |||
| @@ -47,7 +47,7 @@ | |||
| 47 | #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ | 47 | #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ |
| 48 | #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ | 48 | #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ |
| 49 | #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ | 49 | #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ |
| 50 | #define SSCR0_ADC (1 << 30) /* Audio clock select */ | 50 | #define SSCR0_ACS (1 << 30) /* Audio clock select */ |
| 51 | #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ | 51 | #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ |
| 52 | #endif | 52 | #endif |
| 53 | 53 | ||