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authorRussell King <rmk+kernel@arm.linux.org.uk>2013-09-27 15:07:26 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-01-27 09:18:09 -0500
commit208d7baf8085ed639ec896274f1679d4718f2ff3 (patch)
treead5ec8c11c35d27f9beca7e602e3ccb921cd9d63 /arch/arm
parentd8ec26d7f8287f5788a494f56e8814210f0e64be (diff)
ARM: imx: initial SolidRun HummingBoard support
Add support for the SolidRun HummingBoard. This commit adds support for the following interfaces on this board: - Consumer Ir receiver - S/PDIF output - Both USB interfaces - Gigabit Ethernet using AR8035 - UART port Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/imx6dl-hummingboard.dts167
-rw-r--r--arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi62
-rw-r--r--arch/arm/boot/dts/imx6qdl-microsom.dtsi33
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c35
5 files changed, 298 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a65b24f..875af333c6dc 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -136,6 +136,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
136 imx53-mba53.dtb \ 136 imx53-mba53.dtb \
137 imx53-qsb.dtb \ 137 imx53-qsb.dtb \
138 imx53-smd.dtb \ 138 imx53-smd.dtb \
139 imx6dl-hummingboard.dtb \
139 imx6dl-sabreauto.dtb \ 140 imx6dl-sabreauto.dtb \
140 imx6dl-sabresd.dtb \ 141 imx6dl-sabresd.dtb \
141 imx6dl-wandboard.dtb \ 142 imx6dl-wandboard.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
new file mode 100644
index 000000000000..fd8fc7cd53f3
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -0,0 +1,167 @@
1/*
2 * Copyright (C) 2013,2014 Russell King
3 */
4/dts-v1/;
5
6#include "imx6dl.dtsi"
7#include "imx6qdl-microsom.dtsi"
8#include "imx6qdl-microsom-ar8035.dtsi"
9
10/ {
11 model = "SolidRun HummingBoard DL/Solo";
12 compatible = "solidrun,hummingboard", "fsl,imx6dl";
13
14 ir_recv: ir-receiver {
15 compatible = "gpio-ir-receiver";
16 gpios = <&gpio1 2 1>;
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>;
19 };
20
21 regulators {
22 compatible = "simple-bus";
23
24 reg_3p3v: 3p3v {
25 compatible = "regulator-fixed";
26 regulator-name = "3P3V";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-always-on;
30 };
31
32 reg_usbh1_vbus: usb-h1-vbus {
33 compatible = "regulator-fixed";
34 enable-active-high;
35 gpio = <&gpio1 0 0>;
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
38 regulator-name = "usb_h1_vbus";
39 regulator-min-microvolt = <5000000>;
40 regulator-max-microvolt = <5000000>;
41 };
42
43 reg_usbotg_vbus: usb-otg-vbus {
44 compatible = "regulator-fixed";
45 enable-active-high;
46 gpio = <&gpio3 22 0>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
49 regulator-name = "usb_otg_vbus";
50 regulator-min-microvolt = <5000000>;
51 regulator-max-microvolt = <5000000>;
52 };
53 };
54
55 codec: spdif-transmitter {
56 compatible = "linux,spdif-dit";
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_hummingboard_spdif>;
59 };
60
61 sound-spdif {
62 compatible = "fsl,imx-audio-spdif";
63 model = "imx-spdif";
64 /* IMX6 doesn't implement this yet */
65 spdif-controller = <&spdif>;
66 spdif-out;
67 };
68};
69
70&can1 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
73 status = "okay";
74};
75
76&i2c1 {
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
79
80 /*
81 * Not fitted on Carrier-1 board... yet
82 status = "okay";
83
84 rtc: pcf8523@68 {
85 compatible = "nxp,pcf8523";
86 reg = <0x68>;
87 };
88 */
89};
90
91&iomuxc {
92 hummingboard {
93 pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
94 fsl,pins = <
95 MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
96 MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
97 >;
98 };
99
100 pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 {
101 fsl,pins = <
102 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
103 >;
104 };
105
106 pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
107 fsl,pins = <
108 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
109 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
110 >;
111 };
112
113 pinctrl_hummingboard_spdif: hummingboard-spdif {
114 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
115 };
116
117 pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
118 fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
119 };
120
121 pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
122 fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
123 };
124
125 pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
126 fsl,pins = <
127 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
128 >;
129 };
130
131 pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
132 fsl,pins = <
133 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
134 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
135 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
136 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
137 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
138 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
139 >;
140 };
141 };
142};
143
144&spdif {
145 status = "okay";
146};
147
148&usbh1 {
149 vbus-supply = <&reg_usbh1_vbus>;
150 status = "okay";
151};
152
153&usbotg {
154 vbus-supply = <&reg_usbotg_vbus>;
155 status = "okay";
156};
157
158&usdhc2 {
159 pinctrl-names = "default";
160 pinctrl-0 = <
161 &pinctrl_hummingboard_usdhc2_aux
162 &pinctrl_hummingboard_usdhc2
163 >;
164 vmmc-supply = <&reg_3p3v>;
165 cd-gpios = <&gpio1 4 0>;
166 status = "okay";
167};
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
new file mode 100644
index 000000000000..a3cb2fff8f61
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -0,0 +1,62 @@
1/*
2 * Copyright (C) 2013,2014 Russell King
3 *
4 * This describes the hookup for an AR8035 to the iMX6 on the SolidRun
5 * MicroSOM.
6 */
7&fec {
8 pinctrl-names = "default";
9 pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
10 phy-mode = "rgmii";
11 phy-reset-duration = <2>;
12 phy-reset-gpios = <&gpio4 15 0>;
13 status = "okay";
14};
15
16&iomuxc {
17 enet {
18 pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
19 fsl,pins = <
20 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
21 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
22 /* AR8035 reset */
23 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
24 /* AR8035 interrupt */
25 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x80000000
26 /* GPIO16 -> AR8035 25MHz */
27 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
28 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
29 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
30 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
31 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
32 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
33 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
34 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
35 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
36 /* AR8035 pin strapping: IO voltage: pull up */
37 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
38 /* AR8035 pin strapping: PHYADDR#0: pull down */
39 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
40 /* AR8035 pin strapping: PHYADDR#1: pull down */
41 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0
42 /* AR8035 pin strapping: MODE#1: pull up */
43 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
44 /* AR8035 pin strapping: MODE#3: pull up */
45 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
46 /* AR8035 pin strapping: MODE#0: pull down */
47 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
48
49 /*
50 * As the RMII pins are also connected to RGMII
51 * so that an AR8030 can be placed, set these
52 * to high-z with the same pulls as above.
53 * Use the GPIO settings to avoid changing the
54 * input select registers.
55 */
56 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000
57 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000
58 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000
59 >;
60 };
61 };
62};
diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
new file mode 100644
index 000000000000..d729d0b15f25
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
@@ -0,0 +1,33 @@
1/*
2 * Copyright (C) 2013,2014 Russell King
3 */
4
5&iomuxc {
6 microsom {
7 pinctrl_microsom_uart1: microsom-uart1 {
8 fsl,pins = <
9 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
10 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
11 >;
12 };
13
14 pinctrl_microsom_usbotg: microsom-usbotg {
15 /*
16 * Similar to pinctrl_usbotg_2, but we want it
17 * pulled down for a fixed host connection.
18 */
19 fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
20 };
21 };
22};
23
24&uart1 {
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_microsom_uart1>;
27 status = "okay";
28};
29
30&usbotg {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_microsom_usbotg>;
33};
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index d0cfb225ec9a..cb6fa3d61243 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -103,6 +103,39 @@ static int ar8031_phy_fixup(struct phy_device *dev)
103 103
104#define PHY_ID_AR8031 0x004dd074 104#define PHY_ID_AR8031 0x004dd074
105 105
106static int ar8035_phy_fixup(struct phy_device *dev)
107{
108 u16 val;
109
110 /* Ar803x phy SmartEEE feature cause link status generates glitch,
111 * which cause ethernet link down/up issue, so disable SmartEEE
112 */
113 phy_write(dev, 0xd, 0x3);
114 phy_write(dev, 0xe, 0x805d);
115 phy_write(dev, 0xd, 0x4003);
116
117 val = phy_read(dev, 0xe);
118 phy_write(dev, 0xe, val & ~(1 << 8));
119
120 /*
121 * Enable 125MHz clock from CLK_25M on the AR8031. This
122 * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
123 * Also, introduce a tx clock delay.
124 *
125 * This is the same as is the AR8031 fixup.
126 */
127 ar8031_phy_fixup(dev);
128
129 /*check phy power*/
130 val = phy_read(dev, 0x0);
131 if (val & BMCR_PDOWN)
132 phy_write(dev, 0x0, val & ~BMCR_PDOWN);
133
134 return 0;
135}
136
137#define PHY_ID_AR8035 0x004dd072
138
106static void __init imx6q_enet_phy_init(void) 139static void __init imx6q_enet_phy_init(void)
107{ 140{
108 if (IS_BUILTIN(CONFIG_PHYLIB)) { 141 if (IS_BUILTIN(CONFIG_PHYLIB)) {
@@ -112,6 +145,8 @@ static void __init imx6q_enet_phy_init(void)
112 ksz9031rn_phy_fixup); 145 ksz9031rn_phy_fixup);
113 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, 146 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
114 ar8031_phy_fixup); 147 ar8031_phy_fixup);
148 phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
149 ar8035_phy_fixup);
115 } 150 }
116} 151}
117 152
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 19:31:55 -0500