diff options
author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2013-03-27 03:55:07 -0400 |
---|---|---|
committer | Simon Horman <horms+renesas@verge.net.au> | 2013-04-01 22:02:15 -0400 |
commit | 1f7ccd88717d993c5189280034f1d3b6b5af9693 (patch) | |
tree | 2843743ca885928cb8deee41464eb73b5fa5adb3 /arch/arm | |
parent | fe7aa82d62d13d97c9a786707c467357cb8bddc3 (diff) |
ARM: shmobile: sh73a0: remove DIV4_ZT* clocks
DIV4_ZT* clocks are for debugging and trace bus clock.
It is not necessary to control it from Linux/Software.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-shmobile/clock-sh73a0.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index a57ec151674e..26a580324105 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c | |||
@@ -269,7 +269,7 @@ static struct clk_div4_table div4_table = { | |||
269 | }; | 269 | }; |
270 | 270 | ||
271 | enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, | 271 | enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, |
272 | DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR }; | 272 | DIV4_Z, DIV4_ZX, DIV4_HP, DIV4_NR }; |
273 | 273 | ||
274 | #define DIV4(_reg, _bit, _mask, _flags) \ | 274 | #define DIV4(_reg, _bit, _mask, _flags) \ |
275 | SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags) | 275 | SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags) |
@@ -282,8 +282,6 @@ static struct clk div4_clks[DIV4_NR] = { | |||
282 | [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), | 282 | [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), |
283 | [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), | 283 | [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), |
284 | [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0), | 284 | [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0), |
285 | [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0), | ||
286 | [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0), | ||
287 | [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), | 285 | [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), |
288 | [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0), | 286 | [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0), |
289 | }; | 287 | }; |