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authorTomi Valkeinen <tomi.valkeinen@ti.com>2014-02-13 04:15:06 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2014-03-19 03:31:48 -0400
commit1d3361f6229e210f9924f74510708f2e2c08c109 (patch)
tree9c7c1f2dfa4efc7a58c5f6200c6ab858c1ef5028 /arch/arm
parentc368dbe2de0a7fec2488eb7e4dcccfe25714ed2b (diff)
ARM: dts: set 'ti,set-rate-parent' for dpll4_m4 path
Set 'ti,set-rate-parent' property for clocks in the dpll4_m4 clock path, which is used for DSS functional clock. This fixes DSS driver's clock rate configuration, which needs the rate to be propagated properly to the divider node (dpll4_m4_ck). Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Tested-by: Christoph Fritz <chf.fritz@googlemail.com> Tested-by: Marek Belisko <marek@goldelico.com> Acked-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/omap3xxx-clocks.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index df3c699a1893..12be2b35dae9 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -429,6 +429,7 @@
429 clocks = <&dpll4_m4_ck>; 429 clocks = <&dpll4_m4_ck>;
430 ti,clock-mult = <2>; 430 ti,clock-mult = <2>;
431 ti,clock-div = <1>; 431 ti,clock-div = <1>;
432 ti,set-rate-parent;
432 }; 433 };
433 434
434 dpll4_m4x2_ck: dpll4_m4x2_ck { 435 dpll4_m4x2_ck: dpll4_m4x2_ck {
@@ -438,6 +439,7 @@
438 ti,bit-shift = <0x1d>; 439 ti,bit-shift = <0x1d>;
439 reg = <0x0d00>; 440 reg = <0x0d00>;
440 ti,set-bit-to-disable; 441 ti,set-bit-to-disable;
442 ti,set-rate-parent;
441 }; 443 };
442 444
443 dpll4_m5_ck: dpll4_m5_ck { 445 dpll4_m5_ck: dpll4_m5_ck {