diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2011-10-12 08:34:11 -0400 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-12 08:34:32 -0400 |
| commit | 18c55cd466c12ede49638822d3a71eb1f24e0d25 (patch) | |
| tree | 232cb75ed5f6467f1efe8e1b07addea007fc68ef /arch/arm | |
| parent | c034b184597d93ad7749aca3e8bd1c2105104f07 (diff) | |
ARM: SAMSUNG: Add adc registers for S3C2443/S3C2416
The adc blocks of the S3C2443 and S3C2416 define some
additional registers and bits.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/regs-adc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h index 035e8c38d69c..70612100120f 100644 --- a/arch/arm/plat-samsung/include/plat/regs-adc.h +++ b/arch/arm/plat-samsung/include/plat/regs-adc.h | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) | 20 | #define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) |
| 21 | #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) | 21 | #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) |
| 22 | #define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14) | 22 | #define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14) |
| 23 | #define S3C2443_ADCMUX S3C2410_ADCREG(0x18) | ||
| 23 | #define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18) | 24 | #define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18) |
| 24 | #define S5P_ADCMUX S3C2410_ADCREG(0x1C) | 25 | #define S5P_ADCMUX S3C2410_ADCREG(0x1C) |
| 25 | #define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20) | 26 | #define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20) |
| @@ -33,6 +34,7 @@ | |||
| 33 | #define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) | 34 | #define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) |
| 34 | #define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) | 35 | #define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) |
| 35 | #define S3C2410_ADCCON_MUXMASK (0x7<<3) | 36 | #define S3C2410_ADCCON_MUXMASK (0x7<<3) |
| 37 | #define S3C2416_ADCCON_RESSEL (1 << 3) | ||
| 36 | #define S3C2410_ADCCON_STDBM (1<<2) | 38 | #define S3C2410_ADCCON_STDBM (1<<2) |
| 37 | #define S3C2410_ADCCON_READ_START (1<<1) | 39 | #define S3C2410_ADCCON_READ_START (1<<1) |
| 38 | #define S3C2410_ADCCON_ENABLE_START (1<<0) | 40 | #define S3C2410_ADCCON_ENABLE_START (1<<0) |
| @@ -40,6 +42,7 @@ | |||
| 40 | 42 | ||
| 41 | 43 | ||
| 42 | /* ADCTSC Register Bits */ | 44 | /* ADCTSC Register Bits */ |
| 45 | #define S3C2443_ADCTSC_UD_SEN (1 << 8) | ||
| 43 | #define S3C2410_ADCTSC_YM_SEN (1<<7) | 46 | #define S3C2410_ADCTSC_YM_SEN (1<<7) |
| 44 | #define S3C2410_ADCTSC_YP_SEN (1<<6) | 47 | #define S3C2410_ADCTSC_YP_SEN (1<<6) |
| 45 | #define S3C2410_ADCTSC_XM_SEN (1<<5) | 48 | #define S3C2410_ADCTSC_XM_SEN (1<<5) |