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authorSrinivas Kandagatla <srinivas.kandagatla@st.com>2013-06-25 07:15:23 -0400
committerOlof Johansson <olof@lixom.net>2013-06-25 16:26:58 -0400
commit15969b457734feb46cc813745b039cf4ae9089ff (patch)
tree6810ed1da06abedadb9189798660643a4b76d77c /arch/arm
parent65ebcc1158891c8c0abef726d59a7840454ad25d (diff)
ARM: sti: Add STiH416 SOC support
The STiH416 is advanced HD AVC processor with 3D graphics acceleration and 1.2-GHz ARM Cortex-A9 SMP CPU. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Stuart Menefy <stuart.menefy@st.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/stih416-clock.dtsi41
-rw-r--r--arch/arm/boot/dts/stih416-pinctrl.dtsi295
-rw-r--r--arch/arm/boot/dts/stih416.dtsi96
-rw-r--r--arch/arm/mach-sti/Kconfig9
-rw-r--r--arch/arm/mach-sti/board-dt.c3
5 files changed, 443 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
new file mode 100644
index 000000000000..7026bf1158d8
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics R&D Limited
3 * <stlinux-devel@stlinux.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9/ {
10 clocks {
11 /*
12 * Fixed 30MHz oscillator inputs to SoC
13 */
14 CLK_SYSIN: CLK_SYSIN {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <30000000>;
18 clock-output-names = "CLK_SYSIN";
19 };
20
21 /*
22 * ARM Peripheral clock for timers
23 */
24 arm_periph_clk: arm_periph_clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-frequency = <600000000>;
28 };
29
30 /*
31 * Bootloader initialized system infrastructure clock for
32 * serial devices.
33 */
34 CLK_S_ICN_REG_0: clockgenA0@4 {
35 #clock-cells = <0>;
36 compatible = "fixed-clock";
37 clock-frequency = <100000000>;
38 clock-output-names = "CLK_S_ICN_REG_0";
39 };
40 };
41};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
new file mode 100644
index 000000000000..957b21a71b4b
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -0,0 +1,295 @@
1
2/*
3 * Copyright (C) 2013 STMicroelectronics Limited.
4 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 */
10#include "st-pincfg.h"
11/ {
12
13 aliases {
14 gpio0 = &PIO0;
15 gpio1 = &PIO1;
16 gpio2 = &PIO2;
17 gpio3 = &PIO3;
18 gpio4 = &PIO4;
19 gpio5 = &PIO40;
20 gpio6 = &PIO5;
21 gpio7 = &PIO6;
22 gpio8 = &PIO7;
23 gpio9 = &PIO8;
24 gpio10 = &PIO9;
25 gpio11 = &PIO10;
26 gpio12 = &PIO11;
27 gpio13 = &PIO12;
28 gpio14 = &PIO30;
29 gpio15 = &PIO31;
30 gpio16 = &PIO13;
31 gpio17 = &PIO14;
32 gpio18 = &PIO15;
33 gpio19 = &PIO16;
34 gpio20 = &PIO17;
35 gpio21 = &PIO18;
36 gpio22 = &PIO100;
37 gpio23 = &PIO101;
38 gpio24 = &PIO102;
39 gpio25 = &PIO103;
40 gpio26 = &PIO104;
41 gpio27 = &PIO105;
42 gpio28 = &PIO106;
43 gpio29 = &PIO107;
44 };
45
46 soc {
47 pin-controller-sbc {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "st,stih416-sbc-pinctrl";
51 st,syscfg = <&syscfg_sbc>;
52 ranges = <0 0xfe610000 0x6000>;
53
54 PIO0: gpio@fe610000 {
55 gpio-controller;
56 #gpio-cells = <1>;
57 reg = <0 0x100>;
58 st,bank-name = "PIO0";
59 };
60 PIO1: gpio@fe611000 {
61 gpio-controller;
62 #gpio-cells = <1>;
63 reg = <0x1000 0x100>;
64 st,bank-name = "PIO1";
65 };
66 PIO2: gpio@fe612000 {
67 gpio-controller;
68 #gpio-cells = <1>;
69 reg = <0x2000 0x100>;
70 st,bank-name = "PIO2";
71 };
72 PIO3: gpio@fe613000 {
73 gpio-controller;
74 #gpio-cells = <1>;
75 reg = <0x3000 0x100>;
76 st,bank-name = "PIO3";
77 };
78 PIO4: gpio@fe614000 {
79 gpio-controller;
80 #gpio-cells = <1>;
81 reg = <0x4000 0x100>;
82 st,bank-name = "PIO4";
83 };
84 PIO40: gpio@fe615000 {
85 gpio-controller;
86 #gpio-cells = <1>;
87 reg = <0x5000 0x100>;
88 st,bank-name = "PIO40";
89 st,retime-pin-mask = <0x7f>;
90 };
91
92 sbc_serial1 {
93 pinctrl_sbc_serial1: sbc_serial1 {
94 st,pins {
95 tx = <&PIO2 6 ALT3 OUT>;
96 rx = <&PIO2 7 ALT3 IN>;
97 };
98 };
99 };
100 };
101
102 pin-controller-front {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "st,stih416-front-pinctrl";
106 st,syscfg = <&syscfg_front>;
107 ranges = <0 0xfee00000 0x10000>;
108
109 PIO5: gpio@fee00000 {
110 gpio-controller;
111 #gpio-cells = <1>;
112 reg = <0 0x100>;
113 st,bank-name = "PIO5";
114 };
115 PIO6: gpio@fee01000 {
116 gpio-controller;
117 #gpio-cells = <1>;
118 reg = <0x1000 0x100>;
119 st,bank-name = "PIO6";
120 };
121 PIO7: gpio@fee02000 {
122 gpio-controller;
123 #gpio-cells = <1>;
124 reg = <0x2000 0x100>;
125 st,bank-name = "PIO7";
126 };
127 PIO8: gpio@fee03000 {
128 gpio-controller;
129 #gpio-cells = <1>;
130 reg = <0x3000 0x100>;
131 st,bank-name = "PIO8";
132 };
133 PIO9: gpio@fee04000 {
134 gpio-controller;
135 #gpio-cells = <1>;
136 reg = <0x4000 0x100>;
137 st,bank-name = "PIO9";
138 };
139 PIO10: gpio@fee05000 {
140 gpio-controller;
141 #gpio-cells = <1>;
142 reg = <0x5000 0x100>;
143 st,bank-name = "PIO10";
144 };
145 PIO11: gpio@fee06000 {
146 gpio-controller;
147 #gpio-cells = <1>;
148 reg = <0x6000 0x100>;
149 st,bank-name = "PIO11";
150 };
151 PIO12: gpio@fee07000 {
152 gpio-controller;
153 #gpio-cells = <1>;
154 reg = <0x7000 0x100>;
155 st,bank-name = "PIO12";
156 };
157 PIO30: gpio@fee08000 {
158 gpio-controller;
159 #gpio-cells = <1>;
160 reg = <0x8000 0x100>;
161 st,bank-name = "PIO30";
162 };
163 PIO31: gpio@fee09000 {
164 gpio-controller;
165 #gpio-cells = <1>;
166 reg = <0x9000 0x100>;
167 st,bank-name = "PIO31";
168 };
169 };
170
171 pin-controller-rear {
172 #address-cells = <1>;
173 #size-cells = <1>;
174 compatible = "st,stih416-rear-pinctrl";
175 st,syscfg = <&syscfg_rear>;
176 ranges = <0 0xfe820000 0x6000>;
177
178 PIO13: gpio@fe820000 {
179 gpio-controller;
180 #gpio-cells = <1>;
181 reg = <0 0x100>;
182 st,bank-name = "PIO13";
183 };
184 PIO14: gpio@fe821000 {
185 gpio-controller;
186 #gpio-cells = <1>;
187 reg = <0x1000 0x100>;
188 st,bank-name = "PIO14";
189 };
190 PIO15: gpio@fe822000 {
191 gpio-controller;
192 #gpio-cells = <1>;
193 reg = <0x2000 0x100>;
194 st,bank-name = "PIO15";
195 };
196 PIO16: gpio@fe823000 {
197 gpio-controller;
198 #gpio-cells = <1>;
199 reg = <0x3000 0x100>;
200 st,bank-name = "PIO16";
201 };
202 PIO17: gpio@fe824000 {
203 gpio-controller;
204 #gpio-cells = <1>;
205 reg = <0x4000 0x100>;
206 st,bank-name = "PIO17";
207 };
208 PIO18: gpio@fe825000 {
209 gpio-controller;
210 #gpio-cells = <1>;
211 reg = <0x5000 0x100>;
212 st,bank-name = "PIO18";
213 st,retime-pin-mask = <0xf>;
214 };
215
216 serial2 {
217 pinctrl_serial2: serial2-0 {
218 st,pins {
219 tx = <&PIO17 4 ALT2 OUT>;
220 rx = <&PIO17 5 ALT2 IN>;
221 output-enable = <&PIO11 3 ALT2 OUT>;
222 };
223 };
224 };
225 };
226
227 pin-controller-fvdp-fe {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 compatible = "st,stih416-fvdp-fe-pinctrl";
231 st,syscfg = <&syscfg_fvdp_fe>;
232 ranges = <0 0xfd6b0000 0x3000>;
233
234 PIO100: gpio@fd6b0000 {
235 gpio-controller;
236 #gpio-cells = <1>;
237 reg = <0 0x100>;
238 st,bank-name = "PIO100";
239 };
240 PIO101: gpio@fd6b1000 {
241 gpio-controller;
242 #gpio-cells = <1>;
243 reg = <0x1000 0x100>;
244 st,bank-name = "PIO101";
245 };
246 PIO102: gpio@fd6b2000 {
247 gpio-controller;
248 #gpio-cells = <1>;
249 reg = <0x2000 0x100>;
250 st,bank-name = "PIO102";
251 };
252 };
253
254 pin-controller-fvdp-lite {
255 #address-cells = <1>;
256 #size-cells = <1>;
257 compatible = "st,stih416-fvdp-lite-pinctrl";
258 st,syscfg = <&syscfg_fvdp_lite>;
259 ranges = <0 0xfd330000 0x5000>;
260
261 PIO103: gpio@fd330000 {
262 gpio-controller;
263 #gpio-cells = <1>;
264 reg = <0 0x100>;
265 st,bank-name = "PIO103";
266 };
267 PIO104: gpio@fd331000 {
268 gpio-controller;
269 #gpio-cells = <1>;
270 reg = <0x1000 0x100>;
271 st,bank-name = "PIO104";
272 };
273 PIO105: gpio@fd332000 {
274 gpio-controller;
275 #gpio-cells = <1>;
276 reg = <0x2000 0x100>;
277 st,bank-name = "PIO105";
278 };
279 PIO106: gpio@fd333000 {
280 gpio-controller;
281 #gpio-cells = <1>;
282 reg = <0x3000 0x100>;
283 st,bank-name = "PIO106";
284 };
285
286 PIO107: gpio@fd334000 {
287 gpio-controller;
288 #gpio-cells = <1>;
289 reg = <0x4000 0x100>;
290 st,bank-name = "PIO107";
291 st,retime-pin-mask = <0xf>;
292 };
293 };
294 };
295};
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
new file mode 100644
index 000000000000..3cecd9689a49
--- /dev/null
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -0,0 +1,96 @@
1/*
2 * Copyright (C) 2012 STMicroelectronics Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih41x.dtsi"
10#include "stih416-clock.dtsi"
11#include "stih416-pinctrl.dtsi"
12/ {
13 L2: cache-controller {
14 compatible = "arm,pl310-cache";
15 reg = <0xfffe2000 0x1000>;
16 arm,data-latency = <3 3 3>;
17 arm,tag-latency = <2 2 2>;
18 cache-unified;
19 cache-level = <2>;
20 };
21
22 soc {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 interrupt-parent = <&intc>;
26 ranges;
27 compatible = "simple-bus";
28
29 syscfg_sbc:sbc-syscfg@fe600000{
30 compatible = "st,stih416-sbc-syscfg", "syscon";
31 reg = <0xfe600000 0x1000>;
32 };
33
34 syscfg_front:front-syscfg@fee10000{
35 compatible = "st,stih416-front-syscfg", "syscon";
36 reg = <0xfee10000 0x1000>;
37 };
38
39 syscfg_rear:rear-syscfg@fe830000{
40 compatible = "st,stih416-rear-syscfg", "syscon";
41 reg = <0xfe830000 0x1000>;
42 };
43
44 /* MPE */
45 syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{
46 compatible = "st,stih416-fvdp-fe-syscfg", "syscon";
47 reg = <0xfddf0000 0x1000>;
48 };
49
50 syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{
51 compatible = "st,stih416-fvdp-lite-syscfg", "syscon";
52 reg = <0xfd6a0000 0x1000>;
53 };
54
55 syscfg_cpu:cpu-syscfg@fdde0000{
56 compatible = "st,stih416-cpu-syscfg", "syscon";
57 reg = <0xfdde0000 0x1000>;
58 };
59
60 syscfg_compo:compo-syscfg@fd320000{
61 compatible = "st,stih416-compo-syscfg", "syscon";
62 reg = <0xfd320000 0x1000>;
63 };
64
65 syscfg_transport:transport-syscfg@fd690000{
66 compatible = "st,stih416-transport-syscfg", "syscon";
67 reg = <0xfd690000 0x1000>;
68 };
69
70 syscfg_lpm:lpm-syscfg@fe4b5100{
71 compatible = "st,stih416-lpm-syscfg", "syscon";
72 reg = <0xfe4b5100 0x8>;
73 };
74
75 serial2: serial@fed32000{
76 compatible = "st,asc";
77 status = "disabled";
78 reg = <0xfed32000 0x2c>;
79 interrupts = <0 197 0>;
80 clocks = <&CLK_S_ICN_REG_0>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_serial2>;
83 };
84
85 /* SBC_UART1 */
86 sbc_serial1: serial@fe531000 {
87 compatible = "st,asc";
88 status = "disabled";
89 reg = <0xfe531000 0x2c>;
90 interrupts = <0 210 0>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_sbc_serial1>;
93 clocks = <&CLK_SYSIN>;
94 };
95 };
96};
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index 23405b584adb..d04e3bfe1918 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -33,4 +33,13 @@ config SOC_STIH415
33 and other digital audio/video applications using Flattned Device 33 and other digital audio/video applications using Flattned Device
34 Trees. 34 Trees.
35 35
36config SOC_STIH416
37 bool "STiH416 STMicroelectronics Consumer Electronics family"
38 default y
39 help
40 This enables support for STMicroelectronics Digital Consumer
41 Electronics family StiH416 parts, primarily targetted at set-top-box
42 and other digital audio/video applications using Flattened Device
43 Trees.
44
36endif 45endif
diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
index 3faf64221d45..8fe6f0c46480 100644
--- a/arch/arm/mach-sti/board-dt.c
+++ b/arch/arm/mach-sti/board-dt.c
@@ -37,10 +37,11 @@ static void __init stih41x_timer_init(void)
37 37
38static const char *stih41x_dt_match[] __initdata = { 38static const char *stih41x_dt_match[] __initdata = {
39 "st,stih415", 39 "st,stih415",
40 "st,stih416",
40 NULL 41 NULL
41}; 42};
42 43
43DT_MACHINE_START(STM, "STiH415 SoC with Flattened Device Tree") 44DT_MACHINE_START(STM, "STiH415/416 SoC with Flattened Device Tree")
44 .init_time = stih41x_timer_init, 45 .init_time = stih41x_timer_init,
45 .smp = smp_ops(sti_smp_ops), 46 .smp = smp_ops(sti_smp_ops),
46 .dt_compat = stih41x_dt_match, 47 .dt_compat = stih41x_dt_match,
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-15 14:35:35 -0400