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authorMing Lei <ming.lei@canonical.com>2011-10-24 10:45:53 -0400
committerWill Deacon <will.deacon@arm.com>2011-12-02 10:16:33 -0500
commit14eec97ff4635977b026a53b27915ab0dec51e94 (patch)
treec48b6b64694af27d6d94d141980b734d89a5c01a /arch/arm
parent5611cc4572e889b62a7b4c72a413536bf6a9c416 (diff)
arm: introduce cross trigger interface helpers
OMAP4 uses cross trigger interface(CTI) to route performance monitor irq to GIC, so introduce cti helpers to make access for cti easily. Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Ming Lei <ming.lei@canonical.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/include/asm/cti.h179
1 files changed, 179 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
new file mode 100644
index 000000000000..a0ada3ea4358
--- /dev/null
+++ b/arch/arm/include/asm/cti.h
@@ -0,0 +1,179 @@
1#ifndef __ASMARM_CTI_H
2#define __ASMARM_CTI_H
3
4#include <asm/io.h>
5
6/* The registers' definition is from section 3.2 of
7 * Embedded Cross Trigger Revision: r0p0
8 */
9#define CTICONTROL 0x000
10#define CTISTATUS 0x004
11#define CTILOCK 0x008
12#define CTIPROTECTION 0x00C
13#define CTIINTACK 0x010
14#define CTIAPPSET 0x014
15#define CTIAPPCLEAR 0x018
16#define CTIAPPPULSE 0x01c
17#define CTIINEN 0x020
18#define CTIOUTEN 0x0A0
19#define CTITRIGINSTATUS 0x130
20#define CTITRIGOUTSTATUS 0x134
21#define CTICHINSTATUS 0x138
22#define CTICHOUTSTATUS 0x13c
23#define CTIPERIPHID0 0xFE0
24#define CTIPERIPHID1 0xFE4
25#define CTIPERIPHID2 0xFE8
26#define CTIPERIPHID3 0xFEC
27#define CTIPCELLID0 0xFF0
28#define CTIPCELLID1 0xFF4
29#define CTIPCELLID2 0xFF8
30#define CTIPCELLID3 0xFFC
31
32/* The below are from section 3.6.4 of
33 * CoreSight v1.0 Architecture Specification
34 */
35#define LOCKACCESS 0xFB0
36#define LOCKSTATUS 0xFB4
37
38/* write this value to LOCKACCESS will unlock the module, and
39 * other value will lock the module
40 */
41#define LOCKCODE 0xC5ACCE55
42
43/**
44 * struct cti - cross trigger interface struct
45 * @base: mapped virtual address for the cti base
46 * @irq: irq number for the cti
47 * @trig_out_for_irq: triger out number which will cause
48 * the @irq happen
49 *
50 * cti struct used to operate cti registers.
51 */
52struct cti {
53 void __iomem *base;
54 int irq;
55 int trig_out_for_irq;
56};
57
58/**
59 * cti_init - initialize the cti instance
60 * @cti: cti instance
61 * @base: mapped virtual address for the cti base
62 * @irq: irq number for the cti
63 * @trig_out: triger out number which will cause
64 * the @irq happen
65 *
66 * called by machine code to pass the board dependent
67 * @base, @irq and @trig_out to cti.
68 */
69static inline void cti_init(struct cti *cti,
70 void __iomem *base, int irq, int trig_out)
71{
72 cti->base = base;
73 cti->irq = irq;
74 cti->trig_out_for_irq = trig_out;
75}
76
77/**
78 * cti_map_trigger - use the @chan to map @trig_in to @trig_out
79 * @cti: cti instance
80 * @trig_in: trigger in number
81 * @trig_out: trigger out number
82 * @channel: channel number
83 *
84 * This function maps one trigger in of @trig_in to one trigger
85 * out of @trig_out using the channel @chan.
86 */
87static inline void cti_map_trigger(struct cti *cti,
88 int trig_in, int trig_out, int chan)
89{
90 void __iomem *base = cti->base;
91 unsigned long val;
92
93 val = __raw_readl(base + CTIINEN + trig_in * 4);
94 val |= BIT(chan);
95 __raw_writel(val, base + CTIINEN + trig_in * 4);
96
97 val = __raw_readl(base + CTIOUTEN + trig_out * 4);
98 val |= BIT(chan);
99 __raw_writel(val, base + CTIOUTEN + trig_out * 4);
100}
101
102/**
103 * cti_enable - enable the cti module
104 * @cti: cti instance
105 *
106 * enable the cti module
107 */
108static inline void cti_enable(struct cti *cti)
109{
110 __raw_writel(0x1, cti->base + CTICONTROL);
111}
112
113/**
114 * cti_disable - disable the cti module
115 * @cti: cti instance
116 *
117 * enable the cti module
118 */
119static inline void cti_disable(struct cti *cti)
120{
121 __raw_writel(0, cti->base + CTICONTROL);
122}
123
124/**
125 * cti_irq_ack - clear the cti irq
126 * @cti: cti instance
127 *
128 * clear the cti irq
129 */
130static inline void cti_irq_ack(struct cti *cti)
131{
132 void __iomem *base = cti->base;
133 unsigned long val;
134
135 val = __raw_readl(base + CTIINTACK);
136 val |= BIT(cti->trig_out_for_irq);
137 __raw_writel(val, base + CTIINTACK);
138}
139
140/**
141 * cti_unlock - unlock cti module
142 * @cti: cti instance
143 *
144 * unlock the cti module, or else any writes to the cti
145 * module is not allowed.
146 */
147static inline void cti_unlock(struct cti *cti)
148{
149 void __iomem *base = cti->base;
150 unsigned long val;
151
152 val = __raw_readl(base + LOCKSTATUS);
153
154 if (val & 1) {
155 val = LOCKCODE;
156 __raw_writel(val, base + LOCKACCESS);
157 }
158}
159
160/**
161 * cti_lock - lock cti module
162 * @cti: cti instance
163 *
164 * lock the cti module, so any writes to the cti
165 * module will be not allowed.
166 */
167static inline void cti_lock(struct cti *cti)
168{
169 void __iomem *base = cti->base;
170 unsigned long val;
171
172 val = __raw_readl(base + LOCKSTATUS);
173
174 if (!(val & 1)) {
175 val = ~LOCKCODE;
176 __raw_writel(val, base + LOCKACCESS);
177 }
178}
179#endif