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authorTony Prisk <linux@prisktech.co.nz>2013-01-17 21:05:31 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-01-17 21:54:32 -0500
commit12faa35ae5cbfbd0d90e2103688e87ceb46c5886 (patch)
tree483496c3aab85cb54e0d8d19cba2f814718aa44d /arch/arm
parent962963e4ee23bc7518dfee754de5f20d35de71d9 (diff)
serial: vt8500: UART uses gated clock rather than 24Mhz reference
UART modules on Wondermedia SoCs are connected via a gated clock source, rather than directly to the 24Mhz reference clock. While uboot enables UART0 for debugging, other UART ports are unavailable until the clock is enabled. This patch checks that a valid clock is actually passed from devicetree, enables the clock in probe. This change removes the fallback when a clock was not specified as it doesn't apply any longer (and would only work if the UART clock was already enabled). DTSI files are updated for VT8500, WM8505 and WM8650. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/vt8500.dtsi40
-rw-r--r--arch/arm/boot/dts/wm8505.dtsi60
-rw-r--r--arch/arm/boot/dts/wm8650.dtsi20
3 files changed, 108 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index d8645e990b21..cf31ced46602 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -45,6 +45,38 @@
45 compatible = "fixed-clock"; 45 compatible = "fixed-clock";
46 clock-frequency = <24000000>; 46 clock-frequency = <24000000>;
47 }; 47 };
48
49 clkuart0: uart0 {
50 #clock-cells = <0>;
51 compatible = "via,vt8500-device-clock";
52 clocks = <&ref24>;
53 enable-reg = <0x250>;
54 enable-bit = <1>;
55 };
56
57 clkuart1: uart1 {
58 #clock-cells = <0>;
59 compatible = "via,vt8500-device-clock";
60 clocks = <&ref24>;
61 enable-reg = <0x250>;
62 enable-bit = <2>;
63 };
64
65 clkuart2: uart2 {
66 #clock-cells = <0>;
67 compatible = "via,vt8500-device-clock";
68 clocks = <&ref24>;
69 enable-reg = <0x250>;
70 enable-bit = <3>;
71 };
72
73 clkuart3: uart3 {
74 #clock-cells = <0>;
75 compatible = "via,vt8500-device-clock";
76 clocks = <&ref24>;
77 enable-reg = <0x250>;
78 enable-bit = <4>;
79 };
48 }; 80 };
49 }; 81 };
50 82
@@ -83,28 +115,28 @@
83 compatible = "via,vt8500-uart"; 115 compatible = "via,vt8500-uart";
84 reg = <0xd8200000 0x1040>; 116 reg = <0xd8200000 0x1040>;
85 interrupts = <32>; 117 interrupts = <32>;
86 clocks = <&ref24>; 118 clocks = <&clkuart0>;
87 }; 119 };
88 120
89 uart@d82b0000 { 121 uart@d82b0000 {
90 compatible = "via,vt8500-uart"; 122 compatible = "via,vt8500-uart";
91 reg = <0xd82b0000 0x1040>; 123 reg = <0xd82b0000 0x1040>;
92 interrupts = <33>; 124 interrupts = <33>;
93 clocks = <&ref24>; 125 clocks = <&clkuart1>;
94 }; 126 };
95 127
96 uart@d8210000 { 128 uart@d8210000 {
97 compatible = "via,vt8500-uart"; 129 compatible = "via,vt8500-uart";
98 reg = <0xd8210000 0x1040>; 130 reg = <0xd8210000 0x1040>;
99 interrupts = <47>; 131 interrupts = <47>;
100 clocks = <&ref24>; 132 clocks = <&clkuart2>;
101 }; 133 };
102 134
103 uart@d82c0000 { 135 uart@d82c0000 {
104 compatible = "via,vt8500-uart"; 136 compatible = "via,vt8500-uart";
105 reg = <0xd82c0000 0x1040>; 137 reg = <0xd82c0000 0x1040>;
106 interrupts = <50>; 138 interrupts = <50>;
107 clocks = <&ref24>; 139 clocks = <&clkuart3>;
108 }; 140 };
109 141
110 rtc@d8100000 { 142 rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index 330f833ac3b0..e74a1c0fb9a2 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -59,6 +59,54 @@
59 compatible = "fixed-clock"; 59 compatible = "fixed-clock";
60 clock-frequency = <24000000>; 60 clock-frequency = <24000000>;
61 }; 61 };
62
63 clkuart0: uart0 {
64 #clock-cells = <0>;
65 compatible = "via,vt8500-device-clock";
66 clocks = <&ref24>;
67 enable-reg = <0x250>;
68 enable-bit = <1>;
69 };
70
71 clkuart1: uart1 {
72 #clock-cells = <0>;
73 compatible = "via,vt8500-device-clock";
74 clocks = <&ref24>;
75 enable-reg = <0x250>;
76 enable-bit = <2>;
77 };
78
79 clkuart2: uart2 {
80 #clock-cells = <0>;
81 compatible = "via,vt8500-device-clock";
82 clocks = <&ref24>;
83 enable-reg = <0x250>;
84 enable-bit = <3>;
85 };
86
87 clkuart3: uart3 {
88 #clock-cells = <0>;
89 compatible = "via,vt8500-device-clock";
90 clocks = <&ref24>;
91 enable-reg = <0x250>;
92 enable-bit = <4>;
93 };
94
95 clkuart4: uart4 {
96 #clock-cells = <0>;
97 compatible = "via,vt8500-device-clock";
98 clocks = <&ref24>;
99 enable-reg = <0x250>;
100 enable-bit = <22>;
101 };
102
103 clkuart5: uart5 {
104 #clock-cells = <0>;
105 compatible = "via,vt8500-device-clock";
106 clocks = <&ref24>;
107 enable-reg = <0x250>;
108 enable-bit = <23>;
109 };
62 }; 110 };
63 }; 111 };
64 112
@@ -96,42 +144,42 @@
96 compatible = "via,vt8500-uart"; 144 compatible = "via,vt8500-uart";
97 reg = <0xd8200000 0x1040>; 145 reg = <0xd8200000 0x1040>;
98 interrupts = <32>; 146 interrupts = <32>;
99 clocks = <&ref24>; 147 clocks = <&clkuart0>;
100 }; 148 };
101 149
102 uart@d82b0000 { 150 uart@d82b0000 {
103 compatible = "via,vt8500-uart"; 151 compatible = "via,vt8500-uart";
104 reg = <0xd82b0000 0x1040>; 152 reg = <0xd82b0000 0x1040>;
105 interrupts = <33>; 153 interrupts = <33>;
106 clocks = <&ref24>; 154 clocks = <&clkuart1>;
107 }; 155 };
108 156
109 uart@d8210000 { 157 uart@d8210000 {
110 compatible = "via,vt8500-uart"; 158 compatible = "via,vt8500-uart";
111 reg = <0xd8210000 0x1040>; 159 reg = <0xd8210000 0x1040>;
112 interrupts = <47>; 160 interrupts = <47>;
113 clocks = <&ref24>; 161 clocks = <&clkuart2>;
114 }; 162 };
115 163
116 uart@d82c0000 { 164 uart@d82c0000 {
117 compatible = "via,vt8500-uart"; 165 compatible = "via,vt8500-uart";
118 reg = <0xd82c0000 0x1040>; 166 reg = <0xd82c0000 0x1040>;
119 interrupts = <50>; 167 interrupts = <50>;
120 clocks = <&ref24>; 168 clocks = <&clkuart3>;
121 }; 169 };
122 170
123 uart@d8370000 { 171 uart@d8370000 {
124 compatible = "via,vt8500-uart"; 172 compatible = "via,vt8500-uart";
125 reg = <0xd8370000 0x1040>; 173 reg = <0xd8370000 0x1040>;
126 interrupts = <31>; 174 interrupts = <31>;
127 clocks = <&ref24>; 175 clocks = <&clkuart4>;
128 }; 176 };
129 177
130 uart@d8380000 { 178 uart@d8380000 {
131 compatible = "via,vt8500-uart"; 179 compatible = "via,vt8500-uart";
132 reg = <0xd8380000 0x1040>; 180 reg = <0xd8380000 0x1040>;
133 interrupts = <30>; 181 interrupts = <30>;
134 clocks = <&ref24>; 182 clocks = <&clkuart5>;
135 }; 183 };
136 184
137 rtc@d8100000 { 185 rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index 83b9467559bb..db3c0a12e052 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -75,6 +75,22 @@
75 reg = <0x204>; 75 reg = <0x204>;
76 }; 76 };
77 77
78 clkuart0: uart0 {
79 #clock-cells = <0>;
80 compatible = "via,vt8500-device-clock";
81 clocks = <&ref24>;
82 enable-reg = <0x250>;
83 enable-bit = <1>;
84 };
85
86 clkuart1: uart1 {
87 #clock-cells = <0>;
88 compatible = "via,vt8500-device-clock";
89 clocks = <&ref24>;
90 enable-reg = <0x250>;
91 enable-bit = <2>;
92 };
93
78 arm: arm { 94 arm: arm {
79 #clock-cells = <0>; 95 #clock-cells = <0>;
80 compatible = "via,vt8500-device-clock"; 96 compatible = "via,vt8500-device-clock";
@@ -128,14 +144,14 @@
128 compatible = "via,vt8500-uart"; 144 compatible = "via,vt8500-uart";
129 reg = <0xd8200000 0x1040>; 145 reg = <0xd8200000 0x1040>;
130 interrupts = <32>; 146 interrupts = <32>;
131 clocks = <&ref24>; 147 clocks = <&clkuart0>;
132 }; 148 };
133 149
134 uart@d82b0000 { 150 uart@d82b0000 {
135 compatible = "via,vt8500-uart"; 151 compatible = "via,vt8500-uart";
136 reg = <0xd82b0000 0x1040>; 152 reg = <0xd82b0000 0x1040>;
137 interrupts = <33>; 153 interrupts = <33>;
138 clocks = <&ref24>; 154 clocks = <&clkuart1>;
139 }; 155 };
140 156
141 rtc@d8100000 { 157 rtc@d8100000 {