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author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-01-15 07:39:04 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-01-15 07:39:04 -0500 |
commit | 073154459b80a43f7e4f088b11c93c8e9cb07f14 (patch) | |
tree | c81603910b742fbb0e4129034e5011364a9c7418 /arch/arm | |
parent | c76d292db9869ae73fd401e9a3fc728ed5caf0a7 (diff) | |
parent | ea0c4f3ca8a55e7e3138c2c4b3e9f7fe34d3ecab (diff) |
Merge branch 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel-stable
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/common/sa1111.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/mfp-mmp2.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/mfp-pxa910.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-pxa/clock-pxa3xx.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-pxa/irq.c | 49 | ||||
-rw-r--r-- | arch/arm/mach-pxa/spitz.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-pxa/zeus.c | 4 |
7 files changed, 24 insertions, 37 deletions
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index d6c784e78c83..eb9796b0dab2 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c | |||
@@ -279,7 +279,7 @@ static int sa1111_retrigger_lowirq(struct irq_data *d) | |||
279 | for (i = 0; i < 8; i++) { | 279 | for (i = 0; i < 8; i++) { |
280 | sa1111_writel(ip0 ^ mask, mapbase + SA1111_INTPOL0); | 280 | sa1111_writel(ip0 ^ mask, mapbase + SA1111_INTPOL0); |
281 | sa1111_writel(ip0, mapbase + SA1111_INTPOL0); | 281 | sa1111_writel(ip0, mapbase + SA1111_INTPOL0); |
282 | if (sa1111_readl(mapbase + SA1111_INTSTATCLR1) & mask) | 282 | if (sa1111_readl(mapbase + SA1111_INTSTATCLR0) & mask) |
283 | break; | 283 | break; |
284 | } | 284 | } |
285 | 285 | ||
diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h index 117e30366087..4ad38629c3f6 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h +++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h | |||
@@ -6,7 +6,7 @@ | |||
6 | #define MFP_DRIVE_VERY_SLOW (0x0 << 13) | 6 | #define MFP_DRIVE_VERY_SLOW (0x0 << 13) |
7 | #define MFP_DRIVE_SLOW (0x2 << 13) | 7 | #define MFP_DRIVE_SLOW (0x2 << 13) |
8 | #define MFP_DRIVE_MEDIUM (0x4 << 13) | 8 | #define MFP_DRIVE_MEDIUM (0x4 << 13) |
9 | #define MFP_DRIVE_FAST (0x8 << 13) | 9 | #define MFP_DRIVE_FAST (0x6 << 13) |
10 | 10 | ||
11 | /* GPIO */ | 11 | /* GPIO */ |
12 | #define GPIO0_GPIO MFP_CFG(GPIO0, AF0) | 12 | #define GPIO0_GPIO MFP_CFG(GPIO0, AF0) |
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h index 7e8a80f25ddc..fbd7ee8e4897 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h | |||
@@ -6,7 +6,7 @@ | |||
6 | #define MFP_DRIVE_VERY_SLOW (0x0 << 13) | 6 | #define MFP_DRIVE_VERY_SLOW (0x0 << 13) |
7 | #define MFP_DRIVE_SLOW (0x2 << 13) | 7 | #define MFP_DRIVE_SLOW (0x2 << 13) |
8 | #define MFP_DRIVE_MEDIUM (0x4 << 13) | 8 | #define MFP_DRIVE_MEDIUM (0x4 << 13) |
9 | #define MFP_DRIVE_FAST (0x8 << 13) | 9 | #define MFP_DRIVE_FAST (0x6 << 13) |
10 | 10 | ||
11 | /* UART2 */ | 11 | /* UART2 */ |
12 | #define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6) | 12 | #define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6) |
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c index 1b08a34ab234..3f864cd0bd28 100644 --- a/arch/arm/mach-pxa/clock-pxa3xx.c +++ b/arch/arm/mach-pxa/clock-pxa3xx.c | |||
@@ -115,7 +115,6 @@ static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk) | |||
115 | { | 115 | { |
116 | unsigned long acsr = ACSR; | 116 | unsigned long acsr = ACSR; |
117 | unsigned long memclkcfg = __raw_readl(MEMCLKCFG); | 117 | unsigned long memclkcfg = __raw_readl(MEMCLKCFG); |
118 | unsigned int smcfs = (acsr >> 23) & 0x7; | ||
119 | 118 | ||
120 | return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] / | 119 | return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] / |
121 | df_clkdiv[(memclkcfg >> 16) & 0x3]; | 120 | df_clkdiv[(memclkcfg >> 16) & 0x3]; |
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 3f7f5bf05f3a..2693e3c3776f 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
@@ -53,6 +53,17 @@ static inline int cpu_has_ipr(void) | |||
53 | return !cpu_is_pxa25x(); | 53 | return !cpu_is_pxa25x(); |
54 | } | 54 | } |
55 | 55 | ||
56 | static inline void __iomem *irq_base(int i) | ||
57 | { | ||
58 | static unsigned long phys_base[] = { | ||
59 | 0x40d00000, | ||
60 | 0x40d0009c, | ||
61 | 0x40d00130, | ||
62 | }; | ||
63 | |||
64 | return (void __iomem *)io_p2v(phys_base[i]); | ||
65 | } | ||
66 | |||
56 | static void pxa_mask_irq(struct irq_data *d) | 67 | static void pxa_mask_irq(struct irq_data *d) |
57 | { | 68 | { |
58 | void __iomem *base = irq_data_get_irq_chip_data(d); | 69 | void __iomem *base = irq_data_get_irq_chip_data(d); |
@@ -108,25 +119,11 @@ static void pxa_ack_low_gpio(struct irq_data *d) | |||
108 | GEDR0 = (1 << (d->irq - IRQ_GPIO0)); | 119 | GEDR0 = (1 << (d->irq - IRQ_GPIO0)); |
109 | } | 120 | } |
110 | 121 | ||
111 | static void pxa_mask_low_gpio(struct irq_data *d) | ||
112 | { | ||
113 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
114 | |||
115 | desc->irq_data.chip->irq_mask(d); | ||
116 | } | ||
117 | |||
118 | static void pxa_unmask_low_gpio(struct irq_data *d) | ||
119 | { | ||
120 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
121 | |||
122 | desc->irq_data.chip->irq_unmask(d); | ||
123 | } | ||
124 | |||
125 | static struct irq_chip pxa_low_gpio_chip = { | 122 | static struct irq_chip pxa_low_gpio_chip = { |
126 | .name = "GPIO-l", | 123 | .name = "GPIO-l", |
127 | .irq_ack = pxa_ack_low_gpio, | 124 | .irq_ack = pxa_ack_low_gpio, |
128 | .irq_mask = pxa_mask_low_gpio, | 125 | .irq_mask = pxa_mask_irq, |
129 | .irq_unmask = pxa_unmask_low_gpio, | 126 | .irq_unmask = pxa_unmask_irq, |
130 | .irq_set_type = pxa_set_low_gpio_type, | 127 | .irq_set_type = pxa_set_low_gpio_type, |
131 | }; | 128 | }; |
132 | 129 | ||
@@ -141,6 +138,7 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn) | |||
141 | 138 | ||
142 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | 139 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { |
143 | set_irq_chip(irq, &pxa_low_gpio_chip); | 140 | set_irq_chip(irq, &pxa_low_gpio_chip); |
141 | set_irq_chip_data(irq, irq_base(0)); | ||
144 | set_irq_handler(irq, handle_edge_irq); | 142 | set_irq_handler(irq, handle_edge_irq); |
145 | set_irq_flags(irq, IRQF_VALID); | 143 | set_irq_flags(irq, IRQF_VALID); |
146 | } | 144 | } |
@@ -148,17 +146,6 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn) | |||
148 | pxa_low_gpio_chip.irq_set_wake = fn; | 146 | pxa_low_gpio_chip.irq_set_wake = fn; |
149 | } | 147 | } |
150 | 148 | ||
151 | static inline void __iomem *irq_base(int i) | ||
152 | { | ||
153 | static unsigned long phys_base[] = { | ||
154 | 0x40d00000, | ||
155 | 0x40d0009c, | ||
156 | 0x40d00130, | ||
157 | }; | ||
158 | |||
159 | return (void __iomem *)io_p2v(phys_base[i >> 5]); | ||
160 | } | ||
161 | |||
162 | void __init pxa_init_irq(int irq_nr, set_wake_t fn) | 149 | void __init pxa_init_irq(int irq_nr, set_wake_t fn) |
163 | { | 150 | { |
164 | int irq, i, n; | 151 | int irq, i, n; |
@@ -168,7 +155,7 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) | |||
168 | pxa_internal_irq_nr = irq_nr; | 155 | pxa_internal_irq_nr = irq_nr; |
169 | 156 | ||
170 | for (n = 0; n < irq_nr; n += 32) { | 157 | for (n = 0; n < irq_nr; n += 32) { |
171 | void __iomem *base = irq_base(n); | 158 | void __iomem *base = irq_base(n >> 5); |
172 | 159 | ||
173 | __raw_writel(0, base + ICMR); /* disable all IRQs */ | 160 | __raw_writel(0, base + ICMR); /* disable all IRQs */ |
174 | __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ | 161 | __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ |
@@ -200,7 +187,7 @@ static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) | |||
200 | { | 187 | { |
201 | int i; | 188 | int i; |
202 | 189 | ||
203 | for (i = 0; i < pxa_internal_irq_nr; i += 32) { | 190 | for (i = 0; i < pxa_internal_irq_nr / 32; i++) { |
204 | void __iomem *base = irq_base(i); | 191 | void __iomem *base = irq_base(i); |
205 | 192 | ||
206 | saved_icmr[i] = __raw_readl(base + ICMR); | 193 | saved_icmr[i] = __raw_readl(base + ICMR); |
@@ -219,14 +206,14 @@ static int pxa_irq_resume(struct sys_device *dev) | |||
219 | { | 206 | { |
220 | int i; | 207 | int i; |
221 | 208 | ||
222 | for (i = 0; i < pxa_internal_irq_nr; i += 32) { | 209 | for (i = 0; i < pxa_internal_irq_nr / 32; i++) { |
223 | void __iomem *base = irq_base(i); | 210 | void __iomem *base = irq_base(i); |
224 | 211 | ||
225 | __raw_writel(saved_icmr[i], base + ICMR); | 212 | __raw_writel(saved_icmr[i], base + ICMR); |
226 | __raw_writel(0, base + ICLR); | 213 | __raw_writel(0, base + ICLR); |
227 | } | 214 | } |
228 | 215 | ||
229 | if (!cpu_is_pxa25x()) | 216 | if (cpu_has_ipr()) |
230 | for (i = 0; i < pxa_internal_irq_nr; i++) | 217 | for (i = 0; i < pxa_internal_irq_nr; i++) |
231 | __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); | 218 | __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); |
232 | 219 | ||
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 0bc938729c4c..b49a2c21124c 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <linux/spi/corgi_lcd.h> | 25 | #include <linux/spi/corgi_lcd.h> |
26 | #include <linux/spi/pxa2xx_spi.h> | 26 | #include <linux/spi/pxa2xx_spi.h> |
27 | #include <linux/mtd/sharpsl.h> | 27 | #include <linux/mtd/sharpsl.h> |
28 | #include <linux/mtd/physmap.h> | ||
28 | #include <linux/input/matrix_keypad.h> | 29 | #include <linux/input/matrix_keypad.h> |
29 | #include <linux/regulator/machine.h> | 30 | #include <linux/regulator/machine.h> |
30 | #include <linux/io.h> | 31 | #include <linux/io.h> |
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index a894770d203b..f4b053b35815 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c | |||
@@ -830,8 +830,8 @@ static void __init zeus_init(void) | |||
830 | pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f)); | 830 | pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f)); |
831 | 831 | ||
832 | /* Fix timings for dm9000s (CS1/CS2)*/ | 832 | /* Fix timings for dm9000s (CS1/CS2)*/ |
833 | msc0 = __raw_readl(MSC0) & 0x0000ffff | (dm9000_msc << 16); | 833 | msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16); |
834 | msc1 = __raw_readl(MSC1) & 0xffff0000 | dm9000_msc; | 834 | msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc; |
835 | __raw_writel(msc0, MSC0); | 835 | __raw_writel(msc0, MSC0); |
836 | __raw_writel(msc1, MSC1); | 836 | __raw_writel(msc1, MSC1); |
837 | 837 | ||