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authorOlof Johansson <olof@lixom.net>2012-09-13 01:34:11 -0400
committerOlof Johansson <olof@lixom.net>2012-09-13 01:34:11 -0400
commit025c95a6826ad8acfe871f33c2fa9208beeb38df (patch)
tree220fe156ff60db13bd3a1319f5e20d6b723de5f4 /arch/arm
parent0558d7a8ed44e6e53aadb04d2e23145efb2aa8a4 (diff)
parent7f744b17140af1a9c8804a1c81c9dae6bb52a7fb (diff)
Merge branch 'clk' of git://github.com/hzhuang1/linux into next/cleanup
* 'clk' of git://github.com/hzhuang1/linux: ARM: mmp: remove unused definition in APBC and APMU ARM: mmp: move mmp2 clock definition to separated file arm: mmp: move pxa910 clock definition to separated file arm: mmp: move pxa168 clock definition to separated file arm: mmp: make private clock definition exclude from common clock + Linux 3.6-rc4
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi5
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-iconnect.dts6
-rw-r--r--arch/arm/boot/dts/twl6030.dtsi3
-rw-r--r--arch/arm/configs/u8500_defconfig1
-rw-r--r--arch/arm/mach-dove/common.c3
-rw-r--r--arch/arm/mach-exynos/mach-origen.c7
-rw-r--r--arch/arm/mach-exynos/mach-smdkv310.c7
-rw-r--r--arch/arm/mach-imx/Makefile10
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c8
-rw-r--r--arch/arm/mach-imx/headsmp.S (renamed from arch/arm/mach-imx/head-v7.S)0
-rw-r--r--arch/arm/mach-imx/hotplug.c23
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c4
-rw-r--r--arch/arm/mach-kirkwood/Makefile.boot3
-rw-r--r--arch/arm/mach-kirkwood/common.c4
-rw-r--r--arch/arm/mach-mmp/Makefile8
-rw-r--r--arch/arm/mach-mmp/clock-mmp2.c111
-rw-r--r--arch/arm/mach-mmp/clock-pxa168.c91
-rw-r--r--arch/arm/mach-mmp/clock-pxa910.c67
-rw-r--r--arch/arm/mach-mmp/common.h3
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-apbc.h95
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-apmu.h15
-rw-r--r--arch/arm/mach-mmp/mmp2.c71
-rw-r--r--arch/arm/mach-mmp/pxa168.c58
-rw-r--r--arch/arm/mach-mmp/pxa910.c40
-rw-r--r--arch/arm/mach-mmp/sram.c2
-rw-r--r--arch/arm/mach-mv78xx0/addr-map.c2
-rw-r--r--arch/arm/mach-mv78xx0/common.c6
-rw-r--r--arch/arm/mach-omap2/Kconfig3
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c1
-rw-r--r--arch/arm/mach-omap2/common-board-devices.c11
-rw-r--r--arch/arm/mach-omap2/common-board-devices.h1
-rw-r--r--arch/arm/mach-omap2/cpuidle44xx.c3
-rw-r--r--arch/arm/mach-omap2/mux.h1
-rw-r--r--arch/arm/mach-omap2/opp4xxx_data.c2
-rw-r--r--arch/arm/mach-omap2/pm34xx.c19
-rw-r--r--arch/arm/mach-omap2/sleep44xx.S8
-rw-r--r--arch/arm/mach-omap2/twl-common.c1
-rw-r--r--arch/arm/mach-orion5x/common.c3
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/dma.h3
-rw-r--r--arch/arm/mach-ux500/Kconfig1
-rw-r--r--arch/arm/mach-ux500/board-mop500-msp.c10
-rw-r--r--arch/arm/mach-ux500/board-mop500.c4
-rw-r--r--arch/arm/plat-omap/dmtimer.c6
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h3
-rw-r--r--arch/arm/plat-omap/include/plat/multi.h9
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h4
-rw-r--r--arch/arm/plat-orion/common.c8
-rw-r--r--arch/arm/plat-orion/include/plat/common.h6
-rw-r--r--arch/arm/plat-s3c24xx/dma.c2
-rw-r--r--arch/arm/plat-samsung/devs.c29
-rw-r--r--arch/arm/plat-samsung/include/plat/hdmi.h16
-rw-r--r--arch/arm/plat-samsung/pm.c2
55 files changed, 454 insertions, 362 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 012016733838..d1799267a01f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2121,6 +2121,7 @@ source "drivers/cpufreq/Kconfig"
2121config CPU_FREQ_IMX 2121config CPU_FREQ_IMX
2122 tristate "CPUfreq driver for i.MX CPUs" 2122 tristate "CPUfreq driver for i.MX CPUs"
2123 depends on ARCH_MXC && CPU_FREQ 2123 depends on ARCH_MXC && CPU_FREQ
2124 select CPU_FREQ_TABLE
2124 help 2125 help
2125 This enables the CPUfreq driver for i.MX CPUs. 2126 This enables the CPUfreq driver for i.MX CPUs.
2126 2127
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 59509c48d7e5..bd0cff3f808c 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -154,5 +154,10 @@
154 #size-cells = <0>; 154 #size-cells = <0>;
155 ti,hwmods = "i2c3"; 155 ti,hwmods = "i2c3";
156 }; 156 };
157
158 wdt2: wdt@44e35000 {
159 compatible = "ti,omap3-wdt";
160 ti,hwmods = "wd_timer2";
161 };
157 }; 162 };
158}; 163};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index cd86177a3ea2..59d9789e5508 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -25,8 +25,8 @@
25 aips@70000000 { /* aips-1 */ 25 aips@70000000 { /* aips-1 */
26 spba@70000000 { 26 spba@70000000 {
27 esdhc@70004000 { /* ESDHC1 */ 27 esdhc@70004000 { /* ESDHC1 */
28 fsl,cd-internal; 28 fsl,cd-controller;
29 fsl,wp-internal; 29 fsl,wp-controller;
30 status = "okay"; 30 status = "okay";
31 }; 31 };
32 32
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 52d947045106..f8ca6fa88192 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -41,9 +41,13 @@
41 }; 41 };
42 power-blue { 42 power-blue {
43 label = "power:blue"; 43 label = "power:blue";
44 gpios = <&gpio1 11 0>; 44 gpios = <&gpio1 10 0>;
45 linux,default-trigger = "timer"; 45 linux,default-trigger = "timer";
46 }; 46 };
47 power-red {
48 label = "power:red";
49 gpios = <&gpio1 11 0>;
50 };
47 usb1 { 51 usb1 {
48 label = "usb1:blue"; 52 label = "usb1:blue";
49 gpios = <&gpio1 12 0>; 53 gpios = <&gpio1 12 0>;
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index 3b2f3510d7eb..d351b27d7213 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -66,6 +66,7 @@
66 66
67 vcxio: regulator@8 { 67 vcxio: regulator@8 {
68 compatible = "ti,twl6030-vcxio"; 68 compatible = "ti,twl6030-vcxio";
69 regulator-always-on;
69 }; 70 };
70 71
71 vusb: regulator@9 { 72 vusb: regulator@9 {
@@ -74,10 +75,12 @@
74 75
75 v1v8: regulator@10 { 76 v1v8: regulator@10 {
76 compatible = "ti,twl6030-v1v8"; 77 compatible = "ti,twl6030-v1v8";
78 regulator-always-on;
77 }; 79 };
78 80
79 v2v1: regulator@11 { 81 v2v1: regulator@11 {
80 compatible = "ti,twl6030-v2v1"; 82 compatible = "ti,twl6030-v2v1";
83 regulator-always-on;
81 }; 84 };
82 85
83 clk32kg: regulator@12 { 86 clk32kg: regulator@12 {
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 2d4f661d1cf6..da6845493caa 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -86,6 +86,7 @@ CONFIG_NEW_LEDS=y
86CONFIG_LEDS_CLASS=y 86CONFIG_LEDS_CLASS=y
87CONFIG_LEDS_LM3530=y 87CONFIG_LEDS_LM3530=y
88CONFIG_LEDS_LP5521=y 88CONFIG_LEDS_LP5521=y
89CONFIG_LEDS_GPIO=y
89CONFIG_RTC_CLASS=y 90CONFIG_RTC_CLASS=y
90CONFIG_RTC_DRV_AB8500=y 91CONFIG_RTC_DRV_AB8500=y
91CONFIG_RTC_DRV_PL031=y 92CONFIG_RTC_DRV_PL031=y
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index ed4fa5f316ea..cc4c6a5a357c 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -92,7 +92,8 @@ void __init dove_ehci1_init(void)
92void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 92void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
93{ 93{
94 orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, 94 orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
95 IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR); 95 IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
96 1600);
96} 97}
97 98
98/***************************************************************************** 99/*****************************************************************************
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 5ca80307d6d7..4e574c24581c 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -42,6 +42,7 @@
42#include <plat/backlight.h> 42#include <plat/backlight.h>
43#include <plat/fb.h> 43#include <plat/fb.h>
44#include <plat/mfc.h> 44#include <plat/mfc.h>
45#include <plat/hdmi.h>
45 46
46#include <mach/ohci.h> 47#include <mach/ohci.h>
47#include <mach/map.h> 48#include <mach/map.h>
@@ -734,6 +735,11 @@ static void __init origen_bt_setup(void)
734 s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE); 735 s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE);
735} 736}
736 737
738/* I2C module and id for HDMIPHY */
739static struct i2c_board_info hdmiphy_info = {
740 I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
741};
742
737static void s5p_tv_setup(void) 743static void s5p_tv_setup(void)
738{ 744{
739 /* Direct HPD to HDMI chip */ 745 /* Direct HPD to HDMI chip */
@@ -781,6 +787,7 @@ static void __init origen_machine_init(void)
781 787
782 s5p_tv_setup(); 788 s5p_tv_setup();
783 s5p_i2c_hdmiphy_set_platdata(NULL); 789 s5p_i2c_hdmiphy_set_platdata(NULL);
790 s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
784 791
785#ifdef CONFIG_DRM_EXYNOS 792#ifdef CONFIG_DRM_EXYNOS
786 s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; 793 s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 3cfa688d274a..73f2bce097e1 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -40,6 +40,7 @@
40#include <plat/mfc.h> 40#include <plat/mfc.h>
41#include <plat/ehci.h> 41#include <plat/ehci.h>
42#include <plat/clock.h> 42#include <plat/clock.h>
43#include <plat/hdmi.h>
43 44
44#include <mach/map.h> 45#include <mach/map.h>
45#include <mach/ohci.h> 46#include <mach/ohci.h>
@@ -354,6 +355,11 @@ static struct platform_pwm_backlight_data smdkv310_bl_data = {
354 .pwm_period_ns = 1000, 355 .pwm_period_ns = 1000,
355}; 356};
356 357
358/* I2C module and id for HDMIPHY */
359static struct i2c_board_info hdmiphy_info = {
360 I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
361};
362
357static void s5p_tv_setup(void) 363static void s5p_tv_setup(void)
358{ 364{
359 /* direct HPD to HDMI chip */ 365 /* direct HPD to HDMI chip */
@@ -388,6 +394,7 @@ static void __init smdkv310_machine_init(void)
388 394
389 s5p_tv_setup(); 395 s5p_tv_setup();
390 s5p_i2c_hdmiphy_set_platdata(NULL); 396 s5p_i2c_hdmiphy_set_platdata(NULL);
397 s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
391 398
392 samsung_keypad_set_platdata(&smdkv310_keypad_data); 399 samsung_keypad_set_platdata(&smdkv310_keypad_data);
393 400
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 07f7c226e4cf..d004d37ad9d8 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -9,7 +9,8 @@ obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
9obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o 9obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
10obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o 10obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
11 11
12obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o 12imx5-pm-$(CONFIG_PM) += pm-imx5.o
13obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
13 14
14obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ 15obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
15 clk-pfd.o clk-busy.o 16 clk-pfd.o clk-busy.o
@@ -70,14 +71,13 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
70obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o 71obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
71obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o 72obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
72obj-$(CONFIG_HAVE_IMX_SRC) += src.o 73obj-$(CONFIG_HAVE_IMX_SRC) += src.o
73obj-$(CONFIG_CPU_V7) += head-v7.o 74AFLAGS_headsmp.o :=-Wa,-march=armv7-a
74AFLAGS_head-v7.o :=-Wa,-march=armv7-a 75obj-$(CONFIG_SMP) += headsmp.o platsmp.o
75obj-$(CONFIG_SMP) += platsmp.o
76obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 76obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
77obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o 77obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
78 78
79ifeq ($(CONFIG_PM),y) 79ifeq ($(CONFIG_PM),y)
80obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o 80obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
81endif 81endif
82 82
83# i.MX5 based machines 83# i.MX5 based machines
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index ea89520b6e22..4233d9e3531d 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -152,7 +152,7 @@ enum mx6q_clks {
152 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, 152 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
153 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, 153 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
154 pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, 154 pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
155 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, 155 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
156 clk_max 156 clk_max
157}; 157};
158 158
@@ -288,8 +288,10 @@ int __init mx6q_clocks_init(void)
288 clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); 288 clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
289 clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); 289 clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
290 clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); 290 clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
291 clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_sel", base + 0x20, 10, 1); 291 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
292 clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_sel", base + 0x20, 11, 1); 292 clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1);
293 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
294 clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1);
293 clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); 295 clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
294 clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); 296 clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
295 clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); 297 clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/headsmp.S
index 7e49deb128a4..7e49deb128a4 100644
--- a/arch/arm/mach-imx/head-v7.S
+++ b/arch/arm/mach-imx/headsmp.S
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 20ed2d56c1af..f8f7437c83b8 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -42,22 +42,6 @@ static inline void cpu_enter_lowpower(void)
42 : "cc"); 42 : "cc");
43} 43}
44 44
45static inline void cpu_leave_lowpower(void)
46{
47 unsigned int v;
48
49 asm volatile(
50 "mrc p15, 0, %0, c1, c0, 0\n"
51 " orr %0, %0, %1\n"
52 " mcr p15, 0, %0, c1, c0, 0\n"
53 " mrc p15, 0, %0, c1, c0, 1\n"
54 " orr %0, %0, %2\n"
55 " mcr p15, 0, %0, c1, c0, 1\n"
56 : "=&r" (v)
57 : "Ir" (CR_C), "Ir" (0x40)
58 : "cc");
59}
60
61/* 45/*
62 * platform-specific code to shutdown a CPU 46 * platform-specific code to shutdown a CPU
63 * 47 *
@@ -67,11 +51,10 @@ void platform_cpu_die(unsigned int cpu)
67{ 51{
68 cpu_enter_lowpower(); 52 cpu_enter_lowpower();
69 imx_enable_cpu(cpu, false); 53 imx_enable_cpu(cpu, false);
70 cpu_do_idle();
71 cpu_leave_lowpower();
72 54
73 /* We should never return from idle */ 55 /* spin here until hardware takes it down */
74 panic("cpu %d unexpectedly exit from shutdown\n", cpu); 56 while (1)
57 ;
75} 58}
76 59
77int platform_cpu_disable(unsigned int cpu) 60int platform_cpu_disable(unsigned int cpu)
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5ec0608f2a76..045b3f6a387d 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -71,7 +71,7 @@ soft:
71/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ 71/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
72static int ksz9021rn_phy_fixup(struct phy_device *phydev) 72static int ksz9021rn_phy_fixup(struct phy_device *phydev)
73{ 73{
74 if (IS_ENABLED(CONFIG_PHYLIB)) { 74 if (IS_BUILTIN(CONFIG_PHYLIB)) {
75 /* min rx data delay */ 75 /* min rx data delay */
76 phy_write(phydev, 0x0b, 0x8105); 76 phy_write(phydev, 0x0b, 0x8105);
77 phy_write(phydev, 0x0c, 0x0000); 77 phy_write(phydev, 0x0c, 0x0000);
@@ -112,7 +112,7 @@ put_clk:
112 112
113static void __init imx6q_sabrelite_init(void) 113static void __init imx6q_sabrelite_init(void)
114{ 114{
115 if (IS_ENABLED(CONFIG_PHYLIB)) 115 if (IS_BUILTIN(CONFIG_PHYLIB))
116 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, 116 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
117 ksz9021rn_phy_fixup); 117 ksz9021rn_phy_fixup);
118 imx6q_sabrelite_cko1_setup(); 118 imx6q_sabrelite_cko1_setup();
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index a5717558ee89..a13299d758e1 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -7,7 +7,8 @@ dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb
7dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb 7dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb
8dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb 8dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
9dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb 9dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb
10dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-qnap-ts219.dtb 10dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-ts219-6281.dtb
11dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-ts219-6282.dtb
11dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb 12dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
12dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb 13dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
13dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb 14dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 31d9f400ed82..936b31df644c 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -291,7 +291,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
291{ 291{
292 orion_ge00_init(eth_data, 292 orion_ge00_init(eth_data,
293 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, 293 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
294 IRQ_KIRKWOOD_GE00_ERR); 294 IRQ_KIRKWOOD_GE00_ERR, 1600);
295 /* The interface forgets the MAC address assigned by u-boot if 295 /* The interface forgets the MAC address assigned by u-boot if
296 the clock is turned off, so claim the clk now. */ 296 the clock is turned off, so claim the clk now. */
297 clk_prepare_enable(ge0); 297 clk_prepare_enable(ge0);
@@ -305,7 +305,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
305{ 305{
306 orion_ge01_init(eth_data, 306 orion_ge01_init(eth_data,
307 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, 307 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
308 IRQ_KIRKWOOD_GE01_ERR); 308 IRQ_KIRKWOOD_GE01_ERR, 1600);
309 clk_prepare_enable(ge1); 309 clk_prepare_enable(ge1);
310} 310}
311 311
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index b786f7e6cd1f..095c155d6fb8 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,13 +2,19 @@
2# Makefile for Marvell's PXA168 processors line 2# Makefile for Marvell's PXA168 processors line
3# 3#
4 4
5obj-y += common.o clock.o devices.o time.o irq.o 5obj-y += common.o devices.o time.o irq.o
6 6
7# SoC support 7# SoC support
8obj-$(CONFIG_CPU_PXA168) += pxa168.o 8obj-$(CONFIG_CPU_PXA168) += pxa168.o
9obj-$(CONFIG_CPU_PXA910) += pxa910.o 9obj-$(CONFIG_CPU_PXA910) += pxa910.o
10obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o 10obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o
11 11
12ifeq ($(CONFIG_COMMON_CLK), )
13obj-y += clock.o
14obj-$(CONFIG_CPU_PXA168) += clock-pxa168.o
15obj-$(CONFIG_CPU_PXA910) += clock-pxa910.o
16obj-$(CONFIG_CPU_MMP2) += clock-mmp2.o
17endif
12ifeq ($(CONFIG_PM),y) 18ifeq ($(CONFIG_PM),y)
13obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o 19obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o
14obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o 20obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o
diff --git a/arch/arm/mach-mmp/clock-mmp2.c b/arch/arm/mach-mmp/clock-mmp2.c
new file mode 100644
index 000000000000..21d22002cd19
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-mmp2.c
@@ -0,0 +1,111 @@
1#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/list.h>
5#include <linux/io.h>
6#include <linux/clk.h>
7
8#include <mach/addr-map.h>
9
10#include "common.h"
11#include "clock.h"
12
13/*
14 * APB Clock register offsets for MMP2
15 */
16#define APBC_RTC APBC_REG(0x000)
17#define APBC_TWSI1 APBC_REG(0x004)
18#define APBC_TWSI2 APBC_REG(0x008)
19#define APBC_TWSI3 APBC_REG(0x00c)
20#define APBC_TWSI4 APBC_REG(0x010)
21#define APBC_KPC APBC_REG(0x018)
22#define APBC_UART1 APBC_REG(0x02c)
23#define APBC_UART2 APBC_REG(0x030)
24#define APBC_UART3 APBC_REG(0x034)
25#define APBC_GPIO APBC_REG(0x038)
26#define APBC_PWM0 APBC_REG(0x03c)
27#define APBC_PWM1 APBC_REG(0x040)
28#define APBC_PWM2 APBC_REG(0x044)
29#define APBC_PWM3 APBC_REG(0x048)
30#define APBC_SSP0 APBC_REG(0x04c)
31#define APBC_SSP1 APBC_REG(0x050)
32#define APBC_SSP2 APBC_REG(0x054)
33#define APBC_SSP3 APBC_REG(0x058)
34#define APBC_SSP4 APBC_REG(0x05c)
35#define APBC_SSP5 APBC_REG(0x060)
36#define APBC_TWSI5 APBC_REG(0x07c)
37#define APBC_TWSI6 APBC_REG(0x080)
38#define APBC_UART4 APBC_REG(0x088)
39
40#define APMU_USB APMU_REG(0x05c)
41#define APMU_NAND APMU_REG(0x060)
42#define APMU_SDH0 APMU_REG(0x054)
43#define APMU_SDH1 APMU_REG(0x058)
44#define APMU_SDH2 APMU_REG(0x0e8)
45#define APMU_SDH3 APMU_REG(0x0ec)
46
47static void sdhc_clk_enable(struct clk *clk)
48{
49 uint32_t clk_rst;
50
51 clk_rst = __raw_readl(clk->clk_rst);
52 clk_rst |= clk->enable_val;
53 __raw_writel(clk_rst, clk->clk_rst);
54}
55
56static void sdhc_clk_disable(struct clk *clk)
57{
58 uint32_t clk_rst;
59
60 clk_rst = __raw_readl(clk->clk_rst);
61 clk_rst &= ~clk->enable_val;
62 __raw_writel(clk_rst, clk->clk_rst);
63}
64
65struct clkops sdhc_clk_ops = {
66 .enable = sdhc_clk_enable,
67 .disable = sdhc_clk_disable,
68};
69
70/* APB peripheral clocks */
71static APBC_CLK(uart1, UART1, 1, 26000000);
72static APBC_CLK(uart2, UART2, 1, 26000000);
73static APBC_CLK(uart3, UART3, 1, 26000000);
74static APBC_CLK(uart4, UART4, 1, 26000000);
75static APBC_CLK(twsi1, TWSI1, 0, 26000000);
76static APBC_CLK(twsi2, TWSI2, 0, 26000000);
77static APBC_CLK(twsi3, TWSI3, 0, 26000000);
78static APBC_CLK(twsi4, TWSI4, 0, 26000000);
79static APBC_CLK(twsi5, TWSI5, 0, 26000000);
80static APBC_CLK(twsi6, TWSI6, 0, 26000000);
81static APBC_CLK(gpio, GPIO, 0, 26000000);
82
83static APMU_CLK(nand, NAND, 0xbf, 100000000);
84static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
85static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
86static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
87static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
88
89static struct clk_lookup mmp2_clkregs[] = {
90 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
91 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
92 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
93 INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
94 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
95 INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
96 INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
97 INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
98 INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
99 INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
100 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
101 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
102 INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
103 INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
104 INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
105 INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
106};
107
108void __init mmp2_clk_init(void)
109{
110 clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
111}
diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c
new file mode 100644
index 000000000000..5e6c18ccebd4
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-pxa168.c
@@ -0,0 +1,91 @@
1#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/list.h>
5#include <linux/io.h>
6#include <linux/clk.h>
7
8#include <mach/addr-map.h>
9
10#include "common.h"
11#include "clock.h"
12
13/*
14 * APB clock register offsets for PXA168
15 */
16#define APBC_UART1 APBC_REG(0x000)
17#define APBC_UART2 APBC_REG(0x004)
18#define APBC_GPIO APBC_REG(0x008)
19#define APBC_PWM1 APBC_REG(0x00c)
20#define APBC_PWM2 APBC_REG(0x010)
21#define APBC_PWM3 APBC_REG(0x014)
22#define APBC_PWM4 APBC_REG(0x018)
23#define APBC_RTC APBC_REG(0x028)
24#define APBC_TWSI0 APBC_REG(0x02c)
25#define APBC_KPC APBC_REG(0x030)
26#define APBC_TWSI1 APBC_REG(0x06c)
27#define APBC_UART3 APBC_REG(0x070)
28#define APBC_SSP1 APBC_REG(0x81c)
29#define APBC_SSP2 APBC_REG(0x820)
30#define APBC_SSP3 APBC_REG(0x84c)
31#define APBC_SSP4 APBC_REG(0x858)
32#define APBC_SSP5 APBC_REG(0x85c)
33
34#define APMU_NAND APMU_REG(0x060)
35#define APMU_LCD APMU_REG(0x04c)
36#define APMU_ETH APMU_REG(0x0fc)
37#define APMU_USB APMU_REG(0x05c)
38
39/* APB peripheral clocks */
40static APBC_CLK(uart1, UART1, 1, 14745600);
41static APBC_CLK(uart2, UART2, 1, 14745600);
42static APBC_CLK(uart3, UART3, 1, 14745600);
43static APBC_CLK(twsi0, TWSI0, 1, 33000000);
44static APBC_CLK(twsi1, TWSI1, 1, 33000000);
45static APBC_CLK(pwm1, PWM1, 1, 13000000);
46static APBC_CLK(pwm2, PWM2, 1, 13000000);
47static APBC_CLK(pwm3, PWM3, 1, 13000000);
48static APBC_CLK(pwm4, PWM4, 1, 13000000);
49static APBC_CLK(ssp1, SSP1, 4, 0);
50static APBC_CLK(ssp2, SSP2, 4, 0);
51static APBC_CLK(ssp3, SSP3, 4, 0);
52static APBC_CLK(ssp4, SSP4, 4, 0);
53static APBC_CLK(ssp5, SSP5, 4, 0);
54static APBC_CLK(gpio, GPIO, 0, 13000000);
55static APBC_CLK(keypad, KPC, 0, 32000);
56static APBC_CLK(rtc, RTC, 8, 32768);
57
58static APMU_CLK(nand, NAND, 0x19b, 156000000);
59static APMU_CLK(lcd, LCD, 0x7f, 312000000);
60static APMU_CLK(eth, ETH, 0x09, 0);
61static APMU_CLK(usb, USB, 0x12, 0);
62
63/* device and clock bindings */
64static struct clk_lookup pxa168_clkregs[] = {
65 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
66 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
67 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
68 INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
69 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
70 INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
71 INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
72 INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
73 INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
74 INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
75 INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
76 INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
77 INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
78 INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
79 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
80 INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
81 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
82 INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
83 INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
84 INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
85 INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
86};
87
88void __init pxa168_clk_init(void)
89{
90 clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
91}
diff --git a/arch/arm/mach-mmp/clock-pxa910.c b/arch/arm/mach-mmp/clock-pxa910.c
new file mode 100644
index 000000000000..933ea71d0b56
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-pxa910.c
@@ -0,0 +1,67 @@
1#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/list.h>
5#include <linux/io.h>
6#include <linux/clk.h>
7
8#include <mach/addr-map.h>
9
10#include "common.h"
11#include "clock.h"
12
13/*
14 * APB Clock register offsets for PXA910
15 */
16#define APBC_UART0 APBC_REG(0x000)
17#define APBC_UART1 APBC_REG(0x004)
18#define APBC_GPIO APBC_REG(0x008)
19#define APBC_PWM1 APBC_REG(0x00c)
20#define APBC_PWM2 APBC_REG(0x010)
21#define APBC_PWM3 APBC_REG(0x014)
22#define APBC_PWM4 APBC_REG(0x018)
23#define APBC_SSP1 APBC_REG(0x01c)
24#define APBC_SSP2 APBC_REG(0x020)
25#define APBC_RTC APBC_REG(0x028)
26#define APBC_TWSI0 APBC_REG(0x02c)
27#define APBC_KPC APBC_REG(0x030)
28#define APBC_SSP3 APBC_REG(0x04c)
29#define APBC_TWSI1 APBC_REG(0x06c)
30
31#define APMU_NAND APMU_REG(0x060)
32#define APMU_USB APMU_REG(0x05c)
33
34static APBC_CLK(uart1, UART0, 1, 14745600);
35static APBC_CLK(uart2, UART1, 1, 14745600);
36static APBC_CLK(twsi0, TWSI0, 1, 33000000);
37static APBC_CLK(twsi1, TWSI1, 1, 33000000);
38static APBC_CLK(pwm1, PWM1, 1, 13000000);
39static APBC_CLK(pwm2, PWM2, 1, 13000000);
40static APBC_CLK(pwm3, PWM3, 1, 13000000);
41static APBC_CLK(pwm4, PWM4, 1, 13000000);
42static APBC_CLK(gpio, GPIO, 0, 13000000);
43static APBC_CLK(rtc, RTC, 8, 32768);
44
45static APMU_CLK(nand, NAND, 0x19b, 156000000);
46static APMU_CLK(u2o, USB, 0x1b, 480000000);
47
48/* device and clock bindings */
49static struct clk_lookup pxa910_clkregs[] = {
50 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
51 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
52 INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
53 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
54 INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
55 INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
56 INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
57 INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
58 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
59 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
60 INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
61 INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
62};
63
64void __init pxa910_clk_init(void)
65{
66 clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
67}
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 1c9d6c1ea97a..bd453274fca2 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -7,3 +7,6 @@ extern void timer_init(int irq);
7extern void __init icu_init_irq(void); 7extern void __init icu_init_irq(void);
8extern void __init mmp_map_io(void); 8extern void __init mmp_map_io(void);
9extern void mmp_restart(char, const char *); 9extern void mmp_restart(char, const char *);
10extern void __init pxa168_clk_init(void);
11extern void __init pxa910_clk_init(void);
12extern void __init mmp2_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 68b0c93ec6a1..ddc812f40341 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -13,101 +13,6 @@
13 13
14#include <mach/addr-map.h> 14#include <mach/addr-map.h>
15 15
16/*
17 * APB clock register offsets for PXA168
18 */
19#define APBC_PXA168_UART1 APBC_REG(0x000)
20#define APBC_PXA168_UART2 APBC_REG(0x004)
21#define APBC_PXA168_GPIO APBC_REG(0x008)
22#define APBC_PXA168_PWM1 APBC_REG(0x00c)
23#define APBC_PXA168_PWM2 APBC_REG(0x010)
24#define APBC_PXA168_PWM3 APBC_REG(0x014)
25#define APBC_PXA168_PWM4 APBC_REG(0x018)
26#define APBC_PXA168_RTC APBC_REG(0x028)
27#define APBC_PXA168_TWSI0 APBC_REG(0x02c)
28#define APBC_PXA168_KPC APBC_REG(0x030)
29#define APBC_PXA168_TIMERS APBC_REG(0x034)
30#define APBC_PXA168_AIB APBC_REG(0x03c)
31#define APBC_PXA168_SW_JTAG APBC_REG(0x040)
32#define APBC_PXA168_ONEWIRE APBC_REG(0x048)
33#define APBC_PXA168_ASFAR APBC_REG(0x050)
34#define APBC_PXA168_ASSAR APBC_REG(0x054)
35#define APBC_PXA168_TWSI1 APBC_REG(0x06c)
36#define APBC_PXA168_UART3 APBC_REG(0x070)
37#define APBC_PXA168_AC97 APBC_REG(0x084)
38#define APBC_PXA168_SSP1 APBC_REG(0x81c)
39#define APBC_PXA168_SSP2 APBC_REG(0x820)
40#define APBC_PXA168_SSP3 APBC_REG(0x84c)
41#define APBC_PXA168_SSP4 APBC_REG(0x858)
42#define APBC_PXA168_SSP5 APBC_REG(0x85c)
43
44/*
45 * APB Clock register offsets for PXA910
46 */
47#define APBC_PXA910_UART0 APBC_REG(0x000)
48#define APBC_PXA910_UART1 APBC_REG(0x004)
49#define APBC_PXA910_GPIO APBC_REG(0x008)
50#define APBC_PXA910_PWM1 APBC_REG(0x00c)
51#define APBC_PXA910_PWM2 APBC_REG(0x010)
52#define APBC_PXA910_PWM3 APBC_REG(0x014)
53#define APBC_PXA910_PWM4 APBC_REG(0x018)
54#define APBC_PXA910_SSP1 APBC_REG(0x01c)
55#define APBC_PXA910_SSP2 APBC_REG(0x020)
56#define APBC_PXA910_IPC APBC_REG(0x024)
57#define APBC_PXA910_RTC APBC_REG(0x028)
58#define APBC_PXA910_TWSI0 APBC_REG(0x02c)
59#define APBC_PXA910_KPC APBC_REG(0x030)
60#define APBC_PXA910_TIMERS APBC_REG(0x034)
61#define APBC_PXA910_TBROT APBC_REG(0x038)
62#define APBC_PXA910_AIB APBC_REG(0x03c)
63#define APBC_PXA910_SW_JTAG APBC_REG(0x040)
64#define APBC_PXA910_TIMERS1 APBC_REG(0x044)
65#define APBC_PXA910_ONEWIRE APBC_REG(0x048)
66#define APBC_PXA910_SSP3 APBC_REG(0x04c)
67#define APBC_PXA910_ASFAR APBC_REG(0x050)
68#define APBC_PXA910_ASSAR APBC_REG(0x054)
69
70/*
71 * APB Clock register offsets for MMP2
72 */
73#define APBC_MMP2_RTC APBC_REG(0x000)
74#define APBC_MMP2_TWSI1 APBC_REG(0x004)
75#define APBC_MMP2_TWSI2 APBC_REG(0x008)
76#define APBC_MMP2_TWSI3 APBC_REG(0x00c)
77#define APBC_MMP2_TWSI4 APBC_REG(0x010)
78#define APBC_MMP2_ONEWIRE APBC_REG(0x014)
79#define APBC_MMP2_KPC APBC_REG(0x018)
80#define APBC_MMP2_TB_ROTARY APBC_REG(0x01c)
81#define APBC_MMP2_SW_JTAG APBC_REG(0x020)
82#define APBC_MMP2_TIMERS APBC_REG(0x024)
83#define APBC_MMP2_UART1 APBC_REG(0x02c)
84#define APBC_MMP2_UART2 APBC_REG(0x030)
85#define APBC_MMP2_UART3 APBC_REG(0x034)
86#define APBC_MMP2_GPIO APBC_REG(0x038)
87#define APBC_MMP2_PWM0 APBC_REG(0x03c)
88#define APBC_MMP2_PWM1 APBC_REG(0x040)
89#define APBC_MMP2_PWM2 APBC_REG(0x044)
90#define APBC_MMP2_PWM3 APBC_REG(0x048)
91#define APBC_MMP2_SSP0 APBC_REG(0x04c)
92#define APBC_MMP2_SSP1 APBC_REG(0x050)
93#define APBC_MMP2_SSP2 APBC_REG(0x054)
94#define APBC_MMP2_SSP3 APBC_REG(0x058)
95#define APBC_MMP2_SSP4 APBC_REG(0x05c)
96#define APBC_MMP2_SSP5 APBC_REG(0x060)
97#define APBC_MMP2_AIB APBC_REG(0x064)
98#define APBC_MMP2_ASFAR APBC_REG(0x068)
99#define APBC_MMP2_ASSAR APBC_REG(0x06c)
100#define APBC_MMP2_USIM APBC_REG(0x070)
101#define APBC_MMP2_MPMU APBC_REG(0x074)
102#define APBC_MMP2_IPC APBC_REG(0x078)
103#define APBC_MMP2_TWSI5 APBC_REG(0x07c)
104#define APBC_MMP2_TWSI6 APBC_REG(0x080)
105#define APBC_MMP2_TWSI_INTSTS APBC_REG(0x084)
106#define APBC_MMP2_UART4 APBC_REG(0x088)
107#define APBC_MMP2_RIPC APBC_REG(0x08c)
108#define APBC_MMP2_THSENS1 APBC_REG(0x090) /* Thermal Sensor */
109#define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4)
110
111/* Common APB clock register bit definitions */ 16/* Common APB clock register bit definitions */
112#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ 17#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
113#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ 18#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 7af8deb63e83..93c8d0e29bb9 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -13,21 +13,6 @@
13 13
14#include <mach/addr-map.h> 14#include <mach/addr-map.h>
15 15
16/* Clock Reset Control */
17#define APMU_IRE APMU_REG(0x048)
18#define APMU_LCD APMU_REG(0x04c)
19#define APMU_CCIC APMU_REG(0x050)
20#define APMU_SDH0 APMU_REG(0x054)
21#define APMU_SDH1 APMU_REG(0x058)
22#define APMU_USB APMU_REG(0x05c)
23#define APMU_NAND APMU_REG(0x060)
24#define APMU_DMA APMU_REG(0x064)
25#define APMU_GEU APMU_REG(0x068)
26#define APMU_BUS APMU_REG(0x06c)
27#define APMU_SDH2 APMU_REG(0x0e8)
28#define APMU_SDH3 APMU_REG(0x0ec)
29#define APMU_ETH APMU_REG(0x0fc)
30
31#define APMU_FNCLK_EN (1 << 4) 16#define APMU_FNCLK_EN (1 << 4)
32#define APMU_AXICLK_EN (1 << 3) 17#define APMU_AXICLK_EN (1 << 3)
33#define APMU_FNRST_DIS (1 << 1) 18#define APMU_FNRST_DIS (1 << 1)
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index c709a24a9d25..c2ce3d05b044 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -20,7 +20,6 @@
20#include <asm/mach/time.h> 20#include <asm/mach/time.h>
21#include <mach/addr-map.h> 21#include <mach/addr-map.h>
22#include <mach/regs-apbc.h> 22#include <mach/regs-apbc.h>
23#include <mach/regs-apmu.h>
24#include <mach/cputype.h> 23#include <mach/cputype.h>
25#include <mach/irqs.h> 24#include <mach/irqs.h>
26#include <mach/dma.h> 25#include <mach/dma.h>
@@ -29,7 +28,6 @@
29#include <mach/mmp2.h> 28#include <mach/mmp2.h>
30 29
31#include "common.h" 30#include "common.h"
32#include "clock.h"
33 31
34#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) 32#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
35 33
@@ -98,67 +96,6 @@ void __init mmp2_init_irq(void)
98 mmp2_init_icu(); 96 mmp2_init_icu();
99} 97}
100 98
101static void sdhc_clk_enable(struct clk *clk)
102{
103 uint32_t clk_rst;
104
105 clk_rst = __raw_readl(clk->clk_rst);
106 clk_rst |= clk->enable_val;
107 __raw_writel(clk_rst, clk->clk_rst);
108}
109
110static void sdhc_clk_disable(struct clk *clk)
111{
112 uint32_t clk_rst;
113
114 clk_rst = __raw_readl(clk->clk_rst);
115 clk_rst &= ~clk->enable_val;
116 __raw_writel(clk_rst, clk->clk_rst);
117}
118
119struct clkops sdhc_clk_ops = {
120 .enable = sdhc_clk_enable,
121 .disable = sdhc_clk_disable,
122};
123
124/* APB peripheral clocks */
125static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
126static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
127static APBC_CLK(uart3, MMP2_UART3, 1, 26000000);
128static APBC_CLK(uart4, MMP2_UART4, 1, 26000000);
129static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000);
130static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000);
131static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
132static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
133static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
134static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
135static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000);
136
137static APMU_CLK(nand, NAND, 0xbf, 100000000);
138static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
139static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
140static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
141static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
142
143static struct clk_lookup mmp2_clkregs[] = {
144 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
145 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
146 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
147 INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
148 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
149 INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
150 INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
151 INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
152 INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
153 INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
154 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
155 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
156 INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
157 INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
158 INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
159 INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
160};
161
162static int __init mmp2_init(void) 99static int __init mmp2_init(void)
163{ 100{
164 if (cpu_is_mmp2()) { 101 if (cpu_is_mmp2()) {
@@ -168,25 +105,27 @@ static int __init mmp2_init(void)
168 mfp_init_base(MFPR_VIRT_BASE); 105 mfp_init_base(MFPR_VIRT_BASE);
169 mfp_init_addr(mmp2_addr_map); 106 mfp_init_addr(mmp2_addr_map);
170 pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16); 107 pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16);
171 clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); 108 mmp2_clk_init();
172 } 109 }
173 110
174 return 0; 111 return 0;
175} 112}
176postcore_initcall(mmp2_init); 113postcore_initcall(mmp2_init);
177 114
115#define APBC_TIMERS APBC_REG(0x024)
116
178static void __init mmp2_timer_init(void) 117static void __init mmp2_timer_init(void)
179{ 118{
180 unsigned long clk_rst; 119 unsigned long clk_rst;
181 120
182 __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); 121 __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
183 122
184 /* 123 /*
185 * enable bus/functional clock, enable 6.5MHz (divider 4), 124 * enable bus/functional clock, enable 6.5MHz (divider 4),
186 * release reset 125 * release reset
187 */ 126 */
188 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); 127 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
189 __raw_writel(clk_rst, APBC_MMP2_TIMERS); 128 __raw_writel(clk_rst, APBC_TIMERS);
190 129
191 timer_init(IRQ_MMP2_TIMER1); 130 timer_init(IRQ_MMP2_TIMER1);
192} 131}
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 62d787c34475..b7f074f15498 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -18,8 +18,8 @@
18 18
19#include <asm/mach/time.h> 19#include <asm/mach/time.h>
20#include <asm/system_misc.h> 20#include <asm/system_misc.h>
21#include <mach/addr-map.h>
22#include <mach/cputype.h> 21#include <mach/cputype.h>
22#include <mach/addr-map.h>
23#include <mach/regs-apbc.h> 23#include <mach/regs-apbc.h>
24#include <mach/regs-apmu.h> 24#include <mach/regs-apmu.h>
25#include <mach/irqs.h> 25#include <mach/irqs.h>
@@ -50,62 +50,13 @@ void __init pxa168_init_irq(void)
50 icu_init_irq(); 50 icu_init_irq();
51} 51}
52 52
53/* APB peripheral clocks */
54static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
55static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
56static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
57static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
58static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
59static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
60static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
61static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
62static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
63static APBC_CLK(ssp1, PXA168_SSP1, 4, 0);
64static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
65static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
66static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
67static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
68static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
69static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
70static APBC_CLK(rtc, PXA168_RTC, 8, 32768);
71
72static APMU_CLK(nand, NAND, 0x19b, 156000000);
73static APMU_CLK(lcd, LCD, 0x7f, 312000000);
74static APMU_CLK(eth, ETH, 0x09, 0);
75static APMU_CLK(usb, USB, 0x12, 0);
76
77/* device and clock bindings */
78static struct clk_lookup pxa168_clkregs[] = {
79 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
80 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
81 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
82 INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
83 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
84 INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
85 INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
86 INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
87 INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
88 INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
89 INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
90 INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
91 INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
92 INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
93 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
94 INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
95 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
96 INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
97 INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
98 INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
99 INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
100};
101
102static int __init pxa168_init(void) 53static int __init pxa168_init(void)
103{ 54{
104 if (cpu_is_pxa168()) { 55 if (cpu_is_pxa168()) {
105 mfp_init_base(MFPR_VIRT_BASE); 56 mfp_init_base(MFPR_VIRT_BASE);
106 mfp_init_addr(pxa168_mfp_addr_map); 57 mfp_init_addr(pxa168_mfp_addr_map);
107 pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); 58 pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
108 clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); 59 pxa168_clk_init();
109 } 60 }
110 61
111 return 0; 62 return 0;
@@ -114,6 +65,7 @@ postcore_initcall(pxa168_init);
114 65
115/* system timer - clock enabled, 3.25MHz */ 66/* system timer - clock enabled, 3.25MHz */
116#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) 67#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
68#define APBC_TIMERS APBC_REG(0x34)
117 69
118static void __init pxa168_timer_init(void) 70static void __init pxa168_timer_init(void)
119{ 71{
@@ -121,10 +73,10 @@ static void __init pxa168_timer_init(void)
121 * ourselves instead of using clk_* API. Clock rate is defined 73 * ourselves instead of using clk_* API. Clock rate is defined
122 * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running 74 * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
123 */ 75 */
124 __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS); 76 __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
125 77
126 /* 3.25MHz, bus/functional clock enabled, release reset */ 78 /* 3.25MHz, bus/functional clock enabled, release reset */
127 __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS); 79 __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
128 80
129 timer_init(IRQ_PXA168_TIMER1); 81 timer_init(IRQ_PXA168_TIMER1);
130} 82}
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 6da52e9f2bdc..7d84521bb715 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -17,7 +17,6 @@
17#include <asm/mach/time.h> 17#include <asm/mach/time.h>
18#include <mach/addr-map.h> 18#include <mach/addr-map.h>
19#include <mach/regs-apbc.h> 19#include <mach/regs-apbc.h>
20#include <mach/regs-apmu.h>
21#include <mach/cputype.h> 20#include <mach/cputype.h>
22#include <mach/irqs.h> 21#include <mach/irqs.h>
23#include <mach/dma.h> 22#include <mach/dma.h>
@@ -25,7 +24,6 @@
25#include <mach/devices.h> 24#include <mach/devices.h>
26 25
27#include "common.h" 26#include "common.h"
28#include "clock.h"
29 27
30#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) 28#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
31 29
@@ -82,44 +80,13 @@ void __init pxa910_init_irq(void)
82 icu_init_irq(); 80 icu_init_irq();
83} 81}
84 82
85/* APB peripheral clocks */
86static APBC_CLK(uart1, PXA910_UART0, 1, 14745600);
87static APBC_CLK(uart2, PXA910_UART1, 1, 14745600);
88static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
89static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
90static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000);
91static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
92static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
93static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
94static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000);
95static APBC_CLK(rtc, PXA910_RTC, 8, 32768);
96
97static APMU_CLK(nand, NAND, 0x19b, 156000000);
98static APMU_CLK(u2o, USB, 0x1b, 480000000);
99
100/* device and clock bindings */
101static struct clk_lookup pxa910_clkregs[] = {
102 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
103 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
104 INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
105 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
106 INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
107 INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
108 INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
109 INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
110 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
111 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
112 INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
113 INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
114};
115
116static int __init pxa910_init(void) 83static int __init pxa910_init(void)
117{ 84{
118 if (cpu_is_pxa910()) { 85 if (cpu_is_pxa910()) {
119 mfp_init_base(MFPR_VIRT_BASE); 86 mfp_init_base(MFPR_VIRT_BASE);
120 mfp_init_addr(pxa910_mfp_addr_map); 87 mfp_init_addr(pxa910_mfp_addr_map);
121 pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); 88 pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
122 clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs)); 89 pxa910_clk_init();
123 } 90 }
124 91
125 return 0; 92 return 0;
@@ -128,12 +95,13 @@ postcore_initcall(pxa910_init);
128 95
129/* system timer - clock enabled, 3.25MHz */ 96/* system timer - clock enabled, 3.25MHz */
130#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) 97#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
98#define APBC_TIMERS APBC_REG(0x34)
131 99
132static void __init pxa910_timer_init(void) 100static void __init pxa910_timer_init(void)
133{ 101{
134 /* reset and configure */ 102 /* reset and configure */
135 __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS); 103 __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
136 __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS); 104 __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
137 105
138 timer_init(IRQ_PXA910_AP1_TIMER1); 106 timer_init(IRQ_PXA910_AP1_TIMER1);
139} 107}
diff --git a/arch/arm/mach-mmp/sram.c b/arch/arm/mach-mmp/sram.c
index 4304f9519372..7e8a5a2e1ec7 100644
--- a/arch/arm/mach-mmp/sram.c
+++ b/arch/arm/mach-mmp/sram.c
@@ -68,7 +68,7 @@ static int __devinit sram_probe(struct platform_device *pdev)
68 struct resource *res; 68 struct resource *res;
69 int ret = 0; 69 int ret = 0;
70 70
71 if (!pdata && !pdata->pool_name) 71 if (!pdata || !pdata->pool_name)
72 return -ENODEV; 72 return -ENODEV;
73 73
74 info = kzalloc(sizeof(*info), GFP_KERNEL); 74 info = kzalloc(sizeof(*info), GFP_KERNEL);
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 7764d9386f2a..137e479d15a0 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -38,7 +38,7 @@
38#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) 38#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
39#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) 39#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
40 40
41static void __init __iomem *win_cfg_base(int win) 41static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
42{ 42{
43 /* 43 /*
44 * Find the control register base address for this window. 44 * Find the control register base address for this window.
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 20826449e61b..6b0c38735527 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -208,7 +208,8 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
208{ 208{
209 orion_ge00_init(eth_data, 209 orion_ge00_init(eth_data,
210 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, 210 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
211 IRQ_MV78XX0_GE_ERR); 211 IRQ_MV78XX0_GE_ERR,
212 MV643XX_TX_CSUM_DEFAULT_LIMIT);
212} 213}
213 214
214 215
@@ -219,7 +220,8 @@ void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
219{ 220{
220 orion_ge01_init(eth_data, 221 orion_ge01_init(eth_data,
221 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, 222 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
222 NO_IRQ); 223 NO_IRQ,
224 MV643XX_TX_CSUM_DEFAULT_LIMIT);
223} 225}
224 226
225 227
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index dd2db025f778..fcd4e85c4ddc 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -62,13 +62,14 @@ config ARCH_OMAP4
62 select PM_OPP if PM 62 select PM_OPP if PM
63 select USB_ARCH_HAS_EHCI if USB_SUPPORT 63 select USB_ARCH_HAS_EHCI if USB_SUPPORT
64 select ARM_CPU_SUSPEND if PM 64 select ARM_CPU_SUSPEND if PM
65 select ARCH_NEEDS_CPU_IDLE_COUPLED 65 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
66 66
67config SOC_OMAP5 67config SOC_OMAP5
68 bool "TI OMAP5" 68 bool "TI OMAP5"
69 select CPU_V7 69 select CPU_V7
70 select ARM_GIC 70 select ARM_GIC
71 select HAVE_SMP 71 select HAVE_SMP
72 select ARM_CPU_SUSPEND if PM
72 73
73comment "OMAP Core Type" 74comment "OMAP Core Type"
74 depends on ARCH_OMAP2 75 depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 74915295482e..28214483aaba 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -554,6 +554,8 @@ static const struct usbhs_omap_board_data igep3_usbhs_bdata __initconst = {
554 554
555#ifdef CONFIG_OMAP_MUX 555#ifdef CONFIG_OMAP_MUX
556static struct omap_board_mux board_mux[] __initdata = { 556static struct omap_board_mux board_mux[] __initdata = {
557 /* SMSC9221 LAN Controller ETH IRQ (GPIO_176) */
558 OMAP3_MUX(MCSPI1_CS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
557 { .reg_offset = OMAP_MUX_TERMINATOR }, 559 { .reg_offset = OMAP_MUX_TERMINATOR },
558}; 560};
559#endif 561#endif
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index ef230a0eb5eb..0d362e9f9cb9 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -58,6 +58,7 @@
58#include "hsmmc.h" 58#include "hsmmc.h"
59#include "common-board-devices.h" 59#include "common-board-devices.h"
60 60
61#define OMAP3_EVM_TS_GPIO 175
61#define OMAP3_EVM_EHCI_VBUS 22 62#define OMAP3_EVM_EHCI_VBUS 22
62#define OMAP3_EVM_EHCI_SELECT 61 63#define OMAP3_EVM_EHCI_SELECT 61
63 64
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 14734746457c..c1875862679f 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -35,16 +35,6 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
35 .turbo_mode = 0, 35 .turbo_mode = 0,
36}; 36};
37 37
38/*
39 * ADS7846 driver maybe request a gpio according to the value
40 * of pdata->get_pendown_state, but we have done this. So set
41 * get_pendown_state to avoid twice gpio requesting.
42 */
43static int omap3_get_pendown_state(void)
44{
45 return !gpio_get_value(OMAP3_EVM_TS_GPIO);
46}
47
48static struct ads7846_platform_data ads7846_config = { 38static struct ads7846_platform_data ads7846_config = {
49 .x_max = 0x0fff, 39 .x_max = 0x0fff,
50 .y_max = 0x0fff, 40 .y_max = 0x0fff,
@@ -55,7 +45,6 @@ static struct ads7846_platform_data ads7846_config = {
55 .debounce_rep = 1, 45 .debounce_rep = 1,
56 .gpio_pendown = -EINVAL, 46 .gpio_pendown = -EINVAL,
57 .keep_vref_on = 1, 47 .keep_vref_on = 1,
58 .get_pendown_state = &omap3_get_pendown_state,
59}; 48};
60 49
61static struct spi_board_info ads7846_spi_board_info __initdata = { 50static struct spi_board_info ads7846_spi_board_info __initdata = {
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index 4c4ef6a6166b..a0b4a42836ab 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -4,7 +4,6 @@
4#include "twl-common.h" 4#include "twl-common.h"
5 5
6#define NAND_BLOCK_SIZE SZ_128K 6#define NAND_BLOCK_SIZE SZ_128K
7#define OMAP3_EVM_TS_GPIO 175
8 7
9struct mtd_partition; 8struct mtd_partition;
10struct ads7846_platform_data; 9struct ads7846_platform_data;
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index ee05e193fc61..288bee6cbb76 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -238,8 +238,9 @@ int __init omap4_idle_init(void)
238 for_each_cpu(cpu_id, cpu_online_mask) { 238 for_each_cpu(cpu_id, cpu_online_mask) {
239 dev = &per_cpu(omap4_idle_dev, cpu_id); 239 dev = &per_cpu(omap4_idle_dev, cpu_id);
240 dev->cpu = cpu_id; 240 dev->cpu = cpu_id;
241#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
241 dev->coupled_cpus = *cpu_online_mask; 242 dev->coupled_cpus = *cpu_online_mask;
242 243#endif
243 cpuidle_register_driver(&omap4_idle_driver); 244 cpuidle_register_driver(&omap4_idle_driver);
244 245
245 if (cpuidle_register_device(dev)) { 246 if (cpuidle_register_device(dev)) {
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 471e62a74a16..76f9b3c2f586 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -127,7 +127,6 @@ struct omap_mux_partition {
127 * @gpio: GPIO number 127 * @gpio: GPIO number
128 * @muxnames: available signal modes for a ball 128 * @muxnames: available signal modes for a ball
129 * @balls: available balls on the package 129 * @balls: available balls on the package
130 * @partition: mux partition
131 */ 130 */
132struct omap_mux { 131struct omap_mux {
133 u16 reg_offset; 132 u16 reg_offset;
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index 2293ba27101b..c95415da23c2 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -94,7 +94,7 @@ int __init omap4_opp_init(void)
94{ 94{
95 int r = -ENODEV; 95 int r = -ENODEV;
96 96
97 if (!cpu_is_omap44xx()) 97 if (!cpu_is_omap443x())
98 return r; 98 return r;
99 99
100 r = omap_init_opp_table(omap44xx_opp_def_list, 100 r = omap_init_opp_table(omap44xx_opp_def_list,
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e4fc88c65dbd..05bd8f02723f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -272,21 +272,16 @@ void omap_sram_idle(void)
272 per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 272 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
273 core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 273 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
274 274
275 if (mpu_next_state < PWRDM_POWER_ON) { 275 pwrdm_pre_transition(NULL);
276 pwrdm_pre_transition(mpu_pwrdm);
277 pwrdm_pre_transition(neon_pwrdm);
278 }
279 276
280 /* PER */ 277 /* PER */
281 if (per_next_state < PWRDM_POWER_ON) { 278 if (per_next_state < PWRDM_POWER_ON) {
282 pwrdm_pre_transition(per_pwrdm);
283 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; 279 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
284 omap2_gpio_prepare_for_idle(per_going_off); 280 omap2_gpio_prepare_for_idle(per_going_off);
285 } 281 }
286 282
287 /* CORE */ 283 /* CORE */
288 if (core_next_state < PWRDM_POWER_ON) { 284 if (core_next_state < PWRDM_POWER_ON) {
289 pwrdm_pre_transition(core_pwrdm);
290 if (core_next_state == PWRDM_POWER_OFF) { 285 if (core_next_state == PWRDM_POWER_OFF) {
291 omap3_core_save_context(); 286 omap3_core_save_context();
292 omap3_cm_save_context(); 287 omap3_cm_save_context();
@@ -339,20 +334,14 @@ void omap_sram_idle(void)
339 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, 334 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
340 OMAP3430_GR_MOD, 335 OMAP3430_GR_MOD,
341 OMAP3_PRM_VOLTCTRL_OFFSET); 336 OMAP3_PRM_VOLTCTRL_OFFSET);
342 pwrdm_post_transition(core_pwrdm);
343 } 337 }
344 omap3_intc_resume_idle(); 338 omap3_intc_resume_idle();
345 339
340 pwrdm_post_transition(NULL);
341
346 /* PER */ 342 /* PER */
347 if (per_next_state < PWRDM_POWER_ON) { 343 if (per_next_state < PWRDM_POWER_ON)
348 omap2_gpio_resume_after_idle(); 344 omap2_gpio_resume_after_idle();
349 pwrdm_post_transition(per_pwrdm);
350 }
351
352 if (mpu_next_state < PWRDM_POWER_ON) {
353 pwrdm_post_transition(mpu_pwrdm);
354 pwrdm_post_transition(neon_pwrdm);
355 }
356} 345}
357 346
358static void omap3_pm_idle(void) 347static void omap3_pm_idle(void)
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 9f6b83d1b193..91e71d8f46f0 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -56,9 +56,13 @@ ppa_por_params:
56 * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET. 56 * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
57 * It returns to the caller for CPU INACTIVE and ON power states or in case 57 * It returns to the caller for CPU INACTIVE and ON power states or in case
58 * CPU failed to transition to targeted OFF/DORMANT state. 58 * CPU failed to transition to targeted OFF/DORMANT state.
59 *
60 * omap4_finish_suspend() calls v7_flush_dcache_all() which doesn't save
61 * stack frame and it expects the caller to take care of it. Hence the entire
62 * stack frame is saved to avoid possible stack corruption.
59 */ 63 */
60ENTRY(omap4_finish_suspend) 64ENTRY(omap4_finish_suspend)
61 stmfd sp!, {lr} 65 stmfd sp!, {r4-r12, lr}
62 cmp r0, #0x0 66 cmp r0, #0x0
63 beq do_WFI @ No lowpower state, jump to WFI 67 beq do_WFI @ No lowpower state, jump to WFI
64 68
@@ -226,7 +230,7 @@ scu_gp_clear:
226skip_scu_gp_clear: 230skip_scu_gp_clear:
227 isb 231 isb
228 dsb 232 dsb
229 ldmfd sp!, {pc} 233 ldmfd sp!, {r4-r12, pc}
230ENDPROC(omap4_finish_suspend) 234ENDPROC(omap4_finish_suspend)
231 235
232/* 236/*
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index de47f170ba50..db5ff6642375 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -67,6 +67,7 @@ void __init omap_pmic_init(int bus, u32 clkrate,
67 const char *pmic_type, int pmic_irq, 67 const char *pmic_type, int pmic_irq,
68 struct twl4030_platform_data *pmic_data) 68 struct twl4030_platform_data *pmic_data)
69{ 69{
70 omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
70 strncpy(pmic_i2c_board_info.type, pmic_type, 71 strncpy(pmic_i2c_board_info.type, pmic_type,
71 sizeof(pmic_i2c_board_info.type)); 72 sizeof(pmic_i2c_board_info.type));
72 pmic_i2c_board_info.irq = pmic_irq; 73 pmic_i2c_board_info.irq = pmic_irq;
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 70f7d712d6f4..87a6cdabcad5 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -99,7 +99,8 @@ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
99{ 99{
100 orion_ge00_init(eth_data, 100 orion_ge00_init(eth_data,
101 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, 101 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
102 IRQ_ORION5X_ETH_ERR); 102 IRQ_ORION5X_ETH_ERR,
103 MV643XX_TX_CSUM_DEFAULT_LIMIT);
103} 104}
104 105
105 106
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index 454831b66037..ee99fd56c043 100644
--- a/arch/arm/mach-s3c24xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
@@ -24,7 +24,8 @@
24*/ 24*/
25 25
26enum dma_ch { 26enum dma_ch {
27 DMACH_XD0, 27 DMACH_DT_PROP = -1, /* not yet supported, do not use */
28 DMACH_XD0 = 0,
28 DMACH_XD1, 29 DMACH_XD1,
29 DMACH_SDI, 30 DMACH_SDI,
30 DMACH_SPI0, 31 DMACH_SPI0,
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index c013bbf79cac..53d3d46dec12 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -41,7 +41,6 @@ config MACH_HREFV60
41config MACH_SNOWBALL 41config MACH_SNOWBALL
42 bool "U8500 Snowball platform" 42 bool "U8500 Snowball platform"
43 select MACH_MOP500 43 select MACH_MOP500
44 select LEDS_GPIO
45 help 44 help
46 Include support for the snowball development platform. 45 Include support for the snowball development platform.
47 46
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index 996048038743..df15646036aa 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -191,9 +191,9 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent,
191 return pdev; 191 return pdev;
192} 192}
193 193
194/* Platform device for ASoC U8500 machine */ 194/* Platform device for ASoC MOP500 machine */
195static struct platform_device snd_soc_u8500 = { 195static struct platform_device snd_soc_mop500 = {
196 .name = "snd-soc-u8500", 196 .name = "snd-soc-mop500",
197 .id = 0, 197 .id = 0,
198 .dev = { 198 .dev = {
199 .platform_data = NULL, 199 .platform_data = NULL,
@@ -227,8 +227,8 @@ int mop500_msp_init(struct device *parent)
227{ 227{
228 struct platform_device *msp1; 228 struct platform_device *msp1;
229 229
230 pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__); 230 pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
231 platform_device_register(&snd_soc_u8500); 231 platform_device_register(&snd_soc_mop500);
232 232
233 pr_info("Initialize MSP I2S-devices.\n"); 233 pr_info("Initialize MSP I2S-devices.\n");
234 db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, 234 db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 8674a890fd1c..a534d8880de1 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -797,6 +797,7 @@ static void __init u8500_init_machine(void)
797 ARRAY_SIZE(mop500_platform_devs)); 797 ARRAY_SIZE(mop500_platform_devs));
798 798
799 mop500_sdi_init(parent); 799 mop500_sdi_init(parent);
800 mop500_msp_init(parent);
800 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); 801 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
801 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); 802 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
802 i2c_register_board_info(2, mop500_i2c2_devices, 803 i2c_register_board_info(2, mop500_i2c2_devices,
@@ -804,6 +805,8 @@ static void __init u8500_init_machine(void)
804 805
805 mop500_uib_init(); 806 mop500_uib_init();
806 807
808 } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
809 mop500_msp_init(parent);
807 } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { 810 } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
808 /* 811 /*
809 * The HREFv60 board removed a GPIO expander and routed 812 * The HREFv60 board removed a GPIO expander and routed
@@ -815,6 +818,7 @@ static void __init u8500_init_machine(void)
815 ARRAY_SIZE(mop500_platform_devs)); 818 ARRAY_SIZE(mop500_platform_devs));
816 819
817 hrefv60_sdi_init(parent); 820 hrefv60_sdi_init(parent);
821 mop500_msp_init(parent);
818 822
819 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); 823 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
820 i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; 824 i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 626ad8cad7a9..938b50a33439 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -189,6 +189,7 @@ struct omap_dm_timer *omap_dm_timer_request(void)
189 timer->reserved = 1; 189 timer->reserved = 1;
190 break; 190 break;
191 } 191 }
192 spin_unlock_irqrestore(&dm_timer_lock, flags);
192 193
193 if (timer) { 194 if (timer) {
194 ret = omap_dm_timer_prepare(timer); 195 ret = omap_dm_timer_prepare(timer);
@@ -197,7 +198,6 @@ struct omap_dm_timer *omap_dm_timer_request(void)
197 timer = NULL; 198 timer = NULL;
198 } 199 }
199 } 200 }
200 spin_unlock_irqrestore(&dm_timer_lock, flags);
201 201
202 if (!timer) 202 if (!timer)
203 pr_debug("%s: timer request failed!\n", __func__); 203 pr_debug("%s: timer request failed!\n", __func__);
@@ -220,6 +220,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
220 break; 220 break;
221 } 221 }
222 } 222 }
223 spin_unlock_irqrestore(&dm_timer_lock, flags);
223 224
224 if (timer) { 225 if (timer) {
225 ret = omap_dm_timer_prepare(timer); 226 ret = omap_dm_timer_prepare(timer);
@@ -228,7 +229,6 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
228 timer = NULL; 229 timer = NULL;
229 } 230 }
230 } 231 }
231 spin_unlock_irqrestore(&dm_timer_lock, flags);
232 232
233 if (!timer) 233 if (!timer)
234 pr_debug("%s: timer%d request failed!\n", __func__, id); 234 pr_debug("%s: timer%d request failed!\n", __func__, id);
@@ -258,7 +258,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
258 258
259void omap_dm_timer_disable(struct omap_dm_timer *timer) 259void omap_dm_timer_disable(struct omap_dm_timer *timer)
260{ 260{
261 pm_runtime_put(&timer->pdev->dev); 261 pm_runtime_put_sync(&timer->pdev->dev);
262} 262}
263EXPORT_SYMBOL_GPL(omap_dm_timer_disable); 263EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
264 264
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 68b180edcfff..bb5d08a70dbc 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -372,7 +372,8 @@ IS_OMAP_TYPE(3430, 0x3430)
372#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ 372#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
373 cpu_is_omap16xx()) 373 cpu_is_omap16xx())
374#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \ 374#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
375 cpu_is_omap44xx() || soc_is_omap54xx()) 375 cpu_is_omap44xx() || soc_is_omap54xx() || \
376 soc_is_am33xx())
376 377
377/* Various silicon revisions for omap2 */ 378/* Various silicon revisions for omap2 */
378#define OMAP242X_CLASS 0x24200024 379#define OMAP242X_CLASS 0x24200024
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index 045e320f1067..324d31b14852 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -108,4 +108,13 @@
108# endif 108# endif
109#endif 109#endif
110 110
111#ifdef CONFIG_SOC_AM33XX
112# ifdef OMAP_NAME
113# undef MULTI_OMAP2
114# define MULTI_OMAP2
115# else
116# define OMAP_NAME am33xx
117# endif
118#endif
119
111#endif /* __PLAT_OMAP_MULTI_H */ 120#endif /* __PLAT_OMAP_MULTI_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index b8d19a136781..7f7b112acccb 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -110,7 +110,7 @@ static inline void flush(void)
110 _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ 110 _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
111 AM33XXUART##p) 111 AM33XXUART##p)
112 112
113static inline void __arch_decomp_setup(unsigned long arch_id) 113static inline void arch_decomp_setup(void)
114{ 114{
115 int port = 0; 115 int port = 0;
116 116
@@ -198,8 +198,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
198 } while (0); 198 } while (0);
199} 199}
200 200
201#define arch_decomp_setup() __arch_decomp_setup(arch_id)
202
203/* 201/*
204 * nothing to do 202 * nothing to do
205 */ 203 */
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index d245a87dc014..b8b747a9d360 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -291,10 +291,12 @@ static struct platform_device orion_ge00 = {
291void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, 291void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
292 unsigned long mapbase, 292 unsigned long mapbase,
293 unsigned long irq, 293 unsigned long irq,
294 unsigned long irq_err) 294 unsigned long irq_err,
295 unsigned int tx_csum_limit)
295{ 296{
296 fill_resources(&orion_ge00_shared, orion_ge00_shared_resources, 297 fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
297 mapbase + 0x2000, SZ_16K - 1, irq_err); 298 mapbase + 0x2000, SZ_16K - 1, irq_err);
299 orion_ge00_shared_data.tx_csum_limit = tx_csum_limit;
298 ge_complete(&orion_ge00_shared_data, 300 ge_complete(&orion_ge00_shared_data,
299 orion_ge00_resources, irq, &orion_ge00_shared, 301 orion_ge00_resources, irq, &orion_ge00_shared,
300 eth_data, &orion_ge00); 302 eth_data, &orion_ge00);
@@ -343,10 +345,12 @@ static struct platform_device orion_ge01 = {
343void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, 345void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
344 unsigned long mapbase, 346 unsigned long mapbase,
345 unsigned long irq, 347 unsigned long irq,
346 unsigned long irq_err) 348 unsigned long irq_err,
349 unsigned int tx_csum_limit)
347{ 350{
348 fill_resources(&orion_ge01_shared, orion_ge01_shared_resources, 351 fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
349 mapbase + 0x2000, SZ_16K - 1, irq_err); 352 mapbase + 0x2000, SZ_16K - 1, irq_err);
353 orion_ge01_shared_data.tx_csum_limit = tx_csum_limit;
350 ge_complete(&orion_ge01_shared_data, 354 ge_complete(&orion_ge01_shared_data,
351 orion_ge01_resources, irq, &orion_ge01_shared, 355 orion_ge01_resources, irq, &orion_ge01_shared,
352 eth_data, &orion_ge01); 356 eth_data, &orion_ge01);
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index e00fdb213609..ae2377ef63e5 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -39,12 +39,14 @@ void __init orion_rtc_init(unsigned long mapbase,
39void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, 39void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
40 unsigned long mapbase, 40 unsigned long mapbase,
41 unsigned long irq, 41 unsigned long irq,
42 unsigned long irq_err); 42 unsigned long irq_err,
43 unsigned int tx_csum_limit);
43 44
44void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, 45void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
45 unsigned long mapbase, 46 unsigned long mapbase,
46 unsigned long irq, 47 unsigned long irq,
47 unsigned long irq_err); 48 unsigned long irq_err,
49 unsigned int tx_csum_limit);
48 50
49void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, 51void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
50 unsigned long mapbase, 52 unsigned long mapbase,
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 28f898f75380..db98e7021f0d 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -430,7 +430,7 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
430 * when necessary. 430 * when necessary.
431*/ 431*/
432 432
433int s3c2410_dma_enqueue(unsigned int channel, void *id, 433int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
434 dma_addr_t data, int size) 434 dma_addr_t data, int size)
435{ 435{
436 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); 436 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 8154fab70de8..6ff45d53362c 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -32,6 +32,8 @@
32#include <linux/platform_data/s3c-hsudc.h> 32#include <linux/platform_data/s3c-hsudc.h>
33#include <linux/platform_data/s3c-hsotg.h> 33#include <linux/platform_data/s3c-hsotg.h>
34 34
35#include <media/s5p_hdmi.h>
36
35#include <asm/irq.h> 37#include <asm/irq.h>
36#include <asm/mach/arch.h> 38#include <asm/mach/arch.h>
37#include <asm/mach/map.h> 39#include <asm/mach/map.h>
@@ -747,7 +749,8 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
747 if (!pd) { 749 if (!pd) {
748 pd = &default_i2c_data; 750 pd = &default_i2c_data;
749 751
750 if (soc_is_exynos4210()) 752 if (soc_is_exynos4210() ||
753 soc_is_exynos4212() || soc_is_exynos4412())
751 pd->bus_num = 8; 754 pd->bus_num = 8;
752 else if (soc_is_s5pv210()) 755 else if (soc_is_s5pv210())
753 pd->bus_num = 3; 756 pd->bus_num = 3;
@@ -758,6 +761,30 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
758 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), 761 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
759 &s5p_device_i2c_hdmiphy); 762 &s5p_device_i2c_hdmiphy);
760} 763}
764
765struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
766
767void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
768 struct i2c_board_info *mhl_info, int mhl_bus)
769{
770 struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
771
772 if (soc_is_exynos4210() ||
773 soc_is_exynos4212() || soc_is_exynos4412())
774 pd->hdmiphy_bus = 8;
775 else if (soc_is_s5pv210())
776 pd->hdmiphy_bus = 3;
777 else
778 pd->hdmiphy_bus = 0;
779
780 pd->hdmiphy_info = hdmiphy_info;
781 pd->mhl_info = mhl_info;
782 pd->mhl_bus = mhl_bus;
783
784 s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
785 &s5p_device_hdmi);
786}
787
761#endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */ 788#endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
762 789
763/* I2S */ 790/* I2S */
diff --git a/arch/arm/plat-samsung/include/plat/hdmi.h b/arch/arm/plat-samsung/include/plat/hdmi.h
new file mode 100644
index 000000000000..331d046ac2c5
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/hdmi.h
@@ -0,0 +1,16 @@
1/*
2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __PLAT_SAMSUNG_HDMI_H
11#define __PLAT_SAMSUNG_HDMI_H __FILE__
12
13extern void s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
14 struct i2c_board_info *mhl_info, int mhl_bus);
15
16#endif /* __PLAT_SAMSUNG_HDMI_H */
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 64ab65f0fdbc..15070284343e 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -74,7 +74,7 @@ unsigned char pm_uart_udivslot;
74 74
75#ifdef CONFIG_SAMSUNG_PM_DEBUG 75#ifdef CONFIG_SAMSUNG_PM_DEBUG
76 76
77struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; 77static struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
78 78
79static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save) 79static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
80{ 80{
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 16:39:33 -0500