Merge branch 'for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata

Pull libata updates from Tejun Heo:
 "A lot of activities on libata side this time.

   - A lot of changes around ahci.  Various embedded platforms are
     implementing ahci controllers.  Some were built atop ahci_platform,
     others were doing their own things.  Hans made some structural
     changes to libahci and librarized ahci_platform so that ahci
     platform drivers can share more common code.  A couple platform
     drivers are added on top of that and several are added to replace
     older drivers which were doing their own things (older ones are
     scheduled to be removed).

   - Dan finishes the patchset to make libata PM operations
     asynchronous.  Combined with one patch being routed through scsi,
     this should speed resume measurably.

   - Various fixes and cleanups from Bartlomiej and others"

* 'for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: (61 commits)
  ata: fix Marvell SATA driver dependencies
  ata: fix ARASAN CompactFlash PATA driver dependencies
  ata: remove superfluous casts
  ata: sata_highbank: remove superfluous cast
  ata: fix Calxeda Highbank SATA driver dependencies
  ata: fix R-Car SATA driver dependencies
  ARM: davinci: da850: update SATA AHCI support
  ata: add new-style AHCI platform driver for DaVinci DA850 AHCI controller
  ata: move library code from ahci_platform.c to libahci_platform.c
  ata: ahci_platform: fix ahci_platform_data->suspend method handling
  libata: remove unused ata_sas_port_async_resume() stub
  libata.h: add stub for ata_sas_port_resume
  libata: async resume
  libata, libsas: kill pm_result and related cleanup
  ata: Fix compiler warning with APM X-Gene host controller driver
  arm64: Add APM X-Gene SoC AHCI SATA host controller DTS entries
  ata: Add APM X-Gene SoC AHCI SATA host controller driver
  Documentation: Add documentation for the APM X-Gene SoC SATA host controller DTS binding
  arm64: Add APM X-Gene SoC 15Gbps Multi-purpose PHY DTS entries
  ata: ahci_sunxi: fix code formatting
  ...

1 files changed, 152 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi
index d37d7369e260..93f4b2dd9248 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -176,6 +176,87 @@
                                 reg-names = "csr-reg";
                                 clock-output-names = "eth8clk";
                         };
+
+                        sataphy1clk: sataphy1clk@1f21c000 {
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f21c000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "sataphy1clk";
+                                status = "disabled";
+                                csr-offset = <0x4>;
+                                csr-mask = <0x00>;
+                                enable-offset = <0x0>;
+                                enable-mask = <0x06>;
+                        };
+
+                        sataphy2clk: sataphy1clk@1f22c000 {
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f22c000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "sataphy2clk";
+                                status = "ok";
+                                csr-offset = <0x4>;
+                                csr-mask = <0x3a>;
+                                enable-offset = <0x0>;
+                                enable-mask = <0x06>;
+                        };
+
+                        sataphy3clk: sataphy1clk@1f23c000 {
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f23c000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "sataphy3clk";
+                                status = "ok";
+                                csr-offset = <0x4>;
+                                csr-mask = <0x3a>;
+                                enable-offset = <0x0>;
+                                enable-mask = <0x06>;
+                        };
+
+                        sata01clk: sata01clk@1f21c000 {
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f21c000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "sata01clk";
+                                csr-offset = <0x4>;
+                                csr-mask = <0x05>;
+                                enable-offset = <0x0>;
+                                enable-mask = <0x39>;
+                        };
+
+                        sata23clk: sata23clk@1f22c000 {
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f22c000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "sata23clk";
+                                csr-offset = <0x4>;
+                                csr-mask = <0x05>;
+                                enable-offset = <0x0>;
+                                enable-mask = <0x39>;
+                        };
+
+                        sata45clk: sata45clk@1f23c000 {
+                                compatible = "apm,xgene-device-clock";
+                                #clock-cells = <1>;
+                                clocks = <&socplldiv2 0>;
+                                reg = <0x0 0x1f23c000 0x0 0x1000>;
+                                reg-names = "csr-reg";
+                                clock-output-names = "sata45clk";
+                                csr-offset = <0x4>;
+                                csr-mask = <0x05>;
+                                enable-offset = <0x0>;
+                                enable-mask = <0x39>;
+                        };
                 };
 
                 serial0: serial@1c020000 {
@@ -187,5 +268,76 @@
                         interrupt-parent = <&gic>;
                         interrupts = <0x0 0x4c 0x4>;
                 };
+
+                phy1: phy@1f21a000 {
+                        compatible = "apm,xgene-phy";
+                        reg = <0x0 0x1f21a000 0x0 0x100>;
+                        #phy-cells = <1>;
+                        clocks = <&sataphy1clk 0>;
+                        status = "disabled";
+                        apm,tx-boost-gain = <30 30 30 30 30 30>;
+                        apm,tx-eye-tuning = <2 10 10 2 10 10>;
+                };
+
+                phy2: phy@1f22a000 {
+                        compatible = "apm,xgene-phy";
+                        reg = <0x0 0x1f22a000 0x0 0x100>;
+                        #phy-cells = <1>;
+                        clocks = <&sataphy2clk 0>;
+                        status = "ok";
+                        apm,tx-boost-gain = <30 30 30 30 30 30>;
+                        apm,tx-eye-tuning = <1 10 10 2 10 10>;
+                };
+
+                phy3: phy@1f23a000 {
+                        compatible = "apm,xgene-phy";
+                        reg = <0x0 0x1f23a000 0x0 0x100>;
+                        #phy-cells = <1>;
+                        clocks = <&sataphy3clk 0>;
+                        status = "ok";
+                        apm,tx-boost-gain = <31 31 31 31 31 31>;
+                        apm,tx-eye-tuning = <2 10 10 2 10 10>;
+                };
+
+                sata1: sata@1a000000 {
+                        compatible = "apm,xgene-ahci";
+                        reg = <0x0 0x1a000000 0x0 0x1000>,
+                              <0x0 0x1f210000 0x0 0x1000>,
+                              <0x0 0x1f21d000 0x0 0x1000>,
+                              <0x0 0x1f21e000 0x0 0x1000>,
+                              <0x0 0x1f217000 0x0 0x1000>;
+                        interrupts = <0x0 0x86 0x4>;
+                        status = "disabled";
+                        clocks = <&sata01clk 0>;
+                        phys = <&phy1 0>;
+                        phy-names = "sata-phy";
+                };
+
+                sata2: sata@1a400000 {
+                        compatible = "apm,xgene-ahci";
+                        reg = <0x0 0x1a400000 0x0 0x1000>,
+                              <0x0 0x1f220000 0x0 0x1000>,
+                              <0x0 0x1f22d000 0x0 0x1000>,
+                              <0x0 0x1f22e000 0x0 0x1000>,
+                              <0x0 0x1f227000 0x0 0x1000>;
+                        interrupts = <0x0 0x87 0x4>;
+                        status = "ok";
+                        clocks = <&sata23clk 0>;
+                        phys = <&phy2 0>;
+                        phy-names = "sata-phy";
+                };
+
+                sata3: sata@1a800000 {
+                        compatible = "apm,xgene-ahci";
+                        reg = <0x0 0x1a800000 0x0 0x1000>,
+                              <0x0 0x1f230000 0x0 0x1000>,
+                              <0x0 0x1f23d000 0x0 0x1000>,
+                              <0x0 0x1f23e000 0x0 0x1000>;
+                        interrupts = <0x0 0x88 0x4>;
+                        status = "ok";
+                        clocks = <&sata45clk 0>;
+                        phys = <&phy3 0>;
+                        phy-names = "sata-phy";
+                };
         };
 };