diff options
author | Jingoo Han <jg1.han@samsung.com> | 2014-01-20 00:00:21 -0500 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2014-01-22 11:23:58 -0500 |
commit | bd5f6dc304a054ccdc8dab43bef5e41d9a575b61 (patch) | |
tree | 9ebc7702dc516cb52a8ec85ee5ae6ebb222cf021 /arch/arm64/mm | |
parent | 883c057367014d20a14b5054e4eb0d81ce3bea5c (diff) |
arm64: mm: use ubfm for dcache_line_size
Use 'ubfm' for the bitfield move instruction; thus, single
instruction can be used instead of two instructions, when
getting the minimum D-cache line size from CTR_EL0 register.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm')
-rw-r--r-- | arch/arm64/mm/proc-macros.S | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm64/mm/proc-macros.S b/arch/arm64/mm/proc-macros.S index 8957b822010b..005d29e2977d 100644 --- a/arch/arm64/mm/proc-macros.S +++ b/arch/arm64/mm/proc-macros.S | |||
@@ -38,8 +38,7 @@ | |||
38 | */ | 38 | */ |
39 | .macro dcache_line_size, reg, tmp | 39 | .macro dcache_line_size, reg, tmp |
40 | mrs \tmp, ctr_el0 // read CTR | 40 | mrs \tmp, ctr_el0 // read CTR |
41 | lsr \tmp, \tmp, #16 | 41 | ubfm \tmp, \tmp, #16, #19 // cache line size encoding |
42 | and \tmp, \tmp, #0xf // cache line size encoding | ||
43 | mov \reg, #4 // bytes per word | 42 | mov \reg, #4 // bytes per word |
44 | lsl \reg, \reg, \tmp // actual cache line size | 43 | lsl \reg, \reg, \tmp // actual cache line size |
45 | .endm | 44 | .endm |