diff options
author | Vladimir Murzin <vladimir.murzin@arm.com> | 2014-12-01 05:53:08 -0500 |
---|---|---|
committer | Will Deacon <will.deacon@arm.com> | 2014-12-01 08:31:12 -0500 |
commit | a2d25a5391ca219f196f9fee7b535c40d201c6bf (patch) | |
tree | 4b2e208ebac21cf53793db6ba4ed5a74b04a6d59 /arch/arm64/mm | |
parent | a1ae65b219416a72c15577bd4c8c11174fffbb8b (diff) |
arm64: compat: align cacheflush syscall with arch/arm
Update handling of cacheflush syscall with changes made in arch/arm
counterpart:
- return error to userspace when flushing syscall fails
- split user cache-flushing into interruptible chunks
- don't bother rounding to nearest vma
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
[will: changed internal return value from -EINTR to 0 to match arch/arm/]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/mm')
-rw-r--r-- | arch/arm64/mm/cache.S | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 8eaf18577d71..2560e1e1562e 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S | |||
@@ -17,6 +17,7 @@ | |||
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
18 | */ | 18 | */ |
19 | 19 | ||
20 | #include <linux/errno.h> | ||
20 | #include <linux/linkage.h> | 21 | #include <linux/linkage.h> |
21 | #include <linux/init.h> | 22 | #include <linux/init.h> |
22 | #include <asm/assembler.h> | 23 | #include <asm/assembler.h> |
@@ -140,9 +141,12 @@ USER(9f, ic ivau, x4 ) // invalidate I line PoU | |||
140 | add x4, x4, x2 | 141 | add x4, x4, x2 |
141 | cmp x4, x1 | 142 | cmp x4, x1 |
142 | b.lo 1b | 143 | b.lo 1b |
143 | 9: // ignore any faulting cache operation | ||
144 | dsb ish | 144 | dsb ish |
145 | isb | 145 | isb |
146 | mov x0, #0 | ||
147 | ret | ||
148 | 9: | ||
149 | mov x0, #-EFAULT | ||
146 | ret | 150 | ret |
147 | ENDPROC(flush_icache_range) | 151 | ENDPROC(flush_icache_range) |
148 | ENDPROC(__flush_cache_user_range) | 152 | ENDPROC(__flush_cache_user_range) |