diff options
author | Matthew Leach <matthew.leach@arm.com> | 2013-09-25 11:33:13 -0400 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2013-09-25 11:42:23 -0400 |
commit | fc18047c732f6becba92618a397555927687efd3 (patch) | |
tree | ecb437b28ddd3b3e4c90aecc9364e6d2f92a0d5a /arch/arm64/mm/tlb.S | |
parent | 1f65c13efef69b6dc908e588f91a133641d8475c (diff) |
arm64: use correct register width when retrieving ASID
The ASID is represented as an unsigned int in mm_context_t and we
currently use the mmid assembler macro to access this element of the
struct. This should be accessed with a register of 32-bit width. If
the incorrect register width is used the ASID will be returned in
bits[32:63] of the register when running under big-endian.
Fix a use of the mmid macro in tlb.S to use a 32-bit access.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm/tlb.S')
-rw-r--r-- | arch/arm64/mm/tlb.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/mm/tlb.S b/arch/arm64/mm/tlb.S index 8ae80a18e8ec..19da91e0cd27 100644 --- a/arch/arm64/mm/tlb.S +++ b/arch/arm64/mm/tlb.S | |||
@@ -35,7 +35,7 @@ | |||
35 | */ | 35 | */ |
36 | ENTRY(__cpu_flush_user_tlb_range) | 36 | ENTRY(__cpu_flush_user_tlb_range) |
37 | vma_vm_mm x3, x2 // get vma->vm_mm | 37 | vma_vm_mm x3, x2 // get vma->vm_mm |
38 | mmid x3, x3 // get vm_mm->context.id | 38 | mmid w3, x3 // get vm_mm->context.id |
39 | dsb sy | 39 | dsb sy |
40 | lsr x0, x0, #12 // align address | 40 | lsr x0, x0, #12 // align address |
41 | lsr x1, x1, #12 | 41 | lsr x1, x1, #12 |