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authorCatalin Marinas <catalin.marinas@arm.com>2012-03-05 06:49:28 -0500
committerCatalin Marinas <catalin.marinas@arm.com>2012-09-17 08:41:59 -0400
commit9cce7a435f89c9e60f244d44da2cf1cf4ed094ac (patch)
tree7e207bd1afe61abebeabc6b22b8128c7654372a9 /arch/arm64/mm/proc.S
parentb3901d54dc4f73acdc6b7c6e5a7a496d3afeae61 (diff)
arm64: CPU support
This patch adds AArch64 CPU specific functionality. It assumes that the implementation is generic to AArch64 and does not require specific identification. Different CPU implementations may require the setting of various ACTLR_EL1 bits but such information is not currently available and it should ideally be pushed to firmware. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm64/mm/proc.S')
-rw-r--r--arch/arm64/mm/proc.S186
1 files changed, 186 insertions, 0 deletions
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
new file mode 100644
index 000000000000..720aa0b3bee8
--- /dev/null
+++ b/arch/arm64/mm/proc.S
@@ -0,0 +1,186 @@
1/*
2 * Based on arch/arm/mm/proc.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/init.h>
22#include <linux/linkage.h>
23#include <asm/assembler.h>
24#include <asm/asm-offsets.h>
25#include <asm/hwcap.h>
26#include <asm/pgtable-hwdef.h>
27#include <asm/pgtable.h>
28
29#include "proc-macros.S"
30
31#ifndef CONFIG_SMP
32/* PTWs cacheable, inner/outer WBWA not shareable */
33#define TCR_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
34#else
35/* PTWs cacheable, inner/outer WBWA shareable */
36#define TCR_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA | TCR_SHARED
37#endif
38
39#define MAIR(attr, mt) ((attr) << ((mt) * 8))
40
41/*
42 * cpu_cache_off()
43 *
44 * Turn the CPU D-cache off.
45 */
46ENTRY(cpu_cache_off)
47 mrs x0, sctlr_el1
48 bic x0, x0, #1 << 2 // clear SCTLR.C
49 msr sctlr_el1, x0
50 isb
51 ret
52ENDPROC(cpu_cache_off)
53
54/*
55 * cpu_reset(loc)
56 *
57 * Perform a soft reset of the system. Put the CPU into the same state
58 * as it would be if it had been reset, and branch to what would be the
59 * reset vector. It must be executed with the flat identity mapping.
60 *
61 * - loc - location to jump to for soft reset
62 */
63 .align 5
64ENTRY(cpu_reset)
65 mrs x1, sctlr_el1
66 bic x1, x1, #1
67 msr sctlr_el1, x1 // disable the MMU
68 isb
69 ret x0
70ENDPROC(cpu_reset)
71
72/*
73 * cpu_do_idle()
74 *
75 * Idle the processor (wait for interrupt).
76 */
77ENTRY(cpu_do_idle)
78 dsb sy // WFI may enter a low-power mode
79 wfi
80 ret
81ENDPROC(cpu_do_idle)
82
83/*
84 * cpu_switch_mm(pgd_phys, tsk)
85 *
86 * Set the translation table base pointer to be pgd_phys.
87 *
88 * - pgd_phys - physical address of new TTB
89 */
90ENTRY(cpu_do_switch_mm)
91 mmid w1, x1 // get mm->context.id
92 bfi x0, x1, #48, #16 // set the ASID
93 msr ttbr0_el1, x0 // set TTBR0
94 isb
95 ret
96ENDPROC(cpu_do_switch_mm)
97
98cpu_name:
99 .ascii "AArch64 Processor"
100 .align
101
102 .section ".text.init", #alloc, #execinstr
103
104/*
105 * __cpu_setup
106 *
107 * Initialise the processor for turning the MMU on. Return in x0 the
108 * value of the SCTLR_EL1 register.
109 */
110ENTRY(__cpu_setup)
111#ifdef CONFIG_SMP
112 /* TODO: only do this for certain CPUs */
113 /*
114 * Enable SMP/nAMP mode.
115 */
116 mrs x0, actlr_el1
117 tbnz x0, #6, 1f // already enabled?
118 orr x0, x0, #1 << 6
119 msr actlr_el1, x0
1201:
121#endif
122 /*
123 * Preserve the link register across the function call.
124 */
125 mov x28, lr
126 bl __flush_dcache_all
127 mov lr, x28
128 ic iallu // I+BTB cache invalidate
129 dsb sy
130
131 mov x0, #3 << 20
132 msr cpacr_el1, x0 // Enable FP/ASIMD
133 mov x0, #1
134 msr oslar_el1, x0 // Set the debug OS lock
135 tlbi vmalle1is // invalidate I + D TLBs
136 /*
137 * Memory region attributes for LPAE:
138 *
139 * n = AttrIndx[2:0]
140 * n MAIR
141 * DEVICE_nGnRnE 000 00000000
142 * DEVICE_nGnRE 001 00000100
143 * DEVICE_GRE 010 00001100
144 * NORMAL_NC 011 01000100
145 * NORMAL 100 11111111
146 */
147 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
148 MAIR(0x04, MT_DEVICE_nGnRE) | \
149 MAIR(0x0c, MT_DEVICE_GRE) | \
150 MAIR(0x44, MT_NORMAL_NC) | \
151 MAIR(0xff, MT_NORMAL)
152 msr mair_el1, x5
153 /*
154 * Prepare SCTLR
155 */
156 adr x5, crval
157 ldp w5, w6, [x5]
158 mrs x0, sctlr_el1
159 bic x0, x0, x5 // clear bits
160 orr x0, x0, x6 // set bits
161 /*
162 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
163 * both user and kernel.
164 */
165 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \
166 TCR_ASID16 | (1 << 31)
167#ifdef CONFIG_ARM64_64K_PAGES
168 orr x10, x10, TCR_TG0_64K
169 orr x10, x10, TCR_TG1_64K
170#endif
171 msr tcr_el1, x10
172 ret // return to head.S
173ENDPROC(__cpu_setup)
174
175 /*
176 * n n T
177 * U E WT T UD US IHBS
178 * CE0 XWHW CZ ME TEEA S
179 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
180 * 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved
181 * .... .100 .... 01.1 11.1 ..01 0001 1101 < software settings
182 */
183 .type crval, #object
184crval:
185 .word 0x030802e2 // clear
186 .word 0x0405d11d // set
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