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authorCatalin Marinas <catalin.marinas@arm.com>2013-05-21 12:35:19 -0400
committerCatalin Marinas <catalin.marinas@arm.com>2014-02-27 12:16:59 -0500
commit7363590d2c4691593fd280f94b3deaeb5e83dbbd (patch)
tree892b7ac3974015dd23401a1d993cbd930cee2fb9 /arch/arm64/mm/cache.S
parent3690951fc6d42f3a0903987677d0e592c49dd8db (diff)
arm64: Implement coherent DMA API based on swiotlb
This patch adds support for DMA API cache maintenance on SoCs without hardware device cache coherency. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm/cache.S')
-rw-r--r--arch/arm64/mm/cache.S78
1 files changed, 78 insertions, 0 deletions
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 1ea9f26d1b70..97fcef535a8a 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -166,3 +166,81 @@ ENTRY(__flush_dcache_area)
166 dsb sy 166 dsb sy
167 ret 167 ret
168ENDPROC(__flush_dcache_area) 168ENDPROC(__flush_dcache_area)
169
170/*
171 * __dma_inv_range(start, end)
172 * - start - virtual start address of region
173 * - end - virtual end address of region
174 */
175__dma_inv_range:
176 dcache_line_size x2, x3
177 sub x3, x2, #1
178 bic x0, x0, x3
179 bic x1, x1, x3
1801: dc ivac, x0 // invalidate D / U line
181 add x0, x0, x2
182 cmp x0, x1
183 b.lo 1b
184 dsb sy
185 ret
186ENDPROC(__dma_inv_range)
187
188/*
189 * __dma_clean_range(start, end)
190 * - start - virtual start address of region
191 * - end - virtual end address of region
192 */
193__dma_clean_range:
194 dcache_line_size x2, x3
195 sub x3, x2, #1
196 bic x0, x0, x3
1971: dc cvac, x0 // clean D / U line
198 add x0, x0, x2
199 cmp x0, x1
200 b.lo 1b
201 dsb sy
202 ret
203ENDPROC(__dma_clean_range)
204
205/*
206 * __dma_flush_range(start, end)
207 * - start - virtual start address of region
208 * - end - virtual end address of region
209 */
210ENTRY(__dma_flush_range)
211 dcache_line_size x2, x3
212 sub x3, x2, #1
213 bic x0, x0, x3
2141: dc civac, x0 // clean & invalidate D / U line
215 add x0, x0, x2
216 cmp x0, x1
217 b.lo 1b
218 dsb sy
219 ret
220ENDPROC(__dma_flush_range)
221
222/*
223 * __dma_map_area(start, size, dir)
224 * - start - kernel virtual start address
225 * - size - size of region
226 * - dir - DMA direction
227 */
228ENTRY(__dma_map_area)
229 add x1, x1, x0
230 cmp w2, #DMA_FROM_DEVICE
231 b.eq __dma_inv_range
232 b __dma_clean_range
233ENDPROC(__dma_map_area)
234
235/*
236 * __dma_unmap_area(start, size, dir)
237 * - start - kernel virtual start address
238 * - size - size of region
239 * - dir - DMA direction
240 */
241ENTRY(__dma_unmap_area)
242 add x1, x1, x0
243 cmp w2, #DMA_TO_DEVICE
244 b.ne __dma_inv_range
245 ret
246ENDPROC(__dma_unmap_area)