arm64: errata: add workaround for cortex-a53 erratum #845719

When running a compat (AArch32) userspace on Cortex-A53, a load at EL0
from a virtual address that matches the bottom 32 bits of the virtual
address used by a recent load at (AArch64) EL1 might return incorrect
data.

This patch works around the issue by writing to the contextidr_el1
register on the exception return path when returning to a 32-bit task.
This workaround is patched in at runtime based on the MIDR value of the
processor.

Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

2 files changed, 28 insertions, 0 deletions

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index a66f4fa4d541..4672860def1f 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -73,6 +73,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
                 MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 0x12),
         },
 #endif
+#ifdef CONFIG_ARM64_ERRATUM_845719
+        {
+        /* Cortex-A53 r0p[01234] */
+                .desc = "ARM erratum 845719",
+                .capability = ARM64_WORKAROUND_845719,
+                MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
+        },
+#endif
         {
         }
 };
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index cf21bb3bf752..959fe8733560 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -21,8 +21,10 @@
 #include <linux/init.h>
 #include <linux/linkage.h>
 
+#include <asm/alternative-asm.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/cpufeature.h>
 #include <asm/errno.h>
 #include <asm/esr.h>
 #include <asm/thread_info.h>
@@ -120,6 +122,24 @@
         ct_user_enter
         ldr     x23, [sp, #S_SP]                // load return stack pointer
         msr     sp_el0, x23
+
+#ifdef CONFIG_ARM64_ERRATUM_845719
+        alternative_insn                                                \
+        "nop",                                                          \
+        "tbz x22, #4, 1f",                                              \
+        ARM64_WORKAROUND_845719
+#ifdef CONFIG_PID_IN_CONTEXTIDR
+        alternative_insn                                                \
+        "nop; nop",                                                     \
+        "mrs x29, contextidr_el1; msr contextidr_el1, x29; 1:",         \
+        ARM64_WORKAROUND_845719
+#else
+        alternative_insn                                                \
+        "nop",                                                          \
+        "msr contextidr_el1, xzr; 1:",                                  \
+        ARM64_WORKAROUND_845719
+#endif
+#endif
         .endif
         msr     elr_el1, x21                    // set up the return data
         msr     spsr_el1, x22