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authorAndre Przywara <andre.przywara@arm.com>2014-11-14 10:54:11 -0500
committerWill Deacon <will.deacon@arm.com>2014-11-25 10:56:42 -0500
commit5afaa1fc1b320cec48affa7e6949f2493f875c12 (patch)
tree6d7d20ce61c2939548c6b5105bc5130c4f7191ac /arch/arm64/kernel
parent301bcfac42897dbd1b0b3c1be49f24654a1bc49e (diff)
arm64: add Cortex-A57 erratum 832075 workaround
The ARM erratum 832075 applies to certain revisions of Cortex-A57, one of the workarounds is to change device loads into using load-aquire semantics. This is achieved using the alternatives framework. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/kernel')
-rw-r--r--arch/arm64/kernel/cpu_errata.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index e107ed2d66dc..30935d2da55a 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -24,6 +24,7 @@
24#include <asm/cpufeature.h> 24#include <asm/cpufeature.h>
25 25
26#define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) 26#define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
27#define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
27 28
28/* 29/*
29 * Add a struct or another datatype to the union below if you need 30 * Add a struct or another datatype to the union below if you need
@@ -71,6 +72,12 @@ struct arm64_cpu_capabilities arm64_errata[] = {
71 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02), 72 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
72 }, 73 },
73 { 74 {
75 /* Cortex-A57 r0p0 - r1p2 */
76 .desc = "ARM erratum 832075",
77 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
78 MIDR_RANGE(MIDR_CORTEX_A57, 0x00, 0x12),
79 },
80 {
74 } 81 }
75}; 82};
76 83