diff options
author | Marc Zyngier <marc.zyngier@arm.com> | 2012-12-10 05:46:47 -0500 |
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committer | Marc Zyngier <marc.zyngier@arm.com> | 2013-06-07 09:03:32 -0400 |
commit | 0369f6a34b9facd16eea4236518ca6f9cbc9e5ef (patch) | |
tree | cc19286669be680bc54b96eaac3a5baa1bc6aa7c /arch/arm64/include | |
parent | 2240bbb697354f5617d95e3ee104ca61bb812507 (diff) |
arm64: KVM: EL2 register definitions
Define all the useful bitfields for EL2 registers.
Reviewed-by: Christopher Covington <cov@codeaurora.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm64/include')
-rw-r--r-- | arch/arm64/include/asm/kvm_arm.h | 245 |
1 files changed, 245 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h new file mode 100644 index 000000000000..a5f28e2720c7 --- /dev/null +++ b/arch/arm64/include/asm/kvm_arm.h | |||
@@ -0,0 +1,245 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012,2013 - ARM Ltd | ||
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
16 | */ | ||
17 | |||
18 | #ifndef __ARM64_KVM_ARM_H__ | ||
19 | #define __ARM64_KVM_ARM_H__ | ||
20 | |||
21 | #include <asm/types.h> | ||
22 | |||
23 | /* Hyp Configuration Register (HCR) bits */ | ||
24 | #define HCR_ID (UL(1) << 33) | ||
25 | #define HCR_CD (UL(1) << 32) | ||
26 | #define HCR_RW_SHIFT 31 | ||
27 | #define HCR_RW (UL(1) << HCR_RW_SHIFT) | ||
28 | #define HCR_TRVM (UL(1) << 30) | ||
29 | #define HCR_HCD (UL(1) << 29) | ||
30 | #define HCR_TDZ (UL(1) << 28) | ||
31 | #define HCR_TGE (UL(1) << 27) | ||
32 | #define HCR_TVM (UL(1) << 26) | ||
33 | #define HCR_TTLB (UL(1) << 25) | ||
34 | #define HCR_TPU (UL(1) << 24) | ||
35 | #define HCR_TPC (UL(1) << 23) | ||
36 | #define HCR_TSW (UL(1) << 22) | ||
37 | #define HCR_TAC (UL(1) << 21) | ||
38 | #define HCR_TIDCP (UL(1) << 20) | ||
39 | #define HCR_TSC (UL(1) << 19) | ||
40 | #define HCR_TID3 (UL(1) << 18) | ||
41 | #define HCR_TID2 (UL(1) << 17) | ||
42 | #define HCR_TID1 (UL(1) << 16) | ||
43 | #define HCR_TID0 (UL(1) << 15) | ||
44 | #define HCR_TWE (UL(1) << 14) | ||
45 | #define HCR_TWI (UL(1) << 13) | ||
46 | #define HCR_DC (UL(1) << 12) | ||
47 | #define HCR_BSU (3 << 10) | ||
48 | #define HCR_BSU_IS (UL(1) << 10) | ||
49 | #define HCR_FB (UL(1) << 9) | ||
50 | #define HCR_VA (UL(1) << 8) | ||
51 | #define HCR_VI (UL(1) << 7) | ||
52 | #define HCR_VF (UL(1) << 6) | ||
53 | #define HCR_AMO (UL(1) << 5) | ||
54 | #define HCR_IMO (UL(1) << 4) | ||
55 | #define HCR_FMO (UL(1) << 3) | ||
56 | #define HCR_PTW (UL(1) << 2) | ||
57 | #define HCR_SWIO (UL(1) << 1) | ||
58 | #define HCR_VM (UL(1) << 0) | ||
59 | |||
60 | /* | ||
61 | * The bits we set in HCR: | ||
62 | * RW: 64bit by default, can be overriden for 32bit VMs | ||
63 | * TAC: Trap ACTLR | ||
64 | * TSC: Trap SMC | ||
65 | * TSW: Trap cache operations by set/way | ||
66 | * TWI: Trap WFI | ||
67 | * TIDCP: Trap L2CTLR/L2ECTLR | ||
68 | * BSU_IS: Upgrade barriers to the inner shareable domain | ||
69 | * FB: Force broadcast of all maintainance operations | ||
70 | * AMO: Override CPSR.A and enable signaling with VA | ||
71 | * IMO: Override CPSR.I and enable signaling with VI | ||
72 | * FMO: Override CPSR.F and enable signaling with VF | ||
73 | * SWIO: Turn set/way invalidates into set/way clean+invalidate | ||
74 | */ | ||
75 | #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \ | ||
76 | HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \ | ||
77 | HCR_SWIO | HCR_TIDCP | HCR_RW) | ||
78 | #define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF) | ||
79 | |||
80 | /* Hyp System Control Register (SCTLR_EL2) bits */ | ||
81 | #define SCTLR_EL2_EE (1 << 25) | ||
82 | #define SCTLR_EL2_WXN (1 << 19) | ||
83 | #define SCTLR_EL2_I (1 << 12) | ||
84 | #define SCTLR_EL2_SA (1 << 3) | ||
85 | #define SCTLR_EL2_C (1 << 2) | ||
86 | #define SCTLR_EL2_A (1 << 1) | ||
87 | #define SCTLR_EL2_M 1 | ||
88 | #define SCTLR_EL2_FLAGS (SCTLR_EL2_M | SCTLR_EL2_A | SCTLR_EL2_C | \ | ||
89 | SCTLR_EL2_SA | SCTLR_EL2_I) | ||
90 | |||
91 | /* TCR_EL2 Registers bits */ | ||
92 | #define TCR_EL2_TBI (1 << 20) | ||
93 | #define TCR_EL2_PS (7 << 16) | ||
94 | #define TCR_EL2_PS_40B (2 << 16) | ||
95 | #define TCR_EL2_TG0 (1 << 14) | ||
96 | #define TCR_EL2_SH0 (3 << 12) | ||
97 | #define TCR_EL2_ORGN0 (3 << 10) | ||
98 | #define TCR_EL2_IRGN0 (3 << 8) | ||
99 | #define TCR_EL2_T0SZ 0x3f | ||
100 | #define TCR_EL2_MASK (TCR_EL2_TG0 | TCR_EL2_SH0 | \ | ||
101 | TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ) | ||
102 | |||
103 | #define TCR_EL2_FLAGS (TCR_EL2_PS_40B) | ||
104 | |||
105 | /* VTCR_EL2 Registers bits */ | ||
106 | #define VTCR_EL2_PS_MASK (7 << 16) | ||
107 | #define VTCR_EL2_PS_40B (2 << 16) | ||
108 | #define VTCR_EL2_TG0_MASK (1 << 14) | ||
109 | #define VTCR_EL2_TG0_4K (0 << 14) | ||
110 | #define VTCR_EL2_TG0_64K (1 << 14) | ||
111 | #define VTCR_EL2_SH0_MASK (3 << 12) | ||
112 | #define VTCR_EL2_SH0_INNER (3 << 12) | ||
113 | #define VTCR_EL2_ORGN0_MASK (3 << 10) | ||
114 | #define VTCR_EL2_ORGN0_WBWA (1 << 10) | ||
115 | #define VTCR_EL2_IRGN0_MASK (3 << 8) | ||
116 | #define VTCR_EL2_IRGN0_WBWA (1 << 8) | ||
117 | #define VTCR_EL2_SL0_MASK (3 << 6) | ||
118 | #define VTCR_EL2_SL0_LVL1 (1 << 6) | ||
119 | #define VTCR_EL2_T0SZ_MASK 0x3f | ||
120 | #define VTCR_EL2_T0SZ_40B 24 | ||
121 | |||
122 | #ifdef CONFIG_ARM64_64K_PAGES | ||
123 | /* | ||
124 | * Stage2 translation configuration: | ||
125 | * 40bits output (PS = 2) | ||
126 | * 40bits input (T0SZ = 24) | ||
127 | * 64kB pages (TG0 = 1) | ||
128 | * 2 level page tables (SL = 1) | ||
129 | */ | ||
130 | #define VTCR_EL2_FLAGS (VTCR_EL2_PS_40B | VTCR_EL2_TG0_64K | \ | ||
131 | VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ | ||
132 | VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \ | ||
133 | VTCR_EL2_T0SZ_40B) | ||
134 | #define VTTBR_X (38 - VTCR_EL2_T0SZ_40B) | ||
135 | #else | ||
136 | /* | ||
137 | * Stage2 translation configuration: | ||
138 | * 40bits output (PS = 2) | ||
139 | * 40bits input (T0SZ = 24) | ||
140 | * 4kB pages (TG0 = 0) | ||
141 | * 3 level page tables (SL = 1) | ||
142 | */ | ||
143 | #define VTCR_EL2_FLAGS (VTCR_EL2_PS_40B | VTCR_EL2_TG0_4K | \ | ||
144 | VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ | ||
145 | VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \ | ||
146 | VTCR_EL2_T0SZ_40B) | ||
147 | #define VTTBR_X (37 - VTCR_EL2_T0SZ_40B) | ||
148 | #endif | ||
149 | |||
150 | #define VTTBR_BADDR_SHIFT (VTTBR_X - 1) | ||
151 | #define VTTBR_BADDR_MASK (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT) | ||
152 | #define VTTBR_VMID_SHIFT (48LLU) | ||
153 | #define VTTBR_VMID_MASK (0xffLLU << VTTBR_VMID_SHIFT) | ||
154 | |||
155 | /* Hyp System Trap Register */ | ||
156 | #define HSTR_EL2_TTEE (1 << 16) | ||
157 | #define HSTR_EL2_T(x) (1 << x) | ||
158 | |||
159 | /* Hyp Coprocessor Trap Register */ | ||
160 | #define CPTR_EL2_TCPAC (1 << 31) | ||
161 | #define CPTR_EL2_TTA (1 << 20) | ||
162 | #define CPTR_EL2_TFP (1 << 10) | ||
163 | |||
164 | /* Hyp Debug Configuration Register bits */ | ||
165 | #define MDCR_EL2_TDRA (1 << 11) | ||
166 | #define MDCR_EL2_TDOSA (1 << 10) | ||
167 | #define MDCR_EL2_TDA (1 << 9) | ||
168 | #define MDCR_EL2_TDE (1 << 8) | ||
169 | #define MDCR_EL2_HPME (1 << 7) | ||
170 | #define MDCR_EL2_TPM (1 << 6) | ||
171 | #define MDCR_EL2_TPMCR (1 << 5) | ||
172 | #define MDCR_EL2_HPMN_MASK (0x1F) | ||
173 | |||
174 | /* Exception Syndrome Register (ESR) bits */ | ||
175 | #define ESR_EL2_EC_SHIFT (26) | ||
176 | #define ESR_EL2_EC (0x3fU << ESR_EL2_EC_SHIFT) | ||
177 | #define ESR_EL2_IL (1U << 25) | ||
178 | #define ESR_EL2_ISS (ESR_EL2_IL - 1) | ||
179 | #define ESR_EL2_ISV_SHIFT (24) | ||
180 | #define ESR_EL2_ISV (1U << ESR_EL2_ISV_SHIFT) | ||
181 | #define ESR_EL2_SAS_SHIFT (22) | ||
182 | #define ESR_EL2_SAS (3U << ESR_EL2_SAS_SHIFT) | ||
183 | #define ESR_EL2_SSE (1 << 21) | ||
184 | #define ESR_EL2_SRT_SHIFT (16) | ||
185 | #define ESR_EL2_SRT_MASK (0x1f << ESR_EL2_SRT_SHIFT) | ||
186 | #define ESR_EL2_SF (1 << 15) | ||
187 | #define ESR_EL2_AR (1 << 14) | ||
188 | #define ESR_EL2_EA (1 << 9) | ||
189 | #define ESR_EL2_CM (1 << 8) | ||
190 | #define ESR_EL2_S1PTW (1 << 7) | ||
191 | #define ESR_EL2_WNR (1 << 6) | ||
192 | #define ESR_EL2_FSC (0x3f) | ||
193 | #define ESR_EL2_FSC_TYPE (0x3c) | ||
194 | |||
195 | #define ESR_EL2_CV_SHIFT (24) | ||
196 | #define ESR_EL2_CV (1U << ESR_EL2_CV_SHIFT) | ||
197 | #define ESR_EL2_COND_SHIFT (20) | ||
198 | #define ESR_EL2_COND (0xfU << ESR_EL2_COND_SHIFT) | ||
199 | |||
200 | |||
201 | #define FSC_FAULT (0x04) | ||
202 | #define FSC_PERM (0x0c) | ||
203 | |||
204 | /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ | ||
205 | #define HPFAR_MASK (~0xFUL) | ||
206 | |||
207 | #define ESR_EL2_EC_UNKNOWN (0x00) | ||
208 | #define ESR_EL2_EC_WFI (0x01) | ||
209 | #define ESR_EL2_EC_CP15_32 (0x03) | ||
210 | #define ESR_EL2_EC_CP15_64 (0x04) | ||
211 | #define ESR_EL2_EC_CP14_MR (0x05) | ||
212 | #define ESR_EL2_EC_CP14_LS (0x06) | ||
213 | #define ESR_EL2_EC_FP_ASIMD (0x07) | ||
214 | #define ESR_EL2_EC_CP10_ID (0x08) | ||
215 | #define ESR_EL2_EC_CP14_64 (0x0C) | ||
216 | #define ESR_EL2_EC_ILL_ISS (0x0E) | ||
217 | #define ESR_EL2_EC_SVC32 (0x11) | ||
218 | #define ESR_EL2_EC_HVC32 (0x12) | ||
219 | #define ESR_EL2_EC_SMC32 (0x13) | ||
220 | #define ESR_EL2_EC_SVC64 (0x15) | ||
221 | #define ESR_EL2_EC_HVC64 (0x16) | ||
222 | #define ESR_EL2_EC_SMC64 (0x17) | ||
223 | #define ESR_EL2_EC_SYS64 (0x18) | ||
224 | #define ESR_EL2_EC_IABT (0x20) | ||
225 | #define ESR_EL2_EC_IABT_HYP (0x21) | ||
226 | #define ESR_EL2_EC_PC_ALIGN (0x22) | ||
227 | #define ESR_EL2_EC_DABT (0x24) | ||
228 | #define ESR_EL2_EC_DABT_HYP (0x25) | ||
229 | #define ESR_EL2_EC_SP_ALIGN (0x26) | ||
230 | #define ESR_EL2_EC_FP_EXC32 (0x28) | ||
231 | #define ESR_EL2_EC_FP_EXC64 (0x2C) | ||
232 | #define ESR_EL2_EC_SERRROR (0x2F) | ||
233 | #define ESR_EL2_EC_BREAKPT (0x30) | ||
234 | #define ESR_EL2_EC_BREAKPT_HYP (0x31) | ||
235 | #define ESR_EL2_EC_SOFTSTP (0x32) | ||
236 | #define ESR_EL2_EC_SOFTSTP_HYP (0x33) | ||
237 | #define ESR_EL2_EC_WATCHPT (0x34) | ||
238 | #define ESR_EL2_EC_WATCHPT_HYP (0x35) | ||
239 | #define ESR_EL2_EC_BKPT32 (0x38) | ||
240 | #define ESR_EL2_EC_VECTOR32 (0x3A) | ||
241 | #define ESR_EL2_EC_BRK64 (0x3C) | ||
242 | |||
243 | #define ESR_EL2_EC_xABT_xFSR_EXTABT 0x10 | ||
244 | |||
245 | #endif /* __ARM64_KVM_ARM_H__ */ | ||